1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKSRC_MMIO 358 select CPU_ARM920T 359 select GPIOLIB 360 select COMMON_CLK 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select NEED_MACH_MEMORY_H 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_IOP32X 374 bool "IOP32x-based" 375 select CPU_XSCALE 376 select GPIO_IOP 377 select GPIOLIB 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 select ARCH_SUPPORTS_BIG_ENDIAN 387 select ARM_PATCH_PHYS_VIRT 388 select CPU_XSCALE 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 select SPARSE_IRQ 395 select USB_EHCI_BIG_ENDIAN_DESC 396 select USB_EHCI_BIG_ENDIAN_MMIO 397 help 398 Support for Intel's IXP4XX (XScale) family of processors. 399 400config ARCH_DOVE 401 bool "Marvell Dove" 402 select CPU_PJ4 403 select GPIOLIB 404 select HAVE_PCI 405 select MVEBU_MBUS 406 select PINCTRL 407 select PINCTRL_DOVE 408 select PLAT_ORION_LEGACY 409 select SPARSE_IRQ 410 select PM_GENERIC_DOMAINS if PM 411 help 412 Support for the Marvell Dove SoC 88AP510 413 414config ARCH_PXA 415 bool "PXA2xx/PXA3xx-based" 416 select ARCH_MTD_XIP 417 select ARM_CPU_SUSPEND if PM 418 select AUTO_ZRELADDR 419 select COMMON_CLK 420 select CLKSRC_PXA 421 select CLKSRC_MMIO 422 select TIMER_OF 423 select CPU_XSCALE if !CPU_XSC3 424 select GPIO_PXA 425 select GPIOLIB 426 select IRQ_DOMAIN 427 select PLAT_PXA 428 select SPARSE_IRQ 429 help 430 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 431 432config ARCH_RPC 433 bool "RiscPC" 434 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 435 select ARCH_ACORN 436 select ARCH_MAY_HAVE_PC_FDC 437 select ARCH_SPARSEMEM_ENABLE 438 select ARM_HAS_SG_CHAIN 439 select CPU_SA110 440 select FIQ 441 select HAVE_PATA_PLATFORM 442 select ISA_DMA_API 443 select LEGACY_TIMER_TICK 444 select NEED_MACH_IO_H 445 select NEED_MACH_MEMORY_H 446 select NO_IOPORT_MAP 447 help 448 On the Acorn Risc-PC, Linux can support the internal IDE disk and 449 CD-ROM interface, serial and parallel port, and the floppy drive. 450 451config ARCH_SA1100 452 bool "SA1100-based" 453 select ARCH_MTD_XIP 454 select ARCH_SPARSEMEM_ENABLE 455 select CLKSRC_MMIO 456 select CLKSRC_PXA 457 select TIMER_OF if OF 458 select COMMON_CLK 459 select CPU_FREQ 460 select CPU_SA1100 461 select GPIOLIB 462 select IRQ_DOMAIN 463 select ISA 464 select NEED_MACH_MEMORY_H 465 select SPARSE_IRQ 466 help 467 Support for StrongARM 11x0 based boards. 468 469config ARCH_S3C24XX 470 bool "Samsung S3C24XX SoCs" 471 select ATAGS 472 select CLKSRC_SAMSUNG_PWM 473 select GPIO_SAMSUNG 474 select GPIOLIB 475 select NEED_MACH_IO_H 476 select S3C2410_WATCHDOG 477 select SAMSUNG_ATAGS 478 select USE_OF 479 select WATCHDOG 480 help 481 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 482 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 483 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 484 Samsung SMDK2410 development board (and derivatives). 485 486config ARCH_OMAP1 487 bool "TI OMAP1" 488 select ARCH_OMAP 489 select CLKSRC_MMIO 490 select GENERIC_IRQ_CHIP 491 select GPIOLIB 492 select HAVE_LEGACY_CLK 493 select IRQ_DOMAIN 494 select NEED_MACH_IO_H if PCCARD 495 select NEED_MACH_MEMORY_H 496 select SPARSE_IRQ 497 help 498 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 499 500endchoice 501 502menu "Multiple platform selection" 503 depends on ARCH_MULTIPLATFORM 504 505comment "CPU Core family selection" 506 507config ARCH_MULTI_V4 508 bool "ARMv4 based platforms (FA526)" 509 depends on !ARCH_MULTI_V6_V7 510 select ARCH_MULTI_V4_V5 511 select CPU_FA526 512 513config ARCH_MULTI_V4T 514 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 515 depends on !ARCH_MULTI_V6_V7 516 select ARCH_MULTI_V4_V5 517 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 518 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 519 CPU_ARM925T || CPU_ARM940T) 520 521config ARCH_MULTI_V5 522 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 523 depends on !ARCH_MULTI_V6_V7 524 select ARCH_MULTI_V4_V5 525 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 526 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 527 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 528 529config ARCH_MULTI_V4_V5 530 bool 531 532config ARCH_MULTI_V6 533 bool "ARMv6 based platforms (ARM11)" 534 select ARCH_MULTI_V6_V7 535 select CPU_V6K 536 537config ARCH_MULTI_V7 538 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 539 default y 540 select ARCH_MULTI_V6_V7 541 select CPU_V7 542 select HAVE_SMP 543 544config ARCH_MULTI_V6_V7 545 bool 546 select MIGHT_HAVE_CACHE_L2X0 547 548config ARCH_MULTI_CPU_AUTO 549 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 550 select ARCH_MULTI_V5 551 552endmenu 553 554config ARCH_VIRT 555 bool "Dummy Virtual Machine" 556 depends on ARCH_MULTI_V7 557 select ARM_AMBA 558 select ARM_GIC 559 select ARM_GIC_V2M if PCI 560 select ARM_GIC_V3 561 select ARM_GIC_V3_ITS if PCI 562 select ARM_PSCI 563 select HAVE_ARM_ARCH_TIMER 564 select ARCH_SUPPORTS_BIG_ENDIAN 565 566config ARCH_AIROHA 567 bool "Airoha SoC Support" 568 depends on ARCH_MULTI_V7 569 select ARM_AMBA 570 select ARM_GIC 571 select ARM_GIC_V3 572 select ARM_PSCI 573 select HAVE_ARM_ARCH_TIMER 574 select COMMON_CLK 575 help 576 Support for Airoha EN7523 SoCs 577 578# 579# This is sorted alphabetically by mach-* pathname. However, plat-* 580# Kconfigs may be included either alphabetically (according to the 581# plat- suffix) or along side the corresponding mach-* source. 582# 583source "arch/arm/mach-actions/Kconfig" 584 585source "arch/arm/mach-alpine/Kconfig" 586 587source "arch/arm/mach-artpec/Kconfig" 588 589source "arch/arm/mach-asm9260/Kconfig" 590 591source "arch/arm/mach-aspeed/Kconfig" 592 593source "arch/arm/mach-at91/Kconfig" 594 595source "arch/arm/mach-axxia/Kconfig" 596 597source "arch/arm/mach-bcm/Kconfig" 598 599source "arch/arm/mach-berlin/Kconfig" 600 601source "arch/arm/mach-clps711x/Kconfig" 602 603source "arch/arm/mach-cns3xxx/Kconfig" 604 605source "arch/arm/mach-davinci/Kconfig" 606 607source "arch/arm/mach-digicolor/Kconfig" 608 609source "arch/arm/mach-dove/Kconfig" 610 611source "arch/arm/mach-ep93xx/Kconfig" 612 613source "arch/arm/mach-exynos/Kconfig" 614 615source "arch/arm/mach-footbridge/Kconfig" 616 617source "arch/arm/mach-gemini/Kconfig" 618 619source "arch/arm/mach-highbank/Kconfig" 620 621source "arch/arm/mach-hisi/Kconfig" 622 623source "arch/arm/mach-imx/Kconfig" 624 625source "arch/arm/mach-integrator/Kconfig" 626 627source "arch/arm/mach-iop32x/Kconfig" 628 629source "arch/arm/mach-ixp4xx/Kconfig" 630 631source "arch/arm/mach-keystone/Kconfig" 632 633source "arch/arm/mach-lpc32xx/Kconfig" 634 635source "arch/arm/mach-mediatek/Kconfig" 636 637source "arch/arm/mach-meson/Kconfig" 638 639source "arch/arm/mach-milbeaut/Kconfig" 640 641source "arch/arm/mach-mmp/Kconfig" 642 643source "arch/arm/mach-moxart/Kconfig" 644 645source "arch/arm/mach-mstar/Kconfig" 646 647source "arch/arm/mach-mv78xx0/Kconfig" 648 649source "arch/arm/mach-mvebu/Kconfig" 650 651source "arch/arm/mach-mxs/Kconfig" 652 653source "arch/arm/mach-nomadik/Kconfig" 654 655source "arch/arm/mach-npcm/Kconfig" 656 657source "arch/arm/mach-nspire/Kconfig" 658 659source "arch/arm/plat-omap/Kconfig" 660 661source "arch/arm/mach-omap1/Kconfig" 662 663source "arch/arm/mach-omap2/Kconfig" 664 665source "arch/arm/mach-orion5x/Kconfig" 666 667source "arch/arm/mach-oxnas/Kconfig" 668 669source "arch/arm/mach-pxa/Kconfig" 670source "arch/arm/plat-pxa/Kconfig" 671 672source "arch/arm/mach-qcom/Kconfig" 673 674source "arch/arm/mach-rda/Kconfig" 675 676source "arch/arm/mach-realtek/Kconfig" 677 678source "arch/arm/mach-realview/Kconfig" 679 680source "arch/arm/mach-rockchip/Kconfig" 681 682source "arch/arm/mach-s3c/Kconfig" 683 684source "arch/arm/mach-s5pv210/Kconfig" 685 686source "arch/arm/mach-sa1100/Kconfig" 687 688source "arch/arm/mach-shmobile/Kconfig" 689 690source "arch/arm/mach-socfpga/Kconfig" 691 692source "arch/arm/mach-spear/Kconfig" 693 694source "arch/arm/mach-sti/Kconfig" 695 696source "arch/arm/mach-stm32/Kconfig" 697 698source "arch/arm/mach-sunxi/Kconfig" 699 700source "arch/arm/mach-tegra/Kconfig" 701 702source "arch/arm/mach-uniphier/Kconfig" 703 704source "arch/arm/mach-ux500/Kconfig" 705 706source "arch/arm/mach-versatile/Kconfig" 707 708source "arch/arm/mach-vexpress/Kconfig" 709 710source "arch/arm/mach-vt8500/Kconfig" 711 712source "arch/arm/mach-zynq/Kconfig" 713 714# ARMv7-M architecture 715config ARCH_LPC18XX 716 bool "NXP LPC18xx/LPC43xx" 717 depends on ARM_SINGLE_ARMV7M 718 select ARCH_HAS_RESET_CONTROLLER 719 select ARM_AMBA 720 select CLKSRC_LPC32XX 721 select PINCTRL 722 help 723 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 724 high performance microcontrollers. 725 726config ARCH_MPS2 727 bool "ARM MPS2 platform" 728 depends on ARM_SINGLE_ARMV7M 729 select ARM_AMBA 730 select CLKSRC_MPS2 731 help 732 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 733 with a range of available cores like Cortex-M3/M4/M7. 734 735 Please, note that depends which Application Note is used memory map 736 for the platform may vary, so adjustment of RAM base might be needed. 737 738# Definitions to make life easier 739config ARCH_ACORN 740 bool 741 742config PLAT_IOP 743 bool 744 745config PLAT_ORION 746 bool 747 select CLKSRC_MMIO 748 select COMMON_CLK 749 select GENERIC_IRQ_CHIP 750 select IRQ_DOMAIN 751 752config PLAT_ORION_LEGACY 753 bool 754 select PLAT_ORION 755 756config PLAT_PXA 757 bool 758 759config PLAT_VERSATILE 760 bool 761 762source "arch/arm/mm/Kconfig" 763 764config IWMMXT 765 bool "Enable iWMMXt support" 766 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 767 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 768 help 769 Enable support for iWMMXt context switching at run time if 770 running on a CPU that supports it. 771 772if !MMU 773source "arch/arm/Kconfig-nommu" 774endif 775 776config PJ4B_ERRATA_4742 777 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 778 depends on CPU_PJ4B && MACH_ARMADA_370 779 default y 780 help 781 When coming out of either a Wait for Interrupt (WFI) or a Wait for 782 Event (WFE) IDLE states, a specific timing sensitivity exists between 783 the retiring WFI/WFE instructions and the newly issued subsequent 784 instructions. This sensitivity can result in a CPU hang scenario. 785 Workaround: 786 The software must insert either a Data Synchronization Barrier (DSB) 787 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 788 instruction 789 790config ARM_ERRATA_326103 791 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 792 depends on CPU_V6 793 help 794 Executing a SWP instruction to read-only memory does not set bit 11 795 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 796 treat the access as a read, preventing a COW from occurring and 797 causing the faulting task to livelock. 798 799config ARM_ERRATA_411920 800 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 801 depends on CPU_V6 || CPU_V6K 802 help 803 Invalidation of the Instruction Cache operation can 804 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 805 It does not affect the MPCore. This option enables the ARM Ltd. 806 recommended workaround. 807 808config ARM_ERRATA_430973 809 bool "ARM errata: Stale prediction on replaced interworking branch" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 430973 Cortex-A8 813 r1p* erratum. If a code sequence containing an ARM/Thumb 814 interworking branch is replaced with another code sequence at the 815 same virtual address, whether due to self-modifying code or virtual 816 to physical address re-mapping, Cortex-A8 does not recover from the 817 stale interworking branch prediction. This results in Cortex-A8 818 executing the new code sequence in the incorrect ARM or Thumb state. 819 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 820 and also flushes the branch target cache at every context switch. 821 Note that setting specific bits in the ACTLR register may not be 822 available in non-secure mode. 823 824config ARM_ERRATA_458693 825 bool "ARM errata: Processor deadlock when a false hazard is created" 826 depends on CPU_V7 827 depends on !ARCH_MULTIPLATFORM 828 help 829 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 830 erratum. For very specific sequences of memory operations, it is 831 possible for a hazard condition intended for a cache line to instead 832 be incorrectly associated with a different cache line. This false 833 hazard might then cause a processor deadlock. The workaround enables 834 the L1 caching of the NEON accesses and disables the PLD instruction 835 in the ACTLR register. Note that setting specific bits in the ACTLR 836 register may not be available in non-secure mode. 837 838config ARM_ERRATA_460075 839 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 840 depends on CPU_V7 841 depends on !ARCH_MULTIPLATFORM 842 help 843 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 844 erratum. Any asynchronous access to the L2 cache may encounter a 845 situation in which recent store transactions to the L2 cache are lost 846 and overwritten with stale memory contents from external memory. The 847 workaround disables the write-allocate mode for the L2 cache via the 848 ACTLR register. Note that setting specific bits in the ACTLR register 849 may not be available in non-secure mode. 850 851config ARM_ERRATA_742230 852 bool "ARM errata: DMB operation may be faulty" 853 depends on CPU_V7 && SMP 854 depends on !ARCH_MULTIPLATFORM 855 help 856 This option enables the workaround for the 742230 Cortex-A9 857 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 858 between two write operations may not ensure the correct visibility 859 ordering of the two writes. This workaround sets a specific bit in 860 the diagnostic register of the Cortex-A9 which causes the DMB 861 instruction to behave as a DSB, ensuring the correct behaviour of 862 the two writes. 863 864config ARM_ERRATA_742231 865 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 866 depends on CPU_V7 && SMP 867 depends on !ARCH_MULTIPLATFORM 868 help 869 This option enables the workaround for the 742231 Cortex-A9 870 (r2p0..r2p2) erratum. Under certain conditions, specific to the 871 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 872 accessing some data located in the same cache line, may get corrupted 873 data due to bad handling of the address hazard when the line gets 874 replaced from one of the CPUs at the same time as another CPU is 875 accessing it. This workaround sets specific bits in the diagnostic 876 register of the Cortex-A9 which reduces the linefill issuing 877 capabilities of the processor. 878 879config ARM_ERRATA_643719 880 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 881 depends on CPU_V7 && SMP 882 default y 883 help 884 This option enables the workaround for the 643719 Cortex-A9 (prior to 885 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 886 register returns zero when it should return one. The workaround 887 corrects this value, ensuring cache maintenance operations which use 888 it behave as intended and avoiding data corruption. 889 890config ARM_ERRATA_720789 891 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 892 depends on CPU_V7 893 help 894 This option enables the workaround for the 720789 Cortex-A9 (prior to 895 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 896 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 897 As a consequence of this erratum, some TLB entries which should be 898 invalidated are not, resulting in an incoherency in the system page 899 tables. The workaround changes the TLB flushing routines to invalidate 900 entries regardless of the ASID. 901 902config ARM_ERRATA_743622 903 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 904 depends on CPU_V7 905 depends on !ARCH_MULTIPLATFORM 906 help 907 This option enables the workaround for the 743622 Cortex-A9 908 (r2p*) erratum. Under very rare conditions, a faulty 909 optimisation in the Cortex-A9 Store Buffer may lead to data 910 corruption. This workaround sets a specific bit in the diagnostic 911 register of the Cortex-A9 which disables the Store Buffer 912 optimisation, preventing the defect from occurring. This has no 913 visible impact on the overall performance or power consumption of the 914 processor. 915 916config ARM_ERRATA_751472 917 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 918 depends on CPU_V7 919 depends on !ARCH_MULTIPLATFORM 920 help 921 This option enables the workaround for the 751472 Cortex-A9 (prior 922 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 923 completion of a following broadcasted operation if the second 924 operation is received by a CPU before the ICIALLUIS has completed, 925 potentially leading to corrupted entries in the cache or TLB. 926 927config ARM_ERRATA_754322 928 bool "ARM errata: possible faulty MMU translations following an ASID switch" 929 depends on CPU_V7 930 help 931 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 932 r3p*) erratum. A speculative memory access may cause a page table walk 933 which starts prior to an ASID switch but completes afterwards. This 934 can populate the micro-TLB with a stale entry which may be hit with 935 the new ASID. This workaround places two dsb instructions in the mm 936 switching code so that no page table walks can cross the ASID switch. 937 938config ARM_ERRATA_754327 939 bool "ARM errata: no automatic Store Buffer drain" 940 depends on CPU_V7 && SMP 941 help 942 This option enables the workaround for the 754327 Cortex-A9 (prior to 943 r2p0) erratum. The Store Buffer does not have any automatic draining 944 mechanism and therefore a livelock may occur if an external agent 945 continuously polls a memory location waiting to observe an update. 946 This workaround defines cpu_relax() as smp_mb(), preventing correctly 947 written polling loops from denying visibility of updates to memory. 948 949config ARM_ERRATA_364296 950 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 951 depends on CPU_V6 952 help 953 This options enables the workaround for the 364296 ARM1136 954 r0p2 erratum (possible cache data corruption with 955 hit-under-miss enabled). It sets the undocumented bit 31 in 956 the auxiliary control register and the FI bit in the control 957 register, thus disabling hit-under-miss without putting the 958 processor into full low interrupt latency mode. ARM11MPCore 959 is not affected. 960 961config ARM_ERRATA_764369 962 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 963 depends on CPU_V7 && SMP 964 help 965 This option enables the workaround for erratum 764369 966 affecting Cortex-A9 MPCore with two or more processors (all 967 current revisions). Under certain timing circumstances, a data 968 cache line maintenance operation by MVA targeting an Inner 969 Shareable memory region may fail to proceed up to either the 970 Point of Coherency or to the Point of Unification of the 971 system. This workaround adds a DSB instruction before the 972 relevant cache maintenance functions and sets a specific bit 973 in the diagnostic control register of the SCU. 974 975config ARM_ERRATA_775420 976 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 980 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 981 operation aborts with MMU exception, it might cause the processor 982 to deadlock. This workaround puts DSB before executing ISB if 983 an abort may occur on cache maintenance. 984 985config ARM_ERRATA_798181 986 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 987 depends on CPU_V7 && SMP 988 help 989 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 990 adequately shooting down all use of the old entries. This 991 option enables the Linux kernel workaround for this erratum 992 which sends an IPI to the CPUs that are running the same ASID 993 as the one being invalidated. 994 995config ARM_ERRATA_773022 996 bool "ARM errata: incorrect instructions may be executed from loop buffer" 997 depends on CPU_V7 998 help 999 This option enables the workaround for the 773022 Cortex-A15 1000 (up to r0p4) erratum. In certain rare sequences of code, the 1001 loop buffer may deliver incorrect instructions. This 1002 workaround disables the loop buffer to avoid the erratum. 1003 1004config ARM_ERRATA_818325_852422 1005 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1006 depends on CPU_V7 1007 help 1008 This option enables the workaround for: 1009 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1010 instruction might deadlock. Fixed in r0p1. 1011 - Cortex-A12 852422: Execution of a sequence of instructions might 1012 lead to either a data corruption or a CPU deadlock. Not fixed in 1013 any Cortex-A12 cores yet. 1014 This workaround for all both errata involves setting bit[12] of the 1015 Feature Register. This bit disables an optimisation applied to a 1016 sequence of 2 instructions that use opposing condition codes. 1017 1018config ARM_ERRATA_821420 1019 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1020 depends on CPU_V7 1021 help 1022 This option enables the workaround for the 821420 Cortex-A12 1023 (all revs) erratum. In very rare timing conditions, a sequence 1024 of VMOV to Core registers instructions, for which the second 1025 one is in the shadow of a branch or abort, can lead to a 1026 deadlock when the VMOV instructions are issued out-of-order. 1027 1028config ARM_ERRATA_825619 1029 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1030 depends on CPU_V7 1031 help 1032 This option enables the workaround for the 825619 Cortex-A12 1033 (all revs) erratum. Within rare timing constraints, executing a 1034 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1035 and Device/Strongly-Ordered loads and stores might cause deadlock 1036 1037config ARM_ERRATA_857271 1038 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1039 depends on CPU_V7 1040 help 1041 This option enables the workaround for the 857271 Cortex-A12 1042 (all revs) erratum. Under very rare timing conditions, the CPU might 1043 hang. The workaround is expected to have a < 1% performance impact. 1044 1045config ARM_ERRATA_852421 1046 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1047 depends on CPU_V7 1048 help 1049 This option enables the workaround for the 852421 Cortex-A17 1050 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1051 execution of a DMB ST instruction might fail to properly order 1052 stores from GroupA and stores from GroupB. 1053 1054config ARM_ERRATA_852423 1055 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1056 depends on CPU_V7 1057 help 1058 This option enables the workaround for: 1059 - Cortex-A17 852423: Execution of a sequence of instructions might 1060 lead to either a data corruption or a CPU deadlock. Not fixed in 1061 any Cortex-A17 cores yet. 1062 This is identical to Cortex-A12 erratum 852422. It is a separate 1063 config option from the A12 erratum due to the way errata are checked 1064 for and handled. 1065 1066config ARM_ERRATA_857272 1067 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1068 depends on CPU_V7 1069 help 1070 This option enables the workaround for the 857272 Cortex-A17 erratum. 1071 This erratum is not known to be fixed in any A17 revision. 1072 This is identical to Cortex-A12 erratum 857271. It is a separate 1073 config option from the A12 erratum due to the way errata are checked 1074 for and handled. 1075 1076endmenu 1077 1078source "arch/arm/common/Kconfig" 1079 1080menu "Bus support" 1081 1082config ISA 1083 bool 1084 help 1085 Find out whether you have ISA slots on your motherboard. ISA is the 1086 name of a bus system, i.e. the way the CPU talks to the other stuff 1087 inside your box. Other bus systems are PCI, EISA, MicroChannel 1088 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1089 newer boards don't support it. If you have ISA, say Y, otherwise N. 1090 1091# Select ISA DMA controller support 1092config ISA_DMA 1093 bool 1094 select ISA_DMA_API 1095 1096# Select ISA DMA interface 1097config ISA_DMA_API 1098 bool 1099 1100config PCI_NANOENGINE 1101 bool "BSE nanoEngine PCI support" 1102 depends on SA1100_NANOENGINE 1103 help 1104 Enable PCI on the BSE nanoEngine board. 1105 1106config ARM_ERRATA_814220 1107 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1108 depends on CPU_V7 1109 help 1110 The v7 ARM states that all cache and branch predictor maintenance 1111 operations that do not specify an address execute, relative to 1112 each other, in program order. 1113 However, because of this erratum, an L2 set/way cache maintenance 1114 operation can overtake an L1 set/way cache maintenance operation. 1115 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1116 r0p4, r0p5. 1117 1118endmenu 1119 1120menu "Kernel Features" 1121 1122config HAVE_SMP 1123 bool 1124 help 1125 This option should be selected by machines which have an SMP- 1126 capable CPU. 1127 1128 The only effect of this option is to make the SMP-related 1129 options available to the user for configuration. 1130 1131config SMP 1132 bool "Symmetric Multi-Processing" 1133 depends on CPU_V6K || CPU_V7 1134 depends on HAVE_SMP 1135 depends on MMU || ARM_MPU 1136 select IRQ_WORK 1137 help 1138 This enables support for systems with more than one CPU. If you have 1139 a system with only one CPU, say N. If you have a system with more 1140 than one CPU, say Y. 1141 1142 If you say N here, the kernel will run on uni- and multiprocessor 1143 machines, but will use only one CPU of a multiprocessor machine. If 1144 you say Y here, the kernel will run on many, but not all, 1145 uniprocessor machines. On a uniprocessor machine, the kernel 1146 will run faster if you say N here. 1147 1148 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1149 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1150 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1151 1152 If you don't know what to do here, say N. 1153 1154config SMP_ON_UP 1155 bool "Allow booting SMP kernel on uniprocessor systems" 1156 depends on SMP && !XIP_KERNEL && MMU 1157 default y 1158 help 1159 SMP kernels contain instructions which fail on non-SMP processors. 1160 Enabling this option allows the kernel to modify itself to make 1161 these instructions safe. Disabling it allows about 1K of space 1162 savings. 1163 1164 If you don't know what to do here, say Y. 1165 1166 1167config CURRENT_POINTER_IN_TPIDRURO 1168 def_bool y 1169 depends on CPU_32v6K && !CPU_V6 1170 1171config IRQSTACKS 1172 def_bool y 1173 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1174 select HAVE_SOFTIRQ_ON_OWN_STACK 1175 1176config ARM_CPU_TOPOLOGY 1177 bool "Support cpu topology definition" 1178 depends on SMP && CPU_V7 1179 default y 1180 help 1181 Support ARM cpu topology definition. The MPIDR register defines 1182 affinity between processors which is then used to describe the cpu 1183 topology of an ARM System. 1184 1185config SCHED_MC 1186 bool "Multi-core scheduler support" 1187 depends on ARM_CPU_TOPOLOGY 1188 help 1189 Multi-core scheduler support improves the CPU scheduler's decision 1190 making when dealing with multi-core CPU chips at a cost of slightly 1191 increased overhead in some places. If unsure say N here. 1192 1193config SCHED_SMT 1194 bool "SMT scheduler support" 1195 depends on ARM_CPU_TOPOLOGY 1196 help 1197 Improves the CPU scheduler's decision making when dealing with 1198 MultiThreading at a cost of slightly increased overhead in some 1199 places. If unsure say N here. 1200 1201config HAVE_ARM_SCU 1202 bool 1203 help 1204 This option enables support for the ARM snoop control unit 1205 1206config HAVE_ARM_ARCH_TIMER 1207 bool "Architected timer support" 1208 depends on CPU_V7 1209 select ARM_ARCH_TIMER 1210 help 1211 This option enables support for the ARM architected timer 1212 1213config HAVE_ARM_TWD 1214 bool 1215 help 1216 This options enables support for the ARM timer and watchdog unit 1217 1218config MCPM 1219 bool "Multi-Cluster Power Management" 1220 depends on CPU_V7 && SMP 1221 help 1222 This option provides the common power management infrastructure 1223 for (multi-)cluster based systems, such as big.LITTLE based 1224 systems. 1225 1226config MCPM_QUAD_CLUSTER 1227 bool 1228 depends on MCPM 1229 help 1230 To avoid wasting resources unnecessarily, MCPM only supports up 1231 to 2 clusters by default. 1232 Platforms with 3 or 4 clusters that use MCPM must select this 1233 option to allow the additional clusters to be managed. 1234 1235config BIG_LITTLE 1236 bool "big.LITTLE support (Experimental)" 1237 depends on CPU_V7 && SMP 1238 select MCPM 1239 help 1240 This option enables support selections for the big.LITTLE 1241 system architecture. 1242 1243config BL_SWITCHER 1244 bool "big.LITTLE switcher support" 1245 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1246 select CPU_PM 1247 help 1248 The big.LITTLE "switcher" provides the core functionality to 1249 transparently handle transition between a cluster of A15's 1250 and a cluster of A7's in a big.LITTLE system. 1251 1252config BL_SWITCHER_DUMMY_IF 1253 tristate "Simple big.LITTLE switcher user interface" 1254 depends on BL_SWITCHER && DEBUG_KERNEL 1255 help 1256 This is a simple and dummy char dev interface to control 1257 the big.LITTLE switcher core code. It is meant for 1258 debugging purposes only. 1259 1260choice 1261 prompt "Memory split" 1262 depends on MMU 1263 default VMSPLIT_3G 1264 help 1265 Select the desired split between kernel and user memory. 1266 1267 If you are not absolutely sure what you are doing, leave this 1268 option alone! 1269 1270 config VMSPLIT_3G 1271 bool "3G/1G user/kernel split" 1272 config VMSPLIT_3G_OPT 1273 depends on !ARM_LPAE 1274 bool "3G/1G user/kernel split (for full 1G low memory)" 1275 config VMSPLIT_2G 1276 bool "2G/2G user/kernel split" 1277 config VMSPLIT_1G 1278 bool "1G/3G user/kernel split" 1279endchoice 1280 1281config PAGE_OFFSET 1282 hex 1283 default PHYS_OFFSET if !MMU 1284 default 0x40000000 if VMSPLIT_1G 1285 default 0x80000000 if VMSPLIT_2G 1286 default 0xB0000000 if VMSPLIT_3G_OPT 1287 default 0xC0000000 1288 1289config KASAN_SHADOW_OFFSET 1290 hex 1291 depends on KASAN 1292 default 0x1f000000 if PAGE_OFFSET=0x40000000 1293 default 0x5f000000 if PAGE_OFFSET=0x80000000 1294 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1295 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1296 default 0xffffffff 1297 1298config NR_CPUS 1299 int "Maximum number of CPUs (2-32)" 1300 range 2 16 if DEBUG_KMAP_LOCAL 1301 range 2 32 if !DEBUG_KMAP_LOCAL 1302 depends on SMP 1303 default "4" 1304 help 1305 The maximum number of CPUs that the kernel can support. 1306 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1307 debugging is enabled, which uses half of the per-CPU fixmap 1308 slots as guard regions. 1309 1310config HOTPLUG_CPU 1311 bool "Support for hot-pluggable CPUs" 1312 depends on SMP 1313 select GENERIC_IRQ_MIGRATION 1314 help 1315 Say Y here to experiment with turning CPUs off and on. CPUs 1316 can be controlled through /sys/devices/system/cpu. 1317 1318config ARM_PSCI 1319 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1320 depends on HAVE_ARM_SMCCC 1321 select ARM_PSCI_FW 1322 help 1323 Say Y here if you want Linux to communicate with system firmware 1324 implementing the PSCI specification for CPU-centric power 1325 management operations described in ARM document number ARM DEN 1326 0022A ("Power State Coordination Interface System Software on 1327 ARM processors"). 1328 1329# The GPIO number here must be sorted by descending number. In case of 1330# a multiplatform kernel, we just want the highest value required by the 1331# selected platforms. 1332config ARCH_NR_GPIO 1333 int 1334 default 2048 if ARCH_INTEL_SOCFPGA 1335 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1336 ARCH_ZYNQ || ARCH_ASPEED 1337 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1338 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1339 default 416 if ARCH_SUNXI 1340 default 392 if ARCH_U8500 1341 default 352 if ARCH_VT8500 1342 default 288 if ARCH_ROCKCHIP 1343 default 264 if MACH_H4700 1344 default 0 1345 help 1346 Maximum number of GPIOs in the system. 1347 1348 If unsure, leave the default value. 1349 1350config HZ_FIXED 1351 int 1352 default 128 if SOC_AT91RM9200 1353 default 0 1354 1355choice 1356 depends on HZ_FIXED = 0 1357 prompt "Timer frequency" 1358 1359config HZ_100 1360 bool "100 Hz" 1361 1362config HZ_200 1363 bool "200 Hz" 1364 1365config HZ_250 1366 bool "250 Hz" 1367 1368config HZ_300 1369 bool "300 Hz" 1370 1371config HZ_500 1372 bool "500 Hz" 1373 1374config HZ_1000 1375 bool "1000 Hz" 1376 1377endchoice 1378 1379config HZ 1380 int 1381 default HZ_FIXED if HZ_FIXED != 0 1382 default 100 if HZ_100 1383 default 200 if HZ_200 1384 default 250 if HZ_250 1385 default 300 if HZ_300 1386 default 500 if HZ_500 1387 default 1000 1388 1389config SCHED_HRTICK 1390 def_bool HIGH_RES_TIMERS 1391 1392config THUMB2_KERNEL 1393 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1394 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1395 default y if CPU_THUMBONLY 1396 select ARM_UNWIND 1397 help 1398 By enabling this option, the kernel will be compiled in 1399 Thumb-2 mode. 1400 1401 If unsure, say N. 1402 1403config ARM_PATCH_IDIV 1404 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1405 depends on CPU_32v7 && !XIP_KERNEL 1406 default y 1407 help 1408 The ARM compiler inserts calls to __aeabi_idiv() and 1409 __aeabi_uidiv() when it needs to perform division on signed 1410 and unsigned integers. Some v7 CPUs have support for the sdiv 1411 and udiv instructions that can be used to implement those 1412 functions. 1413 1414 Enabling this option allows the kernel to modify itself to 1415 replace the first two instructions of these library functions 1416 with the sdiv or udiv plus "bx lr" instructions when the CPU 1417 it is running on supports them. Typically this will be faster 1418 and less power intensive than running the original library 1419 code to do integer division. 1420 1421config AEABI 1422 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1423 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1424 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1425 help 1426 This option allows for the kernel to be compiled using the latest 1427 ARM ABI (aka EABI). This is only useful if you are using a user 1428 space environment that is also compiled with EABI. 1429 1430 Since there are major incompatibilities between the legacy ABI and 1431 EABI, especially with regard to structure member alignment, this 1432 option also changes the kernel syscall calling convention to 1433 disambiguate both ABIs and allow for backward compatibility support 1434 (selected with CONFIG_OABI_COMPAT). 1435 1436 To use this you need GCC version 4.0.0 or later. 1437 1438config OABI_COMPAT 1439 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1440 depends on AEABI && !THUMB2_KERNEL 1441 help 1442 This option preserves the old syscall interface along with the 1443 new (ARM EABI) one. It also provides a compatibility layer to 1444 intercept syscalls that have structure arguments which layout 1445 in memory differs between the legacy ABI and the new ARM EABI 1446 (only for non "thumb" binaries). This option adds a tiny 1447 overhead to all syscalls and produces a slightly larger kernel. 1448 1449 The seccomp filter system will not be available when this is 1450 selected, since there is no way yet to sensibly distinguish 1451 between calling conventions during filtering. 1452 1453 If you know you'll be using only pure EABI user space then you 1454 can say N here. If this option is not selected and you attempt 1455 to execute a legacy ABI binary then the result will be 1456 UNPREDICTABLE (in fact it can be predicted that it won't work 1457 at all). If in doubt say N. 1458 1459config ARCH_SELECT_MEMORY_MODEL 1460 bool 1461 1462config ARCH_FLATMEM_ENABLE 1463 bool 1464 1465config ARCH_SPARSEMEM_ENABLE 1466 bool 1467 select SPARSEMEM_STATIC if SPARSEMEM 1468 1469config HIGHMEM 1470 bool "High Memory Support" 1471 depends on MMU 1472 select KMAP_LOCAL 1473 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1474 help 1475 The address space of ARM processors is only 4 Gigabytes large 1476 and it has to accommodate user address space, kernel address 1477 space as well as some memory mapped IO. That means that, if you 1478 have a large amount of physical memory and/or IO, not all of the 1479 memory can be "permanently mapped" by the kernel. The physical 1480 memory that is not permanently mapped is called "high memory". 1481 1482 Depending on the selected kernel/user memory split, minimum 1483 vmalloc space and actual amount of RAM, you may not need this 1484 option which should result in a slightly faster kernel. 1485 1486 If unsure, say n. 1487 1488config HIGHPTE 1489 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1490 depends on HIGHMEM 1491 default y 1492 help 1493 The VM uses one page of physical memory for each page table. 1494 For systems with a lot of processes, this can use a lot of 1495 precious low memory, eventually leading to low memory being 1496 consumed by page tables. Setting this option will allow 1497 user-space 2nd level page tables to reside in high memory. 1498 1499config CPU_SW_DOMAIN_PAN 1500 bool "Enable use of CPU domains to implement privileged no-access" 1501 depends on MMU && !ARM_LPAE 1502 default y 1503 help 1504 Increase kernel security by ensuring that normal kernel accesses 1505 are unable to access userspace addresses. This can help prevent 1506 use-after-free bugs becoming an exploitable privilege escalation 1507 by ensuring that magic values (such as LIST_POISON) will always 1508 fault when dereferenced. 1509 1510 CPUs with low-vector mappings use a best-efforts implementation. 1511 Their lower 1MB needs to remain accessible for the vectors, but 1512 the remainder of userspace will become appropriately inaccessible. 1513 1514config HW_PERF_EVENTS 1515 def_bool y 1516 depends on ARM_PMU 1517 1518config ARM_MODULE_PLTS 1519 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1520 depends on MODULES 1521 default y 1522 help 1523 Allocate PLTs when loading modules so that jumps and calls whose 1524 targets are too far away for their relative offsets to be encoded 1525 in the instructions themselves can be bounced via veneers in the 1526 module's PLT. This allows modules to be allocated in the generic 1527 vmalloc area after the dedicated module memory area has been 1528 exhausted. The modules will use slightly more memory, but after 1529 rounding up to page size, the actual memory footprint is usually 1530 the same. 1531 1532 Disabling this is usually safe for small single-platform 1533 configurations. If unsure, say y. 1534 1535config FORCE_MAX_ZONEORDER 1536 int "Maximum zone order" 1537 default "12" if SOC_AM33XX 1538 default "9" if SA1111 1539 default "11" 1540 help 1541 The kernel memory allocator divides physically contiguous memory 1542 blocks into "zones", where each zone is a power of two number of 1543 pages. This option selects the largest power of two that the kernel 1544 keeps in the memory allocator. If you need to allocate very large 1545 blocks of physically contiguous memory, then you may need to 1546 increase this value. 1547 1548 This config option is actually maximum order plus one. For example, 1549 a value of 11 means that the largest free memory block is 2^10 pages. 1550 1551config ALIGNMENT_TRAP 1552 def_bool CPU_CP15_MMU 1553 select HAVE_PROC_CPU if PROC_FS 1554 help 1555 ARM processors cannot fetch/store information which is not 1556 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1557 address divisible by 4. On 32-bit ARM processors, these non-aligned 1558 fetch/store instructions will be emulated in software if you say 1559 here, which has a severe performance impact. This is necessary for 1560 correct operation of some network protocols. With an IP-only 1561 configuration it is safe to say N, otherwise say Y. 1562 1563config UACCESS_WITH_MEMCPY 1564 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1565 depends on MMU 1566 default y if CPU_FEROCEON 1567 help 1568 Implement faster copy_to_user and clear_user methods for CPU 1569 cores where a 8-word STM instruction give significantly higher 1570 memory write throughput than a sequence of individual 32bit stores. 1571 1572 A possible side effect is a slight increase in scheduling latency 1573 between threads sharing the same address space if they invoke 1574 such copy operations with large buffers. 1575 1576 However, if the CPU data cache is using a write-allocate mode, 1577 this option is unlikely to provide any performance gain. 1578 1579config PARAVIRT 1580 bool "Enable paravirtualization code" 1581 help 1582 This changes the kernel so it can modify itself when it is run 1583 under a hypervisor, potentially improving performance significantly 1584 over full virtualization. 1585 1586config PARAVIRT_TIME_ACCOUNTING 1587 bool "Paravirtual steal time accounting" 1588 select PARAVIRT 1589 help 1590 Select this option to enable fine granularity task steal time 1591 accounting. Time spent executing other tasks in parallel with 1592 the current vCPU is discounted from the vCPU power. To account for 1593 that, there can be a small performance impact. 1594 1595 If in doubt, say N here. 1596 1597config XEN_DOM0 1598 def_bool y 1599 depends on XEN 1600 1601config XEN 1602 bool "Xen guest support on ARM" 1603 depends on ARM && AEABI && OF 1604 depends on CPU_V7 && !CPU_V6 1605 depends on !GENERIC_ATOMIC64 1606 depends on MMU 1607 select ARCH_DMA_ADDR_T_64BIT 1608 select ARM_PSCI 1609 select SWIOTLB 1610 select SWIOTLB_XEN 1611 select PARAVIRT 1612 help 1613 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1614 1615config CC_HAVE_STACKPROTECTOR_TLS 1616 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1617 1618config STACKPROTECTOR_PER_TASK 1619 bool "Use a unique stack canary value for each task" 1620 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1621 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1622 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1623 default y 1624 help 1625 Due to the fact that GCC uses an ordinary symbol reference from 1626 which to load the value of the stack canary, this value can only 1627 change at reboot time on SMP systems, and all tasks running in the 1628 kernel's address space are forced to use the same canary value for 1629 the entire duration that the system is up. 1630 1631 Enable this option to switch to a different method that uses a 1632 different canary value for each task. 1633 1634endmenu 1635 1636menu "Boot options" 1637 1638config USE_OF 1639 bool "Flattened Device Tree support" 1640 select IRQ_DOMAIN 1641 select OF 1642 help 1643 Include support for flattened device tree machine descriptions. 1644 1645config ATAGS 1646 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1647 default y 1648 help 1649 This is the traditional way of passing data to the kernel at boot 1650 time. If you are solely relying on the flattened device tree (or 1651 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1652 to remove ATAGS support from your kernel binary. If unsure, 1653 leave this to y. 1654 1655config DEPRECATED_PARAM_STRUCT 1656 bool "Provide old way to pass kernel parameters" 1657 depends on ATAGS 1658 help 1659 This was deprecated in 2001 and announced to live on for 5 years. 1660 Some old boot loaders still use this way. 1661 1662# Compressed boot loader in ROM. Yes, we really want to ask about 1663# TEXT and BSS so we preserve their values in the config files. 1664config ZBOOT_ROM_TEXT 1665 hex "Compressed ROM boot loader base address" 1666 default 0x0 1667 help 1668 The physical address at which the ROM-able zImage is to be 1669 placed in the target. Platforms which normally make use of 1670 ROM-able zImage formats normally set this to a suitable 1671 value in their defconfig file. 1672 1673 If ZBOOT_ROM is not enabled, this has no effect. 1674 1675config ZBOOT_ROM_BSS 1676 hex "Compressed ROM boot loader BSS address" 1677 default 0x0 1678 help 1679 The base address of an area of read/write memory in the target 1680 for the ROM-able zImage which must be available while the 1681 decompressor is running. It must be large enough to hold the 1682 entire decompressed kernel plus an additional 128 KiB. 1683 Platforms which normally make use of ROM-able zImage formats 1684 normally set this to a suitable value in their defconfig file. 1685 1686 If ZBOOT_ROM is not enabled, this has no effect. 1687 1688config ZBOOT_ROM 1689 bool "Compressed boot loader in ROM/flash" 1690 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1691 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1692 help 1693 Say Y here if you intend to execute your compressed kernel image 1694 (zImage) directly from ROM or flash. If unsure, say N. 1695 1696config ARM_APPENDED_DTB 1697 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1698 depends on OF 1699 help 1700 With this option, the boot code will look for a device tree binary 1701 (DTB) appended to zImage 1702 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1703 1704 This is meant as a backward compatibility convenience for those 1705 systems with a bootloader that can't be upgraded to accommodate 1706 the documented boot protocol using a device tree. 1707 1708 Beware that there is very little in terms of protection against 1709 this option being confused by leftover garbage in memory that might 1710 look like a DTB header after a reboot if no actual DTB is appended 1711 to zImage. Do not leave this option active in a production kernel 1712 if you don't intend to always append a DTB. Proper passing of the 1713 location into r2 of a bootloader provided DTB is always preferable 1714 to this option. 1715 1716config ARM_ATAG_DTB_COMPAT 1717 bool "Supplement the appended DTB with traditional ATAG information" 1718 depends on ARM_APPENDED_DTB 1719 help 1720 Some old bootloaders can't be updated to a DTB capable one, yet 1721 they provide ATAGs with memory configuration, the ramdisk address, 1722 the kernel cmdline string, etc. Such information is dynamically 1723 provided by the bootloader and can't always be stored in a static 1724 DTB. To allow a device tree enabled kernel to be used with such 1725 bootloaders, this option allows zImage to extract the information 1726 from the ATAG list and store it at run time into the appended DTB. 1727 1728choice 1729 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1730 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1731 1732config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1733 bool "Use bootloader kernel arguments if available" 1734 help 1735 Uses the command-line options passed by the boot loader instead of 1736 the device tree bootargs property. If the boot loader doesn't provide 1737 any, the device tree bootargs property will be used. 1738 1739config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1740 bool "Extend with bootloader kernel arguments" 1741 help 1742 The command-line arguments provided by the boot loader will be 1743 appended to the the device tree bootargs property. 1744 1745endchoice 1746 1747config CMDLINE 1748 string "Default kernel command string" 1749 default "" 1750 help 1751 On some architectures (e.g. CATS), there is currently no way 1752 for the boot loader to pass arguments to the kernel. For these 1753 architectures, you should supply some command-line options at build 1754 time by entering them here. As a minimum, you should specify the 1755 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1756 1757choice 1758 prompt "Kernel command line type" if CMDLINE != "" 1759 default CMDLINE_FROM_BOOTLOADER 1760 depends on ATAGS 1761 1762config CMDLINE_FROM_BOOTLOADER 1763 bool "Use bootloader kernel arguments if available" 1764 help 1765 Uses the command-line options passed by the boot loader. If 1766 the boot loader doesn't provide any, the default kernel command 1767 string provided in CMDLINE will be used. 1768 1769config CMDLINE_EXTEND 1770 bool "Extend bootloader kernel arguments" 1771 help 1772 The command-line arguments provided by the boot loader will be 1773 appended to the default kernel command string. 1774 1775config CMDLINE_FORCE 1776 bool "Always use the default kernel command string" 1777 help 1778 Always use the default kernel command string, even if the boot 1779 loader passes other arguments to the kernel. 1780 This is useful if you cannot or don't want to change the 1781 command-line options your boot loader passes to the kernel. 1782endchoice 1783 1784config XIP_KERNEL 1785 bool "Kernel Execute-In-Place from ROM" 1786 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1787 help 1788 Execute-In-Place allows the kernel to run from non-volatile storage 1789 directly addressable by the CPU, such as NOR flash. This saves RAM 1790 space since the text section of the kernel is not loaded from flash 1791 to RAM. Read-write sections, such as the data section and stack, 1792 are still copied to RAM. The XIP kernel is not compressed since 1793 it has to run directly from flash, so it will take more space to 1794 store it. The flash address used to link the kernel object files, 1795 and for storing it, is configuration dependent. Therefore, if you 1796 say Y here, you must know the proper physical address where to 1797 store the kernel image depending on your own flash memory usage. 1798 1799 Also note that the make target becomes "make xipImage" rather than 1800 "make zImage" or "make Image". The final kernel binary to put in 1801 ROM memory will be arch/arm/boot/xipImage. 1802 1803 If unsure, say N. 1804 1805config XIP_PHYS_ADDR 1806 hex "XIP Kernel Physical Location" 1807 depends on XIP_KERNEL 1808 default "0x00080000" 1809 help 1810 This is the physical address in your flash memory the kernel will 1811 be linked for and stored to. This address is dependent on your 1812 own flash usage. 1813 1814config XIP_DEFLATED_DATA 1815 bool "Store kernel .data section compressed in ROM" 1816 depends on XIP_KERNEL 1817 select ZLIB_INFLATE 1818 help 1819 Before the kernel is actually executed, its .data section has to be 1820 copied to RAM from ROM. This option allows for storing that data 1821 in compressed form and decompressed to RAM rather than merely being 1822 copied, saving some precious ROM space. A possible drawback is a 1823 slightly longer boot delay. 1824 1825config KEXEC 1826 bool "Kexec system call (EXPERIMENTAL)" 1827 depends on (!SMP || PM_SLEEP_SMP) 1828 depends on MMU 1829 select KEXEC_CORE 1830 help 1831 kexec is a system call that implements the ability to shutdown your 1832 current kernel, and to start another kernel. It is like a reboot 1833 but it is independent of the system firmware. And like a reboot 1834 you can start any kernel with it, not just Linux. 1835 1836 It is an ongoing process to be certain the hardware in a machine 1837 is properly shutdown, so do not be surprised if this code does not 1838 initially work for you. 1839 1840config ATAGS_PROC 1841 bool "Export atags in procfs" 1842 depends on ATAGS && KEXEC 1843 default y 1844 help 1845 Should the atags used to boot the kernel be exported in an "atags" 1846 file in procfs. Useful with kexec. 1847 1848config CRASH_DUMP 1849 bool "Build kdump crash kernel (EXPERIMENTAL)" 1850 help 1851 Generate crash dump after being started by kexec. This should 1852 be normally only set in special crash dump kernels which are 1853 loaded in the main kernel with kexec-tools into a specially 1854 reserved region and then later executed after a crash by 1855 kdump/kexec. The crash dump kernel must be compiled to a 1856 memory address not used by the main kernel 1857 1858 For more details see Documentation/admin-guide/kdump/kdump.rst 1859 1860config AUTO_ZRELADDR 1861 bool "Auto calculation of the decompressed kernel image address" 1862 help 1863 ZRELADDR is the physical address where the decompressed kernel 1864 image will be placed. If AUTO_ZRELADDR is selected, the address 1865 will be determined at run-time, either by masking the current IP 1866 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1867 This assumes the zImage being placed in the first 128MB from 1868 start of memory. 1869 1870config EFI_STUB 1871 bool 1872 1873config EFI 1874 bool "UEFI runtime support" 1875 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1876 select UCS2_STRING 1877 select EFI_PARAMS_FROM_FDT 1878 select EFI_STUB 1879 select EFI_GENERIC_STUB 1880 select EFI_RUNTIME_WRAPPERS 1881 help 1882 This option provides support for runtime services provided 1883 by UEFI firmware (such as non-volatile variables, realtime 1884 clock, and platform reset). A UEFI stub is also provided to 1885 allow the kernel to be booted as an EFI application. This 1886 is only useful for kernels that may run on systems that have 1887 UEFI firmware. 1888 1889config DMI 1890 bool "Enable support for SMBIOS (DMI) tables" 1891 depends on EFI 1892 default y 1893 help 1894 This enables SMBIOS/DMI feature for systems. 1895 1896 This option is only useful on systems that have UEFI firmware. 1897 However, even with this option, the resultant kernel should 1898 continue to boot on existing non-UEFI platforms. 1899 1900 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1901 i.e., the the practice of identifying the platform via DMI to 1902 decide whether certain workarounds for buggy hardware and/or 1903 firmware need to be enabled. This would require the DMI subsystem 1904 to be enabled much earlier than we do on ARM, which is non-trivial. 1905 1906endmenu 1907 1908menu "CPU Power Management" 1909 1910source "drivers/cpufreq/Kconfig" 1911 1912source "drivers/cpuidle/Kconfig" 1913 1914endmenu 1915 1916menu "Floating point emulation" 1917 1918comment "At least one emulation must be selected" 1919 1920config FPE_NWFPE 1921 bool "NWFPE math emulation" 1922 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1923 help 1924 Say Y to include the NWFPE floating point emulator in the kernel. 1925 This is necessary to run most binaries. Linux does not currently 1926 support floating point hardware so you need to say Y here even if 1927 your machine has an FPA or floating point co-processor podule. 1928 1929 You may say N here if you are going to load the Acorn FPEmulator 1930 early in the bootup. 1931 1932config FPE_NWFPE_XP 1933 bool "Support extended precision" 1934 depends on FPE_NWFPE 1935 help 1936 Say Y to include 80-bit support in the kernel floating-point 1937 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1938 Note that gcc does not generate 80-bit operations by default, 1939 so in most cases this option only enlarges the size of the 1940 floating point emulator without any good reason. 1941 1942 You almost surely want to say N here. 1943 1944config FPE_FASTFPE 1945 bool "FastFPE math emulation (EXPERIMENTAL)" 1946 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1947 help 1948 Say Y here to include the FAST floating point emulator in the kernel. 1949 This is an experimental much faster emulator which now also has full 1950 precision for the mantissa. It does not support any exceptions. 1951 It is very simple, and approximately 3-6 times faster than NWFPE. 1952 1953 It should be sufficient for most programs. It may be not suitable 1954 for scientific calculations, but you have to check this for yourself. 1955 If you do not feel you need a faster FP emulation you should better 1956 choose NWFPE. 1957 1958config VFP 1959 bool "VFP-format floating point maths" 1960 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1961 help 1962 Say Y to include VFP support code in the kernel. This is needed 1963 if your hardware includes a VFP unit. 1964 1965 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1966 release notes and additional status information. 1967 1968 Say N if your target does not have VFP hardware. 1969 1970config VFPv3 1971 bool 1972 depends on VFP 1973 default y if CPU_V7 1974 1975config NEON 1976 bool "Advanced SIMD (NEON) Extension support" 1977 depends on VFPv3 && CPU_V7 1978 help 1979 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1980 Extension. 1981 1982config KERNEL_MODE_NEON 1983 bool "Support for NEON in kernel mode" 1984 depends on NEON && AEABI 1985 help 1986 Say Y to include support for NEON in kernel mode. 1987 1988endmenu 1989 1990menu "Power management options" 1991 1992source "kernel/power/Kconfig" 1993 1994config ARCH_SUSPEND_POSSIBLE 1995 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1996 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1997 def_bool y 1998 1999config ARM_CPU_SUSPEND 2000 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2001 depends on ARCH_SUSPEND_POSSIBLE 2002 2003config ARCH_HIBERNATION_POSSIBLE 2004 bool 2005 depends on MMU 2006 default y if ARCH_SUSPEND_POSSIBLE 2007 2008endmenu 2009 2010if CRYPTO 2011source "arch/arm/crypto/Kconfig" 2012endif 2013 2014source "arch/arm/Kconfig.assembler" 2015