1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_STACKWALK 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 24 select ARCH_HAS_SYNC_DMA_FOR_CPU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 80 select HAVE_ARCH_MMAP_RND_BITS if MMU 81 select HAVE_ARCH_PFN_VALID 82 select HAVE_ARCH_SECCOMP 83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 85 select HAVE_ARCH_TRACEHOOK 86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 87 select HAVE_ARM_SMCCC if CPU_V7 88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 89 select HAVE_CONTEXT_TRACKING_USER 90 select HAVE_C_RECORDMCOUNT 91 select HAVE_BUILDTIME_MCOUNT_SORT 92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 93 select HAVE_DMA_CONTIGUOUS if MMU 94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 97 select HAVE_EXIT_THREAD 98 select HAVE_FAST_GUP if ARM_LPAE 99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 100 select HAVE_FUNCTION_ERROR_INJECTION 101 select HAVE_FUNCTION_GRAPH_TRACER 102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 103 select HAVE_GCC_PLUGINS 104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 105 select HAVE_IRQ_TIME_ACCOUNTING 106 select HAVE_KERNEL_GZIP 107 select HAVE_KERNEL_LZ4 108 select HAVE_KERNEL_LZMA 109 select HAVE_KERNEL_LZO 110 select HAVE_KERNEL_XZ 111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 112 select HAVE_KRETPROBES if HAVE_KPROBES 113 select HAVE_MOD_ARCH_SPECIFIC 114 select HAVE_NMI 115 select HAVE_OPTPROBES if !THUMB2_KERNEL 116 select HAVE_PCI if MMU 117 select HAVE_PERF_EVENTS 118 select HAVE_PERF_REGS 119 select HAVE_PERF_USER_STACK_DUMP 120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 121 select HAVE_REGS_AND_STACK_ACCESS_API 122 select HAVE_RSEQ 123 select HAVE_STACKPROTECTOR 124 select HAVE_SYSCALL_TRACEPOINTS 125 select HAVE_UID16 126 select HAVE_VIRT_CPU_ACCOUNTING_GEN 127 select IRQ_FORCED_THREADING 128 select MODULES_USE_ELF_REL 129 select NEED_DMA_MAP_STATE 130 select OF_EARLY_FLATTREE if OF 131 select OLD_SIGACTION 132 select OLD_SIGSUSPEND3 133 select PCI_DOMAINS_GENERIC if PCI 134 select PCI_SYSCALL if PCI 135 select PERF_USE_VMALLOC 136 select RTC_LIB 137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 138 select SYS_SUPPORTS_APM_EMULATION 139 select THREAD_INFO_IN_TASK 140 select TIMER_OF if OF 141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 144 # Above selects are sorted alphabetically; please add new ones 145 # according to that. Thanks. 146 help 147 The ARM series is a line of low-power-consumption RISC chip designs 148 licensed by ARM Ltd and targeted at embedded applications and 149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 150 manufactured, but legacy ARM-based PC hardware remains popular in 151 Europe. There is an ARM Linux project with a web page at 152 <http://www.arm.linux.org.uk/>. 153 154config ARM_HAS_GROUP_RELOCS 155 def_bool y 156 depends on !LD_IS_LLD || LLD_VERSION >= 140000 157 depends on !COMPILE_TEST 158 help 159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 160 relocations, which have been around for a long time, but were not 161 supported in LLD until version 14. The combined range is -/+ 256 MiB, 162 which is usually sufficient, but not for allyesconfig, so we disable 163 this feature when doing compile testing. 164 165config ARM_DMA_USE_IOMMU 166 bool 167 select NEED_SG_DMA_LENGTH 168 169if ARM_DMA_USE_IOMMU 170 171config ARM_DMA_IOMMU_ALIGNMENT 172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 173 range 4 9 174 default 8 175 help 176 DMA mapping framework by default aligns all buffers to the smallest 177 PAGE_SIZE order which is greater than or equal to the requested buffer 178 size. This works well for buffers up to a few hundreds kilobytes, but 179 for larger buffers it just a waste of address space. Drivers which has 180 relatively small addressing window (like 64Mib) might run out of 181 virtual space with just a few allocations. 182 183 With this parameter you can specify the maximum PAGE_SIZE order for 184 DMA IOMMU buffers. Larger buffers will be aligned only to this 185 specified order. The order is expressed as a power of two multiplied 186 by the PAGE_SIZE. 187 188endif 189 190config SYS_SUPPORTS_APM_EMULATION 191 bool 192 193config HAVE_TCM 194 bool 195 select GENERIC_ALLOCATOR 196 197config HAVE_PROC_CPU 198 bool 199 200config NO_IOPORT_MAP 201 bool 202 203config SBUS 204 bool 205 206config STACKTRACE_SUPPORT 207 bool 208 default y 209 210config LOCKDEP_SUPPORT 211 bool 212 default y 213 214config ARCH_HAS_ILOG2_U32 215 bool 216 217config ARCH_HAS_ILOG2_U64 218 bool 219 220config ARCH_HAS_BANDGAP 221 bool 222 223config FIX_EARLYCON_MEM 224 def_bool y if MMU 225 226config GENERIC_HWEIGHT 227 bool 228 default y 229 230config GENERIC_CALIBRATE_DELAY 231 bool 232 default y 233 234config ARCH_MAY_HAVE_PC_FDC 235 bool 236 237config ARCH_SUPPORTS_UPROBES 238 def_bool y 239 240config GENERIC_ISA_DMA 241 bool 242 243config FIQ 244 bool 245 246config ARCH_MTD_XIP 247 bool 248 249config ARM_PATCH_PHYS_VIRT 250 bool "Patch physical to virtual translations at runtime" if EMBEDDED 251 default y 252 depends on MMU 253 help 254 Patch phys-to-virt and virt-to-phys translation functions at 255 boot and module load time according to the position of the 256 kernel in system memory. 257 258 This can only be used with non-XIP MMU kernels where the base 259 of physical memory is at a 2 MiB boundary. 260 261 Only disable this option if you know that you do not require 262 this feature (eg, building a kernel for a single machine) and 263 you need to shrink the kernel to the minimal size. 264 265config NEED_MACH_IO_H 266 bool 267 help 268 Select this when mach/io.h is required to provide special 269 definitions for this platform. The need for mach/io.h should 270 be avoided when possible. 271 272config NEED_MACH_MEMORY_H 273 bool 274 help 275 Select this when mach/memory.h is required to provide special 276 definitions for this platform. The need for mach/memory.h should 277 be avoided when possible. 278 279config PHYS_OFFSET 280 hex "Physical address of main memory" if MMU 281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 282 default DRAM_BASE if !MMU 283 default 0x00000000 if ARCH_FOOTBRIDGE 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0x30000000 if ARCH_S3C24XX 286 default 0xa0000000 if ARCH_PXA 287 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 288 default 0 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARM_SINGLE_ARMV7M 312 def_bool !MMU 313 select ARM_NVIC 314 select CPU_V7M 315 select NO_IOPORT_MAP 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 8 319 320config ARCH_MMAP_RND_BITS_MAX 321 default 14 if PAGE_OFFSET=0x40000000 322 default 15 if PAGE_OFFSET=0x80000000 323 default 16 324 325config ARCH_MULTIPLATFORM 326 bool "Require kernel to be portable to multiple machines" if EXPERT 327 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 328 default y 329 help 330 In general, all Arm machines can be supported in a single 331 kernel image, covering either Armv4/v5 or Armv6/v7. 332 333 However, some configuration options require hardcoding machine 334 specific physical addresses or enable errata workarounds that may 335 break other machines. 336 337 Selecting N here allows using those options, including 338 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 339 340menu "Platform selection" 341 depends on MMU 342 343comment "CPU Core family selection" 344 345config ARCH_MULTI_V4 346 bool "ARMv4 based platforms (FA526, StrongARM)" 347 depends on !ARCH_MULTI_V6_V7 348 depends on !LD_IS_LLD 349 select ARCH_MULTI_V4_V5 350 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 351 352config ARCH_MULTI_V4T 353 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 354 depends on !ARCH_MULTI_V6_V7 355 depends on !LD_IS_LLD 356 select ARCH_MULTI_V4_V5 357 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 358 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 359 CPU_ARM925T || CPU_ARM940T) 360 361config ARCH_MULTI_V5 362 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 363 depends on !ARCH_MULTI_V6_V7 364 select ARCH_MULTI_V4_V5 365 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 366 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 367 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 368 369config ARCH_MULTI_V4_V5 370 bool 371 372config ARCH_MULTI_V6 373 bool "ARMv6 based platforms (ARM11)" 374 select ARCH_MULTI_V6_V7 375 select CPU_V6K 376 377config ARCH_MULTI_V7 378 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 379 default y 380 select ARCH_MULTI_V6_V7 381 select CPU_V7 382 select HAVE_SMP 383 384config ARCH_MULTI_V6_V7 385 bool 386 select MIGHT_HAVE_CACHE_L2X0 387 388config ARCH_MULTI_CPU_AUTO 389 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 390 select ARCH_MULTI_V5 391 392endmenu 393 394config ARCH_VIRT 395 bool "Dummy Virtual Machine" 396 depends on ARCH_MULTI_V7 397 select ARM_AMBA 398 select ARM_GIC 399 select ARM_GIC_V2M if PCI 400 select ARM_GIC_V3 401 select ARM_GIC_V3_ITS if PCI 402 select ARM_PSCI 403 select HAVE_ARM_ARCH_TIMER 404 405config ARCH_AIROHA 406 bool "Airoha SoC Support" 407 depends on ARCH_MULTI_V7 408 select ARM_AMBA 409 select ARM_GIC 410 select ARM_GIC_V3 411 select ARM_PSCI 412 select HAVE_ARM_ARCH_TIMER 413 help 414 Support for Airoha EN7523 SoCs 415 416# 417# This is sorted alphabetically by mach-* pathname. However, plat-* 418# Kconfigs may be included either alphabetically (according to the 419# plat- suffix) or along side the corresponding mach-* source. 420# 421source "arch/arm/mach-actions/Kconfig" 422 423source "arch/arm/mach-alpine/Kconfig" 424 425source "arch/arm/mach-artpec/Kconfig" 426 427source "arch/arm/mach-asm9260/Kconfig" 428 429source "arch/arm/mach-aspeed/Kconfig" 430 431source "arch/arm/mach-at91/Kconfig" 432 433source "arch/arm/mach-axxia/Kconfig" 434 435source "arch/arm/mach-bcm/Kconfig" 436 437source "arch/arm/mach-berlin/Kconfig" 438 439source "arch/arm/mach-clps711x/Kconfig" 440 441source "arch/arm/mach-davinci/Kconfig" 442 443source "arch/arm/mach-digicolor/Kconfig" 444 445source "arch/arm/mach-dove/Kconfig" 446 447source "arch/arm/mach-ep93xx/Kconfig" 448 449source "arch/arm/mach-exynos/Kconfig" 450 451source "arch/arm/mach-footbridge/Kconfig" 452 453source "arch/arm/mach-gemini/Kconfig" 454 455source "arch/arm/mach-highbank/Kconfig" 456 457source "arch/arm/mach-hisi/Kconfig" 458 459source "arch/arm/mach-hpe/Kconfig" 460 461source "arch/arm/mach-imx/Kconfig" 462 463source "arch/arm/mach-ixp4xx/Kconfig" 464 465source "arch/arm/mach-keystone/Kconfig" 466 467source "arch/arm/mach-lpc32xx/Kconfig" 468 469source "arch/arm/mach-mediatek/Kconfig" 470 471source "arch/arm/mach-meson/Kconfig" 472 473source "arch/arm/mach-milbeaut/Kconfig" 474 475source "arch/arm/mach-mmp/Kconfig" 476 477source "arch/arm/mach-moxart/Kconfig" 478 479source "arch/arm/mach-mstar/Kconfig" 480 481source "arch/arm/mach-mv78xx0/Kconfig" 482 483source "arch/arm/mach-mvebu/Kconfig" 484 485source "arch/arm/mach-mxs/Kconfig" 486 487source "arch/arm/mach-nomadik/Kconfig" 488 489source "arch/arm/mach-npcm/Kconfig" 490 491source "arch/arm/mach-nspire/Kconfig" 492 493source "arch/arm/mach-omap1/Kconfig" 494 495source "arch/arm/mach-omap2/Kconfig" 496 497source "arch/arm/mach-orion5x/Kconfig" 498 499source "arch/arm/mach-oxnas/Kconfig" 500 501source "arch/arm/mach-pxa/Kconfig" 502 503source "arch/arm/mach-qcom/Kconfig" 504 505source "arch/arm/mach-rda/Kconfig" 506 507source "arch/arm/mach-realtek/Kconfig" 508 509source "arch/arm/mach-rpc/Kconfig" 510 511source "arch/arm/mach-rockchip/Kconfig" 512 513source "arch/arm/mach-s3c/Kconfig" 514 515source "arch/arm/mach-s5pv210/Kconfig" 516 517source "arch/arm/mach-sa1100/Kconfig" 518 519source "arch/arm/mach-shmobile/Kconfig" 520 521source "arch/arm/mach-socfpga/Kconfig" 522 523source "arch/arm/mach-spear/Kconfig" 524 525source "arch/arm/mach-sti/Kconfig" 526 527source "arch/arm/mach-stm32/Kconfig" 528 529source "arch/arm/mach-sunplus/Kconfig" 530 531source "arch/arm/mach-sunxi/Kconfig" 532 533source "arch/arm/mach-tegra/Kconfig" 534 535source "arch/arm/mach-uniphier/Kconfig" 536 537source "arch/arm/mach-ux500/Kconfig" 538 539source "arch/arm/mach-versatile/Kconfig" 540 541source "arch/arm/mach-vt8500/Kconfig" 542 543source "arch/arm/mach-zynq/Kconfig" 544 545# ARMv7-M architecture 546config ARCH_LPC18XX 547 bool "NXP LPC18xx/LPC43xx" 548 depends on ARM_SINGLE_ARMV7M 549 select ARCH_HAS_RESET_CONTROLLER 550 select ARM_AMBA 551 select CLKSRC_LPC32XX 552 select PINCTRL 553 help 554 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 555 high performance microcontrollers. 556 557config ARCH_MPS2 558 bool "ARM MPS2 platform" 559 depends on ARM_SINGLE_ARMV7M 560 select ARM_AMBA 561 select CLKSRC_MPS2 562 help 563 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 564 with a range of available cores like Cortex-M3/M4/M7. 565 566 Please, note that depends which Application Note is used memory map 567 for the platform may vary, so adjustment of RAM base might be needed. 568 569# Definitions to make life easier 570config ARCH_ACORN 571 bool 572 573config PLAT_ORION 574 bool 575 select CLKSRC_MMIO 576 select GENERIC_IRQ_CHIP 577 select IRQ_DOMAIN 578 579config PLAT_ORION_LEGACY 580 bool 581 select PLAT_ORION 582 583config PLAT_VERSATILE 584 bool 585 586source "arch/arm/mm/Kconfig" 587 588config IWMMXT 589 bool "Enable iWMMXt support" 590 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 591 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 592 help 593 Enable support for iWMMXt context switching at run time if 594 running on a CPU that supports it. 595 596if !MMU 597source "arch/arm/Kconfig-nommu" 598endif 599 600config PJ4B_ERRATA_4742 601 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 602 depends on CPU_PJ4B && MACH_ARMADA_370 603 default y 604 help 605 When coming out of either a Wait for Interrupt (WFI) or a Wait for 606 Event (WFE) IDLE states, a specific timing sensitivity exists between 607 the retiring WFI/WFE instructions and the newly issued subsequent 608 instructions. This sensitivity can result in a CPU hang scenario. 609 Workaround: 610 The software must insert either a Data Synchronization Barrier (DSB) 611 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 612 instruction 613 614config ARM_ERRATA_326103 615 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 616 depends on CPU_V6 617 help 618 Executing a SWP instruction to read-only memory does not set bit 11 619 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 620 treat the access as a read, preventing a COW from occurring and 621 causing the faulting task to livelock. 622 623config ARM_ERRATA_411920 624 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 625 depends on CPU_V6 || CPU_V6K 626 help 627 Invalidation of the Instruction Cache operation can 628 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 629 It does not affect the MPCore. This option enables the ARM Ltd. 630 recommended workaround. 631 632config ARM_ERRATA_430973 633 bool "ARM errata: Stale prediction on replaced interworking branch" 634 depends on CPU_V7 635 help 636 This option enables the workaround for the 430973 Cortex-A8 637 r1p* erratum. If a code sequence containing an ARM/Thumb 638 interworking branch is replaced with another code sequence at the 639 same virtual address, whether due to self-modifying code or virtual 640 to physical address re-mapping, Cortex-A8 does not recover from the 641 stale interworking branch prediction. This results in Cortex-A8 642 executing the new code sequence in the incorrect ARM or Thumb state. 643 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 644 and also flushes the branch target cache at every context switch. 645 Note that setting specific bits in the ACTLR register may not be 646 available in non-secure mode. 647 648config ARM_ERRATA_458693 649 bool "ARM errata: Processor deadlock when a false hazard is created" 650 depends on CPU_V7 651 depends on !ARCH_MULTIPLATFORM 652 help 653 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 654 erratum. For very specific sequences of memory operations, it is 655 possible for a hazard condition intended for a cache line to instead 656 be incorrectly associated with a different cache line. This false 657 hazard might then cause a processor deadlock. The workaround enables 658 the L1 caching of the NEON accesses and disables the PLD instruction 659 in the ACTLR register. Note that setting specific bits in the ACTLR 660 register may not be available in non-secure mode. 661 662config ARM_ERRATA_460075 663 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 664 depends on CPU_V7 665 depends on !ARCH_MULTIPLATFORM 666 help 667 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 668 erratum. Any asynchronous access to the L2 cache may encounter a 669 situation in which recent store transactions to the L2 cache are lost 670 and overwritten with stale memory contents from external memory. The 671 workaround disables the write-allocate mode for the L2 cache via the 672 ACTLR register. Note that setting specific bits in the ACTLR register 673 may not be available in non-secure mode. 674 675config ARM_ERRATA_742230 676 bool "ARM errata: DMB operation may be faulty" 677 depends on CPU_V7 && SMP 678 depends on !ARCH_MULTIPLATFORM 679 help 680 This option enables the workaround for the 742230 Cortex-A9 681 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 682 between two write operations may not ensure the correct visibility 683 ordering of the two writes. This workaround sets a specific bit in 684 the diagnostic register of the Cortex-A9 which causes the DMB 685 instruction to behave as a DSB, ensuring the correct behaviour of 686 the two writes. 687 688config ARM_ERRATA_742231 689 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 690 depends on CPU_V7 && SMP 691 depends on !ARCH_MULTIPLATFORM 692 help 693 This option enables the workaround for the 742231 Cortex-A9 694 (r2p0..r2p2) erratum. Under certain conditions, specific to the 695 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 696 accessing some data located in the same cache line, may get corrupted 697 data due to bad handling of the address hazard when the line gets 698 replaced from one of the CPUs at the same time as another CPU is 699 accessing it. This workaround sets specific bits in the diagnostic 700 register of the Cortex-A9 which reduces the linefill issuing 701 capabilities of the processor. 702 703config ARM_ERRATA_643719 704 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 705 depends on CPU_V7 && SMP 706 default y 707 help 708 This option enables the workaround for the 643719 Cortex-A9 (prior to 709 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 710 register returns zero when it should return one. The workaround 711 corrects this value, ensuring cache maintenance operations which use 712 it behave as intended and avoiding data corruption. 713 714config ARM_ERRATA_720789 715 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 716 depends on CPU_V7 717 help 718 This option enables the workaround for the 720789 Cortex-A9 (prior to 719 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 720 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 721 As a consequence of this erratum, some TLB entries which should be 722 invalidated are not, resulting in an incoherency in the system page 723 tables. The workaround changes the TLB flushing routines to invalidate 724 entries regardless of the ASID. 725 726config ARM_ERRATA_743622 727 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 728 depends on CPU_V7 729 depends on !ARCH_MULTIPLATFORM 730 help 731 This option enables the workaround for the 743622 Cortex-A9 732 (r2p*) erratum. Under very rare conditions, a faulty 733 optimisation in the Cortex-A9 Store Buffer may lead to data 734 corruption. This workaround sets a specific bit in the diagnostic 735 register of the Cortex-A9 which disables the Store Buffer 736 optimisation, preventing the defect from occurring. This has no 737 visible impact on the overall performance or power consumption of the 738 processor. 739 740config ARM_ERRATA_751472 741 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 742 depends on CPU_V7 743 depends on !ARCH_MULTIPLATFORM 744 help 745 This option enables the workaround for the 751472 Cortex-A9 (prior 746 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 747 completion of a following broadcasted operation if the second 748 operation is received by a CPU before the ICIALLUIS has completed, 749 potentially leading to corrupted entries in the cache or TLB. 750 751config ARM_ERRATA_754322 752 bool "ARM errata: possible faulty MMU translations following an ASID switch" 753 depends on CPU_V7 754 help 755 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 756 r3p*) erratum. A speculative memory access may cause a page table walk 757 which starts prior to an ASID switch but completes afterwards. This 758 can populate the micro-TLB with a stale entry which may be hit with 759 the new ASID. This workaround places two dsb instructions in the mm 760 switching code so that no page table walks can cross the ASID switch. 761 762config ARM_ERRATA_754327 763 bool "ARM errata: no automatic Store Buffer drain" 764 depends on CPU_V7 && SMP 765 help 766 This option enables the workaround for the 754327 Cortex-A9 (prior to 767 r2p0) erratum. The Store Buffer does not have any automatic draining 768 mechanism and therefore a livelock may occur if an external agent 769 continuously polls a memory location waiting to observe an update. 770 This workaround defines cpu_relax() as smp_mb(), preventing correctly 771 written polling loops from denying visibility of updates to memory. 772 773config ARM_ERRATA_364296 774 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 775 depends on CPU_V6 776 help 777 This options enables the workaround for the 364296 ARM1136 778 r0p2 erratum (possible cache data corruption with 779 hit-under-miss enabled). It sets the undocumented bit 31 in 780 the auxiliary control register and the FI bit in the control 781 register, thus disabling hit-under-miss without putting the 782 processor into full low interrupt latency mode. ARM11MPCore 783 is not affected. 784 785config ARM_ERRATA_764369 786 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 787 depends on CPU_V7 && SMP 788 help 789 This option enables the workaround for erratum 764369 790 affecting Cortex-A9 MPCore with two or more processors (all 791 current revisions). Under certain timing circumstances, a data 792 cache line maintenance operation by MVA targeting an Inner 793 Shareable memory region may fail to proceed up to either the 794 Point of Coherency or to the Point of Unification of the 795 system. This workaround adds a DSB instruction before the 796 relevant cache maintenance functions and sets a specific bit 797 in the diagnostic control register of the SCU. 798 799config ARM_ERRATA_764319 800 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 801 depends on CPU_V7 802 help 803 This option enables the workaround for the 764319 Cortex A-9 erratum. 804 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 805 unexpected Undefined Instruction exception when the DBGSWENABLE 806 external pin is set to 0, even when the CP14 accesses are performed 807 from a privileged mode. This work around catches the exception in a 808 way the kernel does not stop execution. 809 810config ARM_ERRATA_775420 811 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 812 depends on CPU_V7 813 help 814 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 815 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 816 operation aborts with MMU exception, it might cause the processor 817 to deadlock. This workaround puts DSB before executing ISB if 818 an abort may occur on cache maintenance. 819 820config ARM_ERRATA_798181 821 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 822 depends on CPU_V7 && SMP 823 help 824 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 825 adequately shooting down all use of the old entries. This 826 option enables the Linux kernel workaround for this erratum 827 which sends an IPI to the CPUs that are running the same ASID 828 as the one being invalidated. 829 830config ARM_ERRATA_773022 831 bool "ARM errata: incorrect instructions may be executed from loop buffer" 832 depends on CPU_V7 833 help 834 This option enables the workaround for the 773022 Cortex-A15 835 (up to r0p4) erratum. In certain rare sequences of code, the 836 loop buffer may deliver incorrect instructions. This 837 workaround disables the loop buffer to avoid the erratum. 838 839config ARM_ERRATA_818325_852422 840 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 841 depends on CPU_V7 842 help 843 This option enables the workaround for: 844 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 845 instruction might deadlock. Fixed in r0p1. 846 - Cortex-A12 852422: Execution of a sequence of instructions might 847 lead to either a data corruption or a CPU deadlock. Not fixed in 848 any Cortex-A12 cores yet. 849 This workaround for all both errata involves setting bit[12] of the 850 Feature Register. This bit disables an optimisation applied to a 851 sequence of 2 instructions that use opposing condition codes. 852 853config ARM_ERRATA_821420 854 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 855 depends on CPU_V7 856 help 857 This option enables the workaround for the 821420 Cortex-A12 858 (all revs) erratum. In very rare timing conditions, a sequence 859 of VMOV to Core registers instructions, for which the second 860 one is in the shadow of a branch or abort, can lead to a 861 deadlock when the VMOV instructions are issued out-of-order. 862 863config ARM_ERRATA_825619 864 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 865 depends on CPU_V7 866 help 867 This option enables the workaround for the 825619 Cortex-A12 868 (all revs) erratum. Within rare timing constraints, executing a 869 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 870 and Device/Strongly-Ordered loads and stores might cause deadlock 871 872config ARM_ERRATA_857271 873 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 874 depends on CPU_V7 875 help 876 This option enables the workaround for the 857271 Cortex-A12 877 (all revs) erratum. Under very rare timing conditions, the CPU might 878 hang. The workaround is expected to have a < 1% performance impact. 879 880config ARM_ERRATA_852421 881 bool "ARM errata: A17: DMB ST might fail to create order between stores" 882 depends on CPU_V7 883 help 884 This option enables the workaround for the 852421 Cortex-A17 885 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 886 execution of a DMB ST instruction might fail to properly order 887 stores from GroupA and stores from GroupB. 888 889config ARM_ERRATA_852423 890 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 891 depends on CPU_V7 892 help 893 This option enables the workaround for: 894 - Cortex-A17 852423: Execution of a sequence of instructions might 895 lead to either a data corruption or a CPU deadlock. Not fixed in 896 any Cortex-A17 cores yet. 897 This is identical to Cortex-A12 erratum 852422. It is a separate 898 config option from the A12 erratum due to the way errata are checked 899 for and handled. 900 901config ARM_ERRATA_857272 902 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 903 depends on CPU_V7 904 help 905 This option enables the workaround for the 857272 Cortex-A17 erratum. 906 This erratum is not known to be fixed in any A17 revision. 907 This is identical to Cortex-A12 erratum 857271. It is a separate 908 config option from the A12 erratum due to the way errata are checked 909 for and handled. 910 911endmenu 912 913source "arch/arm/common/Kconfig" 914 915menu "Bus support" 916 917config ISA 918 bool 919 help 920 Find out whether you have ISA slots on your motherboard. ISA is the 921 name of a bus system, i.e. the way the CPU talks to the other stuff 922 inside your box. Other bus systems are PCI, EISA, MicroChannel 923 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 924 newer boards don't support it. If you have ISA, say Y, otherwise N. 925 926# Select ISA DMA interface 927config ISA_DMA_API 928 bool 929 930config PCI_NANOENGINE 931 bool "BSE nanoEngine PCI support" 932 depends on SA1100_NANOENGINE 933 help 934 Enable PCI on the BSE nanoEngine board. 935 936config ARM_ERRATA_814220 937 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 938 depends on CPU_V7 939 help 940 The v7 ARM states that all cache and branch predictor maintenance 941 operations that do not specify an address execute, relative to 942 each other, in program order. 943 However, because of this erratum, an L2 set/way cache maintenance 944 operation can overtake an L1 set/way cache maintenance operation. 945 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 946 r0p4, r0p5. 947 948endmenu 949 950menu "Kernel Features" 951 952config HAVE_SMP 953 bool 954 help 955 This option should be selected by machines which have an SMP- 956 capable CPU. 957 958 The only effect of this option is to make the SMP-related 959 options available to the user for configuration. 960 961config SMP 962 bool "Symmetric Multi-Processing" 963 depends on CPU_V6K || CPU_V7 964 depends on HAVE_SMP 965 depends on MMU || ARM_MPU 966 select IRQ_WORK 967 help 968 This enables support for systems with more than one CPU. If you have 969 a system with only one CPU, say N. If you have a system with more 970 than one CPU, say Y. 971 972 If you say N here, the kernel will run on uni- and multiprocessor 973 machines, but will use only one CPU of a multiprocessor machine. If 974 you say Y here, the kernel will run on many, but not all, 975 uniprocessor machines. On a uniprocessor machine, the kernel 976 will run faster if you say N here. 977 978 See also <file:Documentation/x86/i386/IO-APIC.rst>, 979 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 980 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 981 982 If you don't know what to do here, say N. 983 984config SMP_ON_UP 985 bool "Allow booting SMP kernel on uniprocessor systems" 986 depends on SMP && MMU 987 default y 988 help 989 SMP kernels contain instructions which fail on non-SMP processors. 990 Enabling this option allows the kernel to modify itself to make 991 these instructions safe. Disabling it allows about 1K of space 992 savings. 993 994 If you don't know what to do here, say Y. 995 996 997config CURRENT_POINTER_IN_TPIDRURO 998 def_bool y 999 depends on CPU_32v6K && !CPU_V6 1000 1001config IRQSTACKS 1002 def_bool y 1003 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1004 select HAVE_SOFTIRQ_ON_OWN_STACK 1005 1006config ARM_CPU_TOPOLOGY 1007 bool "Support cpu topology definition" 1008 depends on SMP && CPU_V7 1009 default y 1010 help 1011 Support ARM cpu topology definition. The MPIDR register defines 1012 affinity between processors which is then used to describe the cpu 1013 topology of an ARM System. 1014 1015config SCHED_MC 1016 bool "Multi-core scheduler support" 1017 depends on ARM_CPU_TOPOLOGY 1018 help 1019 Multi-core scheduler support improves the CPU scheduler's decision 1020 making when dealing with multi-core CPU chips at a cost of slightly 1021 increased overhead in some places. If unsure say N here. 1022 1023config SCHED_SMT 1024 bool "SMT scheduler support" 1025 depends on ARM_CPU_TOPOLOGY 1026 help 1027 Improves the CPU scheduler's decision making when dealing with 1028 MultiThreading at a cost of slightly increased overhead in some 1029 places. If unsure say N here. 1030 1031config HAVE_ARM_SCU 1032 bool 1033 help 1034 This option enables support for the ARM snoop control unit 1035 1036config HAVE_ARM_ARCH_TIMER 1037 bool "Architected timer support" 1038 depends on CPU_V7 1039 select ARM_ARCH_TIMER 1040 help 1041 This option enables support for the ARM architected timer 1042 1043config HAVE_ARM_TWD 1044 bool 1045 help 1046 This options enables support for the ARM timer and watchdog unit 1047 1048config MCPM 1049 bool "Multi-Cluster Power Management" 1050 depends on CPU_V7 && SMP 1051 help 1052 This option provides the common power management infrastructure 1053 for (multi-)cluster based systems, such as big.LITTLE based 1054 systems. 1055 1056config MCPM_QUAD_CLUSTER 1057 bool 1058 depends on MCPM 1059 help 1060 To avoid wasting resources unnecessarily, MCPM only supports up 1061 to 2 clusters by default. 1062 Platforms with 3 or 4 clusters that use MCPM must select this 1063 option to allow the additional clusters to be managed. 1064 1065config BIG_LITTLE 1066 bool "big.LITTLE support (Experimental)" 1067 depends on CPU_V7 && SMP 1068 select MCPM 1069 help 1070 This option enables support selections for the big.LITTLE 1071 system architecture. 1072 1073config BL_SWITCHER 1074 bool "big.LITTLE switcher support" 1075 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1076 select CPU_PM 1077 help 1078 The big.LITTLE "switcher" provides the core functionality to 1079 transparently handle transition between a cluster of A15's 1080 and a cluster of A7's in a big.LITTLE system. 1081 1082config BL_SWITCHER_DUMMY_IF 1083 tristate "Simple big.LITTLE switcher user interface" 1084 depends on BL_SWITCHER && DEBUG_KERNEL 1085 help 1086 This is a simple and dummy char dev interface to control 1087 the big.LITTLE switcher core code. It is meant for 1088 debugging purposes only. 1089 1090choice 1091 prompt "Memory split" 1092 depends on MMU 1093 default VMSPLIT_3G 1094 help 1095 Select the desired split between kernel and user memory. 1096 1097 If you are not absolutely sure what you are doing, leave this 1098 option alone! 1099 1100 config VMSPLIT_3G 1101 bool "3G/1G user/kernel split" 1102 config VMSPLIT_3G_OPT 1103 depends on !ARM_LPAE 1104 bool "3G/1G user/kernel split (for full 1G low memory)" 1105 config VMSPLIT_2G 1106 bool "2G/2G user/kernel split" 1107 config VMSPLIT_1G 1108 bool "1G/3G user/kernel split" 1109endchoice 1110 1111config PAGE_OFFSET 1112 hex 1113 default PHYS_OFFSET if !MMU 1114 default 0x40000000 if VMSPLIT_1G 1115 default 0x80000000 if VMSPLIT_2G 1116 default 0xB0000000 if VMSPLIT_3G_OPT 1117 default 0xC0000000 1118 1119config KASAN_SHADOW_OFFSET 1120 hex 1121 depends on KASAN 1122 default 0x1f000000 if PAGE_OFFSET=0x40000000 1123 default 0x5f000000 if PAGE_OFFSET=0x80000000 1124 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1125 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1126 default 0xffffffff 1127 1128config NR_CPUS 1129 int "Maximum number of CPUs (2-32)" 1130 range 2 16 if DEBUG_KMAP_LOCAL 1131 range 2 32 if !DEBUG_KMAP_LOCAL 1132 depends on SMP 1133 default "4" 1134 help 1135 The maximum number of CPUs that the kernel can support. 1136 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1137 debugging is enabled, which uses half of the per-CPU fixmap 1138 slots as guard regions. 1139 1140config HOTPLUG_CPU 1141 bool "Support for hot-pluggable CPUs" 1142 depends on SMP 1143 select GENERIC_IRQ_MIGRATION 1144 help 1145 Say Y here to experiment with turning CPUs off and on. CPUs 1146 can be controlled through /sys/devices/system/cpu. 1147 1148config ARM_PSCI 1149 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1150 depends on HAVE_ARM_SMCCC 1151 select ARM_PSCI_FW 1152 help 1153 Say Y here if you want Linux to communicate with system firmware 1154 implementing the PSCI specification for CPU-centric power 1155 management operations described in ARM document number ARM DEN 1156 0022A ("Power State Coordination Interface System Software on 1157 ARM processors"). 1158 1159config HZ_FIXED 1160 int 1161 default 128 if SOC_AT91RM9200 1162 default 0 1163 1164choice 1165 depends on HZ_FIXED = 0 1166 prompt "Timer frequency" 1167 1168config HZ_100 1169 bool "100 Hz" 1170 1171config HZ_200 1172 bool "200 Hz" 1173 1174config HZ_250 1175 bool "250 Hz" 1176 1177config HZ_300 1178 bool "300 Hz" 1179 1180config HZ_500 1181 bool "500 Hz" 1182 1183config HZ_1000 1184 bool "1000 Hz" 1185 1186endchoice 1187 1188config HZ 1189 int 1190 default HZ_FIXED if HZ_FIXED != 0 1191 default 100 if HZ_100 1192 default 200 if HZ_200 1193 default 250 if HZ_250 1194 default 300 if HZ_300 1195 default 500 if HZ_500 1196 default 1000 1197 1198config SCHED_HRTICK 1199 def_bool HIGH_RES_TIMERS 1200 1201config THUMB2_KERNEL 1202 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1203 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1204 default y if CPU_THUMBONLY 1205 select ARM_UNWIND 1206 help 1207 By enabling this option, the kernel will be compiled in 1208 Thumb-2 mode. 1209 1210 If unsure, say N. 1211 1212config ARM_PATCH_IDIV 1213 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1214 depends on CPU_32v7 1215 default y 1216 help 1217 The ARM compiler inserts calls to __aeabi_idiv() and 1218 __aeabi_uidiv() when it needs to perform division on signed 1219 and unsigned integers. Some v7 CPUs have support for the sdiv 1220 and udiv instructions that can be used to implement those 1221 functions. 1222 1223 Enabling this option allows the kernel to modify itself to 1224 replace the first two instructions of these library functions 1225 with the sdiv or udiv plus "bx lr" instructions when the CPU 1226 it is running on supports them. Typically this will be faster 1227 and less power intensive than running the original library 1228 code to do integer division. 1229 1230config AEABI 1231 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1232 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1233 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1234 help 1235 This option allows for the kernel to be compiled using the latest 1236 ARM ABI (aka EABI). This is only useful if you are using a user 1237 space environment that is also compiled with EABI. 1238 1239 Since there are major incompatibilities between the legacy ABI and 1240 EABI, especially with regard to structure member alignment, this 1241 option also changes the kernel syscall calling convention to 1242 disambiguate both ABIs and allow for backward compatibility support 1243 (selected with CONFIG_OABI_COMPAT). 1244 1245 To use this you need GCC version 4.0.0 or later. 1246 1247config OABI_COMPAT 1248 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1249 depends on AEABI && !THUMB2_KERNEL 1250 help 1251 This option preserves the old syscall interface along with the 1252 new (ARM EABI) one. It also provides a compatibility layer to 1253 intercept syscalls that have structure arguments which layout 1254 in memory differs between the legacy ABI and the new ARM EABI 1255 (only for non "thumb" binaries). This option adds a tiny 1256 overhead to all syscalls and produces a slightly larger kernel. 1257 1258 The seccomp filter system will not be available when this is 1259 selected, since there is no way yet to sensibly distinguish 1260 between calling conventions during filtering. 1261 1262 If you know you'll be using only pure EABI user space then you 1263 can say N here. If this option is not selected and you attempt 1264 to execute a legacy ABI binary then the result will be 1265 UNPREDICTABLE (in fact it can be predicted that it won't work 1266 at all). If in doubt say N. 1267 1268config ARCH_SELECT_MEMORY_MODEL 1269 def_bool y 1270 1271config ARCH_FLATMEM_ENABLE 1272 def_bool !(ARCH_RPC || ARCH_SA1100) 1273 1274config ARCH_SPARSEMEM_ENABLE 1275 def_bool !ARCH_FOOTBRIDGE 1276 select SPARSEMEM_STATIC if SPARSEMEM 1277 1278config HIGHMEM 1279 bool "High Memory Support" 1280 depends on MMU 1281 select KMAP_LOCAL 1282 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1283 help 1284 The address space of ARM processors is only 4 Gigabytes large 1285 and it has to accommodate user address space, kernel address 1286 space as well as some memory mapped IO. That means that, if you 1287 have a large amount of physical memory and/or IO, not all of the 1288 memory can be "permanently mapped" by the kernel. The physical 1289 memory that is not permanently mapped is called "high memory". 1290 1291 Depending on the selected kernel/user memory split, minimum 1292 vmalloc space and actual amount of RAM, you may not need this 1293 option which should result in a slightly faster kernel. 1294 1295 If unsure, say n. 1296 1297config HIGHPTE 1298 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1299 depends on HIGHMEM 1300 default y 1301 help 1302 The VM uses one page of physical memory for each page table. 1303 For systems with a lot of processes, this can use a lot of 1304 precious low memory, eventually leading to low memory being 1305 consumed by page tables. Setting this option will allow 1306 user-space 2nd level page tables to reside in high memory. 1307 1308config CPU_SW_DOMAIN_PAN 1309 bool "Enable use of CPU domains to implement privileged no-access" 1310 depends on MMU && !ARM_LPAE 1311 default y 1312 help 1313 Increase kernel security by ensuring that normal kernel accesses 1314 are unable to access userspace addresses. This can help prevent 1315 use-after-free bugs becoming an exploitable privilege escalation 1316 by ensuring that magic values (such as LIST_POISON) will always 1317 fault when dereferenced. 1318 1319 CPUs with low-vector mappings use a best-efforts implementation. 1320 Their lower 1MB needs to remain accessible for the vectors, but 1321 the remainder of userspace will become appropriately inaccessible. 1322 1323config HW_PERF_EVENTS 1324 def_bool y 1325 depends on ARM_PMU 1326 1327config ARM_MODULE_PLTS 1328 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1329 depends on MODULES 1330 select KASAN_VMALLOC if KASAN 1331 default y 1332 help 1333 Allocate PLTs when loading modules so that jumps and calls whose 1334 targets are too far away for their relative offsets to be encoded 1335 in the instructions themselves can be bounced via veneers in the 1336 module's PLT. This allows modules to be allocated in the generic 1337 vmalloc area after the dedicated module memory area has been 1338 exhausted. The modules will use slightly more memory, but after 1339 rounding up to page size, the actual memory footprint is usually 1340 the same. 1341 1342 Disabling this is usually safe for small single-platform 1343 configurations. If unsure, say y. 1344 1345config ARCH_FORCE_MAX_ORDER 1346 int "Maximum zone order" 1347 default "12" if SOC_AM33XX 1348 default "9" if SA1111 1349 default "11" 1350 help 1351 The kernel memory allocator divides physically contiguous memory 1352 blocks into "zones", where each zone is a power of two number of 1353 pages. This option selects the largest power of two that the kernel 1354 keeps in the memory allocator. If you need to allocate very large 1355 blocks of physically contiguous memory, then you may need to 1356 increase this value. 1357 1358 This config option is actually maximum order plus one. For example, 1359 a value of 11 means that the largest free memory block is 2^10 pages. 1360 1361config ALIGNMENT_TRAP 1362 def_bool CPU_CP15_MMU 1363 select HAVE_PROC_CPU if PROC_FS 1364 help 1365 ARM processors cannot fetch/store information which is not 1366 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1367 address divisible by 4. On 32-bit ARM processors, these non-aligned 1368 fetch/store instructions will be emulated in software if you say 1369 here, which has a severe performance impact. This is necessary for 1370 correct operation of some network protocols. With an IP-only 1371 configuration it is safe to say N, otherwise say Y. 1372 1373config UACCESS_WITH_MEMCPY 1374 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1375 depends on MMU 1376 default y if CPU_FEROCEON 1377 help 1378 Implement faster copy_to_user and clear_user methods for CPU 1379 cores where a 8-word STM instruction give significantly higher 1380 memory write throughput than a sequence of individual 32bit stores. 1381 1382 A possible side effect is a slight increase in scheduling latency 1383 between threads sharing the same address space if they invoke 1384 such copy operations with large buffers. 1385 1386 However, if the CPU data cache is using a write-allocate mode, 1387 this option is unlikely to provide any performance gain. 1388 1389config PARAVIRT 1390 bool "Enable paravirtualization code" 1391 help 1392 This changes the kernel so it can modify itself when it is run 1393 under a hypervisor, potentially improving performance significantly 1394 over full virtualization. 1395 1396config PARAVIRT_TIME_ACCOUNTING 1397 bool "Paravirtual steal time accounting" 1398 select PARAVIRT 1399 help 1400 Select this option to enable fine granularity task steal time 1401 accounting. Time spent executing other tasks in parallel with 1402 the current vCPU is discounted from the vCPU power. To account for 1403 that, there can be a small performance impact. 1404 1405 If in doubt, say N here. 1406 1407config XEN_DOM0 1408 def_bool y 1409 depends on XEN 1410 1411config XEN 1412 bool "Xen guest support on ARM" 1413 depends on ARM && AEABI && OF 1414 depends on CPU_V7 && !CPU_V6 1415 depends on !GENERIC_ATOMIC64 1416 depends on MMU 1417 select ARCH_DMA_ADDR_T_64BIT 1418 select ARM_PSCI 1419 select SWIOTLB 1420 select SWIOTLB_XEN 1421 select PARAVIRT 1422 help 1423 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1424 1425config CC_HAVE_STACKPROTECTOR_TLS 1426 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1427 1428config STACKPROTECTOR_PER_TASK 1429 bool "Use a unique stack canary value for each task" 1430 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1431 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1432 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1433 default y 1434 help 1435 Due to the fact that GCC uses an ordinary symbol reference from 1436 which to load the value of the stack canary, this value can only 1437 change at reboot time on SMP systems, and all tasks running in the 1438 kernel's address space are forced to use the same canary value for 1439 the entire duration that the system is up. 1440 1441 Enable this option to switch to a different method that uses a 1442 different canary value for each task. 1443 1444endmenu 1445 1446menu "Boot options" 1447 1448config USE_OF 1449 bool "Flattened Device Tree support" 1450 select IRQ_DOMAIN 1451 select OF 1452 help 1453 Include support for flattened device tree machine descriptions. 1454 1455config ATAGS 1456 bool "Support for the traditional ATAGS boot data passing" 1457 default y 1458 help 1459 This is the traditional way of passing data to the kernel at boot 1460 time. If you are solely relying on the flattened device tree (or 1461 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1462 to remove ATAGS support from your kernel binary. 1463 1464config UNUSED_BOARD_FILES 1465 bool "Board support for machines without known users" 1466 depends on ATAGS 1467 help 1468 Most ATAGS based board files are completely unused and are 1469 scheduled for removal in early 2023, and left out of kernels 1470 by default now. If you are using a board file that is marked 1471 as unused, turn on this option to build support into the kernel. 1472 1473 To keep support for your individual board from being removed, 1474 send a reply to the email discussion at 1475 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1476 1477config DEPRECATED_PARAM_STRUCT 1478 bool "Provide old way to pass kernel parameters" 1479 depends on ATAGS 1480 help 1481 This was deprecated in 2001 and announced to live on for 5 years. 1482 Some old boot loaders still use this way. 1483 1484# Compressed boot loader in ROM. Yes, we really want to ask about 1485# TEXT and BSS so we preserve their values in the config files. 1486config ZBOOT_ROM_TEXT 1487 hex "Compressed ROM boot loader base address" 1488 default 0x0 1489 help 1490 The physical address at which the ROM-able zImage is to be 1491 placed in the target. Platforms which normally make use of 1492 ROM-able zImage formats normally set this to a suitable 1493 value in their defconfig file. 1494 1495 If ZBOOT_ROM is not enabled, this has no effect. 1496 1497config ZBOOT_ROM_BSS 1498 hex "Compressed ROM boot loader BSS address" 1499 default 0x0 1500 help 1501 The base address of an area of read/write memory in the target 1502 for the ROM-able zImage which must be available while the 1503 decompressor is running. It must be large enough to hold the 1504 entire decompressed kernel plus an additional 128 KiB. 1505 Platforms which normally make use of ROM-able zImage formats 1506 normally set this to a suitable value in their defconfig file. 1507 1508 If ZBOOT_ROM is not enabled, this has no effect. 1509 1510config ZBOOT_ROM 1511 bool "Compressed boot loader in ROM/flash" 1512 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1513 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1514 help 1515 Say Y here if you intend to execute your compressed kernel image 1516 (zImage) directly from ROM or flash. If unsure, say N. 1517 1518config ARM_APPENDED_DTB 1519 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1520 depends on OF 1521 help 1522 With this option, the boot code will look for a device tree binary 1523 (DTB) appended to zImage 1524 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1525 1526 This is meant as a backward compatibility convenience for those 1527 systems with a bootloader that can't be upgraded to accommodate 1528 the documented boot protocol using a device tree. 1529 1530 Beware that there is very little in terms of protection against 1531 this option being confused by leftover garbage in memory that might 1532 look like a DTB header after a reboot if no actual DTB is appended 1533 to zImage. Do not leave this option active in a production kernel 1534 if you don't intend to always append a DTB. Proper passing of the 1535 location into r2 of a bootloader provided DTB is always preferable 1536 to this option. 1537 1538config ARM_ATAG_DTB_COMPAT 1539 bool "Supplement the appended DTB with traditional ATAG information" 1540 depends on ARM_APPENDED_DTB 1541 help 1542 Some old bootloaders can't be updated to a DTB capable one, yet 1543 they provide ATAGs with memory configuration, the ramdisk address, 1544 the kernel cmdline string, etc. Such information is dynamically 1545 provided by the bootloader and can't always be stored in a static 1546 DTB. To allow a device tree enabled kernel to be used with such 1547 bootloaders, this option allows zImage to extract the information 1548 from the ATAG list and store it at run time into the appended DTB. 1549 1550choice 1551 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1552 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1553 1554config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1555 bool "Use bootloader kernel arguments if available" 1556 help 1557 Uses the command-line options passed by the boot loader instead of 1558 the device tree bootargs property. If the boot loader doesn't provide 1559 any, the device tree bootargs property will be used. 1560 1561config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1562 bool "Extend with bootloader kernel arguments" 1563 help 1564 The command-line arguments provided by the boot loader will be 1565 appended to the the device tree bootargs property. 1566 1567endchoice 1568 1569config CMDLINE 1570 string "Default kernel command string" 1571 default "" 1572 help 1573 On some architectures (e.g. CATS), there is currently no way 1574 for the boot loader to pass arguments to the kernel. For these 1575 architectures, you should supply some command-line options at build 1576 time by entering them here. As a minimum, you should specify the 1577 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1578 1579choice 1580 prompt "Kernel command line type" if CMDLINE != "" 1581 default CMDLINE_FROM_BOOTLOADER 1582 1583config CMDLINE_FROM_BOOTLOADER 1584 bool "Use bootloader kernel arguments if available" 1585 help 1586 Uses the command-line options passed by the boot loader. If 1587 the boot loader doesn't provide any, the default kernel command 1588 string provided in CMDLINE will be used. 1589 1590config CMDLINE_EXTEND 1591 bool "Extend bootloader kernel arguments" 1592 help 1593 The command-line arguments provided by the boot loader will be 1594 appended to the default kernel command string. 1595 1596config CMDLINE_FORCE 1597 bool "Always use the default kernel command string" 1598 help 1599 Always use the default kernel command string, even if the boot 1600 loader passes other arguments to the kernel. 1601 This is useful if you cannot or don't want to change the 1602 command-line options your boot loader passes to the kernel. 1603endchoice 1604 1605config XIP_KERNEL 1606 bool "Kernel Execute-In-Place from ROM" 1607 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1608 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1609 help 1610 Execute-In-Place allows the kernel to run from non-volatile storage 1611 directly addressable by the CPU, such as NOR flash. This saves RAM 1612 space since the text section of the kernel is not loaded from flash 1613 to RAM. Read-write sections, such as the data section and stack, 1614 are still copied to RAM. The XIP kernel is not compressed since 1615 it has to run directly from flash, so it will take more space to 1616 store it. The flash address used to link the kernel object files, 1617 and for storing it, is configuration dependent. Therefore, if you 1618 say Y here, you must know the proper physical address where to 1619 store the kernel image depending on your own flash memory usage. 1620 1621 Also note that the make target becomes "make xipImage" rather than 1622 "make zImage" or "make Image". The final kernel binary to put in 1623 ROM memory will be arch/arm/boot/xipImage. 1624 1625 If unsure, say N. 1626 1627config XIP_PHYS_ADDR 1628 hex "XIP Kernel Physical Location" 1629 depends on XIP_KERNEL 1630 default "0x00080000" 1631 help 1632 This is the physical address in your flash memory the kernel will 1633 be linked for and stored to. This address is dependent on your 1634 own flash usage. 1635 1636config XIP_DEFLATED_DATA 1637 bool "Store kernel .data section compressed in ROM" 1638 depends on XIP_KERNEL 1639 select ZLIB_INFLATE 1640 help 1641 Before the kernel is actually executed, its .data section has to be 1642 copied to RAM from ROM. This option allows for storing that data 1643 in compressed form and decompressed to RAM rather than merely being 1644 copied, saving some precious ROM space. A possible drawback is a 1645 slightly longer boot delay. 1646 1647config KEXEC 1648 bool "Kexec system call (EXPERIMENTAL)" 1649 depends on (!SMP || PM_SLEEP_SMP) 1650 depends on MMU 1651 select KEXEC_CORE 1652 help 1653 kexec is a system call that implements the ability to shutdown your 1654 current kernel, and to start another kernel. It is like a reboot 1655 but it is independent of the system firmware. And like a reboot 1656 you can start any kernel with it, not just Linux. 1657 1658 It is an ongoing process to be certain the hardware in a machine 1659 is properly shutdown, so do not be surprised if this code does not 1660 initially work for you. 1661 1662config ATAGS_PROC 1663 bool "Export atags in procfs" 1664 depends on ATAGS && KEXEC 1665 default y 1666 help 1667 Should the atags used to boot the kernel be exported in an "atags" 1668 file in procfs. Useful with kexec. 1669 1670config CRASH_DUMP 1671 bool "Build kdump crash kernel (EXPERIMENTAL)" 1672 help 1673 Generate crash dump after being started by kexec. This should 1674 be normally only set in special crash dump kernels which are 1675 loaded in the main kernel with kexec-tools into a specially 1676 reserved region and then later executed after a crash by 1677 kdump/kexec. The crash dump kernel must be compiled to a 1678 memory address not used by the main kernel 1679 1680 For more details see Documentation/admin-guide/kdump/kdump.rst 1681 1682config AUTO_ZRELADDR 1683 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1684 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1685 help 1686 ZRELADDR is the physical address where the decompressed kernel 1687 image will be placed. If AUTO_ZRELADDR is selected, the address 1688 will be determined at run-time, either by masking the current IP 1689 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1690 This assumes the zImage being placed in the first 128MB from 1691 start of memory. 1692 1693config EFI_STUB 1694 bool 1695 1696config EFI 1697 bool "UEFI runtime support" 1698 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1699 select UCS2_STRING 1700 select EFI_PARAMS_FROM_FDT 1701 select EFI_STUB 1702 select EFI_GENERIC_STUB 1703 select EFI_RUNTIME_WRAPPERS 1704 help 1705 This option provides support for runtime services provided 1706 by UEFI firmware (such as non-volatile variables, realtime 1707 clock, and platform reset). A UEFI stub is also provided to 1708 allow the kernel to be booted as an EFI application. This 1709 is only useful for kernels that may run on systems that have 1710 UEFI firmware. 1711 1712config DMI 1713 bool "Enable support for SMBIOS (DMI) tables" 1714 depends on EFI 1715 default y 1716 help 1717 This enables SMBIOS/DMI feature for systems. 1718 1719 This option is only useful on systems that have UEFI firmware. 1720 However, even with this option, the resultant kernel should 1721 continue to boot on existing non-UEFI platforms. 1722 1723 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1724 i.e., the the practice of identifying the platform via DMI to 1725 decide whether certain workarounds for buggy hardware and/or 1726 firmware need to be enabled. This would require the DMI subsystem 1727 to be enabled much earlier than we do on ARM, which is non-trivial. 1728 1729endmenu 1730 1731menu "CPU Power Management" 1732 1733source "drivers/cpufreq/Kconfig" 1734 1735source "drivers/cpuidle/Kconfig" 1736 1737endmenu 1738 1739menu "Floating point emulation" 1740 1741comment "At least one emulation must be selected" 1742 1743config FPE_NWFPE 1744 bool "NWFPE math emulation" 1745 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1746 help 1747 Say Y to include the NWFPE floating point emulator in the kernel. 1748 This is necessary to run most binaries. Linux does not currently 1749 support floating point hardware so you need to say Y here even if 1750 your machine has an FPA or floating point co-processor podule. 1751 1752 You may say N here if you are going to load the Acorn FPEmulator 1753 early in the bootup. 1754 1755config FPE_NWFPE_XP 1756 bool "Support extended precision" 1757 depends on FPE_NWFPE 1758 help 1759 Say Y to include 80-bit support in the kernel floating-point 1760 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1761 Note that gcc does not generate 80-bit operations by default, 1762 so in most cases this option only enlarges the size of the 1763 floating point emulator without any good reason. 1764 1765 You almost surely want to say N here. 1766 1767config FPE_FASTFPE 1768 bool "FastFPE math emulation (EXPERIMENTAL)" 1769 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1770 help 1771 Say Y here to include the FAST floating point emulator in the kernel. 1772 This is an experimental much faster emulator which now also has full 1773 precision for the mantissa. It does not support any exceptions. 1774 It is very simple, and approximately 3-6 times faster than NWFPE. 1775 1776 It should be sufficient for most programs. It may be not suitable 1777 for scientific calculations, but you have to check this for yourself. 1778 If you do not feel you need a faster FP emulation you should better 1779 choose NWFPE. 1780 1781config VFP 1782 bool "VFP-format floating point maths" 1783 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1784 help 1785 Say Y to include VFP support code in the kernel. This is needed 1786 if your hardware includes a VFP unit. 1787 1788 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1789 release notes and additional status information. 1790 1791 Say N if your target does not have VFP hardware. 1792 1793config VFPv3 1794 bool 1795 depends on VFP 1796 default y if CPU_V7 1797 1798config NEON 1799 bool "Advanced SIMD (NEON) Extension support" 1800 depends on VFPv3 && CPU_V7 1801 help 1802 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1803 Extension. 1804 1805config KERNEL_MODE_NEON 1806 bool "Support for NEON in kernel mode" 1807 depends on NEON && AEABI 1808 help 1809 Say Y to include support for NEON in kernel mode. 1810 1811endmenu 1812 1813menu "Power management options" 1814 1815source "kernel/power/Kconfig" 1816 1817config ARCH_SUSPEND_POSSIBLE 1818 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1819 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1820 def_bool y 1821 1822config ARM_CPU_SUSPEND 1823 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1824 depends on ARCH_SUSPEND_POSSIBLE 1825 1826config ARCH_HIBERNATION_POSSIBLE 1827 bool 1828 depends on MMU 1829 default y if ARCH_SUSPEND_POSSIBLE 1830 1831endmenu 1832 1833source "arch/arm/Kconfig.assembler" 1834