1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CC_CAN_LINK 10 select ARCH_HAS_CPU_CACHE_ALIASING 11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_HAS_DEBUG_VIRTUAL if MMU 14 select ARCH_HAS_DMA_ALLOC if MMU 15 select ARCH_HAS_DMA_OPS 16 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 17 select ARCH_HAS_ELF_RANDOMIZE 18 select ARCH_HAS_FORTIFY_SOURCE 19 select ARCH_HAS_KEEPINITRD 20 select ARCH_HAS_KCOV 21 select ARCH_HAS_MEMBARRIER_SYNC_CORE 22 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 23 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 24 select ARCH_HAS_SETUP_DMA_OPS 25 select ARCH_HAS_SET_MEMORY 26 select ARCH_STACKWALK 27 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 28 select ARCH_HAS_STRICT_MODULE_RWX if MMU 29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 30 select ARCH_HAS_SYNC_DMA_FOR_CPU 31 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 33 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_KEEP_MEMBLOCK 36 select ARCH_HAS_UBSAN 37 select ARCH_MIGHT_HAVE_PC_PARPORT 38 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 39 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 40 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 41 select ARCH_SUPPORTS_ATOMIC_RMW 42 select ARCH_SUPPORTS_CFI 43 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 44 select ARCH_SUPPORTS_PER_VMA_LOCK 45 select ARCH_USE_BUILTIN_BSWAP 46 select ARCH_USE_CMPXCHG_LOCKREF 47 select ARCH_USE_MEMTEST 48 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 49 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 50 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 51 select ARCH_WANT_GENERAL_HUGETLB 52 select ARCH_WANT_IPC_PARSE_VERSION 53 select ARCH_WANT_LD_ORPHAN_WARN 54 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 55 select BUILDTIME_TABLE_SORT if MMU 56 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 57 select CLONE_BACKWARDS 58 select CPU_PM if SUSPEND || CPU_IDLE 59 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 60 select DMA_DECLARE_COHERENT 61 select DMA_GLOBAL_POOL if !MMU 62 select DMA_NONCOHERENT_MMAP if MMU 63 select EDAC_SUPPORT 64 select EDAC_ATOMIC_SCRUB 65 select GENERIC_ALLOCATOR 66 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 67 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 68 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 69 select GENERIC_IRQ_IPI if SMP 70 select GENERIC_CPU_AUTOPROBE 71 select GENERIC_CPU_DEVICES 72 select GENERIC_EARLY_IOREMAP 73 select GENERIC_IDLE_POLL_SETUP 74 select GENERIC_IRQ_MULTI_HANDLER 75 select GENERIC_IRQ_PROBE 76 select GENERIC_IRQ_SHOW 77 select GENERIC_IRQ_SHOW_LEVEL 78 select GENERIC_LIB_DEVMEM_IS_ALLOWED 79 select GENERIC_PCI_IOMAP 80 select GENERIC_SCHED_CLOCK 81 select GENERIC_SMP_IDLE_THREAD 82 select HARDIRQS_SW_RESEND 83 select HAS_IOPORT 84 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 85 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 86 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP) 87 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 88 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 89 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 90 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 91 select HAVE_ARCH_KSTACK_ERASE 92 select HAVE_ARCH_MMAP_RND_BITS if MMU 93 select HAVE_ARCH_PFN_VALID 94 select HAVE_ARCH_SECCOMP 95 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 96 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 97 select HAVE_ARCH_TRACEHOOK 98 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 99 select HAVE_ARM_SMCCC if CPU_V7 100 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 101 select HAVE_CONTEXT_TRACKING_USER 102 select HAVE_C_RECORDMCOUNT 103 select HAVE_BUILDTIME_MCOUNT_SORT 104 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 105 select HAVE_DMA_CONTIGUOUS if MMU 106 select HAVE_EXTRA_IPI_TRACEPOINTS 107 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 108 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 109 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 110 select HAVE_EXIT_THREAD 111 select HAVE_GUP_FAST if ARM_LPAE 112 select HAVE_FUNCTION_ERROR_INJECTION 113 select HAVE_FUNCTION_GRAPH_TRACER 114 select HAVE_FUNCTION_GRAPH_FREGS 115 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 116 select HAVE_GCC_PLUGINS 117 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 118 select HAVE_IRQ_TIME_ACCOUNTING 119 select HAVE_KERNEL_GZIP 120 select HAVE_KERNEL_LZ4 121 select HAVE_KERNEL_LZMA 122 select HAVE_KERNEL_LZO 123 select HAVE_KERNEL_XZ 124 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 125 select HAVE_KRETPROBES if HAVE_KPROBES 126 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 127 select HAVE_MOD_ARCH_SPECIFIC 128 select HAVE_NMI 129 select HAVE_OPTPROBES if !THUMB2_KERNEL 130 select HAVE_PAGE_SIZE_4KB 131 select HAVE_PCI if MMU 132 select HAVE_PERF_EVENTS 133 select HAVE_PERF_REGS 134 select HAVE_PERF_USER_STACK_DUMP 135 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 136 select HAVE_REGS_AND_STACK_ACCESS_API 137 select HAVE_RSEQ 138 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 139 select HAVE_STACKPROTECTOR 140 select HAVE_SYSCALL_TRACEPOINTS 141 select HAVE_UID16 142 select HAVE_VIRT_CPU_ACCOUNTING_GEN 143 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 144 select IRQ_FORCED_THREADING 145 select LOCK_MM_AND_FIND_VMA 146 select MODULES_USE_ELF_REL 147 select NEED_DMA_MAP_STATE 148 select OF_EARLY_FLATTREE if OF 149 select OLD_SIGACTION 150 select OLD_SIGSUSPEND3 151 select PCI_DOMAINS_GENERIC if PCI 152 select PCI_SYSCALL if PCI 153 select PERF_USE_VMALLOC 154 select RTC_LIB 155 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 156 select SYS_SUPPORTS_APM_EMULATION 157 select THREAD_INFO_IN_TASK 158 select TIMER_OF if OF 159 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 160 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 161 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 162 # Above selects are sorted alphabetically; please add new ones 163 # according to that. Thanks. 164 help 165 The ARM series is a line of low-power-consumption RISC chip designs 166 licensed by ARM Ltd and targeted at embedded applications and 167 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 168 manufactured, but legacy ARM-based PC hardware remains popular in 169 Europe. There is an ARM Linux project with a web page at 170 <http://www.arm.linux.org.uk/>. 171 172config ARM_HAS_GROUP_RELOCS 173 def_bool !COMPILE_TEST 174 help 175 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 176 relocations. The combined range is -/+ 256 MiB, which is usually 177 sufficient, but not for allyesconfig, so we disable this feature 178 when doing compile testing. 179 180config ARM_DMA_USE_IOMMU 181 bool 182 select NEED_SG_DMA_LENGTH 183 184if ARM_DMA_USE_IOMMU 185 186config ARM_DMA_IOMMU_ALIGNMENT 187 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 188 range 4 9 189 default 8 190 help 191 DMA mapping framework by default aligns all buffers to the smallest 192 PAGE_SIZE order which is greater than or equal to the requested buffer 193 size. This works well for buffers up to a few hundreds kilobytes, but 194 for larger buffers it just a waste of address space. Drivers which has 195 relatively small addressing window (like 64Mib) might run out of 196 virtual space with just a few allocations. 197 198 With this parameter you can specify the maximum PAGE_SIZE order for 199 DMA IOMMU buffers. Larger buffers will be aligned only to this 200 specified order. The order is expressed as a power of two multiplied 201 by the PAGE_SIZE. 202 203endif 204 205config SYS_SUPPORTS_APM_EMULATION 206 bool 207 208config HAVE_TCM 209 bool 210 select GENERIC_ALLOCATOR 211 212config HAVE_PROC_CPU 213 bool 214 215config NO_IOPORT_MAP 216 bool 217 218config SBUS 219 bool 220 221config STACKTRACE_SUPPORT 222 bool 223 default y 224 225config LOCKDEP_SUPPORT 226 bool 227 default y 228 229config ARCH_HAS_ILOG2_U32 230 bool 231 232config ARCH_HAS_ILOG2_U64 233 bool 234 235config ARCH_HAS_BANDGAP 236 bool 237 238config FIX_EARLYCON_MEM 239 def_bool y if MMU 240 241config GENERIC_HWEIGHT 242 bool 243 default y 244 245config GENERIC_CALIBRATE_DELAY 246 bool 247 default y 248 249config ARCH_MAY_HAVE_PC_FDC 250 bool 251 252config ARCH_SUPPORTS_UPROBES 253 def_bool y 254 255config GENERIC_ISA_DMA 256 bool 257 258config FIQ 259 bool 260 261config ARCH_MTD_XIP 262 bool 263 264config ARM_PATCH_PHYS_VIRT 265 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 266 default y 267 depends on MMU 268 help 269 Patch phys-to-virt and virt-to-phys translation functions at 270 boot and module load time according to the position of the 271 kernel in system memory. 272 273 This can only be used with non-XIP MMU kernels where the base 274 of physical memory is at a 2 MiB boundary. 275 276 Only disable this option if you know that you do not require 277 this feature (eg, building a kernel for a single machine) and 278 you need to shrink the kernel to the minimal size. 279 280config NEED_MACH_IO_H 281 bool 282 help 283 Select this when mach/io.h is required to provide special 284 definitions for this platform. The need for mach/io.h should 285 be avoided when possible. 286 287config NEED_MACH_MEMORY_H 288 bool 289 help 290 Select this when mach/memory.h is required to provide special 291 definitions for this platform. The need for mach/memory.h should 292 be avoided when possible. 293 294config PHYS_OFFSET 295 hex "Physical address of main memory" if MMU 296 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 297 default DRAM_BASE if !MMU 298 default 0x00000000 if ARCH_FOOTBRIDGE 299 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 300 default 0xa0000000 if ARCH_PXA 301 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 302 default 0 303 help 304 Please provide the physical address corresponding to the 305 location of main memory in your system. 306 307config GENERIC_BUG 308 def_bool y 309 depends on BUG 310 311config PGTABLE_LEVELS 312 int 313 default 3 if ARM_LPAE 314 default 2 315 316menu "System Type" 317 318config MMU 319 bool "MMU-based Paged Memory Management Support" 320 default y 321 help 322 Select if you want MMU-based virtualised addressing space 323 support by paged memory management. If unsure, say 'Y'. 324 325config ARM_SINGLE_ARMV7M 326 def_bool !MMU 327 select ARM_NVIC 328 select CPU_V7M 329 select NO_IOPORT_MAP 330 331config ARCH_MMAP_RND_BITS_MIN 332 default 8 333 334config ARCH_MMAP_RND_BITS_MAX 335 default 14 if PAGE_OFFSET=0x40000000 336 default 15 if PAGE_OFFSET=0x80000000 337 default 16 338 339config ARCH_MULTIPLATFORM 340 bool "Require kernel to be portable to multiple machines" if EXPERT 341 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 342 default y 343 help 344 In general, all Arm machines can be supported in a single 345 kernel image, covering either Armv4/v5 or Armv6/v7. 346 347 However, some configuration options require hardcoding machine 348 specific physical addresses or enable errata workarounds that may 349 break other machines. 350 351 Selecting N here allows using those options, including 352 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 353 354source "arch/arm/Kconfig.platforms" 355 356# 357# This is sorted alphabetically by mach-* pathname. However, plat-* 358# Kconfigs may be included either alphabetically (according to the 359# plat- suffix) or along side the corresponding mach-* source. 360# 361source "arch/arm/mach-actions/Kconfig" 362 363source "arch/arm/mach-alpine/Kconfig" 364 365source "arch/arm/mach-artpec/Kconfig" 366 367source "arch/arm/mach-aspeed/Kconfig" 368 369source "arch/arm/mach-at91/Kconfig" 370 371source "arch/arm/mach-axxia/Kconfig" 372 373source "arch/arm/mach-bcm/Kconfig" 374 375source "arch/arm/mach-berlin/Kconfig" 376 377source "arch/arm/mach-clps711x/Kconfig" 378 379source "arch/arm/mach-davinci/Kconfig" 380 381source "arch/arm/mach-digicolor/Kconfig" 382 383source "arch/arm/mach-dove/Kconfig" 384 385source "arch/arm/mach-ep93xx/Kconfig" 386 387source "arch/arm/mach-exynos/Kconfig" 388 389source "arch/arm/mach-footbridge/Kconfig" 390 391source "arch/arm/mach-gemini/Kconfig" 392 393source "arch/arm/mach-highbank/Kconfig" 394 395source "arch/arm/mach-hisi/Kconfig" 396 397source "arch/arm/mach-imx/Kconfig" 398 399source "arch/arm/mach-ixp4xx/Kconfig" 400 401source "arch/arm/mach-keystone/Kconfig" 402 403source "arch/arm/mach-lpc32xx/Kconfig" 404 405source "arch/arm/mach-mediatek/Kconfig" 406 407source "arch/arm/mach-meson/Kconfig" 408 409source "arch/arm/mach-milbeaut/Kconfig" 410 411source "arch/arm/mach-mmp/Kconfig" 412 413source "arch/arm/mach-mstar/Kconfig" 414 415source "arch/arm/mach-mv78xx0/Kconfig" 416 417source "arch/arm/mach-mvebu/Kconfig" 418 419source "arch/arm/mach-mxs/Kconfig" 420 421source "arch/arm/mach-nomadik/Kconfig" 422 423source "arch/arm/mach-npcm/Kconfig" 424 425source "arch/arm/mach-omap1/Kconfig" 426 427source "arch/arm/mach-omap2/Kconfig" 428 429source "arch/arm/mach-orion5x/Kconfig" 430 431source "arch/arm/mach-pxa/Kconfig" 432 433source "arch/arm/mach-qcom/Kconfig" 434 435source "arch/arm/mach-realtek/Kconfig" 436 437source "arch/arm/mach-rpc/Kconfig" 438 439source "arch/arm/mach-rockchip/Kconfig" 440 441source "arch/arm/mach-s3c/Kconfig" 442 443source "arch/arm/mach-s5pv210/Kconfig" 444 445source "arch/arm/mach-sa1100/Kconfig" 446 447source "arch/arm/mach-shmobile/Kconfig" 448 449source "arch/arm/mach-socfpga/Kconfig" 450 451source "arch/arm/mach-spear/Kconfig" 452 453source "arch/arm/mach-sti/Kconfig" 454 455source "arch/arm/mach-stm32/Kconfig" 456 457source "arch/arm/mach-sunxi/Kconfig" 458 459source "arch/arm/mach-tegra/Kconfig" 460 461source "arch/arm/mach-ux500/Kconfig" 462 463source "arch/arm/mach-versatile/Kconfig" 464 465source "arch/arm/mach-vt8500/Kconfig" 466 467source "arch/arm/mach-zynq/Kconfig" 468 469# ARMv7-M architecture 470config ARCH_LPC18XX 471 bool "NXP LPC18xx/LPC43xx" 472 depends on ARM_SINGLE_ARMV7M 473 select ARCH_HAS_RESET_CONTROLLER 474 select ARM_AMBA 475 select CLKSRC_LPC32XX 476 select PINCTRL 477 help 478 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 479 high performance microcontrollers. 480 481config ARCH_MPS2 482 bool "ARM MPS2 platform" 483 depends on ARM_SINGLE_ARMV7M 484 select ARM_AMBA 485 select CLKSRC_MPS2 486 help 487 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 488 with a range of available cores like Cortex-M3/M4/M7. 489 490 Please, note that depends which Application Note is used memory map 491 for the platform may vary, so adjustment of RAM base might be needed. 492 493# Definitions to make life easier 494config ARCH_ACORN 495 bool 496 497config PLAT_ORION 498 bool 499 select CLKSRC_MMIO 500 select GENERIC_IRQ_CHIP 501 select IRQ_DOMAIN 502 503config PLAT_ORION_LEGACY 504 bool 505 select PLAT_ORION 506 507config PLAT_VERSATILE 508 bool 509 510source "arch/arm/mm/Kconfig" 511 512config IWMMXT 513 bool "Enable iWMMXt support" 514 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 515 default y if PXA27x || PXA3xx || ARCH_MMP 516 help 517 Enable support for iWMMXt context switching at run time if 518 running on a CPU that supports it. 519 520if !MMU 521source "arch/arm/Kconfig-nommu" 522endif 523 524config PJ4B_ERRATA_4742 525 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 526 depends on CPU_PJ4B && MACH_ARMADA_370 527 default y 528 help 529 When coming out of either a Wait for Interrupt (WFI) or a Wait for 530 Event (WFE) IDLE states, a specific timing sensitivity exists between 531 the retiring WFI/WFE instructions and the newly issued subsequent 532 instructions. This sensitivity can result in a CPU hang scenario. 533 Workaround: 534 The software must insert either a Data Synchronization Barrier (DSB) 535 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 536 instruction 537 538config ARM_ERRATA_326103 539 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 540 depends on CPU_V6 541 help 542 Executing a SWP instruction to read-only memory does not set bit 11 543 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 544 treat the access as a read, preventing a COW from occurring and 545 causing the faulting task to livelock. 546 547config ARM_ERRATA_411920 548 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 549 depends on CPU_V6 || CPU_V6K 550 help 551 Invalidation of the Instruction Cache operation can 552 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 553 It does not affect the MPCore. This option enables the ARM Ltd. 554 recommended workaround. 555 556config ARM_ERRATA_430973 557 bool "ARM errata: Stale prediction on replaced interworking branch" 558 depends on CPU_V7 559 help 560 This option enables the workaround for the 430973 Cortex-A8 561 r1p* erratum. If a code sequence containing an ARM/Thumb 562 interworking branch is replaced with another code sequence at the 563 same virtual address, whether due to self-modifying code or virtual 564 to physical address re-mapping, Cortex-A8 does not recover from the 565 stale interworking branch prediction. This results in Cortex-A8 566 executing the new code sequence in the incorrect ARM or Thumb state. 567 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 568 and also flushes the branch target cache at every context switch. 569 Note that setting specific bits in the ACTLR register may not be 570 available in non-secure mode. 571 572config ARM_ERRATA_458693 573 bool "ARM errata: Processor deadlock when a false hazard is created" 574 depends on CPU_V7 575 depends on !ARCH_MULTIPLATFORM 576 help 577 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 578 erratum. For very specific sequences of memory operations, it is 579 possible for a hazard condition intended for a cache line to instead 580 be incorrectly associated with a different cache line. This false 581 hazard might then cause a processor deadlock. The workaround enables 582 the L1 caching of the NEON accesses and disables the PLD instruction 583 in the ACTLR register. Note that setting specific bits in the ACTLR 584 register may not be available in non-secure mode and thus is not 585 available on a multiplatform kernel. This should be applied by the 586 bootloader instead. 587 588config ARM_ERRATA_460075 589 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 590 depends on CPU_V7 591 depends on !ARCH_MULTIPLATFORM 592 help 593 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 594 erratum. Any asynchronous access to the L2 cache may encounter a 595 situation in which recent store transactions to the L2 cache are lost 596 and overwritten with stale memory contents from external memory. The 597 workaround disables the write-allocate mode for the L2 cache via the 598 ACTLR register. Note that setting specific bits in the ACTLR register 599 may not be available in non-secure mode and thus is not available on 600 a multiplatform kernel. This should be applied by the bootloader 601 instead. 602 603config ARM_ERRATA_742230 604 bool "ARM errata: DMB operation may be faulty" 605 depends on CPU_V7 && SMP 606 depends on !ARCH_MULTIPLATFORM 607 help 608 This option enables the workaround for the 742230 Cortex-A9 609 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 610 between two write operations may not ensure the correct visibility 611 ordering of the two writes. This workaround sets a specific bit in 612 the diagnostic register of the Cortex-A9 which causes the DMB 613 instruction to behave as a DSB, ensuring the correct behaviour of 614 the two writes. Note that setting specific bits in the diagnostics 615 register may not be available in non-secure mode and thus is not 616 available on a multiplatform kernel. This should be applied by the 617 bootloader instead. 618 619config ARM_ERRATA_742231 620 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 621 depends on CPU_V7 && SMP 622 depends on !ARCH_MULTIPLATFORM 623 help 624 This option enables the workaround for the 742231 Cortex-A9 625 (r2p0..r2p2) erratum. Under certain conditions, specific to the 626 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 627 accessing some data located in the same cache line, may get corrupted 628 data due to bad handling of the address hazard when the line gets 629 replaced from one of the CPUs at the same time as another CPU is 630 accessing it. This workaround sets specific bits in the diagnostic 631 register of the Cortex-A9 which reduces the linefill issuing 632 capabilities of the processor. Note that setting specific bits in the 633 diagnostics register may not be available in non-secure mode and thus 634 is not available on a multiplatform kernel. This should be applied by 635 the bootloader instead. 636 637config ARM_ERRATA_643719 638 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 639 depends on CPU_V7 && SMP 640 default y 641 help 642 This option enables the workaround for the 643719 Cortex-A9 (prior to 643 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 644 register returns zero when it should return one. The workaround 645 corrects this value, ensuring cache maintenance operations which use 646 it behave as intended and avoiding data corruption. 647 648config ARM_ERRATA_720789 649 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 650 depends on CPU_V7 651 help 652 This option enables the workaround for the 720789 Cortex-A9 (prior to 653 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 654 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 655 As a consequence of this erratum, some TLB entries which should be 656 invalidated are not, resulting in an incoherency in the system page 657 tables. The workaround changes the TLB flushing routines to invalidate 658 entries regardless of the ASID. 659 660config ARM_ERRATA_743622 661 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 662 depends on CPU_V7 663 depends on !ARCH_MULTIPLATFORM 664 help 665 This option enables the workaround for the 743622 Cortex-A9 666 (r2p*) erratum. Under very rare conditions, a faulty 667 optimisation in the Cortex-A9 Store Buffer may lead to data 668 corruption. This workaround sets a specific bit in the diagnostic 669 register of the Cortex-A9 which disables the Store Buffer 670 optimisation, preventing the defect from occurring. This has no 671 visible impact on the overall performance or power consumption of the 672 processor. Note that setting specific bits in the diagnostics register 673 may not be available in non-secure mode and thus is not available on a 674 multiplatform kernel. This should be applied by the bootloader instead. 675 676config ARM_ERRATA_751472 677 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 678 depends on CPU_V7 679 depends on !ARCH_MULTIPLATFORM 680 help 681 This option enables the workaround for the 751472 Cortex-A9 (prior 682 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 683 completion of a following broadcasted operation if the second 684 operation is received by a CPU before the ICIALLUIS has completed, 685 potentially leading to corrupted entries in the cache or TLB. 686 Note that setting specific bits in the diagnostics register may 687 not be available in non-secure mode and thus is not available on 688 a multiplatform kernel. This should be applied by the bootloader 689 instead. 690 691config ARM_ERRATA_754322 692 bool "ARM errata: possible faulty MMU translations following an ASID switch" 693 depends on CPU_V7 694 help 695 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 696 r3p*) erratum. A speculative memory access may cause a page table walk 697 which starts prior to an ASID switch but completes afterwards. This 698 can populate the micro-TLB with a stale entry which may be hit with 699 the new ASID. This workaround places two dsb instructions in the mm 700 switching code so that no page table walks can cross the ASID switch. 701 702config ARM_ERRATA_754327 703 bool "ARM errata: no automatic Store Buffer drain" 704 depends on CPU_V7 && SMP 705 help 706 This option enables the workaround for the 754327 Cortex-A9 (prior to 707 r2p0) erratum. The Store Buffer does not have any automatic draining 708 mechanism and therefore a livelock may occur if an external agent 709 continuously polls a memory location waiting to observe an update. 710 This workaround defines cpu_relax() as smp_mb(), preventing correctly 711 written polling loops from denying visibility of updates to memory. 712 713config ARM_ERRATA_364296 714 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 715 depends on CPU_V6 716 help 717 This options enables the workaround for the 364296 ARM1136 718 r0p2 erratum (possible cache data corruption with 719 hit-under-miss enabled). It sets the undocumented bit 31 in 720 the auxiliary control register and the FI bit in the control 721 register, thus disabling hit-under-miss without putting the 722 processor into full low interrupt latency mode. ARM11MPCore 723 is not affected. 724 725config ARM_ERRATA_764369 726 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 727 depends on CPU_V7 && SMP 728 help 729 This option enables the workaround for erratum 764369 730 affecting Cortex-A9 MPCore with two or more processors (all 731 current revisions). Under certain timing circumstances, a data 732 cache line maintenance operation by MVA targeting an Inner 733 Shareable memory region may fail to proceed up to either the 734 Point of Coherency or to the Point of Unification of the 735 system. This workaround adds a DSB instruction before the 736 relevant cache maintenance functions and sets a specific bit 737 in the diagnostic control register of the SCU. 738 739config ARM_ERRATA_764319 740 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 741 depends on CPU_V7 742 help 743 This option enables the workaround for the 764319 Cortex-A9 erratum. 744 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 745 unexpected Undefined Instruction exception when the DBGSWENABLE 746 external pin is set to 0, even when the CP14 accesses are performed 747 from a privileged mode. This work around catches the exception in a 748 way the kernel does not stop execution. 749 750config ARM_ERRATA_775420 751 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 752 depends on CPU_V7 753 help 754 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 755 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 756 operation aborts with MMU exception, it might cause the processor 757 to deadlock. This workaround puts DSB before executing ISB if 758 an abort may occur on cache maintenance. 759 760config ARM_ERRATA_798181 761 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 762 depends on CPU_V7 && SMP 763 help 764 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 765 adequately shooting down all use of the old entries. This 766 option enables the Linux kernel workaround for this erratum 767 which sends an IPI to the CPUs that are running the same ASID 768 as the one being invalidated. 769 770config ARM_ERRATA_773022 771 bool "ARM errata: incorrect instructions may be executed from loop buffer" 772 depends on CPU_V7 773 help 774 This option enables the workaround for the 773022 Cortex-A15 775 (up to r0p4) erratum. In certain rare sequences of code, the 776 loop buffer may deliver incorrect instructions. This 777 workaround disables the loop buffer to avoid the erratum. 778 779config ARM_ERRATA_818325_852422 780 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 781 depends on CPU_V7 782 help 783 This option enables the workaround for: 784 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 785 instruction might deadlock. Fixed in r0p1. 786 - Cortex-A12 852422: Execution of a sequence of instructions might 787 lead to either a data corruption or a CPU deadlock. Not fixed in 788 any Cortex-A12 cores yet. 789 This workaround for all both errata involves setting bit[12] of the 790 Feature Register. This bit disables an optimisation applied to a 791 sequence of 2 instructions that use opposing condition codes. 792 793config ARM_ERRATA_821420 794 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 795 depends on CPU_V7 796 help 797 This option enables the workaround for the 821420 Cortex-A12 798 (all revs) erratum. In very rare timing conditions, a sequence 799 of VMOV to Core registers instructions, for which the second 800 one is in the shadow of a branch or abort, can lead to a 801 deadlock when the VMOV instructions are issued out-of-order. 802 803config ARM_ERRATA_825619 804 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 805 depends on CPU_V7 806 help 807 This option enables the workaround for the 825619 Cortex-A12 808 (all revs) erratum. Within rare timing constraints, executing a 809 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 810 and Device/Strongly-Ordered loads and stores might cause deadlock 811 812config ARM_ERRATA_857271 813 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 814 depends on CPU_V7 815 help 816 This option enables the workaround for the 857271 Cortex-A12 817 (all revs) erratum. Under very rare timing conditions, the CPU might 818 hang. The workaround is expected to have a < 1% performance impact. 819 820config ARM_ERRATA_852421 821 bool "ARM errata: A17: DMB ST might fail to create order between stores" 822 depends on CPU_V7 823 help 824 This option enables the workaround for the 852421 Cortex-A17 825 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 826 execution of a DMB ST instruction might fail to properly order 827 stores from GroupA and stores from GroupB. 828 829config ARM_ERRATA_852423 830 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 831 depends on CPU_V7 832 help 833 This option enables the workaround for: 834 - Cortex-A17 852423: Execution of a sequence of instructions might 835 lead to either a data corruption or a CPU deadlock. Not fixed in 836 any Cortex-A17 cores yet. 837 This is identical to Cortex-A12 erratum 852422. It is a separate 838 config option from the A12 erratum due to the way errata are checked 839 for and handled. 840 841config ARM_ERRATA_857272 842 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 843 depends on CPU_V7 844 help 845 This option enables the workaround for the 857272 Cortex-A17 erratum. 846 This erratum is not known to be fixed in any A17 revision. 847 This is identical to Cortex-A12 erratum 857271. It is a separate 848 config option from the A12 erratum due to the way errata are checked 849 for and handled. 850 851endmenu 852 853source "arch/arm/common/Kconfig" 854 855menu "Bus support" 856 857config ISA 858 bool 859 help 860 Find out whether you have ISA slots on your motherboard. ISA is the 861 name of a bus system, i.e. the way the CPU talks to the other stuff 862 inside your box. Other bus systems are PCI, EISA, MicroChannel 863 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 864 newer boards don't support it. If you have ISA, say Y, otherwise N. 865 866# Select ISA DMA interface 867config ISA_DMA_API 868 bool 869 870config ARM_ERRATA_814220 871 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 872 depends on CPU_V7 873 help 874 The v7 ARM states that all cache and branch predictor maintenance 875 operations that do not specify an address execute, relative to 876 each other, in program order. 877 However, because of this erratum, an L2 set/way cache maintenance 878 operation can overtake an L1 set/way cache maintenance operation. 879 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 880 r0p4, r0p5. 881 882endmenu 883 884menu "Kernel Features" 885 886config HAVE_SMP 887 bool 888 help 889 This option should be selected by machines which have an SMP- 890 capable CPU. 891 892 The only effect of this option is to make the SMP-related 893 options available to the user for configuration. 894 895config SMP 896 bool "Symmetric Multi-Processing" 897 depends on CPU_V6K || CPU_V7 898 depends on HAVE_SMP 899 depends on MMU || ARM_MPU 900 select IRQ_WORK 901 help 902 This enables support for systems with more than one CPU. If you have 903 a system with only one CPU, say N. If you have a system with more 904 than one CPU, say Y. 905 906 If you say N here, the kernel will run on uni- and multiprocessor 907 machines, but will use only one CPU of a multiprocessor machine. If 908 you say Y here, the kernel will run on many, but not all, 909 uniprocessor machines. On a uniprocessor machine, the kernel 910 will run faster if you say N here. 911 912 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 913 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 914 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 915 916 If you don't know what to do here, say N. 917 918config SMP_ON_UP 919 bool "Allow booting SMP kernel on uniprocessor systems" 920 depends on SMP && MMU 921 default y 922 help 923 SMP kernels contain instructions which fail on non-SMP processors. 924 Enabling this option allows the kernel to modify itself to make 925 these instructions safe. Disabling it allows about 1K of space 926 savings. 927 928 If you don't know what to do here, say Y. 929 930 931config CURRENT_POINTER_IN_TPIDRURO 932 def_bool y 933 depends on CPU_32v6K && !CPU_V6 934 935config IRQSTACKS 936 def_bool y 937 select HAVE_IRQ_EXIT_ON_IRQ_STACK 938 select HAVE_SOFTIRQ_ON_OWN_STACK 939 940config ARM_CPU_TOPOLOGY 941 bool "Support cpu topology definition" 942 depends on SMP && CPU_V7 943 select ARCH_SUPPORTS_SCHED_MC 944 select ARCH_SUPPORTS_SCHED_SMT 945 default y 946 help 947 Support ARM cpu topology definition. The MPIDR register defines 948 affinity between processors which is then used to describe the cpu 949 topology of an ARM System. 950 951config HAVE_ARM_SCU 952 bool 953 help 954 This option enables support for the ARM snoop control unit 955 956config HAVE_ARM_ARCH_TIMER 957 bool "Architected timer support" 958 depends on CPU_V7 959 select ARM_ARCH_TIMER 960 help 961 This option enables support for the ARM architected timer 962 963config HAVE_ARM_TWD 964 bool 965 help 966 This options enables support for the ARM timer and watchdog unit 967 968config MCPM 969 bool "Multi-Cluster Power Management" 970 depends on CPU_V7 && SMP 971 help 972 This option provides the common power management infrastructure 973 for (multi-)cluster based systems, such as big.LITTLE based 974 systems. 975 976config MCPM_QUAD_CLUSTER 977 bool 978 depends on MCPM 979 help 980 To avoid wasting resources unnecessarily, MCPM only supports up 981 to 2 clusters by default. 982 Platforms with 3 or 4 clusters that use MCPM must select this 983 option to allow the additional clusters to be managed. 984 985config BIG_LITTLE 986 bool "big.LITTLE support (Experimental)" 987 depends on CPU_V7 && SMP 988 select MCPM 989 help 990 This option enables support selections for the big.LITTLE 991 system architecture. 992 993config BL_SWITCHER 994 bool "big.LITTLE switcher support" 995 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 996 select CPU_PM 997 help 998 The big.LITTLE "switcher" provides the core functionality to 999 transparently handle transition between a cluster of A15's 1000 and a cluster of A7's in a big.LITTLE system. 1001 1002config BL_SWITCHER_DUMMY_IF 1003 tristate "Simple big.LITTLE switcher user interface" 1004 depends on BL_SWITCHER && DEBUG_KERNEL 1005 help 1006 This is a simple and dummy char dev interface to control 1007 the big.LITTLE switcher core code. It is meant for 1008 debugging purposes only. 1009 1010choice 1011 prompt "Memory split" 1012 depends on MMU 1013 default VMSPLIT_3G 1014 help 1015 Select the desired split between kernel and user memory. 1016 1017 If you are not absolutely sure what you are doing, leave this 1018 option alone! 1019 1020 config VMSPLIT_3G 1021 bool "3G/1G user/kernel split" 1022 config VMSPLIT_3G_OPT 1023 depends on !ARM_LPAE 1024 bool "3G/1G user/kernel split (for full 1G low memory)" 1025 config VMSPLIT_2G 1026 bool "2G/2G user/kernel split" 1027 config VMSPLIT_1G 1028 bool "1G/3G user/kernel split" 1029endchoice 1030 1031config PAGE_OFFSET 1032 hex 1033 default PHYS_OFFSET if !MMU 1034 default 0x40000000 if VMSPLIT_1G 1035 default 0x80000000 if VMSPLIT_2G 1036 default 0xB0000000 if VMSPLIT_3G_OPT 1037 default 0xC0000000 1038 1039config KASAN_SHADOW_OFFSET 1040 hex 1041 depends on KASAN 1042 default 0x1f000000 if PAGE_OFFSET=0x40000000 1043 default 0x5f000000 if PAGE_OFFSET=0x80000000 1044 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1045 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1046 default 0xffffffff 1047 1048config NR_CPUS 1049 int "Maximum number of CPUs (2-32)" 1050 range 2 16 if DEBUG_KMAP_LOCAL 1051 range 2 32 if !DEBUG_KMAP_LOCAL 1052 depends on SMP 1053 default "4" 1054 help 1055 The maximum number of CPUs that the kernel can support. 1056 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1057 debugging is enabled, which uses half of the per-CPU fixmap 1058 slots as guard regions. 1059 1060config HOTPLUG_CPU 1061 bool "Support for hot-pluggable CPUs" 1062 depends on SMP 1063 select GENERIC_IRQ_MIGRATION 1064 help 1065 Say Y here to experiment with turning CPUs off and on. CPUs 1066 can be controlled through /sys/devices/system/cpu. 1067 1068config ARM_PSCI 1069 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1070 depends on HAVE_ARM_SMCCC 1071 select ARM_PSCI_FW 1072 help 1073 Say Y here if you want Linux to communicate with system firmware 1074 implementing the PSCI specification for CPU-centric power 1075 management operations described in ARM document number ARM DEN 1076 0022A ("Power State Coordination Interface System Software on 1077 ARM processors"). 1078 1079config HZ_FIXED 1080 int 1081 default 128 if SOC_AT91RM9200 1082 default 0 1083 1084choice 1085 depends on HZ_FIXED = 0 1086 prompt "Timer frequency" 1087 1088config HZ_100 1089 bool "100 Hz" 1090 1091config HZ_200 1092 bool "200 Hz" 1093 1094config HZ_250 1095 bool "250 Hz" 1096 1097config HZ_300 1098 bool "300 Hz" 1099 1100config HZ_500 1101 bool "500 Hz" 1102 1103config HZ_1000 1104 bool "1000 Hz" 1105 1106endchoice 1107 1108config HZ 1109 int 1110 default HZ_FIXED if HZ_FIXED != 0 1111 default 100 if HZ_100 1112 default 200 if HZ_200 1113 default 250 if HZ_250 1114 default 300 if HZ_300 1115 default 500 if HZ_500 1116 default 1000 1117 1118config SCHED_HRTICK 1119 def_bool HIGH_RES_TIMERS 1120 1121config THUMB2_KERNEL 1122 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1123 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1124 default y if CPU_THUMBONLY 1125 select ARM_UNWIND 1126 help 1127 By enabling this option, the kernel will be compiled in 1128 Thumb-2 mode. 1129 1130 If unsure, say N. 1131 1132config ARM_PATCH_IDIV 1133 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1134 depends on CPU_32v7 1135 default y 1136 help 1137 The ARM compiler inserts calls to __aeabi_idiv() and 1138 __aeabi_uidiv() when it needs to perform division on signed 1139 and unsigned integers. Some v7 CPUs have support for the sdiv 1140 and udiv instructions that can be used to implement those 1141 functions. 1142 1143 Enabling this option allows the kernel to modify itself to 1144 replace the first two instructions of these library functions 1145 with the sdiv or udiv plus "bx lr" instructions when the CPU 1146 it is running on supports them. Typically this will be faster 1147 and less power intensive than running the original library 1148 code to do integer division. 1149 1150config AEABI 1151 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1152 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1153 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1154 help 1155 This option allows for the kernel to be compiled using the latest 1156 ARM ABI (aka EABI). This is only useful if you are using a user 1157 space environment that is also compiled with EABI. 1158 1159 Since there are major incompatibilities between the legacy ABI and 1160 EABI, especially with regard to structure member alignment, this 1161 option also changes the kernel syscall calling convention to 1162 disambiguate both ABIs and allow for backward compatibility support 1163 (selected with CONFIG_OABI_COMPAT). 1164 1165config OABI_COMPAT 1166 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1167 depends on AEABI && !THUMB2_KERNEL 1168 help 1169 This option preserves the old syscall interface along with the 1170 new (ARM EABI) one. It also provides a compatibility layer to 1171 intercept syscalls that have structure arguments which layout 1172 in memory differs between the legacy ABI and the new ARM EABI 1173 (only for non "thumb" binaries). This option adds a tiny 1174 overhead to all syscalls and produces a slightly larger kernel. 1175 1176 The seccomp filter system will not be available when this is 1177 selected, since there is no way yet to sensibly distinguish 1178 between calling conventions during filtering. 1179 1180 If you know you'll be using only pure EABI user space then you 1181 can say N here. If this option is not selected and you attempt 1182 to execute a legacy ABI binary then the result will be 1183 UNPREDICTABLE (in fact it can be predicted that it won't work 1184 at all). If in doubt say N. 1185 1186config ARCH_SELECT_MEMORY_MODEL 1187 def_bool y 1188 1189config ARCH_FLATMEM_ENABLE 1190 def_bool !(ARCH_RPC || ARCH_SA1100) 1191 1192config ARCH_SPARSEMEM_ENABLE 1193 def_bool !ARCH_FOOTBRIDGE 1194 select SPARSEMEM_STATIC if SPARSEMEM 1195 1196config HIGHMEM 1197 bool "High Memory Support" 1198 depends on MMU 1199 select KMAP_LOCAL 1200 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1201 help 1202 The address space of ARM processors is only 4 Gigabytes large 1203 and it has to accommodate user address space, kernel address 1204 space as well as some memory mapped IO. That means that, if you 1205 have a large amount of physical memory and/or IO, not all of the 1206 memory can be "permanently mapped" by the kernel. The physical 1207 memory that is not permanently mapped is called "high memory". 1208 1209 Depending on the selected kernel/user memory split, minimum 1210 vmalloc space and actual amount of RAM, you may not need this 1211 option which should result in a slightly faster kernel. 1212 1213 If unsure, say n. 1214 1215config HIGHPTE 1216 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1217 depends on HIGHMEM && !PREEMPT_RT 1218 default y 1219 help 1220 The VM uses one page of physical memory for each page table. 1221 For systems with a lot of processes, this can use a lot of 1222 precious low memory, eventually leading to low memory being 1223 consumed by page tables. Setting this option will allow 1224 user-space 2nd level page tables to reside in high memory. 1225 1226config ARM_PAN 1227 bool "Enable privileged no-access" 1228 depends on MMU 1229 default y 1230 help 1231 Increase kernel security by ensuring that normal kernel accesses 1232 are unable to access userspace addresses. This can help prevent 1233 use-after-free bugs becoming an exploitable privilege escalation 1234 by ensuring that magic values (such as LIST_POISON) will always 1235 fault when dereferenced. 1236 1237 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1238 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1239 1240config CPU_SW_DOMAIN_PAN 1241 def_bool y 1242 depends on ARM_PAN && !ARM_LPAE 1243 help 1244 Enable use of CPU domains to implement privileged no-access. 1245 1246 CPUs with low-vector mappings use a best-efforts implementation. 1247 Their lower 1MB needs to remain accessible for the vectors, but 1248 the remainder of userspace will become appropriately inaccessible. 1249 1250config CPU_TTBR0_PAN 1251 def_bool y 1252 depends on ARM_PAN && ARM_LPAE 1253 help 1254 Enable privileged no-access by disabling TTBR0 page table walks when 1255 running in kernel mode. 1256 1257config HW_PERF_EVENTS 1258 def_bool y 1259 depends on ARM_PMU 1260 1261config ARM_MODULE_PLTS 1262 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1263 depends on MODULES 1264 select KASAN_VMALLOC if KASAN 1265 default y 1266 help 1267 Allocate PLTs when loading modules so that jumps and calls whose 1268 targets are too far away for their relative offsets to be encoded 1269 in the instructions themselves can be bounced via veneers in the 1270 module's PLT. This allows modules to be allocated in the generic 1271 vmalloc area after the dedicated module memory area has been 1272 exhausted. The modules will use slightly more memory, but after 1273 rounding up to page size, the actual memory footprint is usually 1274 the same. 1275 1276 Disabling this is usually safe for small single-platform 1277 configurations. If unsure, say y. 1278 1279config ARCH_FORCE_MAX_ORDER 1280 int "Order of maximal physically contiguous allocations" 1281 default "11" if SOC_AM33XX 1282 default "8" if SA1111 1283 default "10" 1284 help 1285 The kernel page allocator limits the size of maximal physically 1286 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1287 defines the maximal power of two of number of pages that can be 1288 allocated as a single contiguous block. This option allows 1289 overriding the default setting when ability to allocate very 1290 large blocks of physically contiguous memory is required. 1291 1292 Don't change if unsure. 1293 1294config ALIGNMENT_TRAP 1295 def_bool CPU_CP15_MMU 1296 select HAVE_PROC_CPU if PROC_FS 1297 help 1298 ARM processors cannot fetch/store information which is not 1299 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1300 address divisible by 4. On 32-bit ARM processors, these non-aligned 1301 fetch/store instructions will be emulated in software if you say 1302 here, which has a severe performance impact. This is necessary for 1303 correct operation of some network protocols. With an IP-only 1304 configuration it is safe to say N, otherwise say Y. 1305 1306config UACCESS_WITH_MEMCPY 1307 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1308 depends on MMU 1309 default y if CPU_FEROCEON 1310 help 1311 Implement faster copy_to_user and clear_user methods for CPU 1312 cores where a 8-word STM instruction give significantly higher 1313 memory write throughput than a sequence of individual 32bit stores. 1314 1315 A possible side effect is a slight increase in scheduling latency 1316 between threads sharing the same address space if they invoke 1317 such copy operations with large buffers. 1318 1319 However, if the CPU data cache is using a write-allocate mode, 1320 this option is unlikely to provide any performance gain. 1321 1322config PARAVIRT 1323 bool "Enable paravirtualization code" 1324 select HAVE_PV_STEAL_CLOCK_GEN 1325 help 1326 This changes the kernel so it can modify itself when it is run 1327 under a hypervisor, potentially improving performance significantly 1328 over full virtualization. 1329 1330config PARAVIRT_TIME_ACCOUNTING 1331 bool "Paravirtual steal time accounting" 1332 select PARAVIRT 1333 help 1334 Select this option to enable fine granularity task steal time 1335 accounting. Time spent executing other tasks in parallel with 1336 the current vCPU is discounted from the vCPU power. To account for 1337 that, there can be a small performance impact. 1338 1339 If in doubt, say N here. 1340 1341config XEN_DOM0 1342 def_bool y 1343 depends on XEN 1344 1345config XEN 1346 bool "Xen guest support on ARM" 1347 depends on ARM && AEABI && OF 1348 depends on CPU_V7 && !CPU_V6 1349 depends on !GENERIC_ATOMIC64 1350 depends on MMU 1351 select ARCH_DMA_ADDR_T_64BIT 1352 select ARM_PSCI 1353 select SWIOTLB 1354 select SWIOTLB_XEN 1355 select PARAVIRT 1356 help 1357 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1358 1359config CC_HAVE_STACKPROTECTOR_TLS 1360 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1361 1362config STACKPROTECTOR_PER_TASK 1363 bool "Use a unique stack canary value for each task" 1364 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1365 depends on CC_HAVE_STACKPROTECTOR_TLS 1366 default y 1367 help 1368 Due to the fact that GCC uses an ordinary symbol reference from 1369 which to load the value of the stack canary, this value can only 1370 change at reboot time on SMP systems, and all tasks running in the 1371 kernel's address space are forced to use the same canary value for 1372 the entire duration that the system is up. 1373 1374 Enable this option to switch to a different method that uses a 1375 different canary value for each task. 1376 1377endmenu 1378 1379menu "Boot options" 1380 1381config USE_OF 1382 bool "Flattened Device Tree support" 1383 select IRQ_DOMAIN 1384 select OF 1385 help 1386 Include support for flattened device tree machine descriptions. 1387 1388config ARCH_WANT_FLAT_DTB_INSTALL 1389 def_bool y 1390 1391config ATAGS 1392 bool "Support for the traditional ATAGS boot data passing" 1393 default y 1394 help 1395 This is the traditional way of passing data to the kernel at boot 1396 time. If you are solely relying on the flattened device tree (or 1397 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1398 to remove ATAGS support from your kernel binary. 1399 1400config DEPRECATED_PARAM_STRUCT 1401 bool "Provide old way to pass kernel parameters" 1402 depends on ATAGS 1403 help 1404 This was deprecated in 2001 and announced to live on for 5 years. 1405 Some old boot loaders still use this way. 1406 1407# Compressed boot loader in ROM. Yes, we really want to ask about 1408# TEXT and BSS so we preserve their values in the config files. 1409config ZBOOT_ROM_TEXT 1410 hex "Compressed ROM boot loader base address" 1411 default 0x0 1412 help 1413 The physical address at which the ROM-able zImage is to be 1414 placed in the target. Platforms which normally make use of 1415 ROM-able zImage formats normally set this to a suitable 1416 value in their defconfig file. 1417 1418 If ZBOOT_ROM is not enabled, this has no effect. 1419 1420config ZBOOT_ROM_BSS 1421 hex "Compressed ROM boot loader BSS address" 1422 default 0x0 1423 help 1424 The base address of an area of read/write memory in the target 1425 for the ROM-able zImage which must be available while the 1426 decompressor is running. It must be large enough to hold the 1427 entire decompressed kernel plus an additional 128 KiB. 1428 Platforms which normally make use of ROM-able zImage formats 1429 normally set this to a suitable value in their defconfig file. 1430 1431 If ZBOOT_ROM is not enabled, this has no effect. 1432 1433config ZBOOT_ROM 1434 bool "Compressed boot loader in ROM/flash" 1435 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1436 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1437 help 1438 Say Y here if you intend to execute your compressed kernel image 1439 (zImage) directly from ROM or flash. If unsure, say N. 1440 1441config ARM_APPENDED_DTB 1442 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1443 depends on OF 1444 help 1445 With this option, the boot code will look for a device tree binary 1446 (DTB) appended to zImage 1447 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1448 1449 This is meant as a backward compatibility convenience for those 1450 systems with a bootloader that can't be upgraded to accommodate 1451 the documented boot protocol using a device tree. 1452 1453 Beware that there is very little in terms of protection against 1454 this option being confused by leftover garbage in memory that might 1455 look like a DTB header after a reboot if no actual DTB is appended 1456 to zImage. Do not leave this option active in a production kernel 1457 if you don't intend to always append a DTB. Proper passing of the 1458 location into r2 of a bootloader provided DTB is always preferable 1459 to this option. 1460 1461config ARM_ATAG_DTB_COMPAT 1462 bool "Supplement the appended DTB with traditional ATAG information" 1463 depends on ARM_APPENDED_DTB 1464 help 1465 Some old bootloaders can't be updated to a DTB capable one, yet 1466 they provide ATAGs with memory configuration, the ramdisk address, 1467 the kernel cmdline string, etc. Such information is dynamically 1468 provided by the bootloader and can't always be stored in a static 1469 DTB. To allow a device tree enabled kernel to be used with such 1470 bootloaders, this option allows zImage to extract the information 1471 from the ATAG list and store it at run time into the appended DTB. 1472 1473choice 1474 prompt "Kernel command line type" 1475 depends on ARM_ATAG_DTB_COMPAT 1476 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1477 1478config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1479 bool "Use bootloader kernel arguments if available" 1480 help 1481 Uses the command-line options passed by the boot loader instead of 1482 the device tree bootargs property. If the boot loader doesn't provide 1483 any, the device tree bootargs property will be used. 1484 1485config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1486 bool "Extend with bootloader kernel arguments" 1487 help 1488 The command-line arguments provided by the boot loader will be 1489 appended to the the device tree bootargs property. 1490 1491endchoice 1492 1493config CMDLINE 1494 string "Default kernel command string" 1495 default "" 1496 help 1497 On some architectures (e.g. CATS), there is currently no way 1498 for the boot loader to pass arguments to the kernel. For these 1499 architectures, you should supply some command-line options at build 1500 time by entering them here. As a minimum, you should specify the 1501 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1502 1503choice 1504 prompt "Kernel command line type" 1505 depends on CMDLINE != "" 1506 default CMDLINE_FROM_BOOTLOADER 1507 1508config CMDLINE_FROM_BOOTLOADER 1509 bool "Use bootloader kernel arguments if available" 1510 help 1511 Uses the command-line options passed by the boot loader. If 1512 the boot loader doesn't provide any, the default kernel command 1513 string provided in CMDLINE will be used. 1514 1515config CMDLINE_EXTEND 1516 bool "Extend bootloader kernel arguments" 1517 help 1518 The command-line arguments provided by the boot loader will be 1519 appended to the default kernel command string. 1520 1521config CMDLINE_FORCE 1522 bool "Always use the default kernel command string" 1523 help 1524 Always use the default kernel command string, even if the boot 1525 loader passes other arguments to the kernel. 1526 This is useful if you cannot or don't want to change the 1527 command-line options your boot loader passes to the kernel. 1528endchoice 1529 1530config XIP_KERNEL 1531 bool "Kernel Execute-In-Place from ROM" 1532 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1533 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1534 help 1535 Execute-In-Place allows the kernel to run from non-volatile storage 1536 directly addressable by the CPU, such as NOR flash. This saves RAM 1537 space since the text section of the kernel is not loaded from flash 1538 to RAM. Read-write sections, such as the data section and stack, 1539 are still copied to RAM. The XIP kernel is not compressed since 1540 it has to run directly from flash, so it will take more space to 1541 store it. The flash address used to link the kernel object files, 1542 and for storing it, is configuration dependent. Therefore, if you 1543 say Y here, you must know the proper physical address where to 1544 store the kernel image depending on your own flash memory usage. 1545 1546 Also note that the make target becomes "make xipImage" rather than 1547 "make zImage" or "make Image". The final kernel binary to put in 1548 ROM memory will be arch/arm/boot/xipImage. 1549 1550 If unsure, say N. 1551 1552config XIP_PHYS_ADDR 1553 hex "XIP Kernel Physical Location" 1554 depends on XIP_KERNEL 1555 default "0x00080000" 1556 help 1557 This is the physical address in your flash memory the kernel will 1558 be linked for and stored to. This address is dependent on your 1559 own flash usage. 1560 1561config XIP_DEFLATED_DATA 1562 bool "Store kernel .data section compressed in ROM" 1563 depends on XIP_KERNEL 1564 select ZLIB_INFLATE 1565 help 1566 Before the kernel is actually executed, its .data section has to be 1567 copied to RAM from ROM. This option allows for storing that data 1568 in compressed form and decompressed to RAM rather than merely being 1569 copied, saving some precious ROM space. A possible drawback is a 1570 slightly longer boot delay. 1571 1572config ARCH_SUPPORTS_KEXEC 1573 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1574 1575config ATAGS_PROC 1576 bool "Export atags in procfs" 1577 depends on ATAGS && KEXEC 1578 default y 1579 help 1580 Should the atags used to boot the kernel be exported in an "atags" 1581 file in procfs. Useful with kexec. 1582 1583config ARCH_SUPPORTS_CRASH_DUMP 1584 def_bool y 1585 1586config ARCH_DEFAULT_CRASH_DUMP 1587 def_bool y 1588 1589config AUTO_ZRELADDR 1590 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1591 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1592 help 1593 ZRELADDR is the physical address where the decompressed kernel 1594 image will be placed. If AUTO_ZRELADDR is selected, the address 1595 will be determined at run-time, either by masking the current IP 1596 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1597 This assumes the zImage being placed in the first 128MB from 1598 start of memory. 1599 1600config EFI_STUB 1601 bool 1602 1603config EFI 1604 bool "UEFI runtime support" 1605 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1606 select UCS2_STRING 1607 select EFI_PARAMS_FROM_FDT 1608 select EFI_STUB 1609 select EFI_GENERIC_STUB 1610 select EFI_RUNTIME_WRAPPERS 1611 help 1612 This option provides support for runtime services provided 1613 by UEFI firmware (such as non-volatile variables, realtime 1614 clock, and platform reset). A UEFI stub is also provided to 1615 allow the kernel to be booted as an EFI application. This 1616 is only useful for kernels that may run on systems that have 1617 UEFI firmware. 1618 1619config DMI 1620 bool "Enable support for SMBIOS (DMI) tables" 1621 depends on EFI 1622 default y 1623 help 1624 This enables SMBIOS/DMI feature for systems. 1625 1626 This option is only useful on systems that have UEFI firmware. 1627 However, even with this option, the resultant kernel should 1628 continue to boot on existing non-UEFI platforms. 1629 1630 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1631 i.e., the the practice of identifying the platform via DMI to 1632 decide whether certain workarounds for buggy hardware and/or 1633 firmware need to be enabled. This would require the DMI subsystem 1634 to be enabled much earlier than we do on ARM, which is non-trivial. 1635 1636endmenu 1637 1638menu "CPU Power Management" 1639 1640source "drivers/cpufreq/Kconfig" 1641 1642source "drivers/cpuidle/Kconfig" 1643 1644endmenu 1645 1646menu "Floating point emulation" 1647 1648comment "At least one emulation must be selected" 1649 1650config FPE_NWFPE 1651 bool "NWFPE math emulation" 1652 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1653 help 1654 Say Y to include the NWFPE floating point emulator in the kernel. 1655 This is necessary to run most binaries. Linux does not currently 1656 support floating point hardware so you need to say Y here even if 1657 your machine has an FPA or floating point co-processor podule. 1658 1659 You may say N here if you are going to load the Acorn FPEmulator 1660 early in the bootup. 1661 1662config FPE_NWFPE_XP 1663 bool "Support extended precision" 1664 depends on FPE_NWFPE 1665 help 1666 Say Y to include 80-bit support in the kernel floating-point 1667 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1668 Note that gcc does not generate 80-bit operations by default, 1669 so in most cases this option only enlarges the size of the 1670 floating point emulator without any good reason. 1671 1672 You almost surely want to say N here. 1673 1674config FPE_FASTFPE 1675 bool "FastFPE math emulation (EXPERIMENTAL)" 1676 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1677 help 1678 Say Y here to include the FAST floating point emulator in the kernel. 1679 This is an experimental much faster emulator which now also has full 1680 precision for the mantissa. It does not support any exceptions. 1681 It is very simple, and approximately 3-6 times faster than NWFPE. 1682 1683 It should be sufficient for most programs. It may be not suitable 1684 for scientific calculations, but you have to check this for yourself. 1685 If you do not feel you need a faster FP emulation you should better 1686 choose NWFPE. 1687 1688config VFP 1689 bool "VFP-format floating point maths" 1690 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1691 help 1692 Say Y to include VFP support code in the kernel. This is needed 1693 if your hardware includes a VFP unit. 1694 1695 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1696 release notes and additional status information. 1697 1698 Say N if your target does not have VFP hardware. 1699 1700config VFPv3 1701 bool 1702 depends on VFP 1703 default y if CPU_V7 1704 1705config NEON 1706 bool "Advanced SIMD (NEON) Extension support" 1707 depends on VFPv3 && CPU_V7 1708 help 1709 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1710 Extension. 1711 1712config KERNEL_MODE_NEON 1713 bool "Support for NEON in kernel mode" 1714 depends on NEON && AEABI 1715 help 1716 Say Y to include support for NEON in kernel mode. 1717 1718endmenu 1719 1720config ARCH_CC_CAN_LINK 1721 bool 1722 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN 1723 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8 1724 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32 1725 1726config ARCH_USERFLAGS 1727 string 1728 default "-mlittle-endian" if CPU_LITTLE_ENDIAN 1729 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8 1730 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32 1731 1732menu "Power management options" 1733 1734source "kernel/power/Kconfig" 1735 1736config ARCH_SUSPEND_POSSIBLE 1737 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1738 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1739 def_bool y 1740 1741config ARM_CPU_SUSPEND 1742 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1743 depends on ARCH_SUSPEND_POSSIBLE 1744 1745config ARCH_HIBERNATION_POSSIBLE 1746 bool 1747 depends on MMU 1748 default y if ARCH_SUSPEND_POSSIBLE 1749 1750endmenu 1751