1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 72 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 73 select HAVE_ARCH_TRACEHOOK 74 select HAVE_ARM_SMCCC if CPU_V7 75 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 76 select HAVE_CONTEXT_TRACKING 77 select HAVE_C_RECORDMCOUNT 78 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 79 select HAVE_DMA_CONTIGUOUS if MMU 80 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 81 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 82 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 83 select HAVE_EXIT_THREAD 84 select HAVE_FAST_GUP if ARM_LPAE 85 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 86 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 87 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 88 select HAVE_GCC_PLUGINS 89 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 90 select HAVE_IDE if PCI || ISA || PCMCIA 91 select HAVE_IRQ_TIME_ACCOUNTING 92 select HAVE_KERNEL_GZIP 93 select HAVE_KERNEL_LZ4 94 select HAVE_KERNEL_LZMA 95 select HAVE_KERNEL_LZO 96 select HAVE_KERNEL_XZ 97 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 98 select HAVE_KRETPROBES if HAVE_KPROBES 99 select HAVE_MOD_ARCH_SPECIFIC 100 select HAVE_NMI 101 select HAVE_OPROFILE if HAVE_PERF_EVENTS 102 select HAVE_OPTPROBES if !THUMB2_KERNEL 103 select HAVE_PERF_EVENTS 104 select HAVE_PERF_REGS 105 select HAVE_PERF_USER_STACK_DUMP 106 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 107 select HAVE_REGS_AND_STACK_ACCESS_API 108 select HAVE_RSEQ 109 select HAVE_STACKPROTECTOR 110 select HAVE_SYSCALL_TRACEPOINTS 111 select HAVE_UID16 112 select HAVE_VIRT_CPU_ACCOUNTING_GEN 113 select IRQ_FORCED_THREADING 114 select MODULES_USE_ELF_REL 115 select NEED_DMA_MAP_STATE 116 select OF_EARLY_FLATTREE if OF 117 select OLD_SIGACTION 118 select OLD_SIGSUSPEND3 119 select PCI_SYSCALL if PCI 120 select PERF_USE_VMALLOC 121 select RTC_LIB 122 select SYS_SUPPORTS_APM_EMULATION 123 # Above selects are sorted alphabetically; please add new ones 124 # according to that. Thanks. 125 help 126 The ARM series is a line of low-power-consumption RISC chip designs 127 licensed by ARM Ltd and targeted at embedded applications and 128 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 129 manufactured, but legacy ARM-based PC hardware remains popular in 130 Europe. There is an ARM Linux project with a web page at 131 <http://www.arm.linux.org.uk/>. 132 133config ARM_HAS_SG_CHAIN 134 bool 135 136config ARM_DMA_USE_IOMMU 137 bool 138 select ARM_HAS_SG_CHAIN 139 select NEED_SG_DMA_LENGTH 140 141if ARM_DMA_USE_IOMMU 142 143config ARM_DMA_IOMMU_ALIGNMENT 144 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 145 range 4 9 146 default 8 147 help 148 DMA mapping framework by default aligns all buffers to the smallest 149 PAGE_SIZE order which is greater than or equal to the requested buffer 150 size. This works well for buffers up to a few hundreds kilobytes, but 151 for larger buffers it just a waste of address space. Drivers which has 152 relatively small addressing window (like 64Mib) might run out of 153 virtual space with just a few allocations. 154 155 With this parameter you can specify the maximum PAGE_SIZE order for 156 DMA IOMMU buffers. Larger buffers will be aligned only to this 157 specified order. The order is expressed as a power of two multiplied 158 by the PAGE_SIZE. 159 160endif 161 162config SYS_SUPPORTS_APM_EMULATION 163 bool 164 165config HAVE_TCM 166 bool 167 select GENERIC_ALLOCATOR 168 169config HAVE_PROC_CPU 170 bool 171 172config NO_IOPORT_MAP 173 bool 174 175config SBUS 176 bool 177 178config STACKTRACE_SUPPORT 179 bool 180 default y 181 182config LOCKDEP_SUPPORT 183 bool 184 default y 185 186config TRACE_IRQFLAGS_SUPPORT 187 bool 188 default !CPU_V7M 189 190config ARCH_HAS_ILOG2_U32 191 bool 192 193config ARCH_HAS_ILOG2_U64 194 bool 195 196config ARCH_HAS_BANDGAP 197 bool 198 199config FIX_EARLYCON_MEM 200 def_bool y if MMU 201 202config GENERIC_HWEIGHT 203 bool 204 default y 205 206config GENERIC_CALIBRATE_DELAY 207 bool 208 default y 209 210config ARCH_MAY_HAVE_PC_FDC 211 bool 212 213config ZONE_DMA 214 bool 215 216config ARCH_SUPPORTS_UPROBES 217 def_bool y 218 219config ARCH_HAS_DMA_SET_COHERENT_MASK 220 bool 221 222config GENERIC_ISA_DMA 223 bool 224 225config FIQ 226 bool 227 228config NEED_RET_TO_USER 229 bool 230 231config ARCH_MTD_XIP 232 bool 233 234config ARM_PATCH_PHYS_VIRT 235 bool "Patch physical to virtual translations at runtime" if EMBEDDED 236 default y 237 depends on !XIP_KERNEL && MMU 238 help 239 Patch phys-to-virt and virt-to-phys translation functions at 240 boot and module load time according to the position of the 241 kernel in system memory. 242 243 This can only be used with non-XIP MMU kernels where the base 244 of physical memory is at a 16MB boundary. 245 246 Only disable this option if you know that you do not require 247 this feature (eg, building a kernel for a single machine) and 248 you need to shrink the kernel to the minimal size. 249 250config NEED_MACH_IO_H 251 bool 252 help 253 Select this when mach/io.h is required to provide special 254 definitions for this platform. The need for mach/io.h should 255 be avoided when possible. 256 257config NEED_MACH_MEMORY_H 258 bool 259 help 260 Select this when mach/memory.h is required to provide special 261 definitions for this platform. The need for mach/memory.h should 262 be avoided when possible. 263 264config PHYS_OFFSET 265 hex "Physical address of main memory" if MMU 266 depends on !ARM_PATCH_PHYS_VIRT 267 default DRAM_BASE if !MMU 268 default 0x00000000 if ARCH_EBSA110 || \ 269 ARCH_FOOTBRIDGE || \ 270 ARCH_INTEGRATOR || \ 271 ARCH_REALVIEW 272 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 273 default 0x20000000 if ARCH_S5PV210 274 default 0xc0000000 if ARCH_SA1100 275 help 276 Please provide the physical address corresponding to the 277 location of main memory in your system. 278 279config GENERIC_BUG 280 def_bool y 281 depends on BUG 282 283config PGTABLE_LEVELS 284 int 285 default 3 if ARM_LPAE 286 default 2 287 288menu "System Type" 289 290config MMU 291 bool "MMU-based Paged Memory Management Support" 292 default y 293 help 294 Select if you want MMU-based virtualised addressing space 295 support by paged memory management. If unsure, say 'Y'. 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 8 299 300config ARCH_MMAP_RND_BITS_MAX 301 default 14 if PAGE_OFFSET=0x40000000 302 default 15 if PAGE_OFFSET=0x80000000 303 default 16 304 305# 306# The "ARM system type" choice list is ordered alphabetically by option 307# text. Please add new entries in the option alphabetic order. 308# 309choice 310 prompt "ARM system type" 311 default ARM_SINGLE_ARMV7M if !MMU 312 default ARCH_MULTIPLATFORM if MMU 313 314config ARCH_MULTIPLATFORM 315 bool "Allow multiple platforms to be selected" 316 depends on MMU 317 select ARCH_FLATMEM_ENABLE 318 select ARCH_SPARSEMEM_ENABLE 319 select ARCH_SELECT_MEMORY_MODEL 320 select ARM_HAS_SG_CHAIN 321 select ARM_PATCH_PHYS_VIRT 322 select AUTO_ZRELADDR 323 select TIMER_OF 324 select COMMON_CLK 325 select GENERIC_CLOCKEVENTS 326 select GENERIC_IRQ_MULTI_HANDLER 327 select HAVE_PCI 328 select PCI_DOMAINS_GENERIC if PCI 329 select SPARSE_IRQ 330 select USE_OF 331 332config ARM_SINGLE_ARMV7M 333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 334 depends on !MMU 335 select ARM_NVIC 336 select AUTO_ZRELADDR 337 select TIMER_OF 338 select COMMON_CLK 339 select CPU_V7M 340 select GENERIC_CLOCKEVENTS 341 select NO_IOPORT_MAP 342 select SPARSE_IRQ 343 select USE_OF 344 345config ARCH_EBSA110 346 bool "EBSA-110" 347 select ARCH_USES_GETTIMEOFFSET 348 select CPU_SA110 349 select ISA 350 select NEED_MACH_IO_H 351 select NEED_MACH_MEMORY_H 352 select NO_IOPORT_MAP 353 help 354 This is an evaluation board for the StrongARM processor available 355 from Digital. It has limited hardware on-board, including an 356 Ethernet interface, two PCMCIA sockets, two serial ports and a 357 parallel port. 358 359config ARCH_EP93XX 360 bool "EP93xx-based" 361 select ARCH_SPARSEMEM_ENABLE 362 select ARM_AMBA 363 imply ARM_PATCH_PHYS_VIRT 364 select ARM_VIC 365 select AUTO_ZRELADDR 366 select CLKDEV_LOOKUP 367 select CLKSRC_MMIO 368 select CPU_ARM920T 369 select GENERIC_CLOCKEVENTS 370 select GPIOLIB 371 select HAVE_LEGACY_CLK 372 help 373 This enables support for the Cirrus EP93xx series of CPUs. 374 375config ARCH_FOOTBRIDGE 376 bool "FootBridge" 377 select CPU_SA110 378 select FOOTBRIDGE 379 select GENERIC_CLOCKEVENTS 380 select HAVE_IDE 381 select NEED_MACH_IO_H if !MMU 382 select NEED_MACH_MEMORY_H 383 help 384 Support for systems based on the DC21285 companion chip 385 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 386 387config ARCH_IOP32X 388 bool "IOP32x-based" 389 depends on MMU 390 select CPU_XSCALE 391 select GPIO_IOP 392 select GPIOLIB 393 select NEED_RET_TO_USER 394 select FORCE_PCI 395 select PLAT_IOP 396 help 397 Support for Intel's 80219 and IOP32X (XScale) family of 398 processors. 399 400config ARCH_IXP4XX 401 bool "IXP4xx-based" 402 depends on MMU 403 select ARCH_HAS_DMA_SET_COHERENT_MASK 404 select ARCH_SUPPORTS_BIG_ENDIAN 405 select CPU_XSCALE 406 select DMABOUNCE if PCI 407 select GENERIC_CLOCKEVENTS 408 select GENERIC_IRQ_MULTI_HANDLER 409 select GPIO_IXP4XX 410 select GPIOLIB 411 select HAVE_PCI 412 select IXP4XX_IRQ 413 select IXP4XX_TIMER 414 select NEED_MACH_IO_H 415 select USB_EHCI_BIG_ENDIAN_DESC 416 select USB_EHCI_BIG_ENDIAN_MMIO 417 help 418 Support for Intel's IXP4XX (XScale) family of processors. 419 420config ARCH_DOVE 421 bool "Marvell Dove" 422 select CPU_PJ4 423 select GENERIC_CLOCKEVENTS 424 select GENERIC_IRQ_MULTI_HANDLER 425 select GPIOLIB 426 select HAVE_PCI 427 select MVEBU_MBUS 428 select PINCTRL 429 select PINCTRL_DOVE 430 select PLAT_ORION_LEGACY 431 select SPARSE_IRQ 432 select PM_GENERIC_DOMAINS if PM 433 help 434 Support for the Marvell Dove SoC 88AP510 435 436config ARCH_PXA 437 bool "PXA2xx/PXA3xx-based" 438 depends on MMU 439 select ARCH_MTD_XIP 440 select ARM_CPU_SUSPEND if PM 441 select AUTO_ZRELADDR 442 select COMMON_CLK 443 select CLKSRC_PXA 444 select CLKSRC_MMIO 445 select TIMER_OF 446 select CPU_XSCALE if !CPU_XSC3 447 select GENERIC_CLOCKEVENTS 448 select GENERIC_IRQ_MULTI_HANDLER 449 select GPIO_PXA 450 select GPIOLIB 451 select HAVE_IDE 452 select IRQ_DOMAIN 453 select PLAT_PXA 454 select SPARSE_IRQ 455 help 456 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 457 458config ARCH_RPC 459 bool "RiscPC" 460 depends on MMU 461 select ARCH_ACORN 462 select ARCH_MAY_HAVE_PC_FDC 463 select ARCH_SPARSEMEM_ENABLE 464 select ARM_HAS_SG_CHAIN 465 select CPU_SA110 466 select FIQ 467 select HAVE_IDE 468 select HAVE_PATA_PLATFORM 469 select ISA_DMA_API 470 select NEED_MACH_IO_H 471 select NEED_MACH_MEMORY_H 472 select NO_IOPORT_MAP 473 help 474 On the Acorn Risc-PC, Linux can support the internal IDE disk and 475 CD-ROM interface, serial and parallel port, and the floppy drive. 476 477config ARCH_SA1100 478 bool "SA1100-based" 479 select ARCH_MTD_XIP 480 select ARCH_SPARSEMEM_ENABLE 481 select CLKSRC_MMIO 482 select CLKSRC_PXA 483 select TIMER_OF if OF 484 select COMMON_CLK 485 select CPU_FREQ 486 select CPU_SA1100 487 select GENERIC_CLOCKEVENTS 488 select GENERIC_IRQ_MULTI_HANDLER 489 select GPIOLIB 490 select HAVE_IDE 491 select IRQ_DOMAIN 492 select ISA 493 select NEED_MACH_MEMORY_H 494 select SPARSE_IRQ 495 help 496 Support for StrongARM 11x0 based boards. 497 498config ARCH_S3C24XX 499 bool "Samsung S3C24XX SoCs" 500 select ATAGS 501 select CLKSRC_SAMSUNG_PWM 502 select GENERIC_CLOCKEVENTS 503 select GPIO_SAMSUNG 504 select GPIOLIB 505 select GENERIC_IRQ_MULTI_HANDLER 506 select HAVE_S3C2410_I2C if I2C 507 select HAVE_S3C2410_WATCHDOG if WATCHDOG 508 select HAVE_S3C_RTC if RTC_CLASS 509 select NEED_MACH_IO_H 510 select SAMSUNG_ATAGS 511 select USE_OF 512 help 513 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 514 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 515 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 516 Samsung SMDK2410 development board (and derivatives). 517 518config ARCH_OMAP1 519 bool "TI OMAP1" 520 depends on MMU 521 select ARCH_HAS_HOLES_MEMORYMODEL 522 select ARCH_OMAP 523 select CLKDEV_LOOKUP 524 select CLKSRC_MMIO 525 select GENERIC_CLOCKEVENTS 526 select GENERIC_IRQ_CHIP 527 select GENERIC_IRQ_MULTI_HANDLER 528 select GPIOLIB 529 select HAVE_IDE 530 select HAVE_LEGACY_CLK 531 select IRQ_DOMAIN 532 select NEED_MACH_IO_H if PCCARD 533 select NEED_MACH_MEMORY_H 534 select SPARSE_IRQ 535 help 536 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 537 538endchoice 539 540menu "Multiple platform selection" 541 depends on ARCH_MULTIPLATFORM 542 543comment "CPU Core family selection" 544 545config ARCH_MULTI_V4 546 bool "ARMv4 based platforms (FA526)" 547 depends on !ARCH_MULTI_V6_V7 548 select ARCH_MULTI_V4_V5 549 select CPU_FA526 550 551config ARCH_MULTI_V4T 552 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 553 depends on !ARCH_MULTI_V6_V7 554 select ARCH_MULTI_V4_V5 555 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 556 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 557 CPU_ARM925T || CPU_ARM940T) 558 559config ARCH_MULTI_V5 560 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 561 depends on !ARCH_MULTI_V6_V7 562 select ARCH_MULTI_V4_V5 563 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 564 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 565 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 566 567config ARCH_MULTI_V4_V5 568 bool 569 570config ARCH_MULTI_V6 571 bool "ARMv6 based platforms (ARM11)" 572 select ARCH_MULTI_V6_V7 573 select CPU_V6K 574 575config ARCH_MULTI_V7 576 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 577 default y 578 select ARCH_MULTI_V6_V7 579 select CPU_V7 580 select HAVE_SMP 581 582config ARCH_MULTI_V6_V7 583 bool 584 select MIGHT_HAVE_CACHE_L2X0 585 586config ARCH_MULTI_CPU_AUTO 587 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 588 select ARCH_MULTI_V5 589 590endmenu 591 592config ARCH_VIRT 593 bool "Dummy Virtual Machine" 594 depends on ARCH_MULTI_V7 595 select ARM_AMBA 596 select ARM_GIC 597 select ARM_GIC_V2M if PCI 598 select ARM_GIC_V3 599 select ARM_GIC_V3_ITS if PCI 600 select ARM_PSCI 601 select HAVE_ARM_ARCH_TIMER 602 select ARCH_SUPPORTS_BIG_ENDIAN 603 604# 605# This is sorted alphabetically by mach-* pathname. However, plat-* 606# Kconfigs may be included either alphabetically (according to the 607# plat- suffix) or along side the corresponding mach-* source. 608# 609source "arch/arm/mach-actions/Kconfig" 610 611source "arch/arm/mach-alpine/Kconfig" 612 613source "arch/arm/mach-artpec/Kconfig" 614 615source "arch/arm/mach-asm9260/Kconfig" 616 617source "arch/arm/mach-aspeed/Kconfig" 618 619source "arch/arm/mach-at91/Kconfig" 620 621source "arch/arm/mach-axxia/Kconfig" 622 623source "arch/arm/mach-bcm/Kconfig" 624 625source "arch/arm/mach-berlin/Kconfig" 626 627source "arch/arm/mach-clps711x/Kconfig" 628 629source "arch/arm/mach-cns3xxx/Kconfig" 630 631source "arch/arm/mach-davinci/Kconfig" 632 633source "arch/arm/mach-digicolor/Kconfig" 634 635source "arch/arm/mach-dove/Kconfig" 636 637source "arch/arm/mach-ep93xx/Kconfig" 638 639source "arch/arm/mach-exynos/Kconfig" 640source "arch/arm/plat-samsung/Kconfig" 641 642source "arch/arm/mach-footbridge/Kconfig" 643 644source "arch/arm/mach-gemini/Kconfig" 645 646source "arch/arm/mach-highbank/Kconfig" 647 648source "arch/arm/mach-hisi/Kconfig" 649 650source "arch/arm/mach-imx/Kconfig" 651 652source "arch/arm/mach-integrator/Kconfig" 653 654source "arch/arm/mach-iop32x/Kconfig" 655 656source "arch/arm/mach-ixp4xx/Kconfig" 657 658source "arch/arm/mach-keystone/Kconfig" 659 660source "arch/arm/mach-lpc32xx/Kconfig" 661 662source "arch/arm/mach-mediatek/Kconfig" 663 664source "arch/arm/mach-meson/Kconfig" 665 666source "arch/arm/mach-milbeaut/Kconfig" 667 668source "arch/arm/mach-mmp/Kconfig" 669 670source "arch/arm/mach-moxart/Kconfig" 671 672source "arch/arm/mach-mstar/Kconfig" 673 674source "arch/arm/mach-mv78xx0/Kconfig" 675 676source "arch/arm/mach-mvebu/Kconfig" 677 678source "arch/arm/mach-mxs/Kconfig" 679 680source "arch/arm/mach-nomadik/Kconfig" 681 682source "arch/arm/mach-npcm/Kconfig" 683 684source "arch/arm/mach-nspire/Kconfig" 685 686source "arch/arm/plat-omap/Kconfig" 687 688source "arch/arm/mach-omap1/Kconfig" 689 690source "arch/arm/mach-omap2/Kconfig" 691 692source "arch/arm/mach-orion5x/Kconfig" 693 694source "arch/arm/mach-oxnas/Kconfig" 695 696source "arch/arm/mach-picoxcell/Kconfig" 697 698source "arch/arm/mach-prima2/Kconfig" 699 700source "arch/arm/mach-pxa/Kconfig" 701source "arch/arm/plat-pxa/Kconfig" 702 703source "arch/arm/mach-qcom/Kconfig" 704 705source "arch/arm/mach-rda/Kconfig" 706 707source "arch/arm/mach-realtek/Kconfig" 708 709source "arch/arm/mach-realview/Kconfig" 710 711source "arch/arm/mach-rockchip/Kconfig" 712 713source "arch/arm/mach-s3c24xx/Kconfig" 714 715source "arch/arm/mach-s3c64xx/Kconfig" 716 717source "arch/arm/mach-s5pv210/Kconfig" 718 719source "arch/arm/mach-sa1100/Kconfig" 720 721source "arch/arm/mach-shmobile/Kconfig" 722 723source "arch/arm/mach-socfpga/Kconfig" 724 725source "arch/arm/mach-spear/Kconfig" 726 727source "arch/arm/mach-sti/Kconfig" 728 729source "arch/arm/mach-stm32/Kconfig" 730 731source "arch/arm/mach-sunxi/Kconfig" 732 733source "arch/arm/mach-tango/Kconfig" 734 735source "arch/arm/mach-tegra/Kconfig" 736 737source "arch/arm/mach-u300/Kconfig" 738 739source "arch/arm/mach-uniphier/Kconfig" 740 741source "arch/arm/mach-ux500/Kconfig" 742 743source "arch/arm/mach-versatile/Kconfig" 744 745source "arch/arm/mach-vexpress/Kconfig" 746 747source "arch/arm/mach-vt8500/Kconfig" 748 749source "arch/arm/mach-zx/Kconfig" 750 751source "arch/arm/mach-zynq/Kconfig" 752 753# ARMv7-M architecture 754config ARCH_EFM32 755 bool "Energy Micro efm32" 756 depends on ARM_SINGLE_ARMV7M 757 select GPIOLIB 758 help 759 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 760 processors. 761 762config ARCH_LPC18XX 763 bool "NXP LPC18xx/LPC43xx" 764 depends on ARM_SINGLE_ARMV7M 765 select ARCH_HAS_RESET_CONTROLLER 766 select ARM_AMBA 767 select CLKSRC_LPC32XX 768 select PINCTRL 769 help 770 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 771 high performance microcontrollers. 772 773config ARCH_MPS2 774 bool "ARM MPS2 platform" 775 depends on ARM_SINGLE_ARMV7M 776 select ARM_AMBA 777 select CLKSRC_MPS2 778 help 779 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 780 with a range of available cores like Cortex-M3/M4/M7. 781 782 Please, note that depends which Application Note is used memory map 783 for the platform may vary, so adjustment of RAM base might be needed. 784 785# Definitions to make life easier 786config ARCH_ACORN 787 bool 788 789config PLAT_IOP 790 bool 791 select GENERIC_CLOCKEVENTS 792 793config PLAT_ORION 794 bool 795 select CLKSRC_MMIO 796 select COMMON_CLK 797 select GENERIC_IRQ_CHIP 798 select IRQ_DOMAIN 799 800config PLAT_ORION_LEGACY 801 bool 802 select PLAT_ORION 803 804config PLAT_PXA 805 bool 806 807config PLAT_VERSATILE 808 bool 809 810source "arch/arm/mm/Kconfig" 811 812config IWMMXT 813 bool "Enable iWMMXt support" 814 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 815 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 816 help 817 Enable support for iWMMXt context switching at run time if 818 running on a CPU that supports it. 819 820if !MMU 821source "arch/arm/Kconfig-nommu" 822endif 823 824config PJ4B_ERRATA_4742 825 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 826 depends on CPU_PJ4B && MACH_ARMADA_370 827 default y 828 help 829 When coming out of either a Wait for Interrupt (WFI) or a Wait for 830 Event (WFE) IDLE states, a specific timing sensitivity exists between 831 the retiring WFI/WFE instructions and the newly issued subsequent 832 instructions. This sensitivity can result in a CPU hang scenario. 833 Workaround: 834 The software must insert either a Data Synchronization Barrier (DSB) 835 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 836 instruction 837 838config ARM_ERRATA_326103 839 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 840 depends on CPU_V6 841 help 842 Executing a SWP instruction to read-only memory does not set bit 11 843 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 844 treat the access as a read, preventing a COW from occurring and 845 causing the faulting task to livelock. 846 847config ARM_ERRATA_411920 848 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 849 depends on CPU_V6 || CPU_V6K 850 help 851 Invalidation of the Instruction Cache operation can 852 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 853 It does not affect the MPCore. This option enables the ARM Ltd. 854 recommended workaround. 855 856config ARM_ERRATA_430973 857 bool "ARM errata: Stale prediction on replaced interworking branch" 858 depends on CPU_V7 859 help 860 This option enables the workaround for the 430973 Cortex-A8 861 r1p* erratum. If a code sequence containing an ARM/Thumb 862 interworking branch is replaced with another code sequence at the 863 same virtual address, whether due to self-modifying code or virtual 864 to physical address re-mapping, Cortex-A8 does not recover from the 865 stale interworking branch prediction. This results in Cortex-A8 866 executing the new code sequence in the incorrect ARM or Thumb state. 867 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 868 and also flushes the branch target cache at every context switch. 869 Note that setting specific bits in the ACTLR register may not be 870 available in non-secure mode. 871 872config ARM_ERRATA_458693 873 bool "ARM errata: Processor deadlock when a false hazard is created" 874 depends on CPU_V7 875 depends on !ARCH_MULTIPLATFORM 876 help 877 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 878 erratum. For very specific sequences of memory operations, it is 879 possible for a hazard condition intended for a cache line to instead 880 be incorrectly associated with a different cache line. This false 881 hazard might then cause a processor deadlock. The workaround enables 882 the L1 caching of the NEON accesses and disables the PLD instruction 883 in the ACTLR register. Note that setting specific bits in the ACTLR 884 register may not be available in non-secure mode. 885 886config ARM_ERRATA_460075 887 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 888 depends on CPU_V7 889 depends on !ARCH_MULTIPLATFORM 890 help 891 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 892 erratum. Any asynchronous access to the L2 cache may encounter a 893 situation in which recent store transactions to the L2 cache are lost 894 and overwritten with stale memory contents from external memory. The 895 workaround disables the write-allocate mode for the L2 cache via the 896 ACTLR register. Note that setting specific bits in the ACTLR register 897 may not be available in non-secure mode. 898 899config ARM_ERRATA_742230 900 bool "ARM errata: DMB operation may be faulty" 901 depends on CPU_V7 && SMP 902 depends on !ARCH_MULTIPLATFORM 903 help 904 This option enables the workaround for the 742230 Cortex-A9 905 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 906 between two write operations may not ensure the correct visibility 907 ordering of the two writes. This workaround sets a specific bit in 908 the diagnostic register of the Cortex-A9 which causes the DMB 909 instruction to behave as a DSB, ensuring the correct behaviour of 910 the two writes. 911 912config ARM_ERRATA_742231 913 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 914 depends on CPU_V7 && SMP 915 depends on !ARCH_MULTIPLATFORM 916 help 917 This option enables the workaround for the 742231 Cortex-A9 918 (r2p0..r2p2) erratum. Under certain conditions, specific to the 919 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 920 accessing some data located in the same cache line, may get corrupted 921 data due to bad handling of the address hazard when the line gets 922 replaced from one of the CPUs at the same time as another CPU is 923 accessing it. This workaround sets specific bits in the diagnostic 924 register of the Cortex-A9 which reduces the linefill issuing 925 capabilities of the processor. 926 927config ARM_ERRATA_643719 928 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 929 depends on CPU_V7 && SMP 930 default y 931 help 932 This option enables the workaround for the 643719 Cortex-A9 (prior to 933 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 934 register returns zero when it should return one. The workaround 935 corrects this value, ensuring cache maintenance operations which use 936 it behave as intended and avoiding data corruption. 937 938config ARM_ERRATA_720789 939 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 940 depends on CPU_V7 941 help 942 This option enables the workaround for the 720789 Cortex-A9 (prior to 943 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 944 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 945 As a consequence of this erratum, some TLB entries which should be 946 invalidated are not, resulting in an incoherency in the system page 947 tables. The workaround changes the TLB flushing routines to invalidate 948 entries regardless of the ASID. 949 950config ARM_ERRATA_743622 951 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 952 depends on CPU_V7 953 depends on !ARCH_MULTIPLATFORM 954 help 955 This option enables the workaround for the 743622 Cortex-A9 956 (r2p*) erratum. Under very rare conditions, a faulty 957 optimisation in the Cortex-A9 Store Buffer may lead to data 958 corruption. This workaround sets a specific bit in the diagnostic 959 register of the Cortex-A9 which disables the Store Buffer 960 optimisation, preventing the defect from occurring. This has no 961 visible impact on the overall performance or power consumption of the 962 processor. 963 964config ARM_ERRATA_751472 965 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 966 depends on CPU_V7 967 depends on !ARCH_MULTIPLATFORM 968 help 969 This option enables the workaround for the 751472 Cortex-A9 (prior 970 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 971 completion of a following broadcasted operation if the second 972 operation is received by a CPU before the ICIALLUIS has completed, 973 potentially leading to corrupted entries in the cache or TLB. 974 975config ARM_ERRATA_754322 976 bool "ARM errata: possible faulty MMU translations following an ASID switch" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 980 r3p*) erratum. A speculative memory access may cause a page table walk 981 which starts prior to an ASID switch but completes afterwards. This 982 can populate the micro-TLB with a stale entry which may be hit with 983 the new ASID. This workaround places two dsb instructions in the mm 984 switching code so that no page table walks can cross the ASID switch. 985 986config ARM_ERRATA_754327 987 bool "ARM errata: no automatic Store Buffer drain" 988 depends on CPU_V7 && SMP 989 help 990 This option enables the workaround for the 754327 Cortex-A9 (prior to 991 r2p0) erratum. The Store Buffer does not have any automatic draining 992 mechanism and therefore a livelock may occur if an external agent 993 continuously polls a memory location waiting to observe an update. 994 This workaround defines cpu_relax() as smp_mb(), preventing correctly 995 written polling loops from denying visibility of updates to memory. 996 997config ARM_ERRATA_364296 998 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 999 depends on CPU_V6 1000 help 1001 This options enables the workaround for the 364296 ARM1136 1002 r0p2 erratum (possible cache data corruption with 1003 hit-under-miss enabled). It sets the undocumented bit 31 in 1004 the auxiliary control register and the FI bit in the control 1005 register, thus disabling hit-under-miss without putting the 1006 processor into full low interrupt latency mode. ARM11MPCore 1007 is not affected. 1008 1009config ARM_ERRATA_764369 1010 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1011 depends on CPU_V7 && SMP 1012 help 1013 This option enables the workaround for erratum 764369 1014 affecting Cortex-A9 MPCore with two or more processors (all 1015 current revisions). Under certain timing circumstances, a data 1016 cache line maintenance operation by MVA targeting an Inner 1017 Shareable memory region may fail to proceed up to either the 1018 Point of Coherency or to the Point of Unification of the 1019 system. This workaround adds a DSB instruction before the 1020 relevant cache maintenance functions and sets a specific bit 1021 in the diagnostic control register of the SCU. 1022 1023config ARM_ERRATA_775420 1024 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1025 depends on CPU_V7 1026 help 1027 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1028 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1029 operation aborts with MMU exception, it might cause the processor 1030 to deadlock. This workaround puts DSB before executing ISB if 1031 an abort may occur on cache maintenance. 1032 1033config ARM_ERRATA_798181 1034 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1035 depends on CPU_V7 && SMP 1036 help 1037 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1038 adequately shooting down all use of the old entries. This 1039 option enables the Linux kernel workaround for this erratum 1040 which sends an IPI to the CPUs that are running the same ASID 1041 as the one being invalidated. 1042 1043config ARM_ERRATA_773022 1044 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1045 depends on CPU_V7 1046 help 1047 This option enables the workaround for the 773022 Cortex-A15 1048 (up to r0p4) erratum. In certain rare sequences of code, the 1049 loop buffer may deliver incorrect instructions. This 1050 workaround disables the loop buffer to avoid the erratum. 1051 1052config ARM_ERRATA_818325_852422 1053 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1054 depends on CPU_V7 1055 help 1056 This option enables the workaround for: 1057 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1058 instruction might deadlock. Fixed in r0p1. 1059 - Cortex-A12 852422: Execution of a sequence of instructions might 1060 lead to either a data corruption or a CPU deadlock. Not fixed in 1061 any Cortex-A12 cores yet. 1062 This workaround for all both errata involves setting bit[12] of the 1063 Feature Register. This bit disables an optimisation applied to a 1064 sequence of 2 instructions that use opposing condition codes. 1065 1066config ARM_ERRATA_821420 1067 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1068 depends on CPU_V7 1069 help 1070 This option enables the workaround for the 821420 Cortex-A12 1071 (all revs) erratum. In very rare timing conditions, a sequence 1072 of VMOV to Core registers instructions, for which the second 1073 one is in the shadow of a branch or abort, can lead to a 1074 deadlock when the VMOV instructions are issued out-of-order. 1075 1076config ARM_ERRATA_825619 1077 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1078 depends on CPU_V7 1079 help 1080 This option enables the workaround for the 825619 Cortex-A12 1081 (all revs) erratum. Within rare timing constraints, executing a 1082 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1083 and Device/Strongly-Ordered loads and stores might cause deadlock 1084 1085config ARM_ERRATA_857271 1086 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1087 depends on CPU_V7 1088 help 1089 This option enables the workaround for the 857271 Cortex-A12 1090 (all revs) erratum. Under very rare timing conditions, the CPU might 1091 hang. The workaround is expected to have a < 1% performance impact. 1092 1093config ARM_ERRATA_852421 1094 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1095 depends on CPU_V7 1096 help 1097 This option enables the workaround for the 852421 Cortex-A17 1098 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1099 execution of a DMB ST instruction might fail to properly order 1100 stores from GroupA and stores from GroupB. 1101 1102config ARM_ERRATA_852423 1103 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1104 depends on CPU_V7 1105 help 1106 This option enables the workaround for: 1107 - Cortex-A17 852423: Execution of a sequence of instructions might 1108 lead to either a data corruption or a CPU deadlock. Not fixed in 1109 any Cortex-A17 cores yet. 1110 This is identical to Cortex-A12 erratum 852422. It is a separate 1111 config option from the A12 erratum due to the way errata are checked 1112 for and handled. 1113 1114config ARM_ERRATA_857272 1115 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1116 depends on CPU_V7 1117 help 1118 This option enables the workaround for the 857272 Cortex-A17 erratum. 1119 This erratum is not known to be fixed in any A17 revision. 1120 This is identical to Cortex-A12 erratum 857271. It is a separate 1121 config option from the A12 erratum due to the way errata are checked 1122 for and handled. 1123 1124endmenu 1125 1126source "arch/arm/common/Kconfig" 1127 1128menu "Bus support" 1129 1130config ISA 1131 bool 1132 help 1133 Find out whether you have ISA slots on your motherboard. ISA is the 1134 name of a bus system, i.e. the way the CPU talks to the other stuff 1135 inside your box. Other bus systems are PCI, EISA, MicroChannel 1136 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1137 newer boards don't support it. If you have ISA, say Y, otherwise N. 1138 1139# Select ISA DMA controller support 1140config ISA_DMA 1141 bool 1142 select ISA_DMA_API 1143 1144# Select ISA DMA interface 1145config ISA_DMA_API 1146 bool 1147 1148config PCI_NANOENGINE 1149 bool "BSE nanoEngine PCI support" 1150 depends on SA1100_NANOENGINE 1151 help 1152 Enable PCI on the BSE nanoEngine board. 1153 1154config ARM_ERRATA_814220 1155 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1156 depends on CPU_V7 1157 help 1158 The v7 ARM states that all cache and branch predictor maintenance 1159 operations that do not specify an address execute, relative to 1160 each other, in program order. 1161 However, because of this erratum, an L2 set/way cache maintenance 1162 operation can overtake an L1 set/way cache maintenance operation. 1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1164 r0p4, r0p5. 1165 1166endmenu 1167 1168menu "Kernel Features" 1169 1170config HAVE_SMP 1171 bool 1172 help 1173 This option should be selected by machines which have an SMP- 1174 capable CPU. 1175 1176 The only effect of this option is to make the SMP-related 1177 options available to the user for configuration. 1178 1179config SMP 1180 bool "Symmetric Multi-Processing" 1181 depends on CPU_V6K || CPU_V7 1182 depends on GENERIC_CLOCKEVENTS 1183 depends on HAVE_SMP 1184 depends on MMU || ARM_MPU 1185 select IRQ_WORK 1186 help 1187 This enables support for systems with more than one CPU. If you have 1188 a system with only one CPU, say N. If you have a system with more 1189 than one CPU, say Y. 1190 1191 If you say N here, the kernel will run on uni- and multiprocessor 1192 machines, but will use only one CPU of a multiprocessor machine. If 1193 you say Y here, the kernel will run on many, but not all, 1194 uniprocessor machines. On a uniprocessor machine, the kernel 1195 will run faster if you say N here. 1196 1197 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1200 1201 If you don't know what to do here, say N. 1202 1203config SMP_ON_UP 1204 bool "Allow booting SMP kernel on uniprocessor systems" 1205 depends on SMP && !XIP_KERNEL && MMU 1206 default y 1207 help 1208 SMP kernels contain instructions which fail on non-SMP processors. 1209 Enabling this option allows the kernel to modify itself to make 1210 these instructions safe. Disabling it allows about 1K of space 1211 savings. 1212 1213 If you don't know what to do here, say Y. 1214 1215config ARM_CPU_TOPOLOGY 1216 bool "Support cpu topology definition" 1217 depends on SMP && CPU_V7 1218 default y 1219 help 1220 Support ARM cpu topology definition. The MPIDR register defines 1221 affinity between processors which is then used to describe the cpu 1222 topology of an ARM System. 1223 1224config SCHED_MC 1225 bool "Multi-core scheduler support" 1226 depends on ARM_CPU_TOPOLOGY 1227 help 1228 Multi-core scheduler support improves the CPU scheduler's decision 1229 making when dealing with multi-core CPU chips at a cost of slightly 1230 increased overhead in some places. If unsure say N here. 1231 1232config SCHED_SMT 1233 bool "SMT scheduler support" 1234 depends on ARM_CPU_TOPOLOGY 1235 help 1236 Improves the CPU scheduler's decision making when dealing with 1237 MultiThreading at a cost of slightly increased overhead in some 1238 places. If unsure say N here. 1239 1240config HAVE_ARM_SCU 1241 bool 1242 help 1243 This option enables support for the ARM snoop control unit 1244 1245config HAVE_ARM_ARCH_TIMER 1246 bool "Architected timer support" 1247 depends on CPU_V7 1248 select ARM_ARCH_TIMER 1249 help 1250 This option enables support for the ARM architected timer 1251 1252config HAVE_ARM_TWD 1253 bool 1254 help 1255 This options enables support for the ARM timer and watchdog unit 1256 1257config MCPM 1258 bool "Multi-Cluster Power Management" 1259 depends on CPU_V7 && SMP 1260 help 1261 This option provides the common power management infrastructure 1262 for (multi-)cluster based systems, such as big.LITTLE based 1263 systems. 1264 1265config MCPM_QUAD_CLUSTER 1266 bool 1267 depends on MCPM 1268 help 1269 To avoid wasting resources unnecessarily, MCPM only supports up 1270 to 2 clusters by default. 1271 Platforms with 3 or 4 clusters that use MCPM must select this 1272 option to allow the additional clusters to be managed. 1273 1274config BIG_LITTLE 1275 bool "big.LITTLE support (Experimental)" 1276 depends on CPU_V7 && SMP 1277 select MCPM 1278 help 1279 This option enables support selections for the big.LITTLE 1280 system architecture. 1281 1282config BL_SWITCHER 1283 bool "big.LITTLE switcher support" 1284 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1285 select CPU_PM 1286 help 1287 The big.LITTLE "switcher" provides the core functionality to 1288 transparently handle transition between a cluster of A15's 1289 and a cluster of A7's in a big.LITTLE system. 1290 1291config BL_SWITCHER_DUMMY_IF 1292 tristate "Simple big.LITTLE switcher user interface" 1293 depends on BL_SWITCHER && DEBUG_KERNEL 1294 help 1295 This is a simple and dummy char dev interface to control 1296 the big.LITTLE switcher core code. It is meant for 1297 debugging purposes only. 1298 1299choice 1300 prompt "Memory split" 1301 depends on MMU 1302 default VMSPLIT_3G 1303 help 1304 Select the desired split between kernel and user memory. 1305 1306 If you are not absolutely sure what you are doing, leave this 1307 option alone! 1308 1309 config VMSPLIT_3G 1310 bool "3G/1G user/kernel split" 1311 config VMSPLIT_3G_OPT 1312 depends on !ARM_LPAE 1313 bool "3G/1G user/kernel split (for full 1G low memory)" 1314 config VMSPLIT_2G 1315 bool "2G/2G user/kernel split" 1316 config VMSPLIT_1G 1317 bool "1G/3G user/kernel split" 1318endchoice 1319 1320config PAGE_OFFSET 1321 hex 1322 default PHYS_OFFSET if !MMU 1323 default 0x40000000 if VMSPLIT_1G 1324 default 0x80000000 if VMSPLIT_2G 1325 default 0xB0000000 if VMSPLIT_3G_OPT 1326 default 0xC0000000 1327 1328config NR_CPUS 1329 int "Maximum number of CPUs (2-32)" 1330 range 2 32 1331 depends on SMP 1332 default "4" 1333 1334config HOTPLUG_CPU 1335 bool "Support for hot-pluggable CPUs" 1336 depends on SMP 1337 select GENERIC_IRQ_MIGRATION 1338 help 1339 Say Y here to experiment with turning CPUs off and on. CPUs 1340 can be controlled through /sys/devices/system/cpu. 1341 1342config ARM_PSCI 1343 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1344 depends on HAVE_ARM_SMCCC 1345 select ARM_PSCI_FW 1346 help 1347 Say Y here if you want Linux to communicate with system firmware 1348 implementing the PSCI specification for CPU-centric power 1349 management operations described in ARM document number ARM DEN 1350 0022A ("Power State Coordination Interface System Software on 1351 ARM processors"). 1352 1353# The GPIO number here must be sorted by descending number. In case of 1354# a multiplatform kernel, we just want the highest value required by the 1355# selected platforms. 1356config ARCH_NR_GPIO 1357 int 1358 default 2048 if ARCH_SOCFPGA 1359 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1360 ARCH_ZYNQ || ARCH_ASPEED 1361 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1362 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1363 default 416 if ARCH_SUNXI 1364 default 392 if ARCH_U8500 1365 default 352 if ARCH_VT8500 1366 default 288 if ARCH_ROCKCHIP 1367 default 264 if MACH_H4700 1368 default 0 1369 help 1370 Maximum number of GPIOs in the system. 1371 1372 If unsure, leave the default value. 1373 1374config HZ_FIXED 1375 int 1376 default 200 if ARCH_EBSA110 1377 default 128 if SOC_AT91RM9200 1378 default 0 1379 1380choice 1381 depends on HZ_FIXED = 0 1382 prompt "Timer frequency" 1383 1384config HZ_100 1385 bool "100 Hz" 1386 1387config HZ_200 1388 bool "200 Hz" 1389 1390config HZ_250 1391 bool "250 Hz" 1392 1393config HZ_300 1394 bool "300 Hz" 1395 1396config HZ_500 1397 bool "500 Hz" 1398 1399config HZ_1000 1400 bool "1000 Hz" 1401 1402endchoice 1403 1404config HZ 1405 int 1406 default HZ_FIXED if HZ_FIXED != 0 1407 default 100 if HZ_100 1408 default 200 if HZ_200 1409 default 250 if HZ_250 1410 default 300 if HZ_300 1411 default 500 if HZ_500 1412 default 1000 1413 1414config SCHED_HRTICK 1415 def_bool HIGH_RES_TIMERS 1416 1417config THUMB2_KERNEL 1418 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1419 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1420 default y if CPU_THUMBONLY 1421 select ARM_UNWIND 1422 help 1423 By enabling this option, the kernel will be compiled in 1424 Thumb-2 mode. 1425 1426 If unsure, say N. 1427 1428config ARM_PATCH_IDIV 1429 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1430 depends on CPU_32v7 && !XIP_KERNEL 1431 default y 1432 help 1433 The ARM compiler inserts calls to __aeabi_idiv() and 1434 __aeabi_uidiv() when it needs to perform division on signed 1435 and unsigned integers. Some v7 CPUs have support for the sdiv 1436 and udiv instructions that can be used to implement those 1437 functions. 1438 1439 Enabling this option allows the kernel to modify itself to 1440 replace the first two instructions of these library functions 1441 with the sdiv or udiv plus "bx lr" instructions when the CPU 1442 it is running on supports them. Typically this will be faster 1443 and less power intensive than running the original library 1444 code to do integer division. 1445 1446config AEABI 1447 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1448 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1449 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1450 help 1451 This option allows for the kernel to be compiled using the latest 1452 ARM ABI (aka EABI). This is only useful if you are using a user 1453 space environment that is also compiled with EABI. 1454 1455 Since there are major incompatibilities between the legacy ABI and 1456 EABI, especially with regard to structure member alignment, this 1457 option also changes the kernel syscall calling convention to 1458 disambiguate both ABIs and allow for backward compatibility support 1459 (selected with CONFIG_OABI_COMPAT). 1460 1461 To use this you need GCC version 4.0.0 or later. 1462 1463config OABI_COMPAT 1464 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1465 depends on AEABI && !THUMB2_KERNEL 1466 help 1467 This option preserves the old syscall interface along with the 1468 new (ARM EABI) one. It also provides a compatibility layer to 1469 intercept syscalls that have structure arguments which layout 1470 in memory differs between the legacy ABI and the new ARM EABI 1471 (only for non "thumb" binaries). This option adds a tiny 1472 overhead to all syscalls and produces a slightly larger kernel. 1473 1474 The seccomp filter system will not be available when this is 1475 selected, since there is no way yet to sensibly distinguish 1476 between calling conventions during filtering. 1477 1478 If you know you'll be using only pure EABI user space then you 1479 can say N here. If this option is not selected and you attempt 1480 to execute a legacy ABI binary then the result will be 1481 UNPREDICTABLE (in fact it can be predicted that it won't work 1482 at all). If in doubt say N. 1483 1484config ARCH_HAS_HOLES_MEMORYMODEL 1485 bool 1486 1487config ARCH_SELECT_MEMORY_MODEL 1488 bool 1489 1490config ARCH_FLATMEM_ENABLE 1491 bool 1492 1493config ARCH_SPARSEMEM_ENABLE 1494 bool 1495 select SPARSEMEM_STATIC if SPARSEMEM 1496 1497config HAVE_ARCH_PFN_VALID 1498 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1499 1500config HIGHMEM 1501 bool "High Memory Support" 1502 depends on MMU 1503 help 1504 The address space of ARM processors is only 4 Gigabytes large 1505 and it has to accommodate user address space, kernel address 1506 space as well as some memory mapped IO. That means that, if you 1507 have a large amount of physical memory and/or IO, not all of the 1508 memory can be "permanently mapped" by the kernel. The physical 1509 memory that is not permanently mapped is called "high memory". 1510 1511 Depending on the selected kernel/user memory split, minimum 1512 vmalloc space and actual amount of RAM, you may not need this 1513 option which should result in a slightly faster kernel. 1514 1515 If unsure, say n. 1516 1517config HIGHPTE 1518 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1519 depends on HIGHMEM 1520 default y 1521 help 1522 The VM uses one page of physical memory for each page table. 1523 For systems with a lot of processes, this can use a lot of 1524 precious low memory, eventually leading to low memory being 1525 consumed by page tables. Setting this option will allow 1526 user-space 2nd level page tables to reside in high memory. 1527 1528config CPU_SW_DOMAIN_PAN 1529 bool "Enable use of CPU domains to implement privileged no-access" 1530 depends on MMU && !ARM_LPAE 1531 default y 1532 help 1533 Increase kernel security by ensuring that normal kernel accesses 1534 are unable to access userspace addresses. This can help prevent 1535 use-after-free bugs becoming an exploitable privilege escalation 1536 by ensuring that magic values (such as LIST_POISON) will always 1537 fault when dereferenced. 1538 1539 CPUs with low-vector mappings use a best-efforts implementation. 1540 Their lower 1MB needs to remain accessible for the vectors, but 1541 the remainder of userspace will become appropriately inaccessible. 1542 1543config HW_PERF_EVENTS 1544 def_bool y 1545 depends on ARM_PMU 1546 1547config SYS_SUPPORTS_HUGETLBFS 1548 def_bool y 1549 depends on ARM_LPAE 1550 1551config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1552 def_bool y 1553 depends on ARM_LPAE 1554 1555config ARCH_WANT_GENERAL_HUGETLB 1556 def_bool y 1557 1558config ARM_MODULE_PLTS 1559 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1560 depends on MODULES 1561 default y 1562 help 1563 Allocate PLTs when loading modules so that jumps and calls whose 1564 targets are too far away for their relative offsets to be encoded 1565 in the instructions themselves can be bounced via veneers in the 1566 module's PLT. This allows modules to be allocated in the generic 1567 vmalloc area after the dedicated module memory area has been 1568 exhausted. The modules will use slightly more memory, but after 1569 rounding up to page size, the actual memory footprint is usually 1570 the same. 1571 1572 Disabling this is usually safe for small single-platform 1573 configurations. If unsure, say y. 1574 1575config FORCE_MAX_ZONEORDER 1576 int "Maximum zone order" 1577 default "12" if SOC_AM33XX 1578 default "9" if SA1111 || ARCH_EFM32 1579 default "11" 1580 help 1581 The kernel memory allocator divides physically contiguous memory 1582 blocks into "zones", where each zone is a power of two number of 1583 pages. This option selects the largest power of two that the kernel 1584 keeps in the memory allocator. If you need to allocate very large 1585 blocks of physically contiguous memory, then you may need to 1586 increase this value. 1587 1588 This config option is actually maximum order plus one. For example, 1589 a value of 11 means that the largest free memory block is 2^10 pages. 1590 1591config ALIGNMENT_TRAP 1592 bool 1593 depends on CPU_CP15_MMU 1594 default y if !ARCH_EBSA110 1595 select HAVE_PROC_CPU if PROC_FS 1596 help 1597 ARM processors cannot fetch/store information which is not 1598 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1599 address divisible by 4. On 32-bit ARM processors, these non-aligned 1600 fetch/store instructions will be emulated in software if you say 1601 here, which has a severe performance impact. This is necessary for 1602 correct operation of some network protocols. With an IP-only 1603 configuration it is safe to say N, otherwise say Y. 1604 1605config UACCESS_WITH_MEMCPY 1606 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1607 depends on MMU 1608 default y if CPU_FEROCEON 1609 help 1610 Implement faster copy_to_user and clear_user methods for CPU 1611 cores where a 8-word STM instruction give significantly higher 1612 memory write throughput than a sequence of individual 32bit stores. 1613 1614 A possible side effect is a slight increase in scheduling latency 1615 between threads sharing the same address space if they invoke 1616 such copy operations with large buffers. 1617 1618 However, if the CPU data cache is using a write-allocate mode, 1619 this option is unlikely to provide any performance gain. 1620 1621config SECCOMP 1622 bool 1623 prompt "Enable seccomp to safely compute untrusted bytecode" 1624 help 1625 This kernel feature is useful for number crunching applications 1626 that may need to compute untrusted bytecode during their 1627 execution. By using pipes or other transports made available to 1628 the process as file descriptors supporting the read/write 1629 syscalls, it's possible to isolate those applications in 1630 their own address space using seccomp. Once seccomp is 1631 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1632 and the task is only allowed to execute a few safe syscalls 1633 defined by each seccomp mode. 1634 1635config PARAVIRT 1636 bool "Enable paravirtualization code" 1637 help 1638 This changes the kernel so it can modify itself when it is run 1639 under a hypervisor, potentially improving performance significantly 1640 over full virtualization. 1641 1642config PARAVIRT_TIME_ACCOUNTING 1643 bool "Paravirtual steal time accounting" 1644 select PARAVIRT 1645 help 1646 Select this option to enable fine granularity task steal time 1647 accounting. Time spent executing other tasks in parallel with 1648 the current vCPU is discounted from the vCPU power. To account for 1649 that, there can be a small performance impact. 1650 1651 If in doubt, say N here. 1652 1653config XEN_DOM0 1654 def_bool y 1655 depends on XEN 1656 1657config XEN 1658 bool "Xen guest support on ARM" 1659 depends on ARM && AEABI && OF 1660 depends on CPU_V7 && !CPU_V6 1661 depends on !GENERIC_ATOMIC64 1662 depends on MMU 1663 select ARCH_DMA_ADDR_T_64BIT 1664 select ARM_PSCI 1665 select SWIOTLB 1666 select SWIOTLB_XEN 1667 select PARAVIRT 1668 help 1669 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1670 1671config STACKPROTECTOR_PER_TASK 1672 bool "Use a unique stack canary value for each task" 1673 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1674 select GCC_PLUGIN_ARM_SSP_PER_TASK 1675 default y 1676 help 1677 Due to the fact that GCC uses an ordinary symbol reference from 1678 which to load the value of the stack canary, this value can only 1679 change at reboot time on SMP systems, and all tasks running in the 1680 kernel's address space are forced to use the same canary value for 1681 the entire duration that the system is up. 1682 1683 Enable this option to switch to a different method that uses a 1684 different canary value for each task. 1685 1686endmenu 1687 1688menu "Boot options" 1689 1690config USE_OF 1691 bool "Flattened Device Tree support" 1692 select IRQ_DOMAIN 1693 select OF 1694 help 1695 Include support for flattened device tree machine descriptions. 1696 1697config ATAGS 1698 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1699 default y 1700 help 1701 This is the traditional way of passing data to the kernel at boot 1702 time. If you are solely relying on the flattened device tree (or 1703 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1704 to remove ATAGS support from your kernel binary. If unsure, 1705 leave this to y. 1706 1707config DEPRECATED_PARAM_STRUCT 1708 bool "Provide old way to pass kernel parameters" 1709 depends on ATAGS 1710 help 1711 This was deprecated in 2001 and announced to live on for 5 years. 1712 Some old boot loaders still use this way. 1713 1714# Compressed boot loader in ROM. Yes, we really want to ask about 1715# TEXT and BSS so we preserve their values in the config files. 1716config ZBOOT_ROM_TEXT 1717 hex "Compressed ROM boot loader base address" 1718 default 0x0 1719 help 1720 The physical address at which the ROM-able zImage is to be 1721 placed in the target. Platforms which normally make use of 1722 ROM-able zImage formats normally set this to a suitable 1723 value in their defconfig file. 1724 1725 If ZBOOT_ROM is not enabled, this has no effect. 1726 1727config ZBOOT_ROM_BSS 1728 hex "Compressed ROM boot loader BSS address" 1729 default 0x0 1730 help 1731 The base address of an area of read/write memory in the target 1732 for the ROM-able zImage which must be available while the 1733 decompressor is running. It must be large enough to hold the 1734 entire decompressed kernel plus an additional 128 KiB. 1735 Platforms which normally make use of ROM-able zImage formats 1736 normally set this to a suitable value in their defconfig file. 1737 1738 If ZBOOT_ROM is not enabled, this has no effect. 1739 1740config ZBOOT_ROM 1741 bool "Compressed boot loader in ROM/flash" 1742 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1743 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1744 help 1745 Say Y here if you intend to execute your compressed kernel image 1746 (zImage) directly from ROM or flash. If unsure, say N. 1747 1748config ARM_APPENDED_DTB 1749 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1750 depends on OF 1751 help 1752 With this option, the boot code will look for a device tree binary 1753 (DTB) appended to zImage 1754 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1755 1756 This is meant as a backward compatibility convenience for those 1757 systems with a bootloader that can't be upgraded to accommodate 1758 the documented boot protocol using a device tree. 1759 1760 Beware that there is very little in terms of protection against 1761 this option being confused by leftover garbage in memory that might 1762 look like a DTB header after a reboot if no actual DTB is appended 1763 to zImage. Do not leave this option active in a production kernel 1764 if you don't intend to always append a DTB. Proper passing of the 1765 location into r2 of a bootloader provided DTB is always preferable 1766 to this option. 1767 1768config ARM_ATAG_DTB_COMPAT 1769 bool "Supplement the appended DTB with traditional ATAG information" 1770 depends on ARM_APPENDED_DTB 1771 help 1772 Some old bootloaders can't be updated to a DTB capable one, yet 1773 they provide ATAGs with memory configuration, the ramdisk address, 1774 the kernel cmdline string, etc. Such information is dynamically 1775 provided by the bootloader and can't always be stored in a static 1776 DTB. To allow a device tree enabled kernel to be used with such 1777 bootloaders, this option allows zImage to extract the information 1778 from the ATAG list and store it at run time into the appended DTB. 1779 1780choice 1781 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1782 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1783 1784config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1785 bool "Use bootloader kernel arguments if available" 1786 help 1787 Uses the command-line options passed by the boot loader instead of 1788 the device tree bootargs property. If the boot loader doesn't provide 1789 any, the device tree bootargs property will be used. 1790 1791config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1792 bool "Extend with bootloader kernel arguments" 1793 help 1794 The command-line arguments provided by the boot loader will be 1795 appended to the the device tree bootargs property. 1796 1797endchoice 1798 1799config CMDLINE 1800 string "Default kernel command string" 1801 default "" 1802 help 1803 On some architectures (EBSA110 and CATS), there is currently no way 1804 for the boot loader to pass arguments to the kernel. For these 1805 architectures, you should supply some command-line options at build 1806 time by entering them here. As a minimum, you should specify the 1807 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1808 1809choice 1810 prompt "Kernel command line type" if CMDLINE != "" 1811 default CMDLINE_FROM_BOOTLOADER 1812 depends on ATAGS 1813 1814config CMDLINE_FROM_BOOTLOADER 1815 bool "Use bootloader kernel arguments if available" 1816 help 1817 Uses the command-line options passed by the boot loader. If 1818 the boot loader doesn't provide any, the default kernel command 1819 string provided in CMDLINE will be used. 1820 1821config CMDLINE_EXTEND 1822 bool "Extend bootloader kernel arguments" 1823 help 1824 The command-line arguments provided by the boot loader will be 1825 appended to the default kernel command string. 1826 1827config CMDLINE_FORCE 1828 bool "Always use the default kernel command string" 1829 help 1830 Always use the default kernel command string, even if the boot 1831 loader passes other arguments to the kernel. 1832 This is useful if you cannot or don't want to change the 1833 command-line options your boot loader passes to the kernel. 1834endchoice 1835 1836config XIP_KERNEL 1837 bool "Kernel Execute-In-Place from ROM" 1838 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1839 help 1840 Execute-In-Place allows the kernel to run from non-volatile storage 1841 directly addressable by the CPU, such as NOR flash. This saves RAM 1842 space since the text section of the kernel is not loaded from flash 1843 to RAM. Read-write sections, such as the data section and stack, 1844 are still copied to RAM. The XIP kernel is not compressed since 1845 it has to run directly from flash, so it will take more space to 1846 store it. The flash address used to link the kernel object files, 1847 and for storing it, is configuration dependent. Therefore, if you 1848 say Y here, you must know the proper physical address where to 1849 store the kernel image depending on your own flash memory usage. 1850 1851 Also note that the make target becomes "make xipImage" rather than 1852 "make zImage" or "make Image". The final kernel binary to put in 1853 ROM memory will be arch/arm/boot/xipImage. 1854 1855 If unsure, say N. 1856 1857config XIP_PHYS_ADDR 1858 hex "XIP Kernel Physical Location" 1859 depends on XIP_KERNEL 1860 default "0x00080000" 1861 help 1862 This is the physical address in your flash memory the kernel will 1863 be linked for and stored to. This address is dependent on your 1864 own flash usage. 1865 1866config XIP_DEFLATED_DATA 1867 bool "Store kernel .data section compressed in ROM" 1868 depends on XIP_KERNEL 1869 select ZLIB_INFLATE 1870 help 1871 Before the kernel is actually executed, its .data section has to be 1872 copied to RAM from ROM. This option allows for storing that data 1873 in compressed form and decompressed to RAM rather than merely being 1874 copied, saving some precious ROM space. A possible drawback is a 1875 slightly longer boot delay. 1876 1877config KEXEC 1878 bool "Kexec system call (EXPERIMENTAL)" 1879 depends on (!SMP || PM_SLEEP_SMP) 1880 depends on MMU 1881 select KEXEC_CORE 1882 help 1883 kexec is a system call that implements the ability to shutdown your 1884 current kernel, and to start another kernel. It is like a reboot 1885 but it is independent of the system firmware. And like a reboot 1886 you can start any kernel with it, not just Linux. 1887 1888 It is an ongoing process to be certain the hardware in a machine 1889 is properly shutdown, so do not be surprised if this code does not 1890 initially work for you. 1891 1892config ATAGS_PROC 1893 bool "Export atags in procfs" 1894 depends on ATAGS && KEXEC 1895 default y 1896 help 1897 Should the atags used to boot the kernel be exported in an "atags" 1898 file in procfs. Useful with kexec. 1899 1900config CRASH_DUMP 1901 bool "Build kdump crash kernel (EXPERIMENTAL)" 1902 help 1903 Generate crash dump after being started by kexec. This should 1904 be normally only set in special crash dump kernels which are 1905 loaded in the main kernel with kexec-tools into a specially 1906 reserved region and then later executed after a crash by 1907 kdump/kexec. The crash dump kernel must be compiled to a 1908 memory address not used by the main kernel 1909 1910 For more details see Documentation/admin-guide/kdump/kdump.rst 1911 1912config AUTO_ZRELADDR 1913 bool "Auto calculation of the decompressed kernel image address" 1914 help 1915 ZRELADDR is the physical address where the decompressed kernel 1916 image will be placed. If AUTO_ZRELADDR is selected, the address 1917 will be determined at run-time by masking the current IP with 1918 0xf8000000. This assumes the zImage being placed in the first 128MB 1919 from start of memory. 1920 1921config EFI_STUB 1922 bool 1923 1924config EFI 1925 bool "UEFI runtime support" 1926 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1927 select UCS2_STRING 1928 select EFI_PARAMS_FROM_FDT 1929 select EFI_STUB 1930 select EFI_GENERIC_STUB 1931 select EFI_RUNTIME_WRAPPERS 1932 help 1933 This option provides support for runtime services provided 1934 by UEFI firmware (such as non-volatile variables, realtime 1935 clock, and platform reset). A UEFI stub is also provided to 1936 allow the kernel to be booted as an EFI application. This 1937 is only useful for kernels that may run on systems that have 1938 UEFI firmware. 1939 1940config DMI 1941 bool "Enable support for SMBIOS (DMI) tables" 1942 depends on EFI 1943 default y 1944 help 1945 This enables SMBIOS/DMI feature for systems. 1946 1947 This option is only useful on systems that have UEFI firmware. 1948 However, even with this option, the resultant kernel should 1949 continue to boot on existing non-UEFI platforms. 1950 1951 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1952 i.e., the the practice of identifying the platform via DMI to 1953 decide whether certain workarounds for buggy hardware and/or 1954 firmware need to be enabled. This would require the DMI subsystem 1955 to be enabled much earlier than we do on ARM, which is non-trivial. 1956 1957endmenu 1958 1959menu "CPU Power Management" 1960 1961source "drivers/cpufreq/Kconfig" 1962 1963source "drivers/cpuidle/Kconfig" 1964 1965endmenu 1966 1967menu "Floating point emulation" 1968 1969comment "At least one emulation must be selected" 1970 1971config FPE_NWFPE 1972 bool "NWFPE math emulation" 1973 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1974 help 1975 Say Y to include the NWFPE floating point emulator in the kernel. 1976 This is necessary to run most binaries. Linux does not currently 1977 support floating point hardware so you need to say Y here even if 1978 your machine has an FPA or floating point co-processor podule. 1979 1980 You may say N here if you are going to load the Acorn FPEmulator 1981 early in the bootup. 1982 1983config FPE_NWFPE_XP 1984 bool "Support extended precision" 1985 depends on FPE_NWFPE 1986 help 1987 Say Y to include 80-bit support in the kernel floating-point 1988 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1989 Note that gcc does not generate 80-bit operations by default, 1990 so in most cases this option only enlarges the size of the 1991 floating point emulator without any good reason. 1992 1993 You almost surely want to say N here. 1994 1995config FPE_FASTFPE 1996 bool "FastFPE math emulation (EXPERIMENTAL)" 1997 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1998 help 1999 Say Y here to include the FAST floating point emulator in the kernel. 2000 This is an experimental much faster emulator which now also has full 2001 precision for the mantissa. It does not support any exceptions. 2002 It is very simple, and approximately 3-6 times faster than NWFPE. 2003 2004 It should be sufficient for most programs. It may be not suitable 2005 for scientific calculations, but you have to check this for yourself. 2006 If you do not feel you need a faster FP emulation you should better 2007 choose NWFPE. 2008 2009config VFP 2010 bool "VFP-format floating point maths" 2011 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2012 help 2013 Say Y to include VFP support code in the kernel. This is needed 2014 if your hardware includes a VFP unit. 2015 2016 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2017 release notes and additional status information. 2018 2019 Say N if your target does not have VFP hardware. 2020 2021config VFPv3 2022 bool 2023 depends on VFP 2024 default y if CPU_V7 2025 2026config NEON 2027 bool "Advanced SIMD (NEON) Extension support" 2028 depends on VFPv3 && CPU_V7 2029 help 2030 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2031 Extension. 2032 2033config KERNEL_MODE_NEON 2034 bool "Support for NEON in kernel mode" 2035 depends on NEON && AEABI 2036 help 2037 Say Y to include support for NEON in kernel mode. 2038 2039endmenu 2040 2041menu "Power management options" 2042 2043source "kernel/power/Kconfig" 2044 2045config ARCH_SUSPEND_POSSIBLE 2046 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2047 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2048 def_bool y 2049 2050config ARM_CPU_SUSPEND 2051 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2052 depends on ARCH_SUSPEND_POSSIBLE 2053 2054config ARCH_HIBERNATION_POSSIBLE 2055 bool 2056 depends on MMU 2057 default y if ARCH_SUSPEND_POSSIBLE 2058 2059endmenu 2060 2061source "drivers/firmware/Kconfig" 2062 2063if CRYPTO 2064source "arch/arm/crypto/Kconfig" 2065endif 2066 2067source "arch/arm/Kconfig.assembler" 2068