1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_USE_MEMTEST 39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 40 select ARCH_WANT_IPC_PARSE_VERSION 41 select ARCH_WANT_LD_ORPHAN_WARN 42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 43 select BUILDTIME_TABLE_SORT if MMU 44 select CLONE_BACKWARDS 45 select CPU_PM if SUSPEND || CPU_IDLE 46 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 47 select DMA_DECLARE_COHERENT 48 select DMA_GLOBAL_POOL if !MMU 49 select DMA_OPS 50 select DMA_REMAP if MMU 51 select EDAC_SUPPORT 52 select EDAC_ATOMIC_SCRUB 53 select GENERIC_ALLOCATOR 54 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 55 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 56 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 57 select GENERIC_IRQ_IPI if SMP 58 select GENERIC_CPU_AUTOPROBE 59 select GENERIC_EARLY_IOREMAP 60 select GENERIC_IDLE_POLL_SETUP 61 select GENERIC_IRQ_PROBE 62 select GENERIC_IRQ_SHOW 63 select GENERIC_IRQ_SHOW_LEVEL 64 select GENERIC_LIB_DEVMEM_IS_ALLOWED 65 select GENERIC_PCI_IOMAP 66 select GENERIC_SCHED_CLOCK 67 select GENERIC_SMP_IDLE_THREAD 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_BUILDTIME_MCOUNT_SORT 87 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 88 select HAVE_DMA_CONTIGUOUS if MMU 89 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 90 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 91 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 92 select HAVE_EXIT_THREAD 93 select HAVE_FAST_GUP if ARM_LPAE 94 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 95 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 96 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) 97 select HAVE_GCC_PLUGINS 98 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 99 select HAVE_IRQ_TIME_ACCOUNTING 100 select HAVE_KERNEL_GZIP 101 select HAVE_KERNEL_LZ4 102 select HAVE_KERNEL_LZMA 103 select HAVE_KERNEL_LZO 104 select HAVE_KERNEL_XZ 105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 106 select HAVE_KRETPROBES if HAVE_KPROBES 107 select HAVE_MOD_ARCH_SPECIFIC 108 select HAVE_NMI 109 select HAVE_OPTPROBES if !THUMB2_KERNEL 110 select HAVE_PERF_EVENTS 111 select HAVE_PERF_REGS 112 select HAVE_PERF_USER_STACK_DUMP 113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 114 select HAVE_REGS_AND_STACK_ACCESS_API 115 select HAVE_RSEQ 116 select HAVE_STACKPROTECTOR 117 select HAVE_SYSCALL_TRACEPOINTS 118 select HAVE_UID16 119 select HAVE_VIRT_CPU_ACCOUNTING_GEN 120 select IRQ_FORCED_THREADING 121 select MODULES_USE_ELF_REL 122 select NEED_DMA_MAP_STATE 123 select OF_EARLY_FLATTREE if OF 124 select OLD_SIGACTION 125 select OLD_SIGSUSPEND3 126 select PCI_SYSCALL if PCI 127 select PERF_USE_VMALLOC 128 select RTC_LIB 129 select SYS_SUPPORTS_APM_EMULATION 130 select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO 131 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 132 # Above selects are sorted alphabetically; please add new ones 133 # according to that. Thanks. 134 help 135 The ARM series is a line of low-power-consumption RISC chip designs 136 licensed by ARM Ltd and targeted at embedded applications and 137 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 138 manufactured, but legacy ARM-based PC hardware remains popular in 139 Europe. There is an ARM Linux project with a web page at 140 <http://www.arm.linux.org.uk/>. 141 142config ARM_HAS_SG_CHAIN 143 bool 144 145config ARM_DMA_USE_IOMMU 146 bool 147 select ARM_HAS_SG_CHAIN 148 select NEED_SG_DMA_LENGTH 149 150if ARM_DMA_USE_IOMMU 151 152config ARM_DMA_IOMMU_ALIGNMENT 153 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 154 range 4 9 155 default 8 156 help 157 DMA mapping framework by default aligns all buffers to the smallest 158 PAGE_SIZE order which is greater than or equal to the requested buffer 159 size. This works well for buffers up to a few hundreds kilobytes, but 160 for larger buffers it just a waste of address space. Drivers which has 161 relatively small addressing window (like 64Mib) might run out of 162 virtual space with just a few allocations. 163 164 With this parameter you can specify the maximum PAGE_SIZE order for 165 DMA IOMMU buffers. Larger buffers will be aligned only to this 166 specified order. The order is expressed as a power of two multiplied 167 by the PAGE_SIZE. 168 169endif 170 171config SYS_SUPPORTS_APM_EMULATION 172 bool 173 174config HAVE_TCM 175 bool 176 select GENERIC_ALLOCATOR 177 178config HAVE_PROC_CPU 179 bool 180 181config NO_IOPORT_MAP 182 bool 183 184config SBUS 185 bool 186 187config STACKTRACE_SUPPORT 188 bool 189 default y 190 191config LOCKDEP_SUPPORT 192 bool 193 default y 194 195config ARCH_HAS_ILOG2_U32 196 bool 197 198config ARCH_HAS_ILOG2_U64 199 bool 200 201config ARCH_HAS_BANDGAP 202 bool 203 204config FIX_EARLYCON_MEM 205 def_bool y if MMU 206 207config GENERIC_HWEIGHT 208 bool 209 default y 210 211config GENERIC_CALIBRATE_DELAY 212 bool 213 default y 214 215config ARCH_MAY_HAVE_PC_FDC 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config ARM_PATCH_PHYS_VIRT 237 bool "Patch physical to virtual translations at runtime" if EMBEDDED 238 default y 239 depends on !XIP_KERNEL && MMU 240 help 241 Patch phys-to-virt and virt-to-phys translation functions at 242 boot and module load time according to the position of the 243 kernel in system memory. 244 245 This can only be used with non-XIP MMU kernels where the base 246 of physical memory is at a 2 MiB boundary. 247 248 Only disable this option if you know that you do not require 249 this feature (eg, building a kernel for a single machine) and 250 you need to shrink the kernel to the minimal size. 251 252config NEED_MACH_IO_H 253 bool 254 help 255 Select this when mach/io.h is required to provide special 256 definitions for this platform. The need for mach/io.h should 257 be avoided when possible. 258 259config NEED_MACH_MEMORY_H 260 bool 261 help 262 Select this when mach/memory.h is required to provide special 263 definitions for this platform. The need for mach/memory.h should 264 be avoided when possible. 265 266config PHYS_OFFSET 267 hex "Physical address of main memory" if MMU 268 depends on !ARM_PATCH_PHYS_VIRT 269 default DRAM_BASE if !MMU 270 default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x30000000 if ARCH_S3C24XX 273 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 274 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 275 default 0 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARCH_FLATMEM_ENABLE 319 select ARCH_SPARSEMEM_ENABLE 320 select ARCH_SELECT_MEMORY_MODEL 321 select ARM_HAS_SG_CHAIN 322 select ARM_PATCH_PHYS_VIRT 323 select AUTO_ZRELADDR 324 select TIMER_OF 325 select COMMON_CLK 326 select GENERIC_IRQ_MULTI_HANDLER 327 select HAVE_PCI 328 select PCI_DOMAINS_GENERIC if PCI 329 select SPARSE_IRQ 330 select USE_OF 331 332config ARM_SINGLE_ARMV7M 333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 334 depends on !MMU 335 select ARM_NVIC 336 select AUTO_ZRELADDR 337 select TIMER_OF 338 select COMMON_CLK 339 select CPU_V7M 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EP93XX 345 bool "EP93xx-based" 346 select ARCH_SPARSEMEM_ENABLE 347 select ARM_AMBA 348 imply ARM_PATCH_PHYS_VIRT 349 select ARM_VIC 350 select GENERIC_IRQ_MULTI_HANDLER 351 select AUTO_ZRELADDR 352 select CLKSRC_MMIO 353 select CPU_ARM920T 354 select GPIOLIB 355 select COMMON_CLK 356 help 357 This enables support for the Cirrus EP93xx series of CPUs. 358 359config ARCH_FOOTBRIDGE 360 bool "FootBridge" 361 select CPU_SA110 362 select FOOTBRIDGE 363 select NEED_MACH_IO_H if !MMU 364 select NEED_MACH_MEMORY_H 365 help 366 Support for systems based on the DC21285 companion chip 367 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 368 369config ARCH_IOP32X 370 bool "IOP32x-based" 371 depends on MMU 372 select CPU_XSCALE 373 select GPIO_IOP 374 select GPIOLIB 375 select NEED_RET_TO_USER 376 select FORCE_PCI 377 select PLAT_IOP 378 help 379 Support for Intel's 80219 and IOP32X (XScale) family of 380 processors. 381 382config ARCH_IXP4XX 383 bool "IXP4xx-based" 384 depends on MMU 385 select ARCH_HAS_DMA_SET_COHERENT_MASK 386 select ARCH_SUPPORTS_BIG_ENDIAN 387 select CPU_XSCALE 388 select DMABOUNCE if PCI 389 select GENERIC_IRQ_MULTI_HANDLER 390 select GPIO_IXP4XX 391 select GPIOLIB 392 select HAVE_PCI 393 select IXP4XX_IRQ 394 select IXP4XX_TIMER 395 # With the new PCI driver this is not needed 396 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 397 select USB_EHCI_BIG_ENDIAN_DESC 398 select USB_EHCI_BIG_ENDIAN_MMIO 399 help 400 Support for Intel's IXP4XX (XScale) family of processors. 401 402config ARCH_DOVE 403 bool "Marvell Dove" 404 select CPU_PJ4 405 select GENERIC_IRQ_MULTI_HANDLER 406 select GPIOLIB 407 select HAVE_PCI 408 select MVEBU_MBUS 409 select PINCTRL 410 select PINCTRL_DOVE 411 select PLAT_ORION_LEGACY 412 select SPARSE_IRQ 413 select PM_GENERIC_DOMAINS if PM 414 help 415 Support for the Marvell Dove SoC 88AP510 416 417config ARCH_PXA 418 bool "PXA2xx/PXA3xx-based" 419 depends on MMU 420 select ARCH_MTD_XIP 421 select ARM_CPU_SUSPEND if PM 422 select AUTO_ZRELADDR 423 select COMMON_CLK 424 select CLKSRC_PXA 425 select CLKSRC_MMIO 426 select TIMER_OF 427 select CPU_XSCALE if !CPU_XSC3 428 select GENERIC_IRQ_MULTI_HANDLER 429 select GPIO_PXA 430 select GPIOLIB 431 select IRQ_DOMAIN 432 select PLAT_PXA 433 select SPARSE_IRQ 434 help 435 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 436 437config ARCH_RPC 438 bool "RiscPC" 439 depends on MMU 440 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 441 select ARCH_ACORN 442 select ARCH_MAY_HAVE_PC_FDC 443 select ARCH_SPARSEMEM_ENABLE 444 select ARM_HAS_SG_CHAIN 445 select CPU_SA110 446 select FIQ 447 select HAVE_PATA_PLATFORM 448 select ISA_DMA_API 449 select LEGACY_TIMER_TICK 450 select NEED_MACH_IO_H 451 select NEED_MACH_MEMORY_H 452 select NO_IOPORT_MAP 453 help 454 On the Acorn Risc-PC, Linux can support the internal IDE disk and 455 CD-ROM interface, serial and parallel port, and the floppy drive. 456 457config ARCH_SA1100 458 bool "SA1100-based" 459 select ARCH_MTD_XIP 460 select ARCH_SPARSEMEM_ENABLE 461 select CLKSRC_MMIO 462 select CLKSRC_PXA 463 select TIMER_OF if OF 464 select COMMON_CLK 465 select CPU_FREQ 466 select CPU_SA1100 467 select GENERIC_IRQ_MULTI_HANDLER 468 select GPIOLIB 469 select IRQ_DOMAIN 470 select ISA 471 select NEED_MACH_MEMORY_H 472 select SPARSE_IRQ 473 help 474 Support for StrongARM 11x0 based boards. 475 476config ARCH_S3C24XX 477 bool "Samsung S3C24XX SoCs" 478 select ATAGS 479 select CLKSRC_SAMSUNG_PWM 480 select GPIO_SAMSUNG 481 select GPIOLIB 482 select GENERIC_IRQ_MULTI_HANDLER 483 select NEED_MACH_IO_H 484 select S3C2410_WATCHDOG 485 select SAMSUNG_ATAGS 486 select USE_OF 487 select WATCHDOG 488 help 489 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 490 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 491 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 492 Samsung SMDK2410 development board (and derivatives). 493 494config ARCH_OMAP1 495 bool "TI OMAP1" 496 depends on MMU 497 select ARCH_OMAP 498 select CLKSRC_MMIO 499 select GENERIC_IRQ_CHIP 500 select GENERIC_IRQ_MULTI_HANDLER 501 select GPIOLIB 502 select HAVE_LEGACY_CLK 503 select IRQ_DOMAIN 504 select NEED_MACH_IO_H if PCCARD 505 select NEED_MACH_MEMORY_H 506 select SPARSE_IRQ 507 help 508 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 509 510endchoice 511 512menu "Multiple platform selection" 513 depends on ARCH_MULTIPLATFORM 514 515comment "CPU Core family selection" 516 517config ARCH_MULTI_V4 518 bool "ARMv4 based platforms (FA526)" 519 depends on !ARCH_MULTI_V6_V7 520 select ARCH_MULTI_V4_V5 521 select CPU_FA526 522 523config ARCH_MULTI_V4T 524 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 525 depends on !ARCH_MULTI_V6_V7 526 select ARCH_MULTI_V4_V5 527 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 528 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 529 CPU_ARM925T || CPU_ARM940T) 530 531config ARCH_MULTI_V5 532 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 533 depends on !ARCH_MULTI_V6_V7 534 select ARCH_MULTI_V4_V5 535 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 536 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 537 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 538 539config ARCH_MULTI_V4_V5 540 bool 541 542config ARCH_MULTI_V6 543 bool "ARMv6 based platforms (ARM11)" 544 select ARCH_MULTI_V6_V7 545 select CPU_V6K 546 547config ARCH_MULTI_V7 548 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 549 default y 550 select ARCH_MULTI_V6_V7 551 select CPU_V7 552 select HAVE_SMP 553 554config ARCH_MULTI_V6_V7 555 bool 556 select MIGHT_HAVE_CACHE_L2X0 557 558config ARCH_MULTI_CPU_AUTO 559 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 560 select ARCH_MULTI_V5 561 562endmenu 563 564config ARCH_VIRT 565 bool "Dummy Virtual Machine" 566 depends on ARCH_MULTI_V7 567 select ARM_AMBA 568 select ARM_GIC 569 select ARM_GIC_V2M if PCI 570 select ARM_GIC_V3 571 select ARM_GIC_V3_ITS if PCI 572 select ARM_PSCI 573 select HAVE_ARM_ARCH_TIMER 574 select ARCH_SUPPORTS_BIG_ENDIAN 575 576config ARCH_AIROHA 577 bool "Airoha SoC Support" 578 depends on ARCH_MULTI_V7 579 select ARM_AMBA 580 select ARM_GIC 581 select ARM_GIC_V3 582 select ARM_PSCI 583 select HAVE_ARM_ARCH_TIMER 584 select COMMON_CLK 585 help 586 Support for Airoha EN7523 SoCs 587 588# 589# This is sorted alphabetically by mach-* pathname. However, plat-* 590# Kconfigs may be included either alphabetically (according to the 591# plat- suffix) or along side the corresponding mach-* source. 592# 593source "arch/arm/mach-actions/Kconfig" 594 595source "arch/arm/mach-alpine/Kconfig" 596 597source "arch/arm/mach-artpec/Kconfig" 598 599source "arch/arm/mach-asm9260/Kconfig" 600 601source "arch/arm/mach-aspeed/Kconfig" 602 603source "arch/arm/mach-at91/Kconfig" 604 605source "arch/arm/mach-axxia/Kconfig" 606 607source "arch/arm/mach-bcm/Kconfig" 608 609source "arch/arm/mach-berlin/Kconfig" 610 611source "arch/arm/mach-clps711x/Kconfig" 612 613source "arch/arm/mach-cns3xxx/Kconfig" 614 615source "arch/arm/mach-davinci/Kconfig" 616 617source "arch/arm/mach-digicolor/Kconfig" 618 619source "arch/arm/mach-dove/Kconfig" 620 621source "arch/arm/mach-ep93xx/Kconfig" 622 623source "arch/arm/mach-exynos/Kconfig" 624 625source "arch/arm/mach-footbridge/Kconfig" 626 627source "arch/arm/mach-gemini/Kconfig" 628 629source "arch/arm/mach-highbank/Kconfig" 630 631source "arch/arm/mach-hisi/Kconfig" 632 633source "arch/arm/mach-imx/Kconfig" 634 635source "arch/arm/mach-integrator/Kconfig" 636 637source "arch/arm/mach-iop32x/Kconfig" 638 639source "arch/arm/mach-ixp4xx/Kconfig" 640 641source "arch/arm/mach-keystone/Kconfig" 642 643source "arch/arm/mach-lpc32xx/Kconfig" 644 645source "arch/arm/mach-mediatek/Kconfig" 646 647source "arch/arm/mach-meson/Kconfig" 648 649source "arch/arm/mach-milbeaut/Kconfig" 650 651source "arch/arm/mach-mmp/Kconfig" 652 653source "arch/arm/mach-moxart/Kconfig" 654 655source "arch/arm/mach-mstar/Kconfig" 656 657source "arch/arm/mach-mv78xx0/Kconfig" 658 659source "arch/arm/mach-mvebu/Kconfig" 660 661source "arch/arm/mach-mxs/Kconfig" 662 663source "arch/arm/mach-nomadik/Kconfig" 664 665source "arch/arm/mach-npcm/Kconfig" 666 667source "arch/arm/mach-nspire/Kconfig" 668 669source "arch/arm/plat-omap/Kconfig" 670 671source "arch/arm/mach-omap1/Kconfig" 672 673source "arch/arm/mach-omap2/Kconfig" 674 675source "arch/arm/mach-orion5x/Kconfig" 676 677source "arch/arm/mach-oxnas/Kconfig" 678 679source "arch/arm/mach-pxa/Kconfig" 680source "arch/arm/plat-pxa/Kconfig" 681 682source "arch/arm/mach-qcom/Kconfig" 683 684source "arch/arm/mach-rda/Kconfig" 685 686source "arch/arm/mach-realtek/Kconfig" 687 688source "arch/arm/mach-realview/Kconfig" 689 690source "arch/arm/mach-rockchip/Kconfig" 691 692source "arch/arm/mach-s3c/Kconfig" 693 694source "arch/arm/mach-s5pv210/Kconfig" 695 696source "arch/arm/mach-sa1100/Kconfig" 697 698source "arch/arm/mach-shmobile/Kconfig" 699 700source "arch/arm/mach-socfpga/Kconfig" 701 702source "arch/arm/mach-spear/Kconfig" 703 704source "arch/arm/mach-sti/Kconfig" 705 706source "arch/arm/mach-stm32/Kconfig" 707 708source "arch/arm/mach-sunxi/Kconfig" 709 710source "arch/arm/mach-tegra/Kconfig" 711 712source "arch/arm/mach-uniphier/Kconfig" 713 714source "arch/arm/mach-ux500/Kconfig" 715 716source "arch/arm/mach-versatile/Kconfig" 717 718source "arch/arm/mach-vexpress/Kconfig" 719 720source "arch/arm/mach-vt8500/Kconfig" 721 722source "arch/arm/mach-zynq/Kconfig" 723 724# ARMv7-M architecture 725config ARCH_LPC18XX 726 bool "NXP LPC18xx/LPC43xx" 727 depends on ARM_SINGLE_ARMV7M 728 select ARCH_HAS_RESET_CONTROLLER 729 select ARM_AMBA 730 select CLKSRC_LPC32XX 731 select PINCTRL 732 help 733 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 734 high performance microcontrollers. 735 736config ARCH_MPS2 737 bool "ARM MPS2 platform" 738 depends on ARM_SINGLE_ARMV7M 739 select ARM_AMBA 740 select CLKSRC_MPS2 741 help 742 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 743 with a range of available cores like Cortex-M3/M4/M7. 744 745 Please, note that depends which Application Note is used memory map 746 for the platform may vary, so adjustment of RAM base might be needed. 747 748# Definitions to make life easier 749config ARCH_ACORN 750 bool 751 752config PLAT_IOP 753 bool 754 755config PLAT_ORION 756 bool 757 select CLKSRC_MMIO 758 select COMMON_CLK 759 select GENERIC_IRQ_CHIP 760 select IRQ_DOMAIN 761 762config PLAT_ORION_LEGACY 763 bool 764 select PLAT_ORION 765 766config PLAT_PXA 767 bool 768 769config PLAT_VERSATILE 770 bool 771 772source "arch/arm/mm/Kconfig" 773 774config IWMMXT 775 bool "Enable iWMMXt support" 776 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 777 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 778 help 779 Enable support for iWMMXt context switching at run time if 780 running on a CPU that supports it. 781 782if !MMU 783source "arch/arm/Kconfig-nommu" 784endif 785 786config PJ4B_ERRATA_4742 787 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 788 depends on CPU_PJ4B && MACH_ARMADA_370 789 default y 790 help 791 When coming out of either a Wait for Interrupt (WFI) or a Wait for 792 Event (WFE) IDLE states, a specific timing sensitivity exists between 793 the retiring WFI/WFE instructions and the newly issued subsequent 794 instructions. This sensitivity can result in a CPU hang scenario. 795 Workaround: 796 The software must insert either a Data Synchronization Barrier (DSB) 797 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 798 instruction 799 800config ARM_ERRATA_326103 801 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 802 depends on CPU_V6 803 help 804 Executing a SWP instruction to read-only memory does not set bit 11 805 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 806 treat the access as a read, preventing a COW from occurring and 807 causing the faulting task to livelock. 808 809config ARM_ERRATA_411920 810 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 811 depends on CPU_V6 || CPU_V6K 812 help 813 Invalidation of the Instruction Cache operation can 814 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 815 It does not affect the MPCore. This option enables the ARM Ltd. 816 recommended workaround. 817 818config ARM_ERRATA_430973 819 bool "ARM errata: Stale prediction on replaced interworking branch" 820 depends on CPU_V7 821 help 822 This option enables the workaround for the 430973 Cortex-A8 823 r1p* erratum. If a code sequence containing an ARM/Thumb 824 interworking branch is replaced with another code sequence at the 825 same virtual address, whether due to self-modifying code or virtual 826 to physical address re-mapping, Cortex-A8 does not recover from the 827 stale interworking branch prediction. This results in Cortex-A8 828 executing the new code sequence in the incorrect ARM or Thumb state. 829 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 830 and also flushes the branch target cache at every context switch. 831 Note that setting specific bits in the ACTLR register may not be 832 available in non-secure mode. 833 834config ARM_ERRATA_458693 835 bool "ARM errata: Processor deadlock when a false hazard is created" 836 depends on CPU_V7 837 depends on !ARCH_MULTIPLATFORM 838 help 839 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 840 erratum. For very specific sequences of memory operations, it is 841 possible for a hazard condition intended for a cache line to instead 842 be incorrectly associated with a different cache line. This false 843 hazard might then cause a processor deadlock. The workaround enables 844 the L1 caching of the NEON accesses and disables the PLD instruction 845 in the ACTLR register. Note that setting specific bits in the ACTLR 846 register may not be available in non-secure mode. 847 848config ARM_ERRATA_460075 849 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 850 depends on CPU_V7 851 depends on !ARCH_MULTIPLATFORM 852 help 853 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 854 erratum. Any asynchronous access to the L2 cache may encounter a 855 situation in which recent store transactions to the L2 cache are lost 856 and overwritten with stale memory contents from external memory. The 857 workaround disables the write-allocate mode for the L2 cache via the 858 ACTLR register. Note that setting specific bits in the ACTLR register 859 may not be available in non-secure mode. 860 861config ARM_ERRATA_742230 862 bool "ARM errata: DMB operation may be faulty" 863 depends on CPU_V7 && SMP 864 depends on !ARCH_MULTIPLATFORM 865 help 866 This option enables the workaround for the 742230 Cortex-A9 867 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 868 between two write operations may not ensure the correct visibility 869 ordering of the two writes. This workaround sets a specific bit in 870 the diagnostic register of the Cortex-A9 which causes the DMB 871 instruction to behave as a DSB, ensuring the correct behaviour of 872 the two writes. 873 874config ARM_ERRATA_742231 875 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 876 depends on CPU_V7 && SMP 877 depends on !ARCH_MULTIPLATFORM 878 help 879 This option enables the workaround for the 742231 Cortex-A9 880 (r2p0..r2p2) erratum. Under certain conditions, specific to the 881 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 882 accessing some data located in the same cache line, may get corrupted 883 data due to bad handling of the address hazard when the line gets 884 replaced from one of the CPUs at the same time as another CPU is 885 accessing it. This workaround sets specific bits in the diagnostic 886 register of the Cortex-A9 which reduces the linefill issuing 887 capabilities of the processor. 888 889config ARM_ERRATA_643719 890 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 891 depends on CPU_V7 && SMP 892 default y 893 help 894 This option enables the workaround for the 643719 Cortex-A9 (prior to 895 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 896 register returns zero when it should return one. The workaround 897 corrects this value, ensuring cache maintenance operations which use 898 it behave as intended and avoiding data corruption. 899 900config ARM_ERRATA_720789 901 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 902 depends on CPU_V7 903 help 904 This option enables the workaround for the 720789 Cortex-A9 (prior to 905 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 906 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 907 As a consequence of this erratum, some TLB entries which should be 908 invalidated are not, resulting in an incoherency in the system page 909 tables. The workaround changes the TLB flushing routines to invalidate 910 entries regardless of the ASID. 911 912config ARM_ERRATA_743622 913 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 914 depends on CPU_V7 915 depends on !ARCH_MULTIPLATFORM 916 help 917 This option enables the workaround for the 743622 Cortex-A9 918 (r2p*) erratum. Under very rare conditions, a faulty 919 optimisation in the Cortex-A9 Store Buffer may lead to data 920 corruption. This workaround sets a specific bit in the diagnostic 921 register of the Cortex-A9 which disables the Store Buffer 922 optimisation, preventing the defect from occurring. This has no 923 visible impact on the overall performance or power consumption of the 924 processor. 925 926config ARM_ERRATA_751472 927 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 928 depends on CPU_V7 929 depends on !ARCH_MULTIPLATFORM 930 help 931 This option enables the workaround for the 751472 Cortex-A9 (prior 932 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 933 completion of a following broadcasted operation if the second 934 operation is received by a CPU before the ICIALLUIS has completed, 935 potentially leading to corrupted entries in the cache or TLB. 936 937config ARM_ERRATA_754322 938 bool "ARM errata: possible faulty MMU translations following an ASID switch" 939 depends on CPU_V7 940 help 941 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 942 r3p*) erratum. A speculative memory access may cause a page table walk 943 which starts prior to an ASID switch but completes afterwards. This 944 can populate the micro-TLB with a stale entry which may be hit with 945 the new ASID. This workaround places two dsb instructions in the mm 946 switching code so that no page table walks can cross the ASID switch. 947 948config ARM_ERRATA_754327 949 bool "ARM errata: no automatic Store Buffer drain" 950 depends on CPU_V7 && SMP 951 help 952 This option enables the workaround for the 754327 Cortex-A9 (prior to 953 r2p0) erratum. The Store Buffer does not have any automatic draining 954 mechanism and therefore a livelock may occur if an external agent 955 continuously polls a memory location waiting to observe an update. 956 This workaround defines cpu_relax() as smp_mb(), preventing correctly 957 written polling loops from denying visibility of updates to memory. 958 959config ARM_ERRATA_364296 960 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 961 depends on CPU_V6 962 help 963 This options enables the workaround for the 364296 ARM1136 964 r0p2 erratum (possible cache data corruption with 965 hit-under-miss enabled). It sets the undocumented bit 31 in 966 the auxiliary control register and the FI bit in the control 967 register, thus disabling hit-under-miss without putting the 968 processor into full low interrupt latency mode. ARM11MPCore 969 is not affected. 970 971config ARM_ERRATA_764369 972 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 973 depends on CPU_V7 && SMP 974 help 975 This option enables the workaround for erratum 764369 976 affecting Cortex-A9 MPCore with two or more processors (all 977 current revisions). Under certain timing circumstances, a data 978 cache line maintenance operation by MVA targeting an Inner 979 Shareable memory region may fail to proceed up to either the 980 Point of Coherency or to the Point of Unification of the 981 system. This workaround adds a DSB instruction before the 982 relevant cache maintenance functions and sets a specific bit 983 in the diagnostic control register of the SCU. 984 985config ARM_ERRATA_775420 986 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 987 depends on CPU_V7 988 help 989 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 990 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 991 operation aborts with MMU exception, it might cause the processor 992 to deadlock. This workaround puts DSB before executing ISB if 993 an abort may occur on cache maintenance. 994 995config ARM_ERRATA_798181 996 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 997 depends on CPU_V7 && SMP 998 help 999 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1000 adequately shooting down all use of the old entries. This 1001 option enables the Linux kernel workaround for this erratum 1002 which sends an IPI to the CPUs that are running the same ASID 1003 as the one being invalidated. 1004 1005config ARM_ERRATA_773022 1006 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1007 depends on CPU_V7 1008 help 1009 This option enables the workaround for the 773022 Cortex-A15 1010 (up to r0p4) erratum. In certain rare sequences of code, the 1011 loop buffer may deliver incorrect instructions. This 1012 workaround disables the loop buffer to avoid the erratum. 1013 1014config ARM_ERRATA_818325_852422 1015 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1016 depends on CPU_V7 1017 help 1018 This option enables the workaround for: 1019 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1020 instruction might deadlock. Fixed in r0p1. 1021 - Cortex-A12 852422: Execution of a sequence of instructions might 1022 lead to either a data corruption or a CPU deadlock. Not fixed in 1023 any Cortex-A12 cores yet. 1024 This workaround for all both errata involves setting bit[12] of the 1025 Feature Register. This bit disables an optimisation applied to a 1026 sequence of 2 instructions that use opposing condition codes. 1027 1028config ARM_ERRATA_821420 1029 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1030 depends on CPU_V7 1031 help 1032 This option enables the workaround for the 821420 Cortex-A12 1033 (all revs) erratum. In very rare timing conditions, a sequence 1034 of VMOV to Core registers instructions, for which the second 1035 one is in the shadow of a branch or abort, can lead to a 1036 deadlock when the VMOV instructions are issued out-of-order. 1037 1038config ARM_ERRATA_825619 1039 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1040 depends on CPU_V7 1041 help 1042 This option enables the workaround for the 825619 Cortex-A12 1043 (all revs) erratum. Within rare timing constraints, executing a 1044 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1045 and Device/Strongly-Ordered loads and stores might cause deadlock 1046 1047config ARM_ERRATA_857271 1048 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1049 depends on CPU_V7 1050 help 1051 This option enables the workaround for the 857271 Cortex-A12 1052 (all revs) erratum. Under very rare timing conditions, the CPU might 1053 hang. The workaround is expected to have a < 1% performance impact. 1054 1055config ARM_ERRATA_852421 1056 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1057 depends on CPU_V7 1058 help 1059 This option enables the workaround for the 852421 Cortex-A17 1060 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1061 execution of a DMB ST instruction might fail to properly order 1062 stores from GroupA and stores from GroupB. 1063 1064config ARM_ERRATA_852423 1065 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1066 depends on CPU_V7 1067 help 1068 This option enables the workaround for: 1069 - Cortex-A17 852423: Execution of a sequence of instructions might 1070 lead to either a data corruption or a CPU deadlock. Not fixed in 1071 any Cortex-A17 cores yet. 1072 This is identical to Cortex-A12 erratum 852422. It is a separate 1073 config option from the A12 erratum due to the way errata are checked 1074 for and handled. 1075 1076config ARM_ERRATA_857272 1077 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1078 depends on CPU_V7 1079 help 1080 This option enables the workaround for the 857272 Cortex-A17 erratum. 1081 This erratum is not known to be fixed in any A17 revision. 1082 This is identical to Cortex-A12 erratum 857271. It is a separate 1083 config option from the A12 erratum due to the way errata are checked 1084 for and handled. 1085 1086endmenu 1087 1088source "arch/arm/common/Kconfig" 1089 1090menu "Bus support" 1091 1092config ISA 1093 bool 1094 help 1095 Find out whether you have ISA slots on your motherboard. ISA is the 1096 name of a bus system, i.e. the way the CPU talks to the other stuff 1097 inside your box. Other bus systems are PCI, EISA, MicroChannel 1098 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1099 newer boards don't support it. If you have ISA, say Y, otherwise N. 1100 1101# Select ISA DMA controller support 1102config ISA_DMA 1103 bool 1104 select ISA_DMA_API 1105 1106# Select ISA DMA interface 1107config ISA_DMA_API 1108 bool 1109 1110config PCI_NANOENGINE 1111 bool "BSE nanoEngine PCI support" 1112 depends on SA1100_NANOENGINE 1113 help 1114 Enable PCI on the BSE nanoEngine board. 1115 1116config ARM_ERRATA_814220 1117 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1118 depends on CPU_V7 1119 help 1120 The v7 ARM states that all cache and branch predictor maintenance 1121 operations that do not specify an address execute, relative to 1122 each other, in program order. 1123 However, because of this erratum, an L2 set/way cache maintenance 1124 operation can overtake an L1 set/way cache maintenance operation. 1125 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1126 r0p4, r0p5. 1127 1128endmenu 1129 1130menu "Kernel Features" 1131 1132config HAVE_SMP 1133 bool 1134 help 1135 This option should be selected by machines which have an SMP- 1136 capable CPU. 1137 1138 The only effect of this option is to make the SMP-related 1139 options available to the user for configuration. 1140 1141config SMP 1142 bool "Symmetric Multi-Processing" 1143 depends on CPU_V6K || CPU_V7 1144 depends on HAVE_SMP 1145 depends on MMU || ARM_MPU 1146 select IRQ_WORK 1147 help 1148 This enables support for systems with more than one CPU. If you have 1149 a system with only one CPU, say N. If you have a system with more 1150 than one CPU, say Y. 1151 1152 If you say N here, the kernel will run on uni- and multiprocessor 1153 machines, but will use only one CPU of a multiprocessor machine. If 1154 you say Y here, the kernel will run on many, but not all, 1155 uniprocessor machines. On a uniprocessor machine, the kernel 1156 will run faster if you say N here. 1157 1158 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1159 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1160 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1161 1162 If you don't know what to do here, say N. 1163 1164config SMP_ON_UP 1165 bool "Allow booting SMP kernel on uniprocessor systems" 1166 depends on SMP && !XIP_KERNEL && MMU 1167 default y 1168 help 1169 SMP kernels contain instructions which fail on non-SMP processors. 1170 Enabling this option allows the kernel to modify itself to make 1171 these instructions safe. Disabling it allows about 1K of space 1172 savings. 1173 1174 If you don't know what to do here, say Y. 1175 1176 1177config CURRENT_POINTER_IN_TPIDRURO 1178 def_bool y 1179 depends on SMP && CPU_32v6K && !CPU_V6 1180 1181config ARM_CPU_TOPOLOGY 1182 bool "Support cpu topology definition" 1183 depends on SMP && CPU_V7 1184 default y 1185 help 1186 Support ARM cpu topology definition. The MPIDR register defines 1187 affinity between processors which is then used to describe the cpu 1188 topology of an ARM System. 1189 1190config SCHED_MC 1191 bool "Multi-core scheduler support" 1192 depends on ARM_CPU_TOPOLOGY 1193 help 1194 Multi-core scheduler support improves the CPU scheduler's decision 1195 making when dealing with multi-core CPU chips at a cost of slightly 1196 increased overhead in some places. If unsure say N here. 1197 1198config SCHED_SMT 1199 bool "SMT scheduler support" 1200 depends on ARM_CPU_TOPOLOGY 1201 help 1202 Improves the CPU scheduler's decision making when dealing with 1203 MultiThreading at a cost of slightly increased overhead in some 1204 places. If unsure say N here. 1205 1206config HAVE_ARM_SCU 1207 bool 1208 help 1209 This option enables support for the ARM snoop control unit 1210 1211config HAVE_ARM_ARCH_TIMER 1212 bool "Architected timer support" 1213 depends on CPU_V7 1214 select ARM_ARCH_TIMER 1215 help 1216 This option enables support for the ARM architected timer 1217 1218config HAVE_ARM_TWD 1219 bool 1220 help 1221 This options enables support for the ARM timer and watchdog unit 1222 1223config MCPM 1224 bool "Multi-Cluster Power Management" 1225 depends on CPU_V7 && SMP 1226 help 1227 This option provides the common power management infrastructure 1228 for (multi-)cluster based systems, such as big.LITTLE based 1229 systems. 1230 1231config MCPM_QUAD_CLUSTER 1232 bool 1233 depends on MCPM 1234 help 1235 To avoid wasting resources unnecessarily, MCPM only supports up 1236 to 2 clusters by default. 1237 Platforms with 3 or 4 clusters that use MCPM must select this 1238 option to allow the additional clusters to be managed. 1239 1240config BIG_LITTLE 1241 bool "big.LITTLE support (Experimental)" 1242 depends on CPU_V7 && SMP 1243 select MCPM 1244 help 1245 This option enables support selections for the big.LITTLE 1246 system architecture. 1247 1248config BL_SWITCHER 1249 bool "big.LITTLE switcher support" 1250 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1251 select CPU_PM 1252 help 1253 The big.LITTLE "switcher" provides the core functionality to 1254 transparently handle transition between a cluster of A15's 1255 and a cluster of A7's in a big.LITTLE system. 1256 1257config BL_SWITCHER_DUMMY_IF 1258 tristate "Simple big.LITTLE switcher user interface" 1259 depends on BL_SWITCHER && DEBUG_KERNEL 1260 help 1261 This is a simple and dummy char dev interface to control 1262 the big.LITTLE switcher core code. It is meant for 1263 debugging purposes only. 1264 1265choice 1266 prompt "Memory split" 1267 depends on MMU 1268 default VMSPLIT_3G 1269 help 1270 Select the desired split between kernel and user memory. 1271 1272 If you are not absolutely sure what you are doing, leave this 1273 option alone! 1274 1275 config VMSPLIT_3G 1276 bool "3G/1G user/kernel split" 1277 config VMSPLIT_3G_OPT 1278 depends on !ARM_LPAE 1279 bool "3G/1G user/kernel split (for full 1G low memory)" 1280 config VMSPLIT_2G 1281 bool "2G/2G user/kernel split" 1282 config VMSPLIT_1G 1283 bool "1G/3G user/kernel split" 1284endchoice 1285 1286config PAGE_OFFSET 1287 hex 1288 default PHYS_OFFSET if !MMU 1289 default 0x40000000 if VMSPLIT_1G 1290 default 0x80000000 if VMSPLIT_2G 1291 default 0xB0000000 if VMSPLIT_3G_OPT 1292 default 0xC0000000 1293 1294config KASAN_SHADOW_OFFSET 1295 hex 1296 depends on KASAN 1297 default 0x1f000000 if PAGE_OFFSET=0x40000000 1298 default 0x5f000000 if PAGE_OFFSET=0x80000000 1299 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1300 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1301 default 0xffffffff 1302 1303config NR_CPUS 1304 int "Maximum number of CPUs (2-32)" 1305 range 2 16 if DEBUG_KMAP_LOCAL 1306 range 2 32 if !DEBUG_KMAP_LOCAL 1307 depends on SMP 1308 default "4" 1309 help 1310 The maximum number of CPUs that the kernel can support. 1311 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1312 debugging is enabled, which uses half of the per-CPU fixmap 1313 slots as guard regions. 1314 1315config HOTPLUG_CPU 1316 bool "Support for hot-pluggable CPUs" 1317 depends on SMP 1318 select GENERIC_IRQ_MIGRATION 1319 help 1320 Say Y here to experiment with turning CPUs off and on. CPUs 1321 can be controlled through /sys/devices/system/cpu. 1322 1323config ARM_PSCI 1324 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1325 depends on HAVE_ARM_SMCCC 1326 select ARM_PSCI_FW 1327 help 1328 Say Y here if you want Linux to communicate with system firmware 1329 implementing the PSCI specification for CPU-centric power 1330 management operations described in ARM document number ARM DEN 1331 0022A ("Power State Coordination Interface System Software on 1332 ARM processors"). 1333 1334# The GPIO number here must be sorted by descending number. In case of 1335# a multiplatform kernel, we just want the highest value required by the 1336# selected platforms. 1337config ARCH_NR_GPIO 1338 int 1339 default 2048 if ARCH_INTEL_SOCFPGA 1340 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1341 ARCH_ZYNQ || ARCH_ASPEED 1342 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1343 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1344 default 416 if ARCH_SUNXI 1345 default 392 if ARCH_U8500 1346 default 352 if ARCH_VT8500 1347 default 288 if ARCH_ROCKCHIP 1348 default 264 if MACH_H4700 1349 default 0 1350 help 1351 Maximum number of GPIOs in the system. 1352 1353 If unsure, leave the default value. 1354 1355config HZ_FIXED 1356 int 1357 default 128 if SOC_AT91RM9200 1358 default 0 1359 1360choice 1361 depends on HZ_FIXED = 0 1362 prompt "Timer frequency" 1363 1364config HZ_100 1365 bool "100 Hz" 1366 1367config HZ_200 1368 bool "200 Hz" 1369 1370config HZ_250 1371 bool "250 Hz" 1372 1373config HZ_300 1374 bool "300 Hz" 1375 1376config HZ_500 1377 bool "500 Hz" 1378 1379config HZ_1000 1380 bool "1000 Hz" 1381 1382endchoice 1383 1384config HZ 1385 int 1386 default HZ_FIXED if HZ_FIXED != 0 1387 default 100 if HZ_100 1388 default 200 if HZ_200 1389 default 250 if HZ_250 1390 default 300 if HZ_300 1391 default 500 if HZ_500 1392 default 1000 1393 1394config SCHED_HRTICK 1395 def_bool HIGH_RES_TIMERS 1396 1397config THUMB2_KERNEL 1398 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1399 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1400 default y if CPU_THUMBONLY 1401 select ARM_UNWIND 1402 help 1403 By enabling this option, the kernel will be compiled in 1404 Thumb-2 mode. 1405 1406 If unsure, say N. 1407 1408config ARM_PATCH_IDIV 1409 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1410 depends on CPU_32v7 && !XIP_KERNEL 1411 default y 1412 help 1413 The ARM compiler inserts calls to __aeabi_idiv() and 1414 __aeabi_uidiv() when it needs to perform division on signed 1415 and unsigned integers. Some v7 CPUs have support for the sdiv 1416 and udiv instructions that can be used to implement those 1417 functions. 1418 1419 Enabling this option allows the kernel to modify itself to 1420 replace the first two instructions of these library functions 1421 with the sdiv or udiv plus "bx lr" instructions when the CPU 1422 it is running on supports them. Typically this will be faster 1423 and less power intensive than running the original library 1424 code to do integer division. 1425 1426config AEABI 1427 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1428 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1429 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1430 help 1431 This option allows for the kernel to be compiled using the latest 1432 ARM ABI (aka EABI). This is only useful if you are using a user 1433 space environment that is also compiled with EABI. 1434 1435 Since there are major incompatibilities between the legacy ABI and 1436 EABI, especially with regard to structure member alignment, this 1437 option also changes the kernel syscall calling convention to 1438 disambiguate both ABIs and allow for backward compatibility support 1439 (selected with CONFIG_OABI_COMPAT). 1440 1441 To use this you need GCC version 4.0.0 or later. 1442 1443config OABI_COMPAT 1444 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1445 depends on AEABI && !THUMB2_KERNEL 1446 help 1447 This option preserves the old syscall interface along with the 1448 new (ARM EABI) one. It also provides a compatibility layer to 1449 intercept syscalls that have structure arguments which layout 1450 in memory differs between the legacy ABI and the new ARM EABI 1451 (only for non "thumb" binaries). This option adds a tiny 1452 overhead to all syscalls and produces a slightly larger kernel. 1453 1454 The seccomp filter system will not be available when this is 1455 selected, since there is no way yet to sensibly distinguish 1456 between calling conventions during filtering. 1457 1458 If you know you'll be using only pure EABI user space then you 1459 can say N here. If this option is not selected and you attempt 1460 to execute a legacy ABI binary then the result will be 1461 UNPREDICTABLE (in fact it can be predicted that it won't work 1462 at all). If in doubt say N. 1463 1464config ARCH_SELECT_MEMORY_MODEL 1465 bool 1466 1467config ARCH_FLATMEM_ENABLE 1468 bool 1469 1470config ARCH_SPARSEMEM_ENABLE 1471 bool 1472 select SPARSEMEM_STATIC if SPARSEMEM 1473 1474config HIGHMEM 1475 bool "High Memory Support" 1476 depends on MMU 1477 select KMAP_LOCAL 1478 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1479 help 1480 The address space of ARM processors is only 4 Gigabytes large 1481 and it has to accommodate user address space, kernel address 1482 space as well as some memory mapped IO. That means that, if you 1483 have a large amount of physical memory and/or IO, not all of the 1484 memory can be "permanently mapped" by the kernel. The physical 1485 memory that is not permanently mapped is called "high memory". 1486 1487 Depending on the selected kernel/user memory split, minimum 1488 vmalloc space and actual amount of RAM, you may not need this 1489 option which should result in a slightly faster kernel. 1490 1491 If unsure, say n. 1492 1493config HIGHPTE 1494 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1495 depends on HIGHMEM 1496 default y 1497 help 1498 The VM uses one page of physical memory for each page table. 1499 For systems with a lot of processes, this can use a lot of 1500 precious low memory, eventually leading to low memory being 1501 consumed by page tables. Setting this option will allow 1502 user-space 2nd level page tables to reside in high memory. 1503 1504config CPU_SW_DOMAIN_PAN 1505 bool "Enable use of CPU domains to implement privileged no-access" 1506 depends on MMU && !ARM_LPAE 1507 default y 1508 help 1509 Increase kernel security by ensuring that normal kernel accesses 1510 are unable to access userspace addresses. This can help prevent 1511 use-after-free bugs becoming an exploitable privilege escalation 1512 by ensuring that magic values (such as LIST_POISON) will always 1513 fault when dereferenced. 1514 1515 CPUs with low-vector mappings use a best-efforts implementation. 1516 Their lower 1MB needs to remain accessible for the vectors, but 1517 the remainder of userspace will become appropriately inaccessible. 1518 1519config HW_PERF_EVENTS 1520 def_bool y 1521 depends on ARM_PMU 1522 1523config ARCH_WANT_GENERAL_HUGETLB 1524 def_bool y 1525 1526config ARM_MODULE_PLTS 1527 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1528 depends on MODULES 1529 default y 1530 help 1531 Allocate PLTs when loading modules so that jumps and calls whose 1532 targets are too far away for their relative offsets to be encoded 1533 in the instructions themselves can be bounced via veneers in the 1534 module's PLT. This allows modules to be allocated in the generic 1535 vmalloc area after the dedicated module memory area has been 1536 exhausted. The modules will use slightly more memory, but after 1537 rounding up to page size, the actual memory footprint is usually 1538 the same. 1539 1540 Disabling this is usually safe for small single-platform 1541 configurations. If unsure, say y. 1542 1543config FORCE_MAX_ZONEORDER 1544 int "Maximum zone order" 1545 default "12" if SOC_AM33XX 1546 default "9" if SA1111 1547 default "11" 1548 help 1549 The kernel memory allocator divides physically contiguous memory 1550 blocks into "zones", where each zone is a power of two number of 1551 pages. This option selects the largest power of two that the kernel 1552 keeps in the memory allocator. If you need to allocate very large 1553 blocks of physically contiguous memory, then you may need to 1554 increase this value. 1555 1556 This config option is actually maximum order plus one. For example, 1557 a value of 11 means that the largest free memory block is 2^10 pages. 1558 1559config ALIGNMENT_TRAP 1560 def_bool CPU_CP15_MMU 1561 select HAVE_PROC_CPU if PROC_FS 1562 help 1563 ARM processors cannot fetch/store information which is not 1564 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1565 address divisible by 4. On 32-bit ARM processors, these non-aligned 1566 fetch/store instructions will be emulated in software if you say 1567 here, which has a severe performance impact. This is necessary for 1568 correct operation of some network protocols. With an IP-only 1569 configuration it is safe to say N, otherwise say Y. 1570 1571config UACCESS_WITH_MEMCPY 1572 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1573 depends on MMU 1574 default y if CPU_FEROCEON 1575 help 1576 Implement faster copy_to_user and clear_user methods for CPU 1577 cores where a 8-word STM instruction give significantly higher 1578 memory write throughput than a sequence of individual 32bit stores. 1579 1580 A possible side effect is a slight increase in scheduling latency 1581 between threads sharing the same address space if they invoke 1582 such copy operations with large buffers. 1583 1584 However, if the CPU data cache is using a write-allocate mode, 1585 this option is unlikely to provide any performance gain. 1586 1587config PARAVIRT 1588 bool "Enable paravirtualization code" 1589 help 1590 This changes the kernel so it can modify itself when it is run 1591 under a hypervisor, potentially improving performance significantly 1592 over full virtualization. 1593 1594config PARAVIRT_TIME_ACCOUNTING 1595 bool "Paravirtual steal time accounting" 1596 select PARAVIRT 1597 help 1598 Select this option to enable fine granularity task steal time 1599 accounting. Time spent executing other tasks in parallel with 1600 the current vCPU is discounted from the vCPU power. To account for 1601 that, there can be a small performance impact. 1602 1603 If in doubt, say N here. 1604 1605config XEN_DOM0 1606 def_bool y 1607 depends on XEN 1608 1609config XEN 1610 bool "Xen guest support on ARM" 1611 depends on ARM && AEABI && OF 1612 depends on CPU_V7 && !CPU_V6 1613 depends on !GENERIC_ATOMIC64 1614 depends on MMU 1615 select ARCH_DMA_ADDR_T_64BIT 1616 select ARM_PSCI 1617 select SWIOTLB 1618 select SWIOTLB_XEN 1619 select PARAVIRT 1620 help 1621 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1622 1623config STACKPROTECTOR_PER_TASK 1624 bool "Use a unique stack canary value for each task" 1625 depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA 1626 select GCC_PLUGIN_ARM_SSP_PER_TASK 1627 default y 1628 help 1629 Due to the fact that GCC uses an ordinary symbol reference from 1630 which to load the value of the stack canary, this value can only 1631 change at reboot time on SMP systems, and all tasks running in the 1632 kernel's address space are forced to use the same canary value for 1633 the entire duration that the system is up. 1634 1635 Enable this option to switch to a different method that uses a 1636 different canary value for each task. 1637 1638endmenu 1639 1640menu "Boot options" 1641 1642config USE_OF 1643 bool "Flattened Device Tree support" 1644 select IRQ_DOMAIN 1645 select OF 1646 help 1647 Include support for flattened device tree machine descriptions. 1648 1649config ATAGS 1650 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1651 default y 1652 help 1653 This is the traditional way of passing data to the kernel at boot 1654 time. If you are solely relying on the flattened device tree (or 1655 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1656 to remove ATAGS support from your kernel binary. If unsure, 1657 leave this to y. 1658 1659config DEPRECATED_PARAM_STRUCT 1660 bool "Provide old way to pass kernel parameters" 1661 depends on ATAGS 1662 help 1663 This was deprecated in 2001 and announced to live on for 5 years. 1664 Some old boot loaders still use this way. 1665 1666# Compressed boot loader in ROM. Yes, we really want to ask about 1667# TEXT and BSS so we preserve their values in the config files. 1668config ZBOOT_ROM_TEXT 1669 hex "Compressed ROM boot loader base address" 1670 default 0x0 1671 help 1672 The physical address at which the ROM-able zImage is to be 1673 placed in the target. Platforms which normally make use of 1674 ROM-able zImage formats normally set this to a suitable 1675 value in their defconfig file. 1676 1677 If ZBOOT_ROM is not enabled, this has no effect. 1678 1679config ZBOOT_ROM_BSS 1680 hex "Compressed ROM boot loader BSS address" 1681 default 0x0 1682 help 1683 The base address of an area of read/write memory in the target 1684 for the ROM-able zImage which must be available while the 1685 decompressor is running. It must be large enough to hold the 1686 entire decompressed kernel plus an additional 128 KiB. 1687 Platforms which normally make use of ROM-able zImage formats 1688 normally set this to a suitable value in their defconfig file. 1689 1690 If ZBOOT_ROM is not enabled, this has no effect. 1691 1692config ZBOOT_ROM 1693 bool "Compressed boot loader in ROM/flash" 1694 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1695 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1696 help 1697 Say Y here if you intend to execute your compressed kernel image 1698 (zImage) directly from ROM or flash. If unsure, say N. 1699 1700config ARM_APPENDED_DTB 1701 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1702 depends on OF 1703 help 1704 With this option, the boot code will look for a device tree binary 1705 (DTB) appended to zImage 1706 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1707 1708 This is meant as a backward compatibility convenience for those 1709 systems with a bootloader that can't be upgraded to accommodate 1710 the documented boot protocol using a device tree. 1711 1712 Beware that there is very little in terms of protection against 1713 this option being confused by leftover garbage in memory that might 1714 look like a DTB header after a reboot if no actual DTB is appended 1715 to zImage. Do not leave this option active in a production kernel 1716 if you don't intend to always append a DTB. Proper passing of the 1717 location into r2 of a bootloader provided DTB is always preferable 1718 to this option. 1719 1720config ARM_ATAG_DTB_COMPAT 1721 bool "Supplement the appended DTB with traditional ATAG information" 1722 depends on ARM_APPENDED_DTB 1723 help 1724 Some old bootloaders can't be updated to a DTB capable one, yet 1725 they provide ATAGs with memory configuration, the ramdisk address, 1726 the kernel cmdline string, etc. Such information is dynamically 1727 provided by the bootloader and can't always be stored in a static 1728 DTB. To allow a device tree enabled kernel to be used with such 1729 bootloaders, this option allows zImage to extract the information 1730 from the ATAG list and store it at run time into the appended DTB. 1731 1732choice 1733 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1734 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1735 1736config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1737 bool "Use bootloader kernel arguments if available" 1738 help 1739 Uses the command-line options passed by the boot loader instead of 1740 the device tree bootargs property. If the boot loader doesn't provide 1741 any, the device tree bootargs property will be used. 1742 1743config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1744 bool "Extend with bootloader kernel arguments" 1745 help 1746 The command-line arguments provided by the boot loader will be 1747 appended to the the device tree bootargs property. 1748 1749endchoice 1750 1751config CMDLINE 1752 string "Default kernel command string" 1753 default "" 1754 help 1755 On some architectures (e.g. CATS), there is currently no way 1756 for the boot loader to pass arguments to the kernel. For these 1757 architectures, you should supply some command-line options at build 1758 time by entering them here. As a minimum, you should specify the 1759 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1760 1761choice 1762 prompt "Kernel command line type" if CMDLINE != "" 1763 default CMDLINE_FROM_BOOTLOADER 1764 depends on ATAGS 1765 1766config CMDLINE_FROM_BOOTLOADER 1767 bool "Use bootloader kernel arguments if available" 1768 help 1769 Uses the command-line options passed by the boot loader. If 1770 the boot loader doesn't provide any, the default kernel command 1771 string provided in CMDLINE will be used. 1772 1773config CMDLINE_EXTEND 1774 bool "Extend bootloader kernel arguments" 1775 help 1776 The command-line arguments provided by the boot loader will be 1777 appended to the default kernel command string. 1778 1779config CMDLINE_FORCE 1780 bool "Always use the default kernel command string" 1781 help 1782 Always use the default kernel command string, even if the boot 1783 loader passes other arguments to the kernel. 1784 This is useful if you cannot or don't want to change the 1785 command-line options your boot loader passes to the kernel. 1786endchoice 1787 1788config XIP_KERNEL 1789 bool "Kernel Execute-In-Place from ROM" 1790 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1791 help 1792 Execute-In-Place allows the kernel to run from non-volatile storage 1793 directly addressable by the CPU, such as NOR flash. This saves RAM 1794 space since the text section of the kernel is not loaded from flash 1795 to RAM. Read-write sections, such as the data section and stack, 1796 are still copied to RAM. The XIP kernel is not compressed since 1797 it has to run directly from flash, so it will take more space to 1798 store it. The flash address used to link the kernel object files, 1799 and for storing it, is configuration dependent. Therefore, if you 1800 say Y here, you must know the proper physical address where to 1801 store the kernel image depending on your own flash memory usage. 1802 1803 Also note that the make target becomes "make xipImage" rather than 1804 "make zImage" or "make Image". The final kernel binary to put in 1805 ROM memory will be arch/arm/boot/xipImage. 1806 1807 If unsure, say N. 1808 1809config XIP_PHYS_ADDR 1810 hex "XIP Kernel Physical Location" 1811 depends on XIP_KERNEL 1812 default "0x00080000" 1813 help 1814 This is the physical address in your flash memory the kernel will 1815 be linked for and stored to. This address is dependent on your 1816 own flash usage. 1817 1818config XIP_DEFLATED_DATA 1819 bool "Store kernel .data section compressed in ROM" 1820 depends on XIP_KERNEL 1821 select ZLIB_INFLATE 1822 help 1823 Before the kernel is actually executed, its .data section has to be 1824 copied to RAM from ROM. This option allows for storing that data 1825 in compressed form and decompressed to RAM rather than merely being 1826 copied, saving some precious ROM space. A possible drawback is a 1827 slightly longer boot delay. 1828 1829config KEXEC 1830 bool "Kexec system call (EXPERIMENTAL)" 1831 depends on (!SMP || PM_SLEEP_SMP) 1832 depends on MMU 1833 select KEXEC_CORE 1834 help 1835 kexec is a system call that implements the ability to shutdown your 1836 current kernel, and to start another kernel. It is like a reboot 1837 but it is independent of the system firmware. And like a reboot 1838 you can start any kernel with it, not just Linux. 1839 1840 It is an ongoing process to be certain the hardware in a machine 1841 is properly shutdown, so do not be surprised if this code does not 1842 initially work for you. 1843 1844config ATAGS_PROC 1845 bool "Export atags in procfs" 1846 depends on ATAGS && KEXEC 1847 default y 1848 help 1849 Should the atags used to boot the kernel be exported in an "atags" 1850 file in procfs. Useful with kexec. 1851 1852config CRASH_DUMP 1853 bool "Build kdump crash kernel (EXPERIMENTAL)" 1854 help 1855 Generate crash dump after being started by kexec. This should 1856 be normally only set in special crash dump kernels which are 1857 loaded in the main kernel with kexec-tools into a specially 1858 reserved region and then later executed after a crash by 1859 kdump/kexec. The crash dump kernel must be compiled to a 1860 memory address not used by the main kernel 1861 1862 For more details see Documentation/admin-guide/kdump/kdump.rst 1863 1864config AUTO_ZRELADDR 1865 bool "Auto calculation of the decompressed kernel image address" 1866 help 1867 ZRELADDR is the physical address where the decompressed kernel 1868 image will be placed. If AUTO_ZRELADDR is selected, the address 1869 will be determined at run-time, either by masking the current IP 1870 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1871 This assumes the zImage being placed in the first 128MB from 1872 start of memory. 1873 1874config EFI_STUB 1875 bool 1876 1877config EFI 1878 bool "UEFI runtime support" 1879 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1880 select UCS2_STRING 1881 select EFI_PARAMS_FROM_FDT 1882 select EFI_STUB 1883 select EFI_GENERIC_STUB 1884 select EFI_RUNTIME_WRAPPERS 1885 help 1886 This option provides support for runtime services provided 1887 by UEFI firmware (such as non-volatile variables, realtime 1888 clock, and platform reset). A UEFI stub is also provided to 1889 allow the kernel to be booted as an EFI application. This 1890 is only useful for kernels that may run on systems that have 1891 UEFI firmware. 1892 1893config DMI 1894 bool "Enable support for SMBIOS (DMI) tables" 1895 depends on EFI 1896 default y 1897 help 1898 This enables SMBIOS/DMI feature for systems. 1899 1900 This option is only useful on systems that have UEFI firmware. 1901 However, even with this option, the resultant kernel should 1902 continue to boot on existing non-UEFI platforms. 1903 1904 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1905 i.e., the the practice of identifying the platform via DMI to 1906 decide whether certain workarounds for buggy hardware and/or 1907 firmware need to be enabled. This would require the DMI subsystem 1908 to be enabled much earlier than we do on ARM, which is non-trivial. 1909 1910endmenu 1911 1912menu "CPU Power Management" 1913 1914source "drivers/cpufreq/Kconfig" 1915 1916source "drivers/cpuidle/Kconfig" 1917 1918endmenu 1919 1920menu "Floating point emulation" 1921 1922comment "At least one emulation must be selected" 1923 1924config FPE_NWFPE 1925 bool "NWFPE math emulation" 1926 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1927 help 1928 Say Y to include the NWFPE floating point emulator in the kernel. 1929 This is necessary to run most binaries. Linux does not currently 1930 support floating point hardware so you need to say Y here even if 1931 your machine has an FPA or floating point co-processor podule. 1932 1933 You may say N here if you are going to load the Acorn FPEmulator 1934 early in the bootup. 1935 1936config FPE_NWFPE_XP 1937 bool "Support extended precision" 1938 depends on FPE_NWFPE 1939 help 1940 Say Y to include 80-bit support in the kernel floating-point 1941 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1942 Note that gcc does not generate 80-bit operations by default, 1943 so in most cases this option only enlarges the size of the 1944 floating point emulator without any good reason. 1945 1946 You almost surely want to say N here. 1947 1948config FPE_FASTFPE 1949 bool "FastFPE math emulation (EXPERIMENTAL)" 1950 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1951 help 1952 Say Y here to include the FAST floating point emulator in the kernel. 1953 This is an experimental much faster emulator which now also has full 1954 precision for the mantissa. It does not support any exceptions. 1955 It is very simple, and approximately 3-6 times faster than NWFPE. 1956 1957 It should be sufficient for most programs. It may be not suitable 1958 for scientific calculations, but you have to check this for yourself. 1959 If you do not feel you need a faster FP emulation you should better 1960 choose NWFPE. 1961 1962config VFP 1963 bool "VFP-format floating point maths" 1964 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1965 help 1966 Say Y to include VFP support code in the kernel. This is needed 1967 if your hardware includes a VFP unit. 1968 1969 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1970 release notes and additional status information. 1971 1972 Say N if your target does not have VFP hardware. 1973 1974config VFPv3 1975 bool 1976 depends on VFP 1977 default y if CPU_V7 1978 1979config NEON 1980 bool "Advanced SIMD (NEON) Extension support" 1981 depends on VFPv3 && CPU_V7 1982 help 1983 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1984 Extension. 1985 1986config KERNEL_MODE_NEON 1987 bool "Support for NEON in kernel mode" 1988 depends on NEON && AEABI 1989 help 1990 Say Y to include support for NEON in kernel mode. 1991 1992endmenu 1993 1994menu "Power management options" 1995 1996source "kernel/power/Kconfig" 1997 1998config ARCH_SUSPEND_POSSIBLE 1999 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2000 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2001 def_bool y 2002 2003config ARM_CPU_SUSPEND 2004 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2005 depends on ARCH_SUSPEND_POSSIBLE 2006 2007config ARCH_HIBERNATION_POSSIBLE 2008 bool 2009 depends on MMU 2010 default y if ARCH_SUSPEND_POSSIBLE 2011 2012endmenu 2013 2014if CRYPTO 2015source "arch/arm/crypto/Kconfig" 2016endif 2017 2018source "arch/arm/Kconfig.assembler" 2019