1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_REMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKSRC_MMIO 358 select CPU_ARM920T 359 select GPIOLIB 360 select COMMON_CLK 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select NEED_MACH_MEMORY_H 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_IOP32X 374 bool "IOP32x-based" 375 select CPU_XSCALE 376 select GPIO_IOP 377 select GPIOLIB 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 select ARCH_SUPPORTS_BIG_ENDIAN 387 select ARM_PATCH_PHYS_VIRT 388 select CPU_XSCALE 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 select SPARSE_IRQ 395 select USB_EHCI_BIG_ENDIAN_DESC 396 select USB_EHCI_BIG_ENDIAN_MMIO 397 help 398 Support for Intel's IXP4XX (XScale) family of processors. 399 400config ARCH_DOVE 401 bool "Marvell Dove" 402 select CPU_PJ4 403 select GPIOLIB 404 select HAVE_PCI 405 select MVEBU_MBUS 406 select PINCTRL 407 select PINCTRL_DOVE 408 select PLAT_ORION_LEGACY 409 select SPARSE_IRQ 410 select PM_GENERIC_DOMAINS if PM 411 help 412 Support for the Marvell Dove SoC 88AP510 413 414config ARCH_PXA 415 bool "PXA2xx/PXA3xx-based" 416 select ARCH_MTD_XIP 417 select ARM_CPU_SUSPEND if PM 418 select AUTO_ZRELADDR 419 select COMMON_CLK 420 select CLKSRC_PXA 421 select CLKSRC_MMIO 422 select TIMER_OF 423 select CPU_XSCALE if !CPU_XSC3 424 select GPIO_PXA 425 select GPIOLIB 426 select IRQ_DOMAIN 427 select PLAT_PXA 428 select SPARSE_IRQ 429 help 430 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 431 432config ARCH_RPC 433 bool "RiscPC" 434 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 435 select ARCH_ACORN 436 select ARCH_MAY_HAVE_PC_FDC 437 select ARCH_SPARSEMEM_ENABLE 438 select ARM_HAS_SG_CHAIN 439 select CPU_SA110 440 select FIQ 441 select HAVE_PATA_PLATFORM 442 select ISA_DMA_API 443 select LEGACY_TIMER_TICK 444 select NEED_MACH_IO_H 445 select NEED_MACH_MEMORY_H 446 select NO_IOPORT_MAP 447 help 448 On the Acorn Risc-PC, Linux can support the internal IDE disk and 449 CD-ROM interface, serial and parallel port, and the floppy drive. 450 451config ARCH_SA1100 452 bool "SA1100-based" 453 select ARCH_MTD_XIP 454 select ARCH_SPARSEMEM_ENABLE 455 select CLKSRC_MMIO 456 select CLKSRC_PXA 457 select TIMER_OF if OF 458 select COMMON_CLK 459 select CPU_FREQ 460 select CPU_SA1100 461 select GPIOLIB 462 select IRQ_DOMAIN 463 select ISA 464 select NEED_MACH_MEMORY_H 465 select SPARSE_IRQ 466 help 467 Support for StrongARM 11x0 based boards. 468 469config ARCH_S3C24XX 470 bool "Samsung S3C24XX SoCs" 471 select ATAGS 472 select CLKSRC_SAMSUNG_PWM 473 select GPIO_SAMSUNG 474 select GPIOLIB 475 select NEED_MACH_IO_H 476 select S3C2410_WATCHDOG 477 select SAMSUNG_ATAGS 478 select USE_OF 479 select WATCHDOG 480 help 481 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 482 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 483 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 484 Samsung SMDK2410 development board (and derivatives). 485 486config ARCH_OMAP1 487 bool "TI OMAP1" 488 select ARCH_OMAP 489 select CLKSRC_MMIO 490 select GENERIC_IRQ_CHIP 491 select GPIOLIB 492 select HAVE_LEGACY_CLK 493 select IRQ_DOMAIN 494 select NEED_MACH_IO_H if PCCARD 495 select NEED_MACH_MEMORY_H 496 select SPARSE_IRQ 497 help 498 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 499 500endchoice 501 502menu "Multiple platform selection" 503 depends on ARCH_MULTIPLATFORM 504 505comment "CPU Core family selection" 506 507config ARCH_MULTI_V4 508 bool "ARMv4 based platforms (FA526)" 509 depends on !ARCH_MULTI_V6_V7 510 select ARCH_MULTI_V4_V5 511 select CPU_FA526 512 513config ARCH_MULTI_V4T 514 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 515 depends on !ARCH_MULTI_V6_V7 516 select ARCH_MULTI_V4_V5 517 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 518 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 519 CPU_ARM925T || CPU_ARM940T) 520 521config ARCH_MULTI_V5 522 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 523 depends on !ARCH_MULTI_V6_V7 524 select ARCH_MULTI_V4_V5 525 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 526 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 527 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 528 529config ARCH_MULTI_V4_V5 530 bool 531 532config ARCH_MULTI_V6 533 bool "ARMv6 based platforms (ARM11)" 534 select ARCH_MULTI_V6_V7 535 select CPU_V6K 536 537config ARCH_MULTI_V7 538 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 539 default y 540 select ARCH_MULTI_V6_V7 541 select CPU_V7 542 select HAVE_SMP 543 544config ARCH_MULTI_V6_V7 545 bool 546 select MIGHT_HAVE_CACHE_L2X0 547 548config ARCH_MULTI_CPU_AUTO 549 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 550 select ARCH_MULTI_V5 551 552endmenu 553 554config ARCH_VIRT 555 bool "Dummy Virtual Machine" 556 depends on ARCH_MULTI_V7 557 select ARM_AMBA 558 select ARM_GIC 559 select ARM_GIC_V2M if PCI 560 select ARM_GIC_V3 561 select ARM_GIC_V3_ITS if PCI 562 select ARM_PSCI 563 select HAVE_ARM_ARCH_TIMER 564 select ARCH_SUPPORTS_BIG_ENDIAN 565 566# 567# This is sorted alphabetically by mach-* pathname. However, plat-* 568# Kconfigs may be included either alphabetically (according to the 569# plat- suffix) or along side the corresponding mach-* source. 570# 571source "arch/arm/mach-actions/Kconfig" 572 573source "arch/arm/mach-alpine/Kconfig" 574 575source "arch/arm/mach-artpec/Kconfig" 576 577source "arch/arm/mach-asm9260/Kconfig" 578 579source "arch/arm/mach-aspeed/Kconfig" 580 581source "arch/arm/mach-at91/Kconfig" 582 583source "arch/arm/mach-axxia/Kconfig" 584 585source "arch/arm/mach-bcm/Kconfig" 586 587source "arch/arm/mach-berlin/Kconfig" 588 589source "arch/arm/mach-clps711x/Kconfig" 590 591source "arch/arm/mach-cns3xxx/Kconfig" 592 593source "arch/arm/mach-davinci/Kconfig" 594 595source "arch/arm/mach-digicolor/Kconfig" 596 597source "arch/arm/mach-dove/Kconfig" 598 599source "arch/arm/mach-ep93xx/Kconfig" 600 601source "arch/arm/mach-exynos/Kconfig" 602 603source "arch/arm/mach-footbridge/Kconfig" 604 605source "arch/arm/mach-gemini/Kconfig" 606 607source "arch/arm/mach-highbank/Kconfig" 608 609source "arch/arm/mach-hisi/Kconfig" 610 611source "arch/arm/mach-imx/Kconfig" 612 613source "arch/arm/mach-integrator/Kconfig" 614 615source "arch/arm/mach-iop32x/Kconfig" 616 617source "arch/arm/mach-ixp4xx/Kconfig" 618 619source "arch/arm/mach-keystone/Kconfig" 620 621source "arch/arm/mach-lpc32xx/Kconfig" 622 623source "arch/arm/mach-mediatek/Kconfig" 624 625source "arch/arm/mach-meson/Kconfig" 626 627source "arch/arm/mach-milbeaut/Kconfig" 628 629source "arch/arm/mach-mmp/Kconfig" 630 631source "arch/arm/mach-moxart/Kconfig" 632 633source "arch/arm/mach-mstar/Kconfig" 634 635source "arch/arm/mach-mv78xx0/Kconfig" 636 637source "arch/arm/mach-mvebu/Kconfig" 638 639source "arch/arm/mach-mxs/Kconfig" 640 641source "arch/arm/mach-nomadik/Kconfig" 642 643source "arch/arm/mach-npcm/Kconfig" 644 645source "arch/arm/mach-nspire/Kconfig" 646 647source "arch/arm/plat-omap/Kconfig" 648 649source "arch/arm/mach-omap1/Kconfig" 650 651source "arch/arm/mach-omap2/Kconfig" 652 653source "arch/arm/mach-orion5x/Kconfig" 654 655source "arch/arm/mach-oxnas/Kconfig" 656 657source "arch/arm/mach-pxa/Kconfig" 658source "arch/arm/plat-pxa/Kconfig" 659 660source "arch/arm/mach-qcom/Kconfig" 661 662source "arch/arm/mach-rda/Kconfig" 663 664source "arch/arm/mach-realtek/Kconfig" 665 666source "arch/arm/mach-realview/Kconfig" 667 668source "arch/arm/mach-rockchip/Kconfig" 669 670source "arch/arm/mach-s3c/Kconfig" 671 672source "arch/arm/mach-s5pv210/Kconfig" 673 674source "arch/arm/mach-sa1100/Kconfig" 675 676source "arch/arm/mach-shmobile/Kconfig" 677 678source "arch/arm/mach-socfpga/Kconfig" 679 680source "arch/arm/mach-spear/Kconfig" 681 682source "arch/arm/mach-sti/Kconfig" 683 684source "arch/arm/mach-stm32/Kconfig" 685 686source "arch/arm/mach-sunxi/Kconfig" 687 688source "arch/arm/mach-tegra/Kconfig" 689 690source "arch/arm/mach-uniphier/Kconfig" 691 692source "arch/arm/mach-ux500/Kconfig" 693 694source "arch/arm/mach-versatile/Kconfig" 695 696source "arch/arm/mach-vexpress/Kconfig" 697 698source "arch/arm/mach-vt8500/Kconfig" 699 700source "arch/arm/mach-zynq/Kconfig" 701 702# ARMv7-M architecture 703config ARCH_LPC18XX 704 bool "NXP LPC18xx/LPC43xx" 705 depends on ARM_SINGLE_ARMV7M 706 select ARCH_HAS_RESET_CONTROLLER 707 select ARM_AMBA 708 select CLKSRC_LPC32XX 709 select PINCTRL 710 help 711 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 712 high performance microcontrollers. 713 714config ARCH_MPS2 715 bool "ARM MPS2 platform" 716 depends on ARM_SINGLE_ARMV7M 717 select ARM_AMBA 718 select CLKSRC_MPS2 719 help 720 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 721 with a range of available cores like Cortex-M3/M4/M7. 722 723 Please, note that depends which Application Note is used memory map 724 for the platform may vary, so adjustment of RAM base might be needed. 725 726# Definitions to make life easier 727config ARCH_ACORN 728 bool 729 730config PLAT_IOP 731 bool 732 733config PLAT_ORION 734 bool 735 select CLKSRC_MMIO 736 select COMMON_CLK 737 select GENERIC_IRQ_CHIP 738 select IRQ_DOMAIN 739 740config PLAT_ORION_LEGACY 741 bool 742 select PLAT_ORION 743 744config PLAT_PXA 745 bool 746 747config PLAT_VERSATILE 748 bool 749 750source "arch/arm/mm/Kconfig" 751 752config IWMMXT 753 bool "Enable iWMMXt support" 754 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 755 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 756 help 757 Enable support for iWMMXt context switching at run time if 758 running on a CPU that supports it. 759 760if !MMU 761source "arch/arm/Kconfig-nommu" 762endif 763 764config PJ4B_ERRATA_4742 765 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 766 depends on CPU_PJ4B && MACH_ARMADA_370 767 default y 768 help 769 When coming out of either a Wait for Interrupt (WFI) or a Wait for 770 Event (WFE) IDLE states, a specific timing sensitivity exists between 771 the retiring WFI/WFE instructions and the newly issued subsequent 772 instructions. This sensitivity can result in a CPU hang scenario. 773 Workaround: 774 The software must insert either a Data Synchronization Barrier (DSB) 775 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 776 instruction 777 778config ARM_ERRATA_326103 779 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 780 depends on CPU_V6 781 help 782 Executing a SWP instruction to read-only memory does not set bit 11 783 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 784 treat the access as a read, preventing a COW from occurring and 785 causing the faulting task to livelock. 786 787config ARM_ERRATA_411920 788 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 789 depends on CPU_V6 || CPU_V6K 790 help 791 Invalidation of the Instruction Cache operation can 792 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 793 It does not affect the MPCore. This option enables the ARM Ltd. 794 recommended workaround. 795 796config ARM_ERRATA_430973 797 bool "ARM errata: Stale prediction on replaced interworking branch" 798 depends on CPU_V7 799 help 800 This option enables the workaround for the 430973 Cortex-A8 801 r1p* erratum. If a code sequence containing an ARM/Thumb 802 interworking branch is replaced with another code sequence at the 803 same virtual address, whether due to self-modifying code or virtual 804 to physical address re-mapping, Cortex-A8 does not recover from the 805 stale interworking branch prediction. This results in Cortex-A8 806 executing the new code sequence in the incorrect ARM or Thumb state. 807 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 808 and also flushes the branch target cache at every context switch. 809 Note that setting specific bits in the ACTLR register may not be 810 available in non-secure mode. 811 812config ARM_ERRATA_458693 813 bool "ARM errata: Processor deadlock when a false hazard is created" 814 depends on CPU_V7 815 depends on !ARCH_MULTIPLATFORM 816 help 817 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 818 erratum. For very specific sequences of memory operations, it is 819 possible for a hazard condition intended for a cache line to instead 820 be incorrectly associated with a different cache line. This false 821 hazard might then cause a processor deadlock. The workaround enables 822 the L1 caching of the NEON accesses and disables the PLD instruction 823 in the ACTLR register. Note that setting specific bits in the ACTLR 824 register may not be available in non-secure mode. 825 826config ARM_ERRATA_460075 827 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 828 depends on CPU_V7 829 depends on !ARCH_MULTIPLATFORM 830 help 831 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 832 erratum. Any asynchronous access to the L2 cache may encounter a 833 situation in which recent store transactions to the L2 cache are lost 834 and overwritten with stale memory contents from external memory. The 835 workaround disables the write-allocate mode for the L2 cache via the 836 ACTLR register. Note that setting specific bits in the ACTLR register 837 may not be available in non-secure mode. 838 839config ARM_ERRATA_742230 840 bool "ARM errata: DMB operation may be faulty" 841 depends on CPU_V7 && SMP 842 depends on !ARCH_MULTIPLATFORM 843 help 844 This option enables the workaround for the 742230 Cortex-A9 845 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 846 between two write operations may not ensure the correct visibility 847 ordering of the two writes. This workaround sets a specific bit in 848 the diagnostic register of the Cortex-A9 which causes the DMB 849 instruction to behave as a DSB, ensuring the correct behaviour of 850 the two writes. 851 852config ARM_ERRATA_742231 853 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 854 depends on CPU_V7 && SMP 855 depends on !ARCH_MULTIPLATFORM 856 help 857 This option enables the workaround for the 742231 Cortex-A9 858 (r2p0..r2p2) erratum. Under certain conditions, specific to the 859 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 860 accessing some data located in the same cache line, may get corrupted 861 data due to bad handling of the address hazard when the line gets 862 replaced from one of the CPUs at the same time as another CPU is 863 accessing it. This workaround sets specific bits in the diagnostic 864 register of the Cortex-A9 which reduces the linefill issuing 865 capabilities of the processor. 866 867config ARM_ERRATA_643719 868 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 869 depends on CPU_V7 && SMP 870 default y 871 help 872 This option enables the workaround for the 643719 Cortex-A9 (prior to 873 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 874 register returns zero when it should return one. The workaround 875 corrects this value, ensuring cache maintenance operations which use 876 it behave as intended and avoiding data corruption. 877 878config ARM_ERRATA_720789 879 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 880 depends on CPU_V7 881 help 882 This option enables the workaround for the 720789 Cortex-A9 (prior to 883 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 884 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 885 As a consequence of this erratum, some TLB entries which should be 886 invalidated are not, resulting in an incoherency in the system page 887 tables. The workaround changes the TLB flushing routines to invalidate 888 entries regardless of the ASID. 889 890config ARM_ERRATA_743622 891 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 892 depends on CPU_V7 893 depends on !ARCH_MULTIPLATFORM 894 help 895 This option enables the workaround for the 743622 Cortex-A9 896 (r2p*) erratum. Under very rare conditions, a faulty 897 optimisation in the Cortex-A9 Store Buffer may lead to data 898 corruption. This workaround sets a specific bit in the diagnostic 899 register of the Cortex-A9 which disables the Store Buffer 900 optimisation, preventing the defect from occurring. This has no 901 visible impact on the overall performance or power consumption of the 902 processor. 903 904config ARM_ERRATA_751472 905 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 906 depends on CPU_V7 907 depends on !ARCH_MULTIPLATFORM 908 help 909 This option enables the workaround for the 751472 Cortex-A9 (prior 910 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 911 completion of a following broadcasted operation if the second 912 operation is received by a CPU before the ICIALLUIS has completed, 913 potentially leading to corrupted entries in the cache or TLB. 914 915config ARM_ERRATA_754322 916 bool "ARM errata: possible faulty MMU translations following an ASID switch" 917 depends on CPU_V7 918 help 919 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 920 r3p*) erratum. A speculative memory access may cause a page table walk 921 which starts prior to an ASID switch but completes afterwards. This 922 can populate the micro-TLB with a stale entry which may be hit with 923 the new ASID. This workaround places two dsb instructions in the mm 924 switching code so that no page table walks can cross the ASID switch. 925 926config ARM_ERRATA_754327 927 bool "ARM errata: no automatic Store Buffer drain" 928 depends on CPU_V7 && SMP 929 help 930 This option enables the workaround for the 754327 Cortex-A9 (prior to 931 r2p0) erratum. The Store Buffer does not have any automatic draining 932 mechanism and therefore a livelock may occur if an external agent 933 continuously polls a memory location waiting to observe an update. 934 This workaround defines cpu_relax() as smp_mb(), preventing correctly 935 written polling loops from denying visibility of updates to memory. 936 937config ARM_ERRATA_364296 938 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 939 depends on CPU_V6 940 help 941 This options enables the workaround for the 364296 ARM1136 942 r0p2 erratum (possible cache data corruption with 943 hit-under-miss enabled). It sets the undocumented bit 31 in 944 the auxiliary control register and the FI bit in the control 945 register, thus disabling hit-under-miss without putting the 946 processor into full low interrupt latency mode. ARM11MPCore 947 is not affected. 948 949config ARM_ERRATA_764369 950 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 951 depends on CPU_V7 && SMP 952 help 953 This option enables the workaround for erratum 764369 954 affecting Cortex-A9 MPCore with two or more processors (all 955 current revisions). Under certain timing circumstances, a data 956 cache line maintenance operation by MVA targeting an Inner 957 Shareable memory region may fail to proceed up to either the 958 Point of Coherency or to the Point of Unification of the 959 system. This workaround adds a DSB instruction before the 960 relevant cache maintenance functions and sets a specific bit 961 in the diagnostic control register of the SCU. 962 963config ARM_ERRATA_775420 964 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 965 depends on CPU_V7 966 help 967 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 968 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 969 operation aborts with MMU exception, it might cause the processor 970 to deadlock. This workaround puts DSB before executing ISB if 971 an abort may occur on cache maintenance. 972 973config ARM_ERRATA_798181 974 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 975 depends on CPU_V7 && SMP 976 help 977 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 978 adequately shooting down all use of the old entries. This 979 option enables the Linux kernel workaround for this erratum 980 which sends an IPI to the CPUs that are running the same ASID 981 as the one being invalidated. 982 983config ARM_ERRATA_773022 984 bool "ARM errata: incorrect instructions may be executed from loop buffer" 985 depends on CPU_V7 986 help 987 This option enables the workaround for the 773022 Cortex-A15 988 (up to r0p4) erratum. In certain rare sequences of code, the 989 loop buffer may deliver incorrect instructions. This 990 workaround disables the loop buffer to avoid the erratum. 991 992config ARM_ERRATA_818325_852422 993 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 994 depends on CPU_V7 995 help 996 This option enables the workaround for: 997 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 998 instruction might deadlock. Fixed in r0p1. 999 - Cortex-A12 852422: Execution of a sequence of instructions might 1000 lead to either a data corruption or a CPU deadlock. Not fixed in 1001 any Cortex-A12 cores yet. 1002 This workaround for all both errata involves setting bit[12] of the 1003 Feature Register. This bit disables an optimisation applied to a 1004 sequence of 2 instructions that use opposing condition codes. 1005 1006config ARM_ERRATA_821420 1007 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1008 depends on CPU_V7 1009 help 1010 This option enables the workaround for the 821420 Cortex-A12 1011 (all revs) erratum. In very rare timing conditions, a sequence 1012 of VMOV to Core registers instructions, for which the second 1013 one is in the shadow of a branch or abort, can lead to a 1014 deadlock when the VMOV instructions are issued out-of-order. 1015 1016config ARM_ERRATA_825619 1017 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1018 depends on CPU_V7 1019 help 1020 This option enables the workaround for the 825619 Cortex-A12 1021 (all revs) erratum. Within rare timing constraints, executing a 1022 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1023 and Device/Strongly-Ordered loads and stores might cause deadlock 1024 1025config ARM_ERRATA_857271 1026 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1027 depends on CPU_V7 1028 help 1029 This option enables the workaround for the 857271 Cortex-A12 1030 (all revs) erratum. Under very rare timing conditions, the CPU might 1031 hang. The workaround is expected to have a < 1% performance impact. 1032 1033config ARM_ERRATA_852421 1034 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1035 depends on CPU_V7 1036 help 1037 This option enables the workaround for the 852421 Cortex-A17 1038 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1039 execution of a DMB ST instruction might fail to properly order 1040 stores from GroupA and stores from GroupB. 1041 1042config ARM_ERRATA_852423 1043 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1044 depends on CPU_V7 1045 help 1046 This option enables the workaround for: 1047 - Cortex-A17 852423: Execution of a sequence of instructions might 1048 lead to either a data corruption or a CPU deadlock. Not fixed in 1049 any Cortex-A17 cores yet. 1050 This is identical to Cortex-A12 erratum 852422. It is a separate 1051 config option from the A12 erratum due to the way errata are checked 1052 for and handled. 1053 1054config ARM_ERRATA_857272 1055 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1056 depends on CPU_V7 1057 help 1058 This option enables the workaround for the 857272 Cortex-A17 erratum. 1059 This erratum is not known to be fixed in any A17 revision. 1060 This is identical to Cortex-A12 erratum 857271. It is a separate 1061 config option from the A12 erratum due to the way errata are checked 1062 for and handled. 1063 1064endmenu 1065 1066source "arch/arm/common/Kconfig" 1067 1068menu "Bus support" 1069 1070config ISA 1071 bool 1072 help 1073 Find out whether you have ISA slots on your motherboard. ISA is the 1074 name of a bus system, i.e. the way the CPU talks to the other stuff 1075 inside your box. Other bus systems are PCI, EISA, MicroChannel 1076 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1077 newer boards don't support it. If you have ISA, say Y, otherwise N. 1078 1079# Select ISA DMA controller support 1080config ISA_DMA 1081 bool 1082 select ISA_DMA_API 1083 1084# Select ISA DMA interface 1085config ISA_DMA_API 1086 bool 1087 1088config PCI_NANOENGINE 1089 bool "BSE nanoEngine PCI support" 1090 depends on SA1100_NANOENGINE 1091 help 1092 Enable PCI on the BSE nanoEngine board. 1093 1094config ARM_ERRATA_814220 1095 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1096 depends on CPU_V7 1097 help 1098 The v7 ARM states that all cache and branch predictor maintenance 1099 operations that do not specify an address execute, relative to 1100 each other, in program order. 1101 However, because of this erratum, an L2 set/way cache maintenance 1102 operation can overtake an L1 set/way cache maintenance operation. 1103 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1104 r0p4, r0p5. 1105 1106endmenu 1107 1108menu "Kernel Features" 1109 1110config HAVE_SMP 1111 bool 1112 help 1113 This option should be selected by machines which have an SMP- 1114 capable CPU. 1115 1116 The only effect of this option is to make the SMP-related 1117 options available to the user for configuration. 1118 1119config SMP 1120 bool "Symmetric Multi-Processing" 1121 depends on CPU_V6K || CPU_V7 1122 depends on HAVE_SMP 1123 depends on MMU || ARM_MPU 1124 select IRQ_WORK 1125 help 1126 This enables support for systems with more than one CPU. If you have 1127 a system with only one CPU, say N. If you have a system with more 1128 than one CPU, say Y. 1129 1130 If you say N here, the kernel will run on uni- and multiprocessor 1131 machines, but will use only one CPU of a multiprocessor machine. If 1132 you say Y here, the kernel will run on many, but not all, 1133 uniprocessor machines. On a uniprocessor machine, the kernel 1134 will run faster if you say N here. 1135 1136 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1137 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1138 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1139 1140 If you don't know what to do here, say N. 1141 1142config SMP_ON_UP 1143 bool "Allow booting SMP kernel on uniprocessor systems" 1144 depends on SMP && !XIP_KERNEL && MMU 1145 default y 1146 help 1147 SMP kernels contain instructions which fail on non-SMP processors. 1148 Enabling this option allows the kernel to modify itself to make 1149 these instructions safe. Disabling it allows about 1K of space 1150 savings. 1151 1152 If you don't know what to do here, say Y. 1153 1154 1155config CURRENT_POINTER_IN_TPIDRURO 1156 def_bool y 1157 depends on CPU_32v6K && !CPU_V6 1158 1159config IRQSTACKS 1160 def_bool y 1161 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1162 select HAVE_SOFTIRQ_ON_OWN_STACK 1163 1164config ARM_CPU_TOPOLOGY 1165 bool "Support cpu topology definition" 1166 depends on SMP && CPU_V7 1167 default y 1168 help 1169 Support ARM cpu topology definition. The MPIDR register defines 1170 affinity between processors which is then used to describe the cpu 1171 topology of an ARM System. 1172 1173config SCHED_MC 1174 bool "Multi-core scheduler support" 1175 depends on ARM_CPU_TOPOLOGY 1176 help 1177 Multi-core scheduler support improves the CPU scheduler's decision 1178 making when dealing with multi-core CPU chips at a cost of slightly 1179 increased overhead in some places. If unsure say N here. 1180 1181config SCHED_SMT 1182 bool "SMT scheduler support" 1183 depends on ARM_CPU_TOPOLOGY 1184 help 1185 Improves the CPU scheduler's decision making when dealing with 1186 MultiThreading at a cost of slightly increased overhead in some 1187 places. If unsure say N here. 1188 1189config HAVE_ARM_SCU 1190 bool 1191 help 1192 This option enables support for the ARM snoop control unit 1193 1194config HAVE_ARM_ARCH_TIMER 1195 bool "Architected timer support" 1196 depends on CPU_V7 1197 select ARM_ARCH_TIMER 1198 help 1199 This option enables support for the ARM architected timer 1200 1201config HAVE_ARM_TWD 1202 bool 1203 help 1204 This options enables support for the ARM timer and watchdog unit 1205 1206config MCPM 1207 bool "Multi-Cluster Power Management" 1208 depends on CPU_V7 && SMP 1209 help 1210 This option provides the common power management infrastructure 1211 for (multi-)cluster based systems, such as big.LITTLE based 1212 systems. 1213 1214config MCPM_QUAD_CLUSTER 1215 bool 1216 depends on MCPM 1217 help 1218 To avoid wasting resources unnecessarily, MCPM only supports up 1219 to 2 clusters by default. 1220 Platforms with 3 or 4 clusters that use MCPM must select this 1221 option to allow the additional clusters to be managed. 1222 1223config BIG_LITTLE 1224 bool "big.LITTLE support (Experimental)" 1225 depends on CPU_V7 && SMP 1226 select MCPM 1227 help 1228 This option enables support selections for the big.LITTLE 1229 system architecture. 1230 1231config BL_SWITCHER 1232 bool "big.LITTLE switcher support" 1233 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1234 select CPU_PM 1235 help 1236 The big.LITTLE "switcher" provides the core functionality to 1237 transparently handle transition between a cluster of A15's 1238 and a cluster of A7's in a big.LITTLE system. 1239 1240config BL_SWITCHER_DUMMY_IF 1241 tristate "Simple big.LITTLE switcher user interface" 1242 depends on BL_SWITCHER && DEBUG_KERNEL 1243 help 1244 This is a simple and dummy char dev interface to control 1245 the big.LITTLE switcher core code. It is meant for 1246 debugging purposes only. 1247 1248choice 1249 prompt "Memory split" 1250 depends on MMU 1251 default VMSPLIT_3G 1252 help 1253 Select the desired split between kernel and user memory. 1254 1255 If you are not absolutely sure what you are doing, leave this 1256 option alone! 1257 1258 config VMSPLIT_3G 1259 bool "3G/1G user/kernel split" 1260 config VMSPLIT_3G_OPT 1261 depends on !ARM_LPAE 1262 bool "3G/1G user/kernel split (for full 1G low memory)" 1263 config VMSPLIT_2G 1264 bool "2G/2G user/kernel split" 1265 config VMSPLIT_1G 1266 bool "1G/3G user/kernel split" 1267endchoice 1268 1269config PAGE_OFFSET 1270 hex 1271 default PHYS_OFFSET if !MMU 1272 default 0x40000000 if VMSPLIT_1G 1273 default 0x80000000 if VMSPLIT_2G 1274 default 0xB0000000 if VMSPLIT_3G_OPT 1275 default 0xC0000000 1276 1277config KASAN_SHADOW_OFFSET 1278 hex 1279 depends on KASAN 1280 default 0x1f000000 if PAGE_OFFSET=0x40000000 1281 default 0x5f000000 if PAGE_OFFSET=0x80000000 1282 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1283 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1284 default 0xffffffff 1285 1286config NR_CPUS 1287 int "Maximum number of CPUs (2-32)" 1288 range 2 16 if DEBUG_KMAP_LOCAL 1289 range 2 32 if !DEBUG_KMAP_LOCAL 1290 depends on SMP 1291 default "4" 1292 help 1293 The maximum number of CPUs that the kernel can support. 1294 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1295 debugging is enabled, which uses half of the per-CPU fixmap 1296 slots as guard regions. 1297 1298config HOTPLUG_CPU 1299 bool "Support for hot-pluggable CPUs" 1300 depends on SMP 1301 select GENERIC_IRQ_MIGRATION 1302 help 1303 Say Y here to experiment with turning CPUs off and on. CPUs 1304 can be controlled through /sys/devices/system/cpu. 1305 1306config ARM_PSCI 1307 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1308 depends on HAVE_ARM_SMCCC 1309 select ARM_PSCI_FW 1310 help 1311 Say Y here if you want Linux to communicate with system firmware 1312 implementing the PSCI specification for CPU-centric power 1313 management operations described in ARM document number ARM DEN 1314 0022A ("Power State Coordination Interface System Software on 1315 ARM processors"). 1316 1317# The GPIO number here must be sorted by descending number. In case of 1318# a multiplatform kernel, we just want the highest value required by the 1319# selected platforms. 1320config ARCH_NR_GPIO 1321 int 1322 default 2048 if ARCH_INTEL_SOCFPGA 1323 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1324 ARCH_ZYNQ || ARCH_ASPEED 1325 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1326 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1327 default 416 if ARCH_SUNXI 1328 default 392 if ARCH_U8500 1329 default 352 if ARCH_VT8500 1330 default 288 if ARCH_ROCKCHIP 1331 default 264 if MACH_H4700 1332 default 0 1333 help 1334 Maximum number of GPIOs in the system. 1335 1336 If unsure, leave the default value. 1337 1338config HZ_FIXED 1339 int 1340 default 128 if SOC_AT91RM9200 1341 default 0 1342 1343choice 1344 depends on HZ_FIXED = 0 1345 prompt "Timer frequency" 1346 1347config HZ_100 1348 bool "100 Hz" 1349 1350config HZ_200 1351 bool "200 Hz" 1352 1353config HZ_250 1354 bool "250 Hz" 1355 1356config HZ_300 1357 bool "300 Hz" 1358 1359config HZ_500 1360 bool "500 Hz" 1361 1362config HZ_1000 1363 bool "1000 Hz" 1364 1365endchoice 1366 1367config HZ 1368 int 1369 default HZ_FIXED if HZ_FIXED != 0 1370 default 100 if HZ_100 1371 default 200 if HZ_200 1372 default 250 if HZ_250 1373 default 300 if HZ_300 1374 default 500 if HZ_500 1375 default 1000 1376 1377config SCHED_HRTICK 1378 def_bool HIGH_RES_TIMERS 1379 1380config THUMB2_KERNEL 1381 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1382 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1383 default y if CPU_THUMBONLY 1384 select ARM_UNWIND 1385 help 1386 By enabling this option, the kernel will be compiled in 1387 Thumb-2 mode. 1388 1389 If unsure, say N. 1390 1391config ARM_PATCH_IDIV 1392 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1393 depends on CPU_32v7 && !XIP_KERNEL 1394 default y 1395 help 1396 The ARM compiler inserts calls to __aeabi_idiv() and 1397 __aeabi_uidiv() when it needs to perform division on signed 1398 and unsigned integers. Some v7 CPUs have support for the sdiv 1399 and udiv instructions that can be used to implement those 1400 functions. 1401 1402 Enabling this option allows the kernel to modify itself to 1403 replace the first two instructions of these library functions 1404 with the sdiv or udiv plus "bx lr" instructions when the CPU 1405 it is running on supports them. Typically this will be faster 1406 and less power intensive than running the original library 1407 code to do integer division. 1408 1409config AEABI 1410 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1411 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1412 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1413 help 1414 This option allows for the kernel to be compiled using the latest 1415 ARM ABI (aka EABI). This is only useful if you are using a user 1416 space environment that is also compiled with EABI. 1417 1418 Since there are major incompatibilities between the legacy ABI and 1419 EABI, especially with regard to structure member alignment, this 1420 option also changes the kernel syscall calling convention to 1421 disambiguate both ABIs and allow for backward compatibility support 1422 (selected with CONFIG_OABI_COMPAT). 1423 1424 To use this you need GCC version 4.0.0 or later. 1425 1426config OABI_COMPAT 1427 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1428 depends on AEABI && !THUMB2_KERNEL 1429 help 1430 This option preserves the old syscall interface along with the 1431 new (ARM EABI) one. It also provides a compatibility layer to 1432 intercept syscalls that have structure arguments which layout 1433 in memory differs between the legacy ABI and the new ARM EABI 1434 (only for non "thumb" binaries). This option adds a tiny 1435 overhead to all syscalls and produces a slightly larger kernel. 1436 1437 The seccomp filter system will not be available when this is 1438 selected, since there is no way yet to sensibly distinguish 1439 between calling conventions during filtering. 1440 1441 If you know you'll be using only pure EABI user space then you 1442 can say N here. If this option is not selected and you attempt 1443 to execute a legacy ABI binary then the result will be 1444 UNPREDICTABLE (in fact it can be predicted that it won't work 1445 at all). If in doubt say N. 1446 1447config ARCH_SELECT_MEMORY_MODEL 1448 bool 1449 1450config ARCH_FLATMEM_ENABLE 1451 bool 1452 1453config ARCH_SPARSEMEM_ENABLE 1454 bool 1455 select SPARSEMEM_STATIC if SPARSEMEM 1456 1457config HIGHMEM 1458 bool "High Memory Support" 1459 depends on MMU 1460 select KMAP_LOCAL 1461 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1462 help 1463 The address space of ARM processors is only 4 Gigabytes large 1464 and it has to accommodate user address space, kernel address 1465 space as well as some memory mapped IO. That means that, if you 1466 have a large amount of physical memory and/or IO, not all of the 1467 memory can be "permanently mapped" by the kernel. The physical 1468 memory that is not permanently mapped is called "high memory". 1469 1470 Depending on the selected kernel/user memory split, minimum 1471 vmalloc space and actual amount of RAM, you may not need this 1472 option which should result in a slightly faster kernel. 1473 1474 If unsure, say n. 1475 1476config HIGHPTE 1477 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1478 depends on HIGHMEM 1479 default y 1480 help 1481 The VM uses one page of physical memory for each page table. 1482 For systems with a lot of processes, this can use a lot of 1483 precious low memory, eventually leading to low memory being 1484 consumed by page tables. Setting this option will allow 1485 user-space 2nd level page tables to reside in high memory. 1486 1487config CPU_SW_DOMAIN_PAN 1488 bool "Enable use of CPU domains to implement privileged no-access" 1489 depends on MMU && !ARM_LPAE 1490 default y 1491 help 1492 Increase kernel security by ensuring that normal kernel accesses 1493 are unable to access userspace addresses. This can help prevent 1494 use-after-free bugs becoming an exploitable privilege escalation 1495 by ensuring that magic values (such as LIST_POISON) will always 1496 fault when dereferenced. 1497 1498 CPUs with low-vector mappings use a best-efforts implementation. 1499 Their lower 1MB needs to remain accessible for the vectors, but 1500 the remainder of userspace will become appropriately inaccessible. 1501 1502config HW_PERF_EVENTS 1503 def_bool y 1504 depends on ARM_PMU 1505 1506config ARM_MODULE_PLTS 1507 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1508 depends on MODULES 1509 default y 1510 help 1511 Allocate PLTs when loading modules so that jumps and calls whose 1512 targets are too far away for their relative offsets to be encoded 1513 in the instructions themselves can be bounced via veneers in the 1514 module's PLT. This allows modules to be allocated in the generic 1515 vmalloc area after the dedicated module memory area has been 1516 exhausted. The modules will use slightly more memory, but after 1517 rounding up to page size, the actual memory footprint is usually 1518 the same. 1519 1520 Disabling this is usually safe for small single-platform 1521 configurations. If unsure, say y. 1522 1523config FORCE_MAX_ZONEORDER 1524 int "Maximum zone order" 1525 default "12" if SOC_AM33XX 1526 default "9" if SA1111 1527 default "11" 1528 help 1529 The kernel memory allocator divides physically contiguous memory 1530 blocks into "zones", where each zone is a power of two number of 1531 pages. This option selects the largest power of two that the kernel 1532 keeps in the memory allocator. If you need to allocate very large 1533 blocks of physically contiguous memory, then you may need to 1534 increase this value. 1535 1536 This config option is actually maximum order plus one. For example, 1537 a value of 11 means that the largest free memory block is 2^10 pages. 1538 1539config ALIGNMENT_TRAP 1540 def_bool CPU_CP15_MMU 1541 select HAVE_PROC_CPU if PROC_FS 1542 help 1543 ARM processors cannot fetch/store information which is not 1544 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1545 address divisible by 4. On 32-bit ARM processors, these non-aligned 1546 fetch/store instructions will be emulated in software if you say 1547 here, which has a severe performance impact. This is necessary for 1548 correct operation of some network protocols. With an IP-only 1549 configuration it is safe to say N, otherwise say Y. 1550 1551config UACCESS_WITH_MEMCPY 1552 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1553 depends on MMU 1554 default y if CPU_FEROCEON 1555 help 1556 Implement faster copy_to_user and clear_user methods for CPU 1557 cores where a 8-word STM instruction give significantly higher 1558 memory write throughput than a sequence of individual 32bit stores. 1559 1560 A possible side effect is a slight increase in scheduling latency 1561 between threads sharing the same address space if they invoke 1562 such copy operations with large buffers. 1563 1564 However, if the CPU data cache is using a write-allocate mode, 1565 this option is unlikely to provide any performance gain. 1566 1567config PARAVIRT 1568 bool "Enable paravirtualization code" 1569 help 1570 This changes the kernel so it can modify itself when it is run 1571 under a hypervisor, potentially improving performance significantly 1572 over full virtualization. 1573 1574config PARAVIRT_TIME_ACCOUNTING 1575 bool "Paravirtual steal time accounting" 1576 select PARAVIRT 1577 help 1578 Select this option to enable fine granularity task steal time 1579 accounting. Time spent executing other tasks in parallel with 1580 the current vCPU is discounted from the vCPU power. To account for 1581 that, there can be a small performance impact. 1582 1583 If in doubt, say N here. 1584 1585config XEN_DOM0 1586 def_bool y 1587 depends on XEN 1588 1589config XEN 1590 bool "Xen guest support on ARM" 1591 depends on ARM && AEABI && OF 1592 depends on CPU_V7 && !CPU_V6 1593 depends on !GENERIC_ATOMIC64 1594 depends on MMU 1595 select ARCH_DMA_ADDR_T_64BIT 1596 select ARM_PSCI 1597 select SWIOTLB 1598 select SWIOTLB_XEN 1599 select PARAVIRT 1600 help 1601 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1602 1603config CC_HAVE_STACKPROTECTOR_TLS 1604 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1605 1606config STACKPROTECTOR_PER_TASK 1607 bool "Use a unique stack canary value for each task" 1608 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1609 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1610 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1611 default y 1612 help 1613 Due to the fact that GCC uses an ordinary symbol reference from 1614 which to load the value of the stack canary, this value can only 1615 change at reboot time on SMP systems, and all tasks running in the 1616 kernel's address space are forced to use the same canary value for 1617 the entire duration that the system is up. 1618 1619 Enable this option to switch to a different method that uses a 1620 different canary value for each task. 1621 1622endmenu 1623 1624menu "Boot options" 1625 1626config USE_OF 1627 bool "Flattened Device Tree support" 1628 select IRQ_DOMAIN 1629 select OF 1630 help 1631 Include support for flattened device tree machine descriptions. 1632 1633config ATAGS 1634 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1635 default y 1636 help 1637 This is the traditional way of passing data to the kernel at boot 1638 time. If you are solely relying on the flattened device tree (or 1639 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1640 to remove ATAGS support from your kernel binary. If unsure, 1641 leave this to y. 1642 1643config DEPRECATED_PARAM_STRUCT 1644 bool "Provide old way to pass kernel parameters" 1645 depends on ATAGS 1646 help 1647 This was deprecated in 2001 and announced to live on for 5 years. 1648 Some old boot loaders still use this way. 1649 1650# Compressed boot loader in ROM. Yes, we really want to ask about 1651# TEXT and BSS so we preserve their values in the config files. 1652config ZBOOT_ROM_TEXT 1653 hex "Compressed ROM boot loader base address" 1654 default 0x0 1655 help 1656 The physical address at which the ROM-able zImage is to be 1657 placed in the target. Platforms which normally make use of 1658 ROM-able zImage formats normally set this to a suitable 1659 value in their defconfig file. 1660 1661 If ZBOOT_ROM is not enabled, this has no effect. 1662 1663config ZBOOT_ROM_BSS 1664 hex "Compressed ROM boot loader BSS address" 1665 default 0x0 1666 help 1667 The base address of an area of read/write memory in the target 1668 for the ROM-able zImage which must be available while the 1669 decompressor is running. It must be large enough to hold the 1670 entire decompressed kernel plus an additional 128 KiB. 1671 Platforms which normally make use of ROM-able zImage formats 1672 normally set this to a suitable value in their defconfig file. 1673 1674 If ZBOOT_ROM is not enabled, this has no effect. 1675 1676config ZBOOT_ROM 1677 bool "Compressed boot loader in ROM/flash" 1678 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1679 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1680 help 1681 Say Y here if you intend to execute your compressed kernel image 1682 (zImage) directly from ROM or flash. If unsure, say N. 1683 1684config ARM_APPENDED_DTB 1685 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1686 depends on OF 1687 help 1688 With this option, the boot code will look for a device tree binary 1689 (DTB) appended to zImage 1690 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1691 1692 This is meant as a backward compatibility convenience for those 1693 systems with a bootloader that can't be upgraded to accommodate 1694 the documented boot protocol using a device tree. 1695 1696 Beware that there is very little in terms of protection against 1697 this option being confused by leftover garbage in memory that might 1698 look like a DTB header after a reboot if no actual DTB is appended 1699 to zImage. Do not leave this option active in a production kernel 1700 if you don't intend to always append a DTB. Proper passing of the 1701 location into r2 of a bootloader provided DTB is always preferable 1702 to this option. 1703 1704config ARM_ATAG_DTB_COMPAT 1705 bool "Supplement the appended DTB with traditional ATAG information" 1706 depends on ARM_APPENDED_DTB 1707 help 1708 Some old bootloaders can't be updated to a DTB capable one, yet 1709 they provide ATAGs with memory configuration, the ramdisk address, 1710 the kernel cmdline string, etc. Such information is dynamically 1711 provided by the bootloader and can't always be stored in a static 1712 DTB. To allow a device tree enabled kernel to be used with such 1713 bootloaders, this option allows zImage to extract the information 1714 from the ATAG list and store it at run time into the appended DTB. 1715 1716choice 1717 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1718 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1719 1720config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1721 bool "Use bootloader kernel arguments if available" 1722 help 1723 Uses the command-line options passed by the boot loader instead of 1724 the device tree bootargs property. If the boot loader doesn't provide 1725 any, the device tree bootargs property will be used. 1726 1727config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1728 bool "Extend with bootloader kernel arguments" 1729 help 1730 The command-line arguments provided by the boot loader will be 1731 appended to the the device tree bootargs property. 1732 1733endchoice 1734 1735config CMDLINE 1736 string "Default kernel command string" 1737 default "" 1738 help 1739 On some architectures (e.g. CATS), there is currently no way 1740 for the boot loader to pass arguments to the kernel. For these 1741 architectures, you should supply some command-line options at build 1742 time by entering them here. As a minimum, you should specify the 1743 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1744 1745choice 1746 prompt "Kernel command line type" if CMDLINE != "" 1747 default CMDLINE_FROM_BOOTLOADER 1748 depends on ATAGS 1749 1750config CMDLINE_FROM_BOOTLOADER 1751 bool "Use bootloader kernel arguments if available" 1752 help 1753 Uses the command-line options passed by the boot loader. If 1754 the boot loader doesn't provide any, the default kernel command 1755 string provided in CMDLINE will be used. 1756 1757config CMDLINE_EXTEND 1758 bool "Extend bootloader kernel arguments" 1759 help 1760 The command-line arguments provided by the boot loader will be 1761 appended to the default kernel command string. 1762 1763config CMDLINE_FORCE 1764 bool "Always use the default kernel command string" 1765 help 1766 Always use the default kernel command string, even if the boot 1767 loader passes other arguments to the kernel. 1768 This is useful if you cannot or don't want to change the 1769 command-line options your boot loader passes to the kernel. 1770endchoice 1771 1772config XIP_KERNEL 1773 bool "Kernel Execute-In-Place from ROM" 1774 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1775 help 1776 Execute-In-Place allows the kernel to run from non-volatile storage 1777 directly addressable by the CPU, such as NOR flash. This saves RAM 1778 space since the text section of the kernel is not loaded from flash 1779 to RAM. Read-write sections, such as the data section and stack, 1780 are still copied to RAM. The XIP kernel is not compressed since 1781 it has to run directly from flash, so it will take more space to 1782 store it. The flash address used to link the kernel object files, 1783 and for storing it, is configuration dependent. Therefore, if you 1784 say Y here, you must know the proper physical address where to 1785 store the kernel image depending on your own flash memory usage. 1786 1787 Also note that the make target becomes "make xipImage" rather than 1788 "make zImage" or "make Image". The final kernel binary to put in 1789 ROM memory will be arch/arm/boot/xipImage. 1790 1791 If unsure, say N. 1792 1793config XIP_PHYS_ADDR 1794 hex "XIP Kernel Physical Location" 1795 depends on XIP_KERNEL 1796 default "0x00080000" 1797 help 1798 This is the physical address in your flash memory the kernel will 1799 be linked for and stored to. This address is dependent on your 1800 own flash usage. 1801 1802config XIP_DEFLATED_DATA 1803 bool "Store kernel .data section compressed in ROM" 1804 depends on XIP_KERNEL 1805 select ZLIB_INFLATE 1806 help 1807 Before the kernel is actually executed, its .data section has to be 1808 copied to RAM from ROM. This option allows for storing that data 1809 in compressed form and decompressed to RAM rather than merely being 1810 copied, saving some precious ROM space. A possible drawback is a 1811 slightly longer boot delay. 1812 1813config KEXEC 1814 bool "Kexec system call (EXPERIMENTAL)" 1815 depends on (!SMP || PM_SLEEP_SMP) 1816 depends on MMU 1817 select KEXEC_CORE 1818 help 1819 kexec is a system call that implements the ability to shutdown your 1820 current kernel, and to start another kernel. It is like a reboot 1821 but it is independent of the system firmware. And like a reboot 1822 you can start any kernel with it, not just Linux. 1823 1824 It is an ongoing process to be certain the hardware in a machine 1825 is properly shutdown, so do not be surprised if this code does not 1826 initially work for you. 1827 1828config ATAGS_PROC 1829 bool "Export atags in procfs" 1830 depends on ATAGS && KEXEC 1831 default y 1832 help 1833 Should the atags used to boot the kernel be exported in an "atags" 1834 file in procfs. Useful with kexec. 1835 1836config CRASH_DUMP 1837 bool "Build kdump crash kernel (EXPERIMENTAL)" 1838 help 1839 Generate crash dump after being started by kexec. This should 1840 be normally only set in special crash dump kernels which are 1841 loaded in the main kernel with kexec-tools into a specially 1842 reserved region and then later executed after a crash by 1843 kdump/kexec. The crash dump kernel must be compiled to a 1844 memory address not used by the main kernel 1845 1846 For more details see Documentation/admin-guide/kdump/kdump.rst 1847 1848config AUTO_ZRELADDR 1849 bool "Auto calculation of the decompressed kernel image address" 1850 help 1851 ZRELADDR is the physical address where the decompressed kernel 1852 image will be placed. If AUTO_ZRELADDR is selected, the address 1853 will be determined at run-time, either by masking the current IP 1854 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1855 This assumes the zImage being placed in the first 128MB from 1856 start of memory. 1857 1858config EFI_STUB 1859 bool 1860 1861config EFI 1862 bool "UEFI runtime support" 1863 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1864 select UCS2_STRING 1865 select EFI_PARAMS_FROM_FDT 1866 select EFI_STUB 1867 select EFI_GENERIC_STUB 1868 select EFI_RUNTIME_WRAPPERS 1869 help 1870 This option provides support for runtime services provided 1871 by UEFI firmware (such as non-volatile variables, realtime 1872 clock, and platform reset). A UEFI stub is also provided to 1873 allow the kernel to be booted as an EFI application. This 1874 is only useful for kernels that may run on systems that have 1875 UEFI firmware. 1876 1877config DMI 1878 bool "Enable support for SMBIOS (DMI) tables" 1879 depends on EFI 1880 default y 1881 help 1882 This enables SMBIOS/DMI feature for systems. 1883 1884 This option is only useful on systems that have UEFI firmware. 1885 However, even with this option, the resultant kernel should 1886 continue to boot on existing non-UEFI platforms. 1887 1888 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1889 i.e., the the practice of identifying the platform via DMI to 1890 decide whether certain workarounds for buggy hardware and/or 1891 firmware need to be enabled. This would require the DMI subsystem 1892 to be enabled much earlier than we do on ARM, which is non-trivial. 1893 1894endmenu 1895 1896menu "CPU Power Management" 1897 1898source "drivers/cpufreq/Kconfig" 1899 1900source "drivers/cpuidle/Kconfig" 1901 1902endmenu 1903 1904menu "Floating point emulation" 1905 1906comment "At least one emulation must be selected" 1907 1908config FPE_NWFPE 1909 bool "NWFPE math emulation" 1910 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1911 help 1912 Say Y to include the NWFPE floating point emulator in the kernel. 1913 This is necessary to run most binaries. Linux does not currently 1914 support floating point hardware so you need to say Y here even if 1915 your machine has an FPA or floating point co-processor podule. 1916 1917 You may say N here if you are going to load the Acorn FPEmulator 1918 early in the bootup. 1919 1920config FPE_NWFPE_XP 1921 bool "Support extended precision" 1922 depends on FPE_NWFPE 1923 help 1924 Say Y to include 80-bit support in the kernel floating-point 1925 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1926 Note that gcc does not generate 80-bit operations by default, 1927 so in most cases this option only enlarges the size of the 1928 floating point emulator without any good reason. 1929 1930 You almost surely want to say N here. 1931 1932config FPE_FASTFPE 1933 bool "FastFPE math emulation (EXPERIMENTAL)" 1934 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1935 help 1936 Say Y here to include the FAST floating point emulator in the kernel. 1937 This is an experimental much faster emulator which now also has full 1938 precision for the mantissa. It does not support any exceptions. 1939 It is very simple, and approximately 3-6 times faster than NWFPE. 1940 1941 It should be sufficient for most programs. It may be not suitable 1942 for scientific calculations, but you have to check this for yourself. 1943 If you do not feel you need a faster FP emulation you should better 1944 choose NWFPE. 1945 1946config VFP 1947 bool "VFP-format floating point maths" 1948 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1949 help 1950 Say Y to include VFP support code in the kernel. This is needed 1951 if your hardware includes a VFP unit. 1952 1953 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1954 release notes and additional status information. 1955 1956 Say N if your target does not have VFP hardware. 1957 1958config VFPv3 1959 bool 1960 depends on VFP 1961 default y if CPU_V7 1962 1963config NEON 1964 bool "Advanced SIMD (NEON) Extension support" 1965 depends on VFPv3 && CPU_V7 1966 help 1967 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1968 Extension. 1969 1970config KERNEL_MODE_NEON 1971 bool "Support for NEON in kernel mode" 1972 depends on NEON && AEABI 1973 help 1974 Say Y to include support for NEON in kernel mode. 1975 1976endmenu 1977 1978menu "Power management options" 1979 1980source "kernel/power/Kconfig" 1981 1982config ARCH_SUSPEND_POSSIBLE 1983 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1984 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1985 def_bool y 1986 1987config ARM_CPU_SUSPEND 1988 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1989 depends on ARCH_SUSPEND_POSSIBLE 1990 1991config ARCH_HIBERNATION_POSSIBLE 1992 bool 1993 depends on MMU 1994 default y if ARCH_SUSPEND_POSSIBLE 1995 1996endmenu 1997 1998if CRYPTO 1999source "arch/arm/crypto/Kconfig" 2000endif 2001 2002source "arch/arm/Kconfig.assembler" 2003