1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if !XIP_KERNEL 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 20 select HAVE_GENERIC_DMA_COHERENT 21 select HAVE_KERNEL_GZIP 22 select HAVE_KERNEL_LZO 23 select HAVE_KERNEL_LZMA 24 select HAVE_KERNEL_XZ 25 select HAVE_IRQ_WORK 26 select HAVE_PERF_EVENTS 27 select PERF_USE_VMALLOC 28 select HAVE_REGS_AND_STACK_ACCESS_API 29 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 30 select HAVE_C_RECORDMCOUNT 31 select HAVE_GENERIC_HARDIRQS 32 select HAVE_SPARSE_IRQ 33 select GENERIC_IRQ_SHOW 34 select CPU_PM if (SUSPEND || CPU_IDLE) 35 select GENERIC_PCI_IOMAP 36 help 37 The ARM series is a line of low-power-consumption RISC chip designs 38 licensed by ARM Ltd and targeted at embedded applications and 39 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 40 manufactured, but legacy ARM-based PC hardware remains popular in 41 Europe. There is an ARM Linux project with a web page at 42 <http://www.arm.linux.org.uk/>. 43 44config ARM_HAS_SG_CHAIN 45 bool 46 47config HAVE_PWM 48 bool 49 50config MIGHT_HAVE_PCI 51 bool 52 53config SYS_SUPPORTS_APM_EMULATION 54 bool 55 56config HAVE_SCHED_CLOCK 57 bool 58 59config GENERIC_GPIO 60 bool 61 62config ARCH_USES_GETTIMEOFFSET 63 bool 64 default n 65 66config GENERIC_CLOCKEVENTS 67 bool 68 69config GENERIC_CLOCKEVENTS_BROADCAST 70 bool 71 depends on GENERIC_CLOCKEVENTS 72 default y if SMP 73 74config KTIME_SCALAR 75 bool 76 default y 77 78config HAVE_TCM 79 bool 80 select GENERIC_ALLOCATOR 81 82config HAVE_PROC_CPU 83 bool 84 85config NO_IOPORT 86 bool 87 88config EISA 89 bool 90 ---help--- 91 The Extended Industry Standard Architecture (EISA) bus was 92 developed as an open alternative to the IBM MicroChannel bus. 93 94 The EISA bus provided some of the features of the IBM MicroChannel 95 bus while maintaining backward compatibility with cards made for 96 the older ISA bus. The EISA bus saw limited use between 1988 and 97 1995 when it was made obsolete by the PCI bus. 98 99 Say Y here if you are building a kernel for an EISA-based machine. 100 101 Otherwise, say N. 102 103config SBUS 104 bool 105 106config MCA 107 bool 108 help 109 MicroChannel Architecture is found in some IBM PS/2 machines and 110 laptops. It is a bus system similar to PCI or ISA. See 111 <file:Documentation/mca.txt> (and especially the web page given 112 there) before attempting to build an MCA bus kernel. 113 114config STACKTRACE_SUPPORT 115 bool 116 default y 117 118config HAVE_LATENCYTOP_SUPPORT 119 bool 120 depends on !SMP 121 default y 122 123config LOCKDEP_SUPPORT 124 bool 125 default y 126 127config TRACE_IRQFLAGS_SUPPORT 128 bool 129 default y 130 131config HARDIRQS_SW_RESEND 132 bool 133 default y 134 135config GENERIC_IRQ_PROBE 136 bool 137 default y 138 139config GENERIC_LOCKBREAK 140 bool 141 default y 142 depends on SMP && PREEMPT 143 144config RWSEM_GENERIC_SPINLOCK 145 bool 146 default y 147 148config RWSEM_XCHGADD_ALGORITHM 149 bool 150 151config ARCH_HAS_ILOG2_U32 152 bool 153 154config ARCH_HAS_ILOG2_U64 155 bool 156 157config ARCH_HAS_CPUFREQ 158 bool 159 help 160 Internal node to signify that the ARCH has CPUFREQ support 161 and that the relevant menu configurations are displayed for 162 it. 163 164config ARCH_HAS_CPU_IDLE_WAIT 165 def_bool y 166 167config GENERIC_HWEIGHT 168 bool 169 default y 170 171config GENERIC_CALIBRATE_DELAY 172 bool 173 default y 174 175config ARCH_MAY_HAVE_PC_FDC 176 bool 177 178config ZONE_DMA 179 bool 180 181config NEED_DMA_MAP_STATE 182 def_bool y 183 184config GENERIC_ISA_DMA 185 bool 186 187config FIQ 188 bool 189 190config ARCH_MTD_XIP 191 bool 192 193config VECTORS_BASE 194 hex 195 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 196 default DRAM_BASE if REMAP_VECTORS_TO_RAM 197 default 0x00000000 198 help 199 The base address of exception vectors. 200 201config ARM_PATCH_PHYS_VIRT 202 bool "Patch physical to virtual translations at runtime" if EMBEDDED 203 default y 204 depends on !XIP_KERNEL && MMU 205 depends on !ARCH_REALVIEW || !SPARSEMEM 206 help 207 Patch phys-to-virt and virt-to-phys translation functions at 208 boot and module load time according to the position of the 209 kernel in system memory. 210 211 This can only be used with non-XIP MMU kernels where the base 212 of physical memory is at a 16MB boundary. 213 214 Only disable this option if you know that you do not require 215 this feature (eg, building a kernel for a single machine) and 216 you need to shrink the kernel to the minimal size. 217 218config NEED_MACH_MEMORY_H 219 bool 220 help 221 Select this when mach/memory.h is required to provide special 222 definitions for this platform. The need for mach/memory.h should 223 be avoided when possible. 224 225config PHYS_OFFSET 226 hex "Physical address of main memory" if MMU 227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 228 default DRAM_BASE if !MMU 229 help 230 Please provide the physical address corresponding to the 231 location of main memory in your system. 232 233config GENERIC_BUG 234 def_bool y 235 depends on BUG 236 237source "init/Kconfig" 238 239source "kernel/Kconfig.freezer" 240 241menu "System Type" 242 243config MMU 244 bool "MMU-based Paged Memory Management Support" 245 default y 246 help 247 Select if you want MMU-based virtualised addressing space 248 support by paged memory management. If unsure, say 'Y'. 249 250# 251# The "ARM system type" choice list is ordered alphabetically by option 252# text. Please add new entries in the option alphabetic order. 253# 254choice 255 prompt "ARM system type" 256 default ARCH_VERSATILE 257 258config ARCH_INTEGRATOR 259 bool "ARM Ltd. Integrator family" 260 select ARM_AMBA 261 select ARCH_HAS_CPUFREQ 262 select CLKDEV_LOOKUP 263 select HAVE_MACH_CLKDEV 264 select HAVE_TCM 265 select ICST 266 select GENERIC_CLOCKEVENTS 267 select PLAT_VERSATILE 268 select PLAT_VERSATILE_FPGA_IRQ 269 select NEED_MACH_MEMORY_H 270 help 271 Support for ARM's Integrator platform. 272 273config ARCH_REALVIEW 274 bool "ARM Ltd. RealView family" 275 select ARM_AMBA 276 select CLKDEV_LOOKUP 277 select HAVE_MACH_CLKDEV 278 select ICST 279 select GENERIC_CLOCKEVENTS 280 select ARCH_WANT_OPTIONAL_GPIOLIB 281 select PLAT_VERSATILE 282 select PLAT_VERSATILE_CLCD 283 select ARM_TIMER_SP804 284 select GPIO_PL061 if GPIOLIB 285 select NEED_MACH_MEMORY_H 286 help 287 This enables support for ARM Ltd RealView boards. 288 289config ARCH_VERSATILE 290 bool "ARM Ltd. Versatile family" 291 select ARM_AMBA 292 select ARM_VIC 293 select CLKDEV_LOOKUP 294 select HAVE_MACH_CLKDEV 295 select ICST 296 select GENERIC_CLOCKEVENTS 297 select ARCH_WANT_OPTIONAL_GPIOLIB 298 select PLAT_VERSATILE 299 select PLAT_VERSATILE_CLCD 300 select PLAT_VERSATILE_FPGA_IRQ 301 select ARM_TIMER_SP804 302 help 303 This enables support for ARM Ltd Versatile board. 304 305config ARCH_VEXPRESS 306 bool "ARM Ltd. Versatile Express family" 307 select ARCH_WANT_OPTIONAL_GPIOLIB 308 select ARM_AMBA 309 select ARM_TIMER_SP804 310 select CLKDEV_LOOKUP 311 select HAVE_MACH_CLKDEV 312 select GENERIC_CLOCKEVENTS 313 select HAVE_CLK 314 select HAVE_PATA_PLATFORM 315 select ICST 316 select NO_IOPORT 317 select PLAT_VERSATILE 318 select PLAT_VERSATILE_CLCD 319 help 320 This enables support for the ARM Ltd Versatile Express boards. 321 322config ARCH_AT91 323 bool "Atmel AT91" 324 select ARCH_REQUIRE_GPIOLIB 325 select HAVE_CLK 326 select CLKDEV_LOOKUP 327 help 328 This enables support for systems based on the Atmel AT91RM9200, 329 AT91SAM9 and AT91CAP9 processors. 330 331config ARCH_BCMRING 332 bool "Broadcom BCMRING" 333 depends on MMU 334 select CPU_V6 335 select ARM_AMBA 336 select ARM_TIMER_SP804 337 select CLKDEV_LOOKUP 338 select GENERIC_CLOCKEVENTS 339 select ARCH_WANT_OPTIONAL_GPIOLIB 340 help 341 Support for Broadcom's BCMRing platform. 342 343config ARCH_HIGHBANK 344 bool "Calxeda Highbank-based" 345 select ARCH_WANT_OPTIONAL_GPIOLIB 346 select ARM_AMBA 347 select ARM_GIC 348 select ARM_TIMER_SP804 349 select CACHE_L2X0 350 select CLKDEV_LOOKUP 351 select CPU_V7 352 select GENERIC_CLOCKEVENTS 353 select HAVE_ARM_SCU 354 select HAVE_SMP 355 select USE_OF 356 help 357 Support for the Calxeda Highbank SoC based boards. 358 359config ARCH_CLPS711X 360 bool "Cirrus Logic CLPS711x/EP721x-based" 361 select CPU_ARM720T 362 select ARCH_USES_GETTIMEOFFSET 363 select NEED_MACH_MEMORY_H 364 help 365 Support for Cirrus Logic 711x/721x based boards. 366 367config ARCH_CNS3XXX 368 bool "Cavium Networks CNS3XXX family" 369 select CPU_V6K 370 select GENERIC_CLOCKEVENTS 371 select ARM_GIC 372 select MIGHT_HAVE_CACHE_L2X0 373 select MIGHT_HAVE_PCI 374 select PCI_DOMAINS if PCI 375 help 376 Support for Cavium Networks CNS3XXX platform. 377 378config ARCH_GEMINI 379 bool "Cortina Systems Gemini" 380 select CPU_FA526 381 select ARCH_REQUIRE_GPIOLIB 382 select ARCH_USES_GETTIMEOFFSET 383 help 384 Support for the Cortina Systems Gemini family SoCs 385 386config ARCH_PRIMA2 387 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 388 select CPU_V7 389 select NO_IOPORT 390 select GENERIC_CLOCKEVENTS 391 select CLKDEV_LOOKUP 392 select GENERIC_IRQ_CHIP 393 select MIGHT_HAVE_CACHE_L2X0 394 select USE_OF 395 select ZONE_DMA 396 help 397 Support for CSR SiRFSoC ARM Cortex A9 Platform 398 399config ARCH_EBSA110 400 bool "EBSA-110" 401 select CPU_SA110 402 select ISA 403 select NO_IOPORT 404 select ARCH_USES_GETTIMEOFFSET 405 select NEED_MACH_MEMORY_H 406 help 407 This is an evaluation board for the StrongARM processor available 408 from Digital. It has limited hardware on-board, including an 409 Ethernet interface, two PCMCIA sockets, two serial ports and a 410 parallel port. 411 412config ARCH_EP93XX 413 bool "EP93xx-based" 414 select CPU_ARM920T 415 select ARM_AMBA 416 select ARM_VIC 417 select CLKDEV_LOOKUP 418 select ARCH_REQUIRE_GPIOLIB 419 select ARCH_HAS_HOLES_MEMORYMODEL 420 select ARCH_USES_GETTIMEOFFSET 421 select NEED_MACH_MEMORY_H 422 help 423 This enables support for the Cirrus EP93xx series of CPUs. 424 425config ARCH_FOOTBRIDGE 426 bool "FootBridge" 427 select CPU_SA110 428 select FOOTBRIDGE 429 select GENERIC_CLOCKEVENTS 430 select HAVE_IDE 431 select NEED_MACH_MEMORY_H 432 help 433 Support for systems based on the DC21285 companion chip 434 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 435 436config ARCH_MXC 437 bool "Freescale MXC/iMX-based" 438 select GENERIC_CLOCKEVENTS 439 select ARCH_REQUIRE_GPIOLIB 440 select CLKDEV_LOOKUP 441 select CLKSRC_MMIO 442 select GENERIC_IRQ_CHIP 443 select HAVE_SCHED_CLOCK 444 select MULTI_IRQ_HANDLER 445 help 446 Support for Freescale MXC/iMX-based family of processors 447 448config ARCH_MXS 449 bool "Freescale MXS-based" 450 select GENERIC_CLOCKEVENTS 451 select ARCH_REQUIRE_GPIOLIB 452 select CLKDEV_LOOKUP 453 select CLKSRC_MMIO 454 select HAVE_CLK_PREPARE 455 help 456 Support for Freescale MXS-based family of processors 457 458config ARCH_NETX 459 bool "Hilscher NetX based" 460 select CLKSRC_MMIO 461 select CPU_ARM926T 462 select ARM_VIC 463 select GENERIC_CLOCKEVENTS 464 help 465 This enables support for systems based on the Hilscher NetX Soc 466 467config ARCH_H720X 468 bool "Hynix HMS720x-based" 469 select CPU_ARM720T 470 select ISA_DMA_API 471 select ARCH_USES_GETTIMEOFFSET 472 help 473 This enables support for systems based on the Hynix HMS720x 474 475config ARCH_IOP13XX 476 bool "IOP13xx-based" 477 depends on MMU 478 select CPU_XSC3 479 select PLAT_IOP 480 select PCI 481 select ARCH_SUPPORTS_MSI 482 select VMSPLIT_1G 483 select NEED_MACH_MEMORY_H 484 help 485 Support for Intel's IOP13XX (XScale) family of processors. 486 487config ARCH_IOP32X 488 bool "IOP32x-based" 489 depends on MMU 490 select CPU_XSCALE 491 select PLAT_IOP 492 select PCI 493 select ARCH_REQUIRE_GPIOLIB 494 help 495 Support for Intel's 80219 and IOP32X (XScale) family of 496 processors. 497 498config ARCH_IOP33X 499 bool "IOP33x-based" 500 depends on MMU 501 select CPU_XSCALE 502 select PLAT_IOP 503 select PCI 504 select ARCH_REQUIRE_GPIOLIB 505 help 506 Support for Intel's IOP33X (XScale) family of processors. 507 508config ARCH_IXP23XX 509 bool "IXP23XX-based" 510 depends on MMU 511 select CPU_XSC3 512 select PCI 513 select ARCH_USES_GETTIMEOFFSET 514 select NEED_MACH_MEMORY_H 515 help 516 Support for Intel's IXP23xx (XScale) family of processors. 517 518config ARCH_IXP2000 519 bool "IXP2400/2800-based" 520 depends on MMU 521 select CPU_XSCALE 522 select PCI 523 select ARCH_USES_GETTIMEOFFSET 524 select NEED_MACH_MEMORY_H 525 help 526 Support for Intel's IXP2400/2800 (XScale) family of processors. 527 528config ARCH_IXP4XX 529 bool "IXP4xx-based" 530 depends on MMU 531 select CLKSRC_MMIO 532 select CPU_XSCALE 533 select GENERIC_GPIO 534 select GENERIC_CLOCKEVENTS 535 select HAVE_SCHED_CLOCK 536 select MIGHT_HAVE_PCI 537 select DMABOUNCE if PCI 538 help 539 Support for Intel's IXP4XX (XScale) family of processors. 540 541config ARCH_DOVE 542 bool "Marvell Dove" 543 select CPU_V7 544 select PCI 545 select ARCH_REQUIRE_GPIOLIB 546 select GENERIC_CLOCKEVENTS 547 select PLAT_ORION 548 help 549 Support for the Marvell Dove SoC 88AP510 550 551config ARCH_KIRKWOOD 552 bool "Marvell Kirkwood" 553 select CPU_FEROCEON 554 select PCI 555 select ARCH_REQUIRE_GPIOLIB 556 select GENERIC_CLOCKEVENTS 557 select PLAT_ORION 558 help 559 Support for the following Marvell Kirkwood series SoCs: 560 88F6180, 88F6192 and 88F6281. 561 562config ARCH_LPC32XX 563 bool "NXP LPC32XX" 564 select CLKSRC_MMIO 565 select CPU_ARM926T 566 select ARCH_REQUIRE_GPIOLIB 567 select HAVE_IDE 568 select ARM_AMBA 569 select USB_ARCH_HAS_OHCI 570 select CLKDEV_LOOKUP 571 select GENERIC_CLOCKEVENTS 572 help 573 Support for the NXP LPC32XX family of processors 574 575config ARCH_MV78XX0 576 bool "Marvell MV78xx0" 577 select CPU_FEROCEON 578 select PCI 579 select ARCH_REQUIRE_GPIOLIB 580 select GENERIC_CLOCKEVENTS 581 select PLAT_ORION 582 help 583 Support for the following Marvell MV78xx0 series SoCs: 584 MV781x0, MV782x0. 585 586config ARCH_ORION5X 587 bool "Marvell Orion" 588 depends on MMU 589 select CPU_FEROCEON 590 select PCI 591 select ARCH_REQUIRE_GPIOLIB 592 select GENERIC_CLOCKEVENTS 593 select PLAT_ORION 594 help 595 Support for the following Marvell Orion 5x series SoCs: 596 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 597 Orion-2 (5281), Orion-1-90 (6183). 598 599config ARCH_MMP 600 bool "Marvell PXA168/910/MMP2" 601 depends on MMU 602 select ARCH_REQUIRE_GPIOLIB 603 select CLKDEV_LOOKUP 604 select GENERIC_CLOCKEVENTS 605 select GPIO_PXA 606 select HAVE_SCHED_CLOCK 607 select TICK_ONESHOT 608 select PLAT_PXA 609 select SPARSE_IRQ 610 select GENERIC_ALLOCATOR 611 help 612 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 613 614config ARCH_KS8695 615 bool "Micrel/Kendin KS8695" 616 select CPU_ARM922T 617 select ARCH_REQUIRE_GPIOLIB 618 select ARCH_USES_GETTIMEOFFSET 619 select NEED_MACH_MEMORY_H 620 help 621 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 622 System-on-Chip devices. 623 624config ARCH_W90X900 625 bool "Nuvoton W90X900 CPU" 626 select CPU_ARM926T 627 select ARCH_REQUIRE_GPIOLIB 628 select CLKDEV_LOOKUP 629 select CLKSRC_MMIO 630 select GENERIC_CLOCKEVENTS 631 help 632 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 633 At present, the w90x900 has been renamed nuc900, regarding 634 the ARM series product line, you can login the following 635 link address to know more. 636 637 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 638 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 639 640config ARCH_TEGRA 641 bool "NVIDIA Tegra" 642 select CLKDEV_LOOKUP 643 select CLKSRC_MMIO 644 select GENERIC_CLOCKEVENTS 645 select GENERIC_GPIO 646 select HAVE_CLK 647 select HAVE_SCHED_CLOCK 648 select HAVE_SMP 649 select MIGHT_HAVE_CACHE_L2X0 650 select ARCH_HAS_CPUFREQ 651 help 652 This enables support for NVIDIA Tegra based systems (Tegra APX, 653 Tegra 6xx and Tegra 2 series). 654 655config ARCH_PICOXCELL 656 bool "Picochip picoXcell" 657 select ARCH_REQUIRE_GPIOLIB 658 select ARM_PATCH_PHYS_VIRT 659 select ARM_VIC 660 select CPU_V6K 661 select DW_APB_TIMER 662 select GENERIC_CLOCKEVENTS 663 select GENERIC_GPIO 664 select HAVE_SCHED_CLOCK 665 select HAVE_TCM 666 select NO_IOPORT 667 select SPARSE_IRQ 668 select USE_OF 669 help 670 This enables support for systems based on the Picochip picoXcell 671 family of Femtocell devices. The picoxcell support requires device tree 672 for all boards. 673 674config ARCH_PNX4008 675 bool "Philips Nexperia PNX4008 Mobile" 676 select CPU_ARM926T 677 select CLKDEV_LOOKUP 678 select ARCH_USES_GETTIMEOFFSET 679 help 680 This enables support for Philips PNX4008 mobile platform. 681 682config ARCH_PXA 683 bool "PXA2xx/PXA3xx-based" 684 depends on MMU 685 select ARCH_MTD_XIP 686 select ARCH_HAS_CPUFREQ 687 select CLKDEV_LOOKUP 688 select CLKSRC_MMIO 689 select ARCH_REQUIRE_GPIOLIB 690 select GENERIC_CLOCKEVENTS 691 select GPIO_PXA 692 select HAVE_SCHED_CLOCK 693 select TICK_ONESHOT 694 select PLAT_PXA 695 select SPARSE_IRQ 696 select AUTO_ZRELADDR 697 select MULTI_IRQ_HANDLER 698 select ARM_CPU_SUSPEND if PM 699 select HAVE_IDE 700 help 701 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 702 703config ARCH_MSM 704 bool "Qualcomm MSM" 705 select HAVE_CLK 706 select GENERIC_CLOCKEVENTS 707 select ARCH_REQUIRE_GPIOLIB 708 select CLKDEV_LOOKUP 709 help 710 Support for Qualcomm MSM/QSD based systems. This runs on the 711 apps processor of the MSM/QSD and depends on a shared memory 712 interface to the modem processor which runs the baseband 713 stack and controls some vital subsystems 714 (clock and power control, etc). 715 716config ARCH_SHMOBILE 717 bool "Renesas SH-Mobile / R-Mobile" 718 select HAVE_CLK 719 select CLKDEV_LOOKUP 720 select HAVE_MACH_CLKDEV 721 select HAVE_SMP 722 select GENERIC_CLOCKEVENTS 723 select MIGHT_HAVE_CACHE_L2X0 724 select NO_IOPORT 725 select SPARSE_IRQ 726 select MULTI_IRQ_HANDLER 727 select PM_GENERIC_DOMAINS if PM 728 select NEED_MACH_MEMORY_H 729 help 730 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 731 732config ARCH_RPC 733 bool "RiscPC" 734 select ARCH_ACORN 735 select FIQ 736 select TIMER_ACORN 737 select ARCH_MAY_HAVE_PC_FDC 738 select HAVE_PATA_PLATFORM 739 select ISA_DMA_API 740 select NO_IOPORT 741 select ARCH_SPARSEMEM_ENABLE 742 select ARCH_USES_GETTIMEOFFSET 743 select HAVE_IDE 744 select NEED_MACH_MEMORY_H 745 help 746 On the Acorn Risc-PC, Linux can support the internal IDE disk and 747 CD-ROM interface, serial and parallel port, and the floppy drive. 748 749config ARCH_SA1100 750 bool "SA1100-based" 751 select CLKSRC_MMIO 752 select CPU_SA1100 753 select ISA 754 select ARCH_SPARSEMEM_ENABLE 755 select ARCH_MTD_XIP 756 select ARCH_HAS_CPUFREQ 757 select CPU_FREQ 758 select GENERIC_CLOCKEVENTS 759 select CLKDEV_LOOKUP 760 select HAVE_SCHED_CLOCK 761 select TICK_ONESHOT 762 select ARCH_REQUIRE_GPIOLIB 763 select HAVE_IDE 764 select NEED_MACH_MEMORY_H 765 help 766 Support for StrongARM 11x0 based boards. 767 768config ARCH_S3C2410 769 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 770 select GENERIC_GPIO 771 select ARCH_HAS_CPUFREQ 772 select HAVE_CLK 773 select CLKDEV_LOOKUP 774 select ARCH_USES_GETTIMEOFFSET 775 select HAVE_S3C2410_I2C if I2C 776 help 777 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 778 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 779 the Samsung SMDK2410 development board (and derivatives). 780 781 Note, the S3C2416 and the S3C2450 are so close that they even share 782 the same SoC ID code. This means that there is no separate machine 783 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 784 785config ARCH_S3C64XX 786 bool "Samsung S3C64XX" 787 select PLAT_SAMSUNG 788 select CPU_V6 789 select ARM_VIC 790 select HAVE_CLK 791 select HAVE_TCM 792 select CLKDEV_LOOKUP 793 select NO_IOPORT 794 select ARCH_USES_GETTIMEOFFSET 795 select ARCH_HAS_CPUFREQ 796 select ARCH_REQUIRE_GPIOLIB 797 select SAMSUNG_CLKSRC 798 select SAMSUNG_IRQ_VIC_TIMER 799 select S3C_GPIO_TRACK 800 select S3C_DEV_NAND 801 select USB_ARCH_HAS_OHCI 802 select SAMSUNG_GPIOLIB_4BIT 803 select HAVE_S3C2410_I2C if I2C 804 select HAVE_S3C2410_WATCHDOG if WATCHDOG 805 help 806 Samsung S3C64XX series based systems 807 808config ARCH_S5P64X0 809 bool "Samsung S5P6440 S5P6450" 810 select CPU_V6 811 select GENERIC_GPIO 812 select HAVE_CLK 813 select CLKDEV_LOOKUP 814 select CLKSRC_MMIO 815 select HAVE_S3C2410_WATCHDOG if WATCHDOG 816 select GENERIC_CLOCKEVENTS 817 select HAVE_SCHED_CLOCK 818 select HAVE_S3C2410_I2C if I2C 819 select HAVE_S3C_RTC if RTC_CLASS 820 help 821 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 822 SMDK6450. 823 824config ARCH_S5PC100 825 bool "Samsung S5PC100" 826 select GENERIC_GPIO 827 select HAVE_CLK 828 select CLKDEV_LOOKUP 829 select CPU_V7 830 select ARM_L1_CACHE_SHIFT_6 831 select ARCH_USES_GETTIMEOFFSET 832 select HAVE_S3C2410_I2C if I2C 833 select HAVE_S3C_RTC if RTC_CLASS 834 select HAVE_S3C2410_WATCHDOG if WATCHDOG 835 help 836 Samsung S5PC100 series based systems 837 838config ARCH_S5PV210 839 bool "Samsung S5PV210/S5PC110" 840 select CPU_V7 841 select ARCH_SPARSEMEM_ENABLE 842 select ARCH_HAS_HOLES_MEMORYMODEL 843 select GENERIC_GPIO 844 select HAVE_CLK 845 select CLKDEV_LOOKUP 846 select CLKSRC_MMIO 847 select ARM_L1_CACHE_SHIFT_6 848 select ARCH_HAS_CPUFREQ 849 select GENERIC_CLOCKEVENTS 850 select HAVE_SCHED_CLOCK 851 select HAVE_S3C2410_I2C if I2C 852 select HAVE_S3C_RTC if RTC_CLASS 853 select HAVE_S3C2410_WATCHDOG if WATCHDOG 854 select NEED_MACH_MEMORY_H 855 help 856 Samsung S5PV210/S5PC110 series based systems 857 858config ARCH_EXYNOS 859 bool "SAMSUNG EXYNOS" 860 select CPU_V7 861 select ARCH_SPARSEMEM_ENABLE 862 select ARCH_HAS_HOLES_MEMORYMODEL 863 select GENERIC_GPIO 864 select HAVE_CLK 865 select CLKDEV_LOOKUP 866 select ARCH_HAS_CPUFREQ 867 select GENERIC_CLOCKEVENTS 868 select HAVE_S3C_RTC if RTC_CLASS 869 select HAVE_S3C2410_I2C if I2C 870 select HAVE_S3C2410_WATCHDOG if WATCHDOG 871 select NEED_MACH_MEMORY_H 872 help 873 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 874 875config ARCH_SHARK 876 bool "Shark" 877 select CPU_SA110 878 select ISA 879 select ISA_DMA 880 select ZONE_DMA 881 select PCI 882 select ARCH_USES_GETTIMEOFFSET 883 select NEED_MACH_MEMORY_H 884 help 885 Support for the StrongARM based Digital DNARD machine, also known 886 as "Shark" (<http://www.shark-linux.de/shark.html>). 887 888config ARCH_U300 889 bool "ST-Ericsson U300 Series" 890 depends on MMU 891 select CLKSRC_MMIO 892 select CPU_ARM926T 893 select HAVE_SCHED_CLOCK 894 select HAVE_TCM 895 select ARM_AMBA 896 select ARM_PATCH_PHYS_VIRT 897 select ARM_VIC 898 select GENERIC_CLOCKEVENTS 899 select CLKDEV_LOOKUP 900 select HAVE_MACH_CLKDEV 901 select GENERIC_GPIO 902 select ARCH_REQUIRE_GPIOLIB 903 help 904 Support for ST-Ericsson U300 series mobile platforms. 905 906config ARCH_U8500 907 bool "ST-Ericsson U8500 Series" 908 select CPU_V7 909 select ARM_AMBA 910 select GENERIC_CLOCKEVENTS 911 select CLKDEV_LOOKUP 912 select ARCH_REQUIRE_GPIOLIB 913 select ARCH_HAS_CPUFREQ 914 select HAVE_SMP 915 select MIGHT_HAVE_CACHE_L2X0 916 help 917 Support for ST-Ericsson's Ux500 architecture 918 919config ARCH_NOMADIK 920 bool "STMicroelectronics Nomadik" 921 select ARM_AMBA 922 select ARM_VIC 923 select CPU_ARM926T 924 select CLKDEV_LOOKUP 925 select GENERIC_CLOCKEVENTS 926 select MIGHT_HAVE_CACHE_L2X0 927 select ARCH_REQUIRE_GPIOLIB 928 help 929 Support for the Nomadik platform by ST-Ericsson 930 931config ARCH_DAVINCI 932 bool "TI DaVinci" 933 select GENERIC_CLOCKEVENTS 934 select ARCH_REQUIRE_GPIOLIB 935 select ZONE_DMA 936 select HAVE_IDE 937 select CLKDEV_LOOKUP 938 select GENERIC_ALLOCATOR 939 select GENERIC_IRQ_CHIP 940 select ARCH_HAS_HOLES_MEMORYMODEL 941 help 942 Support for TI's DaVinci platform. 943 944config ARCH_OMAP 945 bool "TI OMAP" 946 select HAVE_CLK 947 select ARCH_REQUIRE_GPIOLIB 948 select ARCH_HAS_CPUFREQ 949 select CLKSRC_MMIO 950 select GENERIC_CLOCKEVENTS 951 select HAVE_SCHED_CLOCK 952 select ARCH_HAS_HOLES_MEMORYMODEL 953 help 954 Support for TI's OMAP platform (OMAP1/2/3/4). 955 956config PLAT_SPEAR 957 bool "ST SPEAr" 958 select ARM_AMBA 959 select ARCH_REQUIRE_GPIOLIB 960 select CLKDEV_LOOKUP 961 select CLKSRC_MMIO 962 select GENERIC_CLOCKEVENTS 963 select HAVE_CLK 964 help 965 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 966 967config ARCH_VT8500 968 bool "VIA/WonderMedia 85xx" 969 select CPU_ARM926T 970 select GENERIC_GPIO 971 select ARCH_HAS_CPUFREQ 972 select GENERIC_CLOCKEVENTS 973 select ARCH_REQUIRE_GPIOLIB 974 select HAVE_PWM 975 help 976 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 977 978config ARCH_ZYNQ 979 bool "Xilinx Zynq ARM Cortex A9 Platform" 980 select CPU_V7 981 select GENERIC_CLOCKEVENTS 982 select CLKDEV_LOOKUP 983 select ARM_GIC 984 select ARM_AMBA 985 select ICST 986 select MIGHT_HAVE_CACHE_L2X0 987 select USE_OF 988 help 989 Support for Xilinx Zynq ARM Cortex A9 Platform 990endchoice 991 992# 993# This is sorted alphabetically by mach-* pathname. However, plat-* 994# Kconfigs may be included either alphabetically (according to the 995# plat- suffix) or along side the corresponding mach-* source. 996# 997source "arch/arm/mach-at91/Kconfig" 998 999source "arch/arm/mach-bcmring/Kconfig" 1000 1001source "arch/arm/mach-clps711x/Kconfig" 1002 1003source "arch/arm/mach-cns3xxx/Kconfig" 1004 1005source "arch/arm/mach-davinci/Kconfig" 1006 1007source "arch/arm/mach-dove/Kconfig" 1008 1009source "arch/arm/mach-ep93xx/Kconfig" 1010 1011source "arch/arm/mach-footbridge/Kconfig" 1012 1013source "arch/arm/mach-gemini/Kconfig" 1014 1015source "arch/arm/mach-h720x/Kconfig" 1016 1017source "arch/arm/mach-integrator/Kconfig" 1018 1019source "arch/arm/mach-iop32x/Kconfig" 1020 1021source "arch/arm/mach-iop33x/Kconfig" 1022 1023source "arch/arm/mach-iop13xx/Kconfig" 1024 1025source "arch/arm/mach-ixp4xx/Kconfig" 1026 1027source "arch/arm/mach-ixp2000/Kconfig" 1028 1029source "arch/arm/mach-ixp23xx/Kconfig" 1030 1031source "arch/arm/mach-kirkwood/Kconfig" 1032 1033source "arch/arm/mach-ks8695/Kconfig" 1034 1035source "arch/arm/mach-lpc32xx/Kconfig" 1036 1037source "arch/arm/mach-msm/Kconfig" 1038 1039source "arch/arm/mach-mv78xx0/Kconfig" 1040 1041source "arch/arm/plat-mxc/Kconfig" 1042 1043source "arch/arm/mach-mxs/Kconfig" 1044 1045source "arch/arm/mach-netx/Kconfig" 1046 1047source "arch/arm/mach-nomadik/Kconfig" 1048source "arch/arm/plat-nomadik/Kconfig" 1049 1050source "arch/arm/plat-omap/Kconfig" 1051 1052source "arch/arm/mach-omap1/Kconfig" 1053 1054source "arch/arm/mach-omap2/Kconfig" 1055 1056source "arch/arm/mach-orion5x/Kconfig" 1057 1058source "arch/arm/mach-pxa/Kconfig" 1059source "arch/arm/plat-pxa/Kconfig" 1060 1061source "arch/arm/mach-mmp/Kconfig" 1062 1063source "arch/arm/mach-realview/Kconfig" 1064 1065source "arch/arm/mach-sa1100/Kconfig" 1066 1067source "arch/arm/plat-samsung/Kconfig" 1068source "arch/arm/plat-s3c24xx/Kconfig" 1069source "arch/arm/plat-s5p/Kconfig" 1070 1071source "arch/arm/plat-spear/Kconfig" 1072 1073if ARCH_S3C2410 1074source "arch/arm/mach-s3c2410/Kconfig" 1075source "arch/arm/mach-s3c2412/Kconfig" 1076source "arch/arm/mach-s3c2416/Kconfig" 1077source "arch/arm/mach-s3c2440/Kconfig" 1078source "arch/arm/mach-s3c2443/Kconfig" 1079endif 1080 1081if ARCH_S3C64XX 1082source "arch/arm/mach-s3c64xx/Kconfig" 1083endif 1084 1085source "arch/arm/mach-s5p64x0/Kconfig" 1086 1087source "arch/arm/mach-s5pc100/Kconfig" 1088 1089source "arch/arm/mach-s5pv210/Kconfig" 1090 1091source "arch/arm/mach-exynos/Kconfig" 1092 1093source "arch/arm/mach-shmobile/Kconfig" 1094 1095source "arch/arm/mach-tegra/Kconfig" 1096 1097source "arch/arm/mach-u300/Kconfig" 1098 1099source "arch/arm/mach-ux500/Kconfig" 1100 1101source "arch/arm/mach-versatile/Kconfig" 1102 1103source "arch/arm/mach-vexpress/Kconfig" 1104source "arch/arm/plat-versatile/Kconfig" 1105 1106source "arch/arm/mach-vt8500/Kconfig" 1107 1108source "arch/arm/mach-w90x900/Kconfig" 1109 1110# Definitions to make life easier 1111config ARCH_ACORN 1112 bool 1113 1114config PLAT_IOP 1115 bool 1116 select GENERIC_CLOCKEVENTS 1117 select HAVE_SCHED_CLOCK 1118 1119config PLAT_ORION 1120 bool 1121 select CLKSRC_MMIO 1122 select GENERIC_IRQ_CHIP 1123 select HAVE_SCHED_CLOCK 1124 1125config PLAT_PXA 1126 bool 1127 1128config PLAT_VERSATILE 1129 bool 1130 1131config ARM_TIMER_SP804 1132 bool 1133 select CLKSRC_MMIO 1134 1135source arch/arm/mm/Kconfig 1136 1137config ARM_NR_BANKS 1138 int 1139 default 16 if ARCH_EP93XX 1140 default 8 1141 1142config IWMMXT 1143 bool "Enable iWMMXt support" 1144 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1145 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1146 help 1147 Enable support for iWMMXt context switching at run time if 1148 running on a CPU that supports it. 1149 1150config XSCALE_PMU 1151 bool 1152 depends on CPU_XSCALE 1153 default y 1154 1155config CPU_HAS_PMU 1156 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1157 (!ARCH_OMAP3 || OMAP3_EMU) 1158 default y 1159 bool 1160 1161config MULTI_IRQ_HANDLER 1162 bool 1163 help 1164 Allow each machine to specify it's own IRQ handler at run time. 1165 1166if !MMU 1167source "arch/arm/Kconfig-nommu" 1168endif 1169 1170config ARM_ERRATA_411920 1171 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1172 depends on CPU_V6 || CPU_V6K 1173 help 1174 Invalidation of the Instruction Cache operation can 1175 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1176 It does not affect the MPCore. This option enables the ARM Ltd. 1177 recommended workaround. 1178 1179config ARM_ERRATA_430973 1180 bool "ARM errata: Stale prediction on replaced interworking branch" 1181 depends on CPU_V7 1182 help 1183 This option enables the workaround for the 430973 Cortex-A8 1184 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1185 interworking branch is replaced with another code sequence at the 1186 same virtual address, whether due to self-modifying code or virtual 1187 to physical address re-mapping, Cortex-A8 does not recover from the 1188 stale interworking branch prediction. This results in Cortex-A8 1189 executing the new code sequence in the incorrect ARM or Thumb state. 1190 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1191 and also flushes the branch target cache at every context switch. 1192 Note that setting specific bits in the ACTLR register may not be 1193 available in non-secure mode. 1194 1195config ARM_ERRATA_458693 1196 bool "ARM errata: Processor deadlock when a false hazard is created" 1197 depends on CPU_V7 1198 help 1199 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1200 erratum. For very specific sequences of memory operations, it is 1201 possible for a hazard condition intended for a cache line to instead 1202 be incorrectly associated with a different cache line. This false 1203 hazard might then cause a processor deadlock. The workaround enables 1204 the L1 caching of the NEON accesses and disables the PLD instruction 1205 in the ACTLR register. Note that setting specific bits in the ACTLR 1206 register may not be available in non-secure mode. 1207 1208config ARM_ERRATA_460075 1209 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1210 depends on CPU_V7 1211 help 1212 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1213 erratum. Any asynchronous access to the L2 cache may encounter a 1214 situation in which recent store transactions to the L2 cache are lost 1215 and overwritten with stale memory contents from external memory. The 1216 workaround disables the write-allocate mode for the L2 cache via the 1217 ACTLR register. Note that setting specific bits in the ACTLR register 1218 may not be available in non-secure mode. 1219 1220config ARM_ERRATA_742230 1221 bool "ARM errata: DMB operation may be faulty" 1222 depends on CPU_V7 && SMP 1223 help 1224 This option enables the workaround for the 742230 Cortex-A9 1225 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1226 between two write operations may not ensure the correct visibility 1227 ordering of the two writes. This workaround sets a specific bit in 1228 the diagnostic register of the Cortex-A9 which causes the DMB 1229 instruction to behave as a DSB, ensuring the correct behaviour of 1230 the two writes. 1231 1232config ARM_ERRATA_742231 1233 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1234 depends on CPU_V7 && SMP 1235 help 1236 This option enables the workaround for the 742231 Cortex-A9 1237 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1238 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1239 accessing some data located in the same cache line, may get corrupted 1240 data due to bad handling of the address hazard when the line gets 1241 replaced from one of the CPUs at the same time as another CPU is 1242 accessing it. This workaround sets specific bits in the diagnostic 1243 register of the Cortex-A9 which reduces the linefill issuing 1244 capabilities of the processor. 1245 1246config PL310_ERRATA_588369 1247 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1248 depends on CACHE_L2X0 1249 help 1250 The PL310 L2 cache controller implements three types of Clean & 1251 Invalidate maintenance operations: by Physical Address 1252 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1253 They are architecturally defined to behave as the execution of a 1254 clean operation followed immediately by an invalidate operation, 1255 both performing to the same memory location. This functionality 1256 is not correctly implemented in PL310 as clean lines are not 1257 invalidated as a result of these operations. 1258 1259config ARM_ERRATA_720789 1260 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1261 depends on CPU_V7 1262 help 1263 This option enables the workaround for the 720789 Cortex-A9 (prior to 1264 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1265 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1266 As a consequence of this erratum, some TLB entries which should be 1267 invalidated are not, resulting in an incoherency in the system page 1268 tables. The workaround changes the TLB flushing routines to invalidate 1269 entries regardless of the ASID. 1270 1271config PL310_ERRATA_727915 1272 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1273 depends on CACHE_L2X0 1274 help 1275 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1276 operation (offset 0x7FC). This operation runs in background so that 1277 PL310 can handle normal accesses while it is in progress. Under very 1278 rare circumstances, due to this erratum, write data can be lost when 1279 PL310 treats a cacheable write transaction during a Clean & 1280 Invalidate by Way operation. 1281 1282config ARM_ERRATA_743622 1283 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1284 depends on CPU_V7 1285 help 1286 This option enables the workaround for the 743622 Cortex-A9 1287 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1288 optimisation in the Cortex-A9 Store Buffer may lead to data 1289 corruption. This workaround sets a specific bit in the diagnostic 1290 register of the Cortex-A9 which disables the Store Buffer 1291 optimisation, preventing the defect from occurring. This has no 1292 visible impact on the overall performance or power consumption of the 1293 processor. 1294 1295config ARM_ERRATA_751472 1296 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1297 depends on CPU_V7 1298 help 1299 This option enables the workaround for the 751472 Cortex-A9 (prior 1300 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1301 completion of a following broadcasted operation if the second 1302 operation is received by a CPU before the ICIALLUIS has completed, 1303 potentially leading to corrupted entries in the cache or TLB. 1304 1305config PL310_ERRATA_753970 1306 bool "PL310 errata: cache sync operation may be faulty" 1307 depends on CACHE_PL310 1308 help 1309 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1310 1311 Under some condition the effect of cache sync operation on 1312 the store buffer still remains when the operation completes. 1313 This means that the store buffer is always asked to drain and 1314 this prevents it from merging any further writes. The workaround 1315 is to replace the normal offset of cache sync operation (0x730) 1316 by another offset targeting an unmapped PL310 register 0x740. 1317 This has the same effect as the cache sync operation: store buffer 1318 drain and waiting for all buffers empty. 1319 1320config ARM_ERRATA_754322 1321 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1322 depends on CPU_V7 1323 help 1324 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1325 r3p*) erratum. A speculative memory access may cause a page table walk 1326 which starts prior to an ASID switch but completes afterwards. This 1327 can populate the micro-TLB with a stale entry which may be hit with 1328 the new ASID. This workaround places two dsb instructions in the mm 1329 switching code so that no page table walks can cross the ASID switch. 1330 1331config ARM_ERRATA_754327 1332 bool "ARM errata: no automatic Store Buffer drain" 1333 depends on CPU_V7 && SMP 1334 help 1335 This option enables the workaround for the 754327 Cortex-A9 (prior to 1336 r2p0) erratum. The Store Buffer does not have any automatic draining 1337 mechanism and therefore a livelock may occur if an external agent 1338 continuously polls a memory location waiting to observe an update. 1339 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1340 written polling loops from denying visibility of updates to memory. 1341 1342config ARM_ERRATA_364296 1343 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1344 depends on CPU_V6 && !SMP 1345 help 1346 This options enables the workaround for the 364296 ARM1136 1347 r0p2 erratum (possible cache data corruption with 1348 hit-under-miss enabled). It sets the undocumented bit 31 in 1349 the auxiliary control register and the FI bit in the control 1350 register, thus disabling hit-under-miss without putting the 1351 processor into full low interrupt latency mode. ARM11MPCore 1352 is not affected. 1353 1354config ARM_ERRATA_764369 1355 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1356 depends on CPU_V7 && SMP 1357 help 1358 This option enables the workaround for erratum 764369 1359 affecting Cortex-A9 MPCore with two or more processors (all 1360 current revisions). Under certain timing circumstances, a data 1361 cache line maintenance operation by MVA targeting an Inner 1362 Shareable memory region may fail to proceed up to either the 1363 Point of Coherency or to the Point of Unification of the 1364 system. This workaround adds a DSB instruction before the 1365 relevant cache maintenance functions and sets a specific bit 1366 in the diagnostic control register of the SCU. 1367 1368config PL310_ERRATA_769419 1369 bool "PL310 errata: no automatic Store Buffer drain" 1370 depends on CACHE_L2X0 1371 help 1372 On revisions of the PL310 prior to r3p2, the Store Buffer does 1373 not automatically drain. This can cause normal, non-cacheable 1374 writes to be retained when the memory system is idle, leading 1375 to suboptimal I/O performance for drivers using coherent DMA. 1376 This option adds a write barrier to the cpu_idle loop so that, 1377 on systems with an outer cache, the store buffer is drained 1378 explicitly. 1379 1380endmenu 1381 1382source "arch/arm/common/Kconfig" 1383 1384menu "Bus support" 1385 1386config ARM_AMBA 1387 bool 1388 1389config ISA 1390 bool 1391 help 1392 Find out whether you have ISA slots on your motherboard. ISA is the 1393 name of a bus system, i.e. the way the CPU talks to the other stuff 1394 inside your box. Other bus systems are PCI, EISA, MicroChannel 1395 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1396 newer boards don't support it. If you have ISA, say Y, otherwise N. 1397 1398# Select ISA DMA controller support 1399config ISA_DMA 1400 bool 1401 select ISA_DMA_API 1402 1403# Select ISA DMA interface 1404config ISA_DMA_API 1405 bool 1406 1407config PCI 1408 bool "PCI support" if MIGHT_HAVE_PCI 1409 help 1410 Find out whether you have a PCI motherboard. PCI is the name of a 1411 bus system, i.e. the way the CPU talks to the other stuff inside 1412 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1413 VESA. If you have PCI, say Y, otherwise N. 1414 1415config PCI_DOMAINS 1416 bool 1417 depends on PCI 1418 1419config PCI_NANOENGINE 1420 bool "BSE nanoEngine PCI support" 1421 depends on SA1100_NANOENGINE 1422 help 1423 Enable PCI on the BSE nanoEngine board. 1424 1425config PCI_SYSCALL 1426 def_bool PCI 1427 1428# Select the host bridge type 1429config PCI_HOST_VIA82C505 1430 bool 1431 depends on PCI && ARCH_SHARK 1432 default y 1433 1434config PCI_HOST_ITE8152 1435 bool 1436 depends on PCI && MACH_ARMCORE 1437 default y 1438 select DMABOUNCE 1439 1440source "drivers/pci/Kconfig" 1441 1442source "drivers/pcmcia/Kconfig" 1443 1444endmenu 1445 1446menu "Kernel Features" 1447 1448source "kernel/time/Kconfig" 1449 1450config HAVE_SMP 1451 bool 1452 help 1453 This option should be selected by machines which have an SMP- 1454 capable CPU. 1455 1456 The only effect of this option is to make the SMP-related 1457 options available to the user for configuration. 1458 1459config SMP 1460 bool "Symmetric Multi-Processing" 1461 depends on CPU_V6K || CPU_V7 1462 depends on GENERIC_CLOCKEVENTS 1463 depends on HAVE_SMP 1464 depends on MMU 1465 select USE_GENERIC_SMP_HELPERS 1466 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1467 help 1468 This enables support for systems with more than one CPU. If you have 1469 a system with only one CPU, like most personal computers, say N. If 1470 you have a system with more than one CPU, say Y. 1471 1472 If you say N here, the kernel will run on single and multiprocessor 1473 machines, but will use only one CPU of a multiprocessor machine. If 1474 you say Y here, the kernel will run on many, but not all, single 1475 processor machines. On a single processor machine, the kernel will 1476 run faster if you say N here. 1477 1478 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1479 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1480 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1481 1482 If you don't know what to do here, say N. 1483 1484config SMP_ON_UP 1485 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1486 depends on EXPERIMENTAL 1487 depends on SMP && !XIP_KERNEL 1488 default y 1489 help 1490 SMP kernels contain instructions which fail on non-SMP processors. 1491 Enabling this option allows the kernel to modify itself to make 1492 these instructions safe. Disabling it allows about 1K of space 1493 savings. 1494 1495 If you don't know what to do here, say Y. 1496 1497config ARM_CPU_TOPOLOGY 1498 bool "Support cpu topology definition" 1499 depends on SMP && CPU_V7 1500 default y 1501 help 1502 Support ARM cpu topology definition. The MPIDR register defines 1503 affinity between processors which is then used to describe the cpu 1504 topology of an ARM System. 1505 1506config SCHED_MC 1507 bool "Multi-core scheduler support" 1508 depends on ARM_CPU_TOPOLOGY 1509 help 1510 Multi-core scheduler support improves the CPU scheduler's decision 1511 making when dealing with multi-core CPU chips at a cost of slightly 1512 increased overhead in some places. If unsure say N here. 1513 1514config SCHED_SMT 1515 bool "SMT scheduler support" 1516 depends on ARM_CPU_TOPOLOGY 1517 help 1518 Improves the CPU scheduler's decision making when dealing with 1519 MultiThreading at a cost of slightly increased overhead in some 1520 places. If unsure say N here. 1521 1522config HAVE_ARM_SCU 1523 bool 1524 help 1525 This option enables support for the ARM system coherency unit 1526 1527config HAVE_ARM_TWD 1528 bool 1529 depends on SMP 1530 select TICK_ONESHOT 1531 help 1532 This options enables support for the ARM timer and watchdog unit 1533 1534choice 1535 prompt "Memory split" 1536 default VMSPLIT_3G 1537 help 1538 Select the desired split between kernel and user memory. 1539 1540 If you are not absolutely sure what you are doing, leave this 1541 option alone! 1542 1543 config VMSPLIT_3G 1544 bool "3G/1G user/kernel split" 1545 config VMSPLIT_2G 1546 bool "2G/2G user/kernel split" 1547 config VMSPLIT_1G 1548 bool "1G/3G user/kernel split" 1549endchoice 1550 1551config PAGE_OFFSET 1552 hex 1553 default 0x40000000 if VMSPLIT_1G 1554 default 0x80000000 if VMSPLIT_2G 1555 default 0xC0000000 1556 1557config NR_CPUS 1558 int "Maximum number of CPUs (2-32)" 1559 range 2 32 1560 depends on SMP 1561 default "4" 1562 1563config HOTPLUG_CPU 1564 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1565 depends on SMP && HOTPLUG && EXPERIMENTAL 1566 help 1567 Say Y here to experiment with turning CPUs off and on. CPUs 1568 can be controlled through /sys/devices/system/cpu. 1569 1570config LOCAL_TIMERS 1571 bool "Use local timer interrupts" 1572 depends on SMP 1573 default y 1574 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1575 help 1576 Enable support for local timers on SMP platforms, rather then the 1577 legacy IPI broadcast method. Local timers allows the system 1578 accounting to be spread across the timer interval, preventing a 1579 "thundering herd" at every timer tick. 1580 1581config ARCH_NR_GPIO 1582 int 1583 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1584 default 350 if ARCH_U8500 1585 default 0 1586 help 1587 Maximum number of GPIOs in the system. 1588 1589 If unsure, leave the default value. 1590 1591source kernel/Kconfig.preempt 1592 1593config HZ 1594 int 1595 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1596 ARCH_S5PV210 || ARCH_EXYNOS4 1597 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1598 default AT91_TIMER_HZ if ARCH_AT91 1599 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1600 default 100 1601 1602config THUMB2_KERNEL 1603 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1604 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1605 select AEABI 1606 select ARM_ASM_UNIFIED 1607 select ARM_UNWIND 1608 help 1609 By enabling this option, the kernel will be compiled in 1610 Thumb-2 mode. A compiler/assembler that understand the unified 1611 ARM-Thumb syntax is needed. 1612 1613 If unsure, say N. 1614 1615config THUMB2_AVOID_R_ARM_THM_JUMP11 1616 bool "Work around buggy Thumb-2 short branch relocations in gas" 1617 depends on THUMB2_KERNEL && MODULES 1618 default y 1619 help 1620 Various binutils versions can resolve Thumb-2 branches to 1621 locally-defined, preemptible global symbols as short-range "b.n" 1622 branch instructions. 1623 1624 This is a problem, because there's no guarantee the final 1625 destination of the symbol, or any candidate locations for a 1626 trampoline, are within range of the branch. For this reason, the 1627 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1628 relocation in modules at all, and it makes little sense to add 1629 support. 1630 1631 The symptom is that the kernel fails with an "unsupported 1632 relocation" error when loading some modules. 1633 1634 Until fixed tools are available, passing 1635 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1636 code which hits this problem, at the cost of a bit of extra runtime 1637 stack usage in some cases. 1638 1639 The problem is described in more detail at: 1640 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1641 1642 Only Thumb-2 kernels are affected. 1643 1644 Unless you are sure your tools don't have this problem, say Y. 1645 1646config ARM_ASM_UNIFIED 1647 bool 1648 1649config AEABI 1650 bool "Use the ARM EABI to compile the kernel" 1651 help 1652 This option allows for the kernel to be compiled using the latest 1653 ARM ABI (aka EABI). This is only useful if you are using a user 1654 space environment that is also compiled with EABI. 1655 1656 Since there are major incompatibilities between the legacy ABI and 1657 EABI, especially with regard to structure member alignment, this 1658 option also changes the kernel syscall calling convention to 1659 disambiguate both ABIs and allow for backward compatibility support 1660 (selected with CONFIG_OABI_COMPAT). 1661 1662 To use this you need GCC version 4.0.0 or later. 1663 1664config OABI_COMPAT 1665 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1666 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1667 default y 1668 help 1669 This option preserves the old syscall interface along with the 1670 new (ARM EABI) one. It also provides a compatibility layer to 1671 intercept syscalls that have structure arguments which layout 1672 in memory differs between the legacy ABI and the new ARM EABI 1673 (only for non "thumb" binaries). This option adds a tiny 1674 overhead to all syscalls and produces a slightly larger kernel. 1675 If you know you'll be using only pure EABI user space then you 1676 can say N here. If this option is not selected and you attempt 1677 to execute a legacy ABI binary then the result will be 1678 UNPREDICTABLE (in fact it can be predicted that it won't work 1679 at all). If in doubt say Y. 1680 1681config ARCH_HAS_HOLES_MEMORYMODEL 1682 bool 1683 1684config ARCH_SPARSEMEM_ENABLE 1685 bool 1686 1687config ARCH_SPARSEMEM_DEFAULT 1688 def_bool ARCH_SPARSEMEM_ENABLE 1689 1690config ARCH_SELECT_MEMORY_MODEL 1691 def_bool ARCH_SPARSEMEM_ENABLE 1692 1693config HAVE_ARCH_PFN_VALID 1694 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1695 1696config HIGHMEM 1697 bool "High Memory Support" 1698 depends on MMU 1699 help 1700 The address space of ARM processors is only 4 Gigabytes large 1701 and it has to accommodate user address space, kernel address 1702 space as well as some memory mapped IO. That means that, if you 1703 have a large amount of physical memory and/or IO, not all of the 1704 memory can be "permanently mapped" by the kernel. The physical 1705 memory that is not permanently mapped is called "high memory". 1706 1707 Depending on the selected kernel/user memory split, minimum 1708 vmalloc space and actual amount of RAM, you may not need this 1709 option which should result in a slightly faster kernel. 1710 1711 If unsure, say n. 1712 1713config HIGHPTE 1714 bool "Allocate 2nd-level pagetables from highmem" 1715 depends on HIGHMEM 1716 1717config HW_PERF_EVENTS 1718 bool "Enable hardware performance counter support for perf events" 1719 depends on PERF_EVENTS && CPU_HAS_PMU 1720 default y 1721 help 1722 Enable hardware performance counter support for perf events. If 1723 disabled, perf events will use software events only. 1724 1725source "mm/Kconfig" 1726 1727config FORCE_MAX_ZONEORDER 1728 int "Maximum zone order" if ARCH_SHMOBILE 1729 range 11 64 if ARCH_SHMOBILE 1730 default "9" if SA1111 1731 default "11" 1732 help 1733 The kernel memory allocator divides physically contiguous memory 1734 blocks into "zones", where each zone is a power of two number of 1735 pages. This option selects the largest power of two that the kernel 1736 keeps in the memory allocator. If you need to allocate very large 1737 blocks of physically contiguous memory, then you may need to 1738 increase this value. 1739 1740 This config option is actually maximum order plus one. For example, 1741 a value of 11 means that the largest free memory block is 2^10 pages. 1742 1743config LEDS 1744 bool "Timer and CPU usage LEDs" 1745 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1746 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1747 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1748 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1749 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1750 ARCH_AT91 || ARCH_DAVINCI || \ 1751 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1752 help 1753 If you say Y here, the LEDs on your machine will be used 1754 to provide useful information about your current system status. 1755 1756 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1757 be able to select which LEDs are active using the options below. If 1758 you are compiling a kernel for the EBSA-110 or the LART however, the 1759 red LED will simply flash regularly to indicate that the system is 1760 still functional. It is safe to say Y here if you have a CATS 1761 system, but the driver will do nothing. 1762 1763config LEDS_TIMER 1764 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1765 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1766 || MACH_OMAP_PERSEUS2 1767 depends on LEDS 1768 depends on !GENERIC_CLOCKEVENTS 1769 default y if ARCH_EBSA110 1770 help 1771 If you say Y here, one of the system LEDs (the green one on the 1772 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1773 will flash regularly to indicate that the system is still 1774 operational. This is mainly useful to kernel hackers who are 1775 debugging unstable kernels. 1776 1777 The LART uses the same LED for both Timer LED and CPU usage LED 1778 functions. You may choose to use both, but the Timer LED function 1779 will overrule the CPU usage LED. 1780 1781config LEDS_CPU 1782 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1783 !ARCH_OMAP) \ 1784 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1785 || MACH_OMAP_PERSEUS2 1786 depends on LEDS 1787 help 1788 If you say Y here, the red LED will be used to give a good real 1789 time indication of CPU usage, by lighting whenever the idle task 1790 is not currently executing. 1791 1792 The LART uses the same LED for both Timer LED and CPU usage LED 1793 functions. You may choose to use both, but the Timer LED function 1794 will overrule the CPU usage LED. 1795 1796config ALIGNMENT_TRAP 1797 bool 1798 depends on CPU_CP15_MMU 1799 default y if !ARCH_EBSA110 1800 select HAVE_PROC_CPU if PROC_FS 1801 help 1802 ARM processors cannot fetch/store information which is not 1803 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1804 address divisible by 4. On 32-bit ARM processors, these non-aligned 1805 fetch/store instructions will be emulated in software if you say 1806 here, which has a severe performance impact. This is necessary for 1807 correct operation of some network protocols. With an IP-only 1808 configuration it is safe to say N, otherwise say Y. 1809 1810config UACCESS_WITH_MEMCPY 1811 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1812 depends on MMU && EXPERIMENTAL 1813 default y if CPU_FEROCEON 1814 help 1815 Implement faster copy_to_user and clear_user methods for CPU 1816 cores where a 8-word STM instruction give significantly higher 1817 memory write throughput than a sequence of individual 32bit stores. 1818 1819 A possible side effect is a slight increase in scheduling latency 1820 between threads sharing the same address space if they invoke 1821 such copy operations with large buffers. 1822 1823 However, if the CPU data cache is using a write-allocate mode, 1824 this option is unlikely to provide any performance gain. 1825 1826config SECCOMP 1827 bool 1828 prompt "Enable seccomp to safely compute untrusted bytecode" 1829 ---help--- 1830 This kernel feature is useful for number crunching applications 1831 that may need to compute untrusted bytecode during their 1832 execution. By using pipes or other transports made available to 1833 the process as file descriptors supporting the read/write 1834 syscalls, it's possible to isolate those applications in 1835 their own address space using seccomp. Once seccomp is 1836 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1837 and the task is only allowed to execute a few safe syscalls 1838 defined by each seccomp mode. 1839 1840config CC_STACKPROTECTOR 1841 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1842 depends on EXPERIMENTAL 1843 help 1844 This option turns on the -fstack-protector GCC feature. This 1845 feature puts, at the beginning of functions, a canary value on 1846 the stack just before the return address, and validates 1847 the value just before actually returning. Stack based buffer 1848 overflows (that need to overwrite this return address) now also 1849 overwrite the canary, which gets detected and the attack is then 1850 neutralized via a kernel panic. 1851 This feature requires gcc version 4.2 or above. 1852 1853config DEPRECATED_PARAM_STRUCT 1854 bool "Provide old way to pass kernel parameters" 1855 help 1856 This was deprecated in 2001 and announced to live on for 5 years. 1857 Some old boot loaders still use this way. 1858 1859endmenu 1860 1861menu "Boot options" 1862 1863config USE_OF 1864 bool "Flattened Device Tree support" 1865 select OF 1866 select OF_EARLY_FLATTREE 1867 select IRQ_DOMAIN 1868 help 1869 Include support for flattened device tree machine descriptions. 1870 1871# Compressed boot loader in ROM. Yes, we really want to ask about 1872# TEXT and BSS so we preserve their values in the config files. 1873config ZBOOT_ROM_TEXT 1874 hex "Compressed ROM boot loader base address" 1875 default "0" 1876 help 1877 The physical address at which the ROM-able zImage is to be 1878 placed in the target. Platforms which normally make use of 1879 ROM-able zImage formats normally set this to a suitable 1880 value in their defconfig file. 1881 1882 If ZBOOT_ROM is not enabled, this has no effect. 1883 1884config ZBOOT_ROM_BSS 1885 hex "Compressed ROM boot loader BSS address" 1886 default "0" 1887 help 1888 The base address of an area of read/write memory in the target 1889 for the ROM-able zImage which must be available while the 1890 decompressor is running. It must be large enough to hold the 1891 entire decompressed kernel plus an additional 128 KiB. 1892 Platforms which normally make use of ROM-able zImage formats 1893 normally set this to a suitable value in their defconfig file. 1894 1895 If ZBOOT_ROM is not enabled, this has no effect. 1896 1897config ZBOOT_ROM 1898 bool "Compressed boot loader in ROM/flash" 1899 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1900 help 1901 Say Y here if you intend to execute your compressed kernel image 1902 (zImage) directly from ROM or flash. If unsure, say N. 1903 1904choice 1905 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1906 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1907 default ZBOOT_ROM_NONE 1908 help 1909 Include experimental SD/MMC loading code in the ROM-able zImage. 1910 With this enabled it is possible to write the the ROM-able zImage 1911 kernel image to an MMC or SD card and boot the kernel straight 1912 from the reset vector. At reset the processor Mask ROM will load 1913 the first part of the the ROM-able zImage which in turn loads the 1914 rest the kernel image to RAM. 1915 1916config ZBOOT_ROM_NONE 1917 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1918 help 1919 Do not load image from SD or MMC 1920 1921config ZBOOT_ROM_MMCIF 1922 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1923 help 1924 Load image from MMCIF hardware block. 1925 1926config ZBOOT_ROM_SH_MOBILE_SDHI 1927 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1928 help 1929 Load image from SDHI hardware block 1930 1931endchoice 1932 1933config ARM_APPENDED_DTB 1934 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1935 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1936 help 1937 With this option, the boot code will look for a device tree binary 1938 (DTB) appended to zImage 1939 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1940 1941 This is meant as a backward compatibility convenience for those 1942 systems with a bootloader that can't be upgraded to accommodate 1943 the documented boot protocol using a device tree. 1944 1945 Beware that there is very little in terms of protection against 1946 this option being confused by leftover garbage in memory that might 1947 look like a DTB header after a reboot if no actual DTB is appended 1948 to zImage. Do not leave this option active in a production kernel 1949 if you don't intend to always append a DTB. Proper passing of the 1950 location into r2 of a bootloader provided DTB is always preferable 1951 to this option. 1952 1953config ARM_ATAG_DTB_COMPAT 1954 bool "Supplement the appended DTB with traditional ATAG information" 1955 depends on ARM_APPENDED_DTB 1956 help 1957 Some old bootloaders can't be updated to a DTB capable one, yet 1958 they provide ATAGs with memory configuration, the ramdisk address, 1959 the kernel cmdline string, etc. Such information is dynamically 1960 provided by the bootloader and can't always be stored in a static 1961 DTB. To allow a device tree enabled kernel to be used with such 1962 bootloaders, this option allows zImage to extract the information 1963 from the ATAG list and store it at run time into the appended DTB. 1964 1965config CMDLINE 1966 string "Default kernel command string" 1967 default "" 1968 help 1969 On some architectures (EBSA110 and CATS), there is currently no way 1970 for the boot loader to pass arguments to the kernel. For these 1971 architectures, you should supply some command-line options at build 1972 time by entering them here. As a minimum, you should specify the 1973 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1974 1975choice 1976 prompt "Kernel command line type" if CMDLINE != "" 1977 default CMDLINE_FROM_BOOTLOADER 1978 1979config CMDLINE_FROM_BOOTLOADER 1980 bool "Use bootloader kernel arguments if available" 1981 help 1982 Uses the command-line options passed by the boot loader. If 1983 the boot loader doesn't provide any, the default kernel command 1984 string provided in CMDLINE will be used. 1985 1986config CMDLINE_EXTEND 1987 bool "Extend bootloader kernel arguments" 1988 help 1989 The command-line arguments provided by the boot loader will be 1990 appended to the default kernel command string. 1991 1992config CMDLINE_FORCE 1993 bool "Always use the default kernel command string" 1994 help 1995 Always use the default kernel command string, even if the boot 1996 loader passes other arguments to the kernel. 1997 This is useful if you cannot or don't want to change the 1998 command-line options your boot loader passes to the kernel. 1999endchoice 2000 2001config XIP_KERNEL 2002 bool "Kernel Execute-In-Place from ROM" 2003 depends on !ZBOOT_ROM && !ARM_LPAE 2004 help 2005 Execute-In-Place allows the kernel to run from non-volatile storage 2006 directly addressable by the CPU, such as NOR flash. This saves RAM 2007 space since the text section of the kernel is not loaded from flash 2008 to RAM. Read-write sections, such as the data section and stack, 2009 are still copied to RAM. The XIP kernel is not compressed since 2010 it has to run directly from flash, so it will take more space to 2011 store it. The flash address used to link the kernel object files, 2012 and for storing it, is configuration dependent. Therefore, if you 2013 say Y here, you must know the proper physical address where to 2014 store the kernel image depending on your own flash memory usage. 2015 2016 Also note that the make target becomes "make xipImage" rather than 2017 "make zImage" or "make Image". The final kernel binary to put in 2018 ROM memory will be arch/arm/boot/xipImage. 2019 2020 If unsure, say N. 2021 2022config XIP_PHYS_ADDR 2023 hex "XIP Kernel Physical Location" 2024 depends on XIP_KERNEL 2025 default "0x00080000" 2026 help 2027 This is the physical address in your flash memory the kernel will 2028 be linked for and stored to. This address is dependent on your 2029 own flash usage. 2030 2031config KEXEC 2032 bool "Kexec system call (EXPERIMENTAL)" 2033 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2034 help 2035 kexec is a system call that implements the ability to shutdown your 2036 current kernel, and to start another kernel. It is like a reboot 2037 but it is independent of the system firmware. And like a reboot 2038 you can start any kernel with it, not just Linux. 2039 2040 It is an ongoing process to be certain the hardware in a machine 2041 is properly shutdown, so do not be surprised if this code does not 2042 initially work for you. It may help to enable device hotplugging 2043 support. 2044 2045config ATAGS_PROC 2046 bool "Export atags in procfs" 2047 depends on KEXEC 2048 default y 2049 help 2050 Should the atags used to boot the kernel be exported in an "atags" 2051 file in procfs. Useful with kexec. 2052 2053config CRASH_DUMP 2054 bool "Build kdump crash kernel (EXPERIMENTAL)" 2055 depends on EXPERIMENTAL 2056 help 2057 Generate crash dump after being started by kexec. This should 2058 be normally only set in special crash dump kernels which are 2059 loaded in the main kernel with kexec-tools into a specially 2060 reserved region and then later executed after a crash by 2061 kdump/kexec. The crash dump kernel must be compiled to a 2062 memory address not used by the main kernel 2063 2064 For more details see Documentation/kdump/kdump.txt 2065 2066config AUTO_ZRELADDR 2067 bool "Auto calculation of the decompressed kernel image address" 2068 depends on !ZBOOT_ROM && !ARCH_U300 2069 help 2070 ZRELADDR is the physical address where the decompressed kernel 2071 image will be placed. If AUTO_ZRELADDR is selected, the address 2072 will be determined at run-time by masking the current IP with 2073 0xf8000000. This assumes the zImage being placed in the first 128MB 2074 from start of memory. 2075 2076endmenu 2077 2078menu "CPU Power Management" 2079 2080if ARCH_HAS_CPUFREQ 2081 2082source "drivers/cpufreq/Kconfig" 2083 2084config CPU_FREQ_IMX 2085 tristate "CPUfreq driver for i.MX CPUs" 2086 depends on ARCH_MXC && CPU_FREQ 2087 help 2088 This enables the CPUfreq driver for i.MX CPUs. 2089 2090config CPU_FREQ_SA1100 2091 bool 2092 2093config CPU_FREQ_SA1110 2094 bool 2095 2096config CPU_FREQ_INTEGRATOR 2097 tristate "CPUfreq driver for ARM Integrator CPUs" 2098 depends on ARCH_INTEGRATOR && CPU_FREQ 2099 default y 2100 help 2101 This enables the CPUfreq driver for ARM Integrator CPUs. 2102 2103 For details, take a look at <file:Documentation/cpu-freq>. 2104 2105 If in doubt, say Y. 2106 2107config CPU_FREQ_PXA 2108 bool 2109 depends on CPU_FREQ && ARCH_PXA && PXA25x 2110 default y 2111 select CPU_FREQ_TABLE 2112 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2113 2114config CPU_FREQ_S3C 2115 bool 2116 help 2117 Internal configuration node for common cpufreq on Samsung SoC 2118 2119config CPU_FREQ_S3C24XX 2120 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2121 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 2122 select CPU_FREQ_S3C 2123 help 2124 This enables the CPUfreq driver for the Samsung S3C24XX family 2125 of CPUs. 2126 2127 For details, take a look at <file:Documentation/cpu-freq>. 2128 2129 If in doubt, say N. 2130 2131config CPU_FREQ_S3C24XX_PLL 2132 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2133 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2134 help 2135 Compile in support for changing the PLL frequency from the 2136 S3C24XX series CPUfreq driver. The PLL takes time to settle 2137 after a frequency change, so by default it is not enabled. 2138 2139 This also means that the PLL tables for the selected CPU(s) will 2140 be built which may increase the size of the kernel image. 2141 2142config CPU_FREQ_S3C24XX_DEBUG 2143 bool "Debug CPUfreq Samsung driver core" 2144 depends on CPU_FREQ_S3C24XX 2145 help 2146 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2147 2148config CPU_FREQ_S3C24XX_IODEBUG 2149 bool "Debug CPUfreq Samsung driver IO timing" 2150 depends on CPU_FREQ_S3C24XX 2151 help 2152 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2153 2154config CPU_FREQ_S3C24XX_DEBUGFS 2155 bool "Export debugfs for CPUFreq" 2156 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2157 help 2158 Export status information via debugfs. 2159 2160endif 2161 2162source "drivers/cpuidle/Kconfig" 2163 2164endmenu 2165 2166menu "Floating point emulation" 2167 2168comment "At least one emulation must be selected" 2169 2170config FPE_NWFPE 2171 bool "NWFPE math emulation" 2172 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2173 ---help--- 2174 Say Y to include the NWFPE floating point emulator in the kernel. 2175 This is necessary to run most binaries. Linux does not currently 2176 support floating point hardware so you need to say Y here even if 2177 your machine has an FPA or floating point co-processor podule. 2178 2179 You may say N here if you are going to load the Acorn FPEmulator 2180 early in the bootup. 2181 2182config FPE_NWFPE_XP 2183 bool "Support extended precision" 2184 depends on FPE_NWFPE 2185 help 2186 Say Y to include 80-bit support in the kernel floating-point 2187 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2188 Note that gcc does not generate 80-bit operations by default, 2189 so in most cases this option only enlarges the size of the 2190 floating point emulator without any good reason. 2191 2192 You almost surely want to say N here. 2193 2194config FPE_FASTFPE 2195 bool "FastFPE math emulation (EXPERIMENTAL)" 2196 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2197 ---help--- 2198 Say Y here to include the FAST floating point emulator in the kernel. 2199 This is an experimental much faster emulator which now also has full 2200 precision for the mantissa. It does not support any exceptions. 2201 It is very simple, and approximately 3-6 times faster than NWFPE. 2202 2203 It should be sufficient for most programs. It may be not suitable 2204 for scientific calculations, but you have to check this for yourself. 2205 If you do not feel you need a faster FP emulation you should better 2206 choose NWFPE. 2207 2208config VFP 2209 bool "VFP-format floating point maths" 2210 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2211 help 2212 Say Y to include VFP support code in the kernel. This is needed 2213 if your hardware includes a VFP unit. 2214 2215 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2216 release notes and additional status information. 2217 2218 Say N if your target does not have VFP hardware. 2219 2220config VFPv3 2221 bool 2222 depends on VFP 2223 default y if CPU_V7 2224 2225config NEON 2226 bool "Advanced SIMD (NEON) Extension support" 2227 depends on VFPv3 && CPU_V7 2228 help 2229 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2230 Extension. 2231 2232endmenu 2233 2234menu "Userspace binary formats" 2235 2236source "fs/Kconfig.binfmt" 2237 2238config ARTHUR 2239 tristate "RISC OS personality" 2240 depends on !AEABI 2241 help 2242 Say Y here to include the kernel code necessary if you want to run 2243 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2244 experimental; if this sounds frightening, say N and sleep in peace. 2245 You can also say M here to compile this support as a module (which 2246 will be called arthur). 2247 2248endmenu 2249 2250menu "Power management options" 2251 2252source "kernel/power/Kconfig" 2253 2254config ARCH_SUSPEND_POSSIBLE 2255 depends on !ARCH_S5PC100 2256 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2257 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2258 def_bool y 2259 2260config ARM_CPU_SUSPEND 2261 def_bool PM_SLEEP 2262 2263endmenu 2264 2265source "net/Kconfig" 2266 2267source "drivers/Kconfig" 2268 2269source "fs/Kconfig" 2270 2271source "arch/arm/Kconfig.debug" 2272 2273source "security/Kconfig" 2274 2275source "crypto/Kconfig" 2276 2277source "lib/Kconfig" 2278