1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 15 select ARCH_HAS_PHYS_TO_DMA 16 select ARCH_HAS_SETUP_DMA_OPS 17 select ARCH_HAS_SET_MEMORY 18 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 19 select ARCH_HAS_STRICT_MODULE_RWX if MMU 20 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 22 select ARCH_HAVE_CUSTOM_GPIO_H 23 select ARCH_HAS_GCOV_PROFILE_ALL 24 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 25 select ARCH_MIGHT_HAVE_PC_PARPORT 26 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 27 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 28 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 29 select ARCH_SUPPORTS_ATOMIC_RMW 30 select ARCH_USE_BUILTIN_BSWAP 31 select ARCH_USE_CMPXCHG_LOCKREF 32 select ARCH_WANT_IPC_PARSE_VERSION 33 select BUILDTIME_EXTABLE_SORT if MMU 34 select CLONE_BACKWARDS 35 select CPU_PM if SUSPEND || CPU_IDLE 36 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 37 select DMA_DECLARE_COHERENT 38 select DMA_REMAP if MMU 39 select EDAC_SUPPORT 40 select EDAC_ATOMIC_SCRUB 41 select GENERIC_ALLOCATOR 42 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 43 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 44 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 45 select GENERIC_CPU_AUTOPROBE 46 select GENERIC_EARLY_IOREMAP 47 select GENERIC_IDLE_POLL_SETUP 48 select GENERIC_IRQ_PROBE 49 select GENERIC_IRQ_SHOW 50 select GENERIC_IRQ_SHOW_LEVEL 51 select GENERIC_PCI_IOMAP 52 select GENERIC_SCHED_CLOCK 53 select GENERIC_SMP_IDLE_THREAD 54 select GENERIC_STRNCPY_FROM_USER 55 select GENERIC_STRNLEN_USER 56 select HANDLE_DOMAIN_IRQ 57 select HARDIRQS_SW_RESEND 58 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 59 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 60 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 61 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 62 select HAVE_ARCH_MMAP_RND_BITS if MMU 63 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 64 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 65 select HAVE_ARCH_TRACEHOOK 66 select HAVE_ARM_SMCCC if CPU_V7 67 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 68 select HAVE_CONTEXT_TRACKING 69 select HAVE_C_RECORDMCOUNT 70 select HAVE_DEBUG_KMEMLEAK 71 select HAVE_DMA_CONTIGUOUS if MMU 72 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 74 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 75 select HAVE_EXIT_THREAD 76 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 77 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 78 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 79 select HAVE_GCC_PLUGINS 80 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 81 select HAVE_IDE if PCI || ISA || PCMCIA 82 select HAVE_IRQ_TIME_ACCOUNTING 83 select HAVE_KERNEL_GZIP 84 select HAVE_KERNEL_LZ4 85 select HAVE_KERNEL_LZMA 86 select HAVE_KERNEL_LZO 87 select HAVE_KERNEL_XZ 88 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 89 select HAVE_KRETPROBES if HAVE_KPROBES 90 select HAVE_MOD_ARCH_SPECIFIC 91 select HAVE_NMI 92 select HAVE_OPROFILE if HAVE_PERF_EVENTS 93 select HAVE_OPTPROBES if !THUMB2_KERNEL 94 select HAVE_PERF_EVENTS 95 select HAVE_PERF_REGS 96 select HAVE_PERF_USER_STACK_DUMP 97 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 98 select HAVE_REGS_AND_STACK_ACCESS_API 99 select HAVE_RSEQ 100 select HAVE_STACKPROTECTOR 101 select HAVE_SYSCALL_TRACEPOINTS 102 select HAVE_UID16 103 select HAVE_VIRT_CPU_ACCOUNTING_GEN 104 select IRQ_FORCED_THREADING 105 select MODULES_USE_ELF_REL 106 select NEED_DMA_MAP_STATE 107 select OF_EARLY_FLATTREE if OF 108 select OLD_SIGACTION 109 select OLD_SIGSUSPEND3 110 select PCI_SYSCALL if PCI 111 select PERF_USE_VMALLOC 112 select REFCOUNT_FULL 113 select RTC_LIB 114 select SYS_SUPPORTS_APM_EMULATION 115 # Above selects are sorted alphabetically; please add new ones 116 # according to that. Thanks. 117 help 118 The ARM series is a line of low-power-consumption RISC chip designs 119 licensed by ARM Ltd and targeted at embedded applications and 120 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 121 manufactured, but legacy ARM-based PC hardware remains popular in 122 Europe. There is an ARM Linux project with a web page at 123 <http://www.arm.linux.org.uk/>. 124 125config ARM_HAS_SG_CHAIN 126 bool 127 128config ARM_DMA_USE_IOMMU 129 bool 130 select ARM_HAS_SG_CHAIN 131 select NEED_SG_DMA_LENGTH 132 133if ARM_DMA_USE_IOMMU 134 135config ARM_DMA_IOMMU_ALIGNMENT 136 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 137 range 4 9 138 default 8 139 help 140 DMA mapping framework by default aligns all buffers to the smallest 141 PAGE_SIZE order which is greater than or equal to the requested buffer 142 size. This works well for buffers up to a few hundreds kilobytes, but 143 for larger buffers it just a waste of address space. Drivers which has 144 relatively small addressing window (like 64Mib) might run out of 145 virtual space with just a few allocations. 146 147 With this parameter you can specify the maximum PAGE_SIZE order for 148 DMA IOMMU buffers. Larger buffers will be aligned only to this 149 specified order. The order is expressed as a power of two multiplied 150 by the PAGE_SIZE. 151 152endif 153 154config SYS_SUPPORTS_APM_EMULATION 155 bool 156 157config HAVE_TCM 158 bool 159 select GENERIC_ALLOCATOR 160 161config HAVE_PROC_CPU 162 bool 163 164config NO_IOPORT_MAP 165 bool 166 167config SBUS 168 bool 169 170config STACKTRACE_SUPPORT 171 bool 172 default y 173 174config LOCKDEP_SUPPORT 175 bool 176 default y 177 178config TRACE_IRQFLAGS_SUPPORT 179 bool 180 default !CPU_V7M 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config ARCH_SUPPORTS_UPROBES 209 def_bool y 210 211config ARCH_HAS_DMA_SET_COHERENT_MASK 212 bool 213 214config GENERIC_ISA_DMA 215 bool 216 217config FIQ 218 bool 219 220config NEED_RET_TO_USER 221 bool 222 223config ARCH_MTD_XIP 224 bool 225 226config ARM_PATCH_PHYS_VIRT 227 bool "Patch physical to virtual translations at runtime" if EMBEDDED 228 default y 229 depends on !XIP_KERNEL && MMU 230 help 231 Patch phys-to-virt and virt-to-phys translation functions at 232 boot and module load time according to the position of the 233 kernel in system memory. 234 235 This can only be used with non-XIP MMU kernels where the base 236 of physical memory is at a 16MB boundary. 237 238 Only disable this option if you know that you do not require 239 this feature (eg, building a kernel for a single machine) and 240 you need to shrink the kernel to the minimal size. 241 242config NEED_MACH_IO_H 243 bool 244 help 245 Select this when mach/io.h is required to provide special 246 definitions for this platform. The need for mach/io.h should 247 be avoided when possible. 248 249config NEED_MACH_MEMORY_H 250 bool 251 help 252 Select this when mach/memory.h is required to provide special 253 definitions for this platform. The need for mach/memory.h should 254 be avoided when possible. 255 256config PHYS_OFFSET 257 hex "Physical address of main memory" if MMU 258 depends on !ARM_PATCH_PHYS_VIRT 259 default DRAM_BASE if !MMU 260 default 0x00000000 if ARCH_EBSA110 || \ 261 ARCH_FOOTBRIDGE || \ 262 ARCH_INTEGRATOR || \ 263 ARCH_IOP13XX || \ 264 ARCH_KS8695 || \ 265 ARCH_REALVIEW 266 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 267 default 0x20000000 if ARCH_S5PV210 268 default 0xc0000000 if ARCH_SA1100 269 help 270 Please provide the physical address corresponding to the 271 location of main memory in your system. 272 273config GENERIC_BUG 274 def_bool y 275 depends on BUG 276 277config PGTABLE_LEVELS 278 int 279 default 3 if ARM_LPAE 280 default 2 281 282menu "System Type" 283 284config MMU 285 bool "MMU-based Paged Memory Management Support" 286 default y 287 help 288 Select if you want MMU-based virtualised addressing space 289 support by paged memory management. If unsure, say 'Y'. 290 291config ARCH_MMAP_RND_BITS_MIN 292 default 8 293 294config ARCH_MMAP_RND_BITS_MAX 295 default 14 if PAGE_OFFSET=0x40000000 296 default 15 if PAGE_OFFSET=0x80000000 297 default 16 298 299# 300# The "ARM system type" choice list is ordered alphabetically by option 301# text. Please add new entries in the option alphabetic order. 302# 303choice 304 prompt "ARM system type" 305 default ARM_SINGLE_ARMV7M if !MMU 306 default ARCH_MULTIPLATFORM if MMU 307 308config ARCH_MULTIPLATFORM 309 bool "Allow multiple platforms to be selected" 310 depends on MMU 311 select ARM_HAS_SG_CHAIN 312 select ARM_PATCH_PHYS_VIRT 313 select AUTO_ZRELADDR 314 select TIMER_OF 315 select COMMON_CLK 316 select GENERIC_CLOCKEVENTS 317 select GENERIC_IRQ_MULTI_HANDLER 318 select HAVE_PCI 319 select PCI_DOMAINS_GENERIC if PCI 320 select SPARSE_IRQ 321 select USE_OF 322 323config ARM_SINGLE_ARMV7M 324 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 325 depends on !MMU 326 select ARM_NVIC 327 select AUTO_ZRELADDR 328 select TIMER_OF 329 select COMMON_CLK 330 select CPU_V7M 331 select GENERIC_CLOCKEVENTS 332 select NO_IOPORT_MAP 333 select SPARSE_IRQ 334 select USE_OF 335 336config ARCH_EBSA110 337 bool "EBSA-110" 338 select ARCH_USES_GETTIMEOFFSET 339 select CPU_SA110 340 select ISA 341 select NEED_MACH_IO_H 342 select NEED_MACH_MEMORY_H 343 select NO_IOPORT_MAP 344 help 345 This is an evaluation board for the StrongARM processor available 346 from Digital. It has limited hardware on-board, including an 347 Ethernet interface, two PCMCIA sockets, two serial ports and a 348 parallel port. 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKDEV_LOOKUP 358 select CLKSRC_MMIO 359 select CPU_ARM920T 360 select GENERIC_CLOCKEVENTS 361 select GPIOLIB 362 help 363 This enables support for the Cirrus EP93xx series of CPUs. 364 365config ARCH_FOOTBRIDGE 366 bool "FootBridge" 367 select CPU_SA110 368 select FOOTBRIDGE 369 select GENERIC_CLOCKEVENTS 370 select HAVE_IDE 371 select NEED_MACH_IO_H if !MMU 372 select NEED_MACH_MEMORY_H 373 help 374 Support for systems based on the DC21285 companion chip 375 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 376 377config ARCH_NETX 378 bool "Hilscher NetX based" 379 select ARM_VIC 380 select CLKSRC_MMIO 381 select CPU_ARM926T 382 select GENERIC_CLOCKEVENTS 383 help 384 This enables support for systems based on the Hilscher NetX Soc 385 386config ARCH_IOP13XX 387 bool "IOP13xx-based" 388 depends on MMU 389 select CPU_XSC3 390 select NEED_MACH_MEMORY_H 391 select NEED_RET_TO_USER 392 select FORCE_PCI 393 select PLAT_IOP 394 select VMSPLIT_1G 395 select SPARSE_IRQ 396 help 397 Support for Intel's IOP13XX (XScale) family of processors. 398 399config ARCH_IOP32X 400 bool "IOP32x-based" 401 depends on MMU 402 select CPU_XSCALE 403 select GPIO_IOP 404 select GPIOLIB 405 select NEED_RET_TO_USER 406 select FORCE_PCI 407 select PLAT_IOP 408 help 409 Support for Intel's 80219 and IOP32X (XScale) family of 410 processors. 411 412config ARCH_IOP33X 413 bool "IOP33x-based" 414 depends on MMU 415 select CPU_XSCALE 416 select GPIO_IOP 417 select GPIOLIB 418 select NEED_RET_TO_USER 419 select FORCE_PCI 420 select PLAT_IOP 421 help 422 Support for Intel's IOP33X (XScale) family of processors. 423 424config ARCH_IXP4XX 425 bool "IXP4xx-based" 426 depends on MMU 427 select ARCH_HAS_DMA_SET_COHERENT_MASK 428 select ARCH_SUPPORTS_BIG_ENDIAN 429 select CPU_XSCALE 430 select DMABOUNCE if PCI 431 select GENERIC_CLOCKEVENTS 432 select GENERIC_IRQ_MULTI_HANDLER 433 select GPIO_IXP4XX 434 select GPIOLIB 435 select HAVE_PCI 436 select IXP4XX_IRQ 437 select IXP4XX_TIMER 438 select NEED_MACH_IO_H 439 select USB_EHCI_BIG_ENDIAN_DESC 440 select USB_EHCI_BIG_ENDIAN_MMIO 441 help 442 Support for Intel's IXP4XX (XScale) family of processors. 443 444config ARCH_DOVE 445 bool "Marvell Dove" 446 select CPU_PJ4 447 select GENERIC_CLOCKEVENTS 448 select GENERIC_IRQ_MULTI_HANDLER 449 select GPIOLIB 450 select HAVE_PCI 451 select MVEBU_MBUS 452 select PINCTRL 453 select PINCTRL_DOVE 454 select PLAT_ORION_LEGACY 455 select SPARSE_IRQ 456 select PM_GENERIC_DOMAINS if PM 457 help 458 Support for the Marvell Dove SoC 88AP510 459 460config ARCH_KS8695 461 bool "Micrel/Kendin KS8695" 462 select CLKSRC_MMIO 463 select CPU_ARM922T 464 select GENERIC_CLOCKEVENTS 465 select GPIOLIB 466 select NEED_MACH_MEMORY_H 467 help 468 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 469 System-on-Chip devices. 470 471config ARCH_W90X900 472 bool "Nuvoton W90X900 CPU" 473 select CLKDEV_LOOKUP 474 select CLKSRC_MMIO 475 select CPU_ARM926T 476 select GENERIC_CLOCKEVENTS 477 select GPIOLIB 478 help 479 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 480 At present, the w90x900 has been renamed nuc900, regarding 481 the ARM series product line, you can login the following 482 link address to know more. 483 484 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 485 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 486 487config ARCH_LPC32XX 488 bool "NXP LPC32XX" 489 select ARM_AMBA 490 select CLKDEV_LOOKUP 491 select CLKSRC_LPC32XX 492 select COMMON_CLK 493 select CPU_ARM926T 494 select GENERIC_CLOCKEVENTS 495 select GENERIC_IRQ_MULTI_HANDLER 496 select GPIOLIB 497 select SPARSE_IRQ 498 select USE_OF 499 help 500 Support for the NXP LPC32XX family of processors 501 502config ARCH_PXA 503 bool "PXA2xx/PXA3xx-based" 504 depends on MMU 505 select ARCH_MTD_XIP 506 select ARM_CPU_SUSPEND if PM 507 select AUTO_ZRELADDR 508 select COMMON_CLK 509 select CLKDEV_LOOKUP 510 select CLKSRC_PXA 511 select CLKSRC_MMIO 512 select TIMER_OF 513 select CPU_XSCALE if !CPU_XSC3 514 select GENERIC_CLOCKEVENTS 515 select GENERIC_IRQ_MULTI_HANDLER 516 select GPIO_PXA 517 select GPIOLIB 518 select HAVE_IDE 519 select IRQ_DOMAIN 520 select PLAT_PXA 521 select SPARSE_IRQ 522 help 523 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 524 525config ARCH_RPC 526 bool "RiscPC" 527 depends on MMU 528 select ARCH_ACORN 529 select ARCH_MAY_HAVE_PC_FDC 530 select ARCH_SPARSEMEM_ENABLE 531 select ARCH_USES_GETTIMEOFFSET 532 select CPU_SA110 533 select FIQ 534 select HAVE_IDE 535 select HAVE_PATA_PLATFORM 536 select ISA_DMA_API 537 select NEED_MACH_IO_H 538 select NEED_MACH_MEMORY_H 539 select NO_IOPORT_MAP 540 help 541 On the Acorn Risc-PC, Linux can support the internal IDE disk and 542 CD-ROM interface, serial and parallel port, and the floppy drive. 543 544config ARCH_SA1100 545 bool "SA1100-based" 546 select ARCH_MTD_XIP 547 select ARCH_SPARSEMEM_ENABLE 548 select CLKDEV_LOOKUP 549 select CLKSRC_MMIO 550 select CLKSRC_PXA 551 select TIMER_OF if OF 552 select CPU_FREQ 553 select CPU_SA1100 554 select GENERIC_CLOCKEVENTS 555 select GENERIC_IRQ_MULTI_HANDLER 556 select GPIOLIB 557 select HAVE_IDE 558 select IRQ_DOMAIN 559 select ISA 560 select NEED_MACH_MEMORY_H 561 select SPARSE_IRQ 562 help 563 Support for StrongARM 11x0 based boards. 564 565config ARCH_S3C24XX 566 bool "Samsung S3C24XX SoCs" 567 select ATAGS 568 select CLKDEV_LOOKUP 569 select CLKSRC_SAMSUNG_PWM 570 select GENERIC_CLOCKEVENTS 571 select GPIO_SAMSUNG 572 select GPIOLIB 573 select GENERIC_IRQ_MULTI_HANDLER 574 select HAVE_S3C2410_I2C if I2C 575 select HAVE_S3C2410_WATCHDOG if WATCHDOG 576 select HAVE_S3C_RTC if RTC_CLASS 577 select NEED_MACH_IO_H 578 select SAMSUNG_ATAGS 579 select USE_OF 580 help 581 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 582 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 583 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 584 Samsung SMDK2410 development board (and derivatives). 585 586config ARCH_DAVINCI 587 bool "TI DaVinci" 588 select ARCH_HAS_HOLES_MEMORYMODEL 589 select COMMON_CLK 590 select CPU_ARM926T 591 select GENERIC_ALLOCATOR 592 select GENERIC_CLOCKEVENTS 593 select GENERIC_IRQ_CHIP 594 select GENERIC_IRQ_MULTI_HANDLER 595 select GPIOLIB 596 select HAVE_IDE 597 select PM_GENERIC_DOMAINS if PM 598 select PM_GENERIC_DOMAINS_OF if PM && OF 599 select REGMAP_MMIO 600 select RESET_CONTROLLER 601 select SPARSE_IRQ 602 select USE_OF 603 select ZONE_DMA 604 help 605 Support for TI's DaVinci platform. 606 607config ARCH_OMAP1 608 bool "TI OMAP1" 609 depends on MMU 610 select ARCH_HAS_HOLES_MEMORYMODEL 611 select ARCH_OMAP 612 select CLKDEV_LOOKUP 613 select CLKSRC_MMIO 614 select GENERIC_CLOCKEVENTS 615 select GENERIC_IRQ_CHIP 616 select GENERIC_IRQ_MULTI_HANDLER 617 select GPIOLIB 618 select HAVE_IDE 619 select IRQ_DOMAIN 620 select NEED_MACH_IO_H if PCCARD 621 select NEED_MACH_MEMORY_H 622 select SPARSE_IRQ 623 help 624 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 625 626endchoice 627 628menu "Multiple platform selection" 629 depends on ARCH_MULTIPLATFORM 630 631comment "CPU Core family selection" 632 633config ARCH_MULTI_V4 634 bool "ARMv4 based platforms (FA526)" 635 depends on !ARCH_MULTI_V6_V7 636 select ARCH_MULTI_V4_V5 637 select CPU_FA526 638 639config ARCH_MULTI_V4T 640 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 641 depends on !ARCH_MULTI_V6_V7 642 select ARCH_MULTI_V4_V5 643 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 644 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 645 CPU_ARM925T || CPU_ARM940T) 646 647config ARCH_MULTI_V5 648 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 649 depends on !ARCH_MULTI_V6_V7 650 select ARCH_MULTI_V4_V5 651 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 652 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 653 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 654 655config ARCH_MULTI_V4_V5 656 bool 657 658config ARCH_MULTI_V6 659 bool "ARMv6 based platforms (ARM11)" 660 select ARCH_MULTI_V6_V7 661 select CPU_V6K 662 663config ARCH_MULTI_V7 664 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 665 default y 666 select ARCH_MULTI_V6_V7 667 select CPU_V7 668 select HAVE_SMP 669 670config ARCH_MULTI_V6_V7 671 bool 672 select MIGHT_HAVE_CACHE_L2X0 673 674config ARCH_MULTI_CPU_AUTO 675 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 676 select ARCH_MULTI_V5 677 678endmenu 679 680config ARCH_VIRT 681 bool "Dummy Virtual Machine" 682 depends on ARCH_MULTI_V7 683 select ARM_AMBA 684 select ARM_GIC 685 select ARM_GIC_V2M if PCI 686 select ARM_GIC_V3 687 select ARM_GIC_V3_ITS if PCI 688 select ARM_PSCI 689 select HAVE_ARM_ARCH_TIMER 690 select ARCH_SUPPORTS_BIG_ENDIAN 691 692# 693# This is sorted alphabetically by mach-* pathname. However, plat-* 694# Kconfigs may be included either alphabetically (according to the 695# plat- suffix) or along side the corresponding mach-* source. 696# 697source "arch/arm/mach-actions/Kconfig" 698 699source "arch/arm/mach-alpine/Kconfig" 700 701source "arch/arm/mach-artpec/Kconfig" 702 703source "arch/arm/mach-asm9260/Kconfig" 704 705source "arch/arm/mach-aspeed/Kconfig" 706 707source "arch/arm/mach-at91/Kconfig" 708 709source "arch/arm/mach-axxia/Kconfig" 710 711source "arch/arm/mach-bcm/Kconfig" 712 713source "arch/arm/mach-berlin/Kconfig" 714 715source "arch/arm/mach-clps711x/Kconfig" 716 717source "arch/arm/mach-cns3xxx/Kconfig" 718 719source "arch/arm/mach-davinci/Kconfig" 720 721source "arch/arm/mach-digicolor/Kconfig" 722 723source "arch/arm/mach-dove/Kconfig" 724 725source "arch/arm/mach-ep93xx/Kconfig" 726 727source "arch/arm/mach-exynos/Kconfig" 728source "arch/arm/plat-samsung/Kconfig" 729 730source "arch/arm/mach-footbridge/Kconfig" 731 732source "arch/arm/mach-gemini/Kconfig" 733 734source "arch/arm/mach-highbank/Kconfig" 735 736source "arch/arm/mach-hisi/Kconfig" 737 738source "arch/arm/mach-imx/Kconfig" 739 740source "arch/arm/mach-integrator/Kconfig" 741 742source "arch/arm/mach-iop13xx/Kconfig" 743 744source "arch/arm/mach-iop32x/Kconfig" 745 746source "arch/arm/mach-iop33x/Kconfig" 747 748source "arch/arm/mach-ixp4xx/Kconfig" 749 750source "arch/arm/mach-keystone/Kconfig" 751 752source "arch/arm/mach-ks8695/Kconfig" 753 754source "arch/arm/mach-mediatek/Kconfig" 755 756source "arch/arm/mach-meson/Kconfig" 757 758source "arch/arm/mach-milbeaut/Kconfig" 759 760source "arch/arm/mach-mmp/Kconfig" 761 762source "arch/arm/mach-moxart/Kconfig" 763 764source "arch/arm/mach-mv78xx0/Kconfig" 765 766source "arch/arm/mach-mvebu/Kconfig" 767 768source "arch/arm/mach-mxs/Kconfig" 769 770source "arch/arm/mach-netx/Kconfig" 771 772source "arch/arm/mach-nomadik/Kconfig" 773 774source "arch/arm/mach-npcm/Kconfig" 775 776source "arch/arm/mach-nspire/Kconfig" 777 778source "arch/arm/plat-omap/Kconfig" 779 780source "arch/arm/mach-omap1/Kconfig" 781 782source "arch/arm/mach-omap2/Kconfig" 783 784source "arch/arm/mach-orion5x/Kconfig" 785 786source "arch/arm/mach-oxnas/Kconfig" 787 788source "arch/arm/mach-picoxcell/Kconfig" 789 790source "arch/arm/mach-prima2/Kconfig" 791 792source "arch/arm/mach-pxa/Kconfig" 793source "arch/arm/plat-pxa/Kconfig" 794 795source "arch/arm/mach-qcom/Kconfig" 796 797source "arch/arm/mach-rda/Kconfig" 798 799source "arch/arm/mach-realview/Kconfig" 800 801source "arch/arm/mach-rockchip/Kconfig" 802 803source "arch/arm/mach-s3c24xx/Kconfig" 804 805source "arch/arm/mach-s3c64xx/Kconfig" 806 807source "arch/arm/mach-s5pv210/Kconfig" 808 809source "arch/arm/mach-sa1100/Kconfig" 810 811source "arch/arm/mach-shmobile/Kconfig" 812 813source "arch/arm/mach-socfpga/Kconfig" 814 815source "arch/arm/mach-spear/Kconfig" 816 817source "arch/arm/mach-sti/Kconfig" 818 819source "arch/arm/mach-stm32/Kconfig" 820 821source "arch/arm/mach-sunxi/Kconfig" 822 823source "arch/arm/mach-tango/Kconfig" 824 825source "arch/arm/mach-tegra/Kconfig" 826 827source "arch/arm/mach-u300/Kconfig" 828 829source "arch/arm/mach-uniphier/Kconfig" 830 831source "arch/arm/mach-ux500/Kconfig" 832 833source "arch/arm/mach-versatile/Kconfig" 834 835source "arch/arm/mach-vexpress/Kconfig" 836source "arch/arm/plat-versatile/Kconfig" 837 838source "arch/arm/mach-vt8500/Kconfig" 839 840source "arch/arm/mach-w90x900/Kconfig" 841 842source "arch/arm/mach-zx/Kconfig" 843 844source "arch/arm/mach-zynq/Kconfig" 845 846# ARMv7-M architecture 847config ARCH_EFM32 848 bool "Energy Micro efm32" 849 depends on ARM_SINGLE_ARMV7M 850 select GPIOLIB 851 help 852 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 853 processors. 854 855config ARCH_LPC18XX 856 bool "NXP LPC18xx/LPC43xx" 857 depends on ARM_SINGLE_ARMV7M 858 select ARCH_HAS_RESET_CONTROLLER 859 select ARM_AMBA 860 select CLKSRC_LPC32XX 861 select PINCTRL 862 help 863 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 864 high performance microcontrollers. 865 866config ARCH_MPS2 867 bool "ARM MPS2 platform" 868 depends on ARM_SINGLE_ARMV7M 869 select ARM_AMBA 870 select CLKSRC_MPS2 871 help 872 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 873 with a range of available cores like Cortex-M3/M4/M7. 874 875 Please, note that depends which Application Note is used memory map 876 for the platform may vary, so adjustment of RAM base might be needed. 877 878# Definitions to make life easier 879config ARCH_ACORN 880 bool 881 882config PLAT_IOP 883 bool 884 select GENERIC_CLOCKEVENTS 885 886config PLAT_ORION 887 bool 888 select CLKSRC_MMIO 889 select COMMON_CLK 890 select GENERIC_IRQ_CHIP 891 select IRQ_DOMAIN 892 893config PLAT_ORION_LEGACY 894 bool 895 select PLAT_ORION 896 897config PLAT_PXA 898 bool 899 900config PLAT_VERSATILE 901 bool 902 903source "arch/arm/mm/Kconfig" 904 905config IWMMXT 906 bool "Enable iWMMXt support" 907 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 908 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 909 help 910 Enable support for iWMMXt context switching at run time if 911 running on a CPU that supports it. 912 913if !MMU 914source "arch/arm/Kconfig-nommu" 915endif 916 917config PJ4B_ERRATA_4742 918 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 919 depends on CPU_PJ4B && MACH_ARMADA_370 920 default y 921 help 922 When coming out of either a Wait for Interrupt (WFI) or a Wait for 923 Event (WFE) IDLE states, a specific timing sensitivity exists between 924 the retiring WFI/WFE instructions and the newly issued subsequent 925 instructions. This sensitivity can result in a CPU hang scenario. 926 Workaround: 927 The software must insert either a Data Synchronization Barrier (DSB) 928 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 929 instruction 930 931config ARM_ERRATA_326103 932 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 933 depends on CPU_V6 934 help 935 Executing a SWP instruction to read-only memory does not set bit 11 936 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 937 treat the access as a read, preventing a COW from occurring and 938 causing the faulting task to livelock. 939 940config ARM_ERRATA_411920 941 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 942 depends on CPU_V6 || CPU_V6K 943 help 944 Invalidation of the Instruction Cache operation can 945 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 946 It does not affect the MPCore. This option enables the ARM Ltd. 947 recommended workaround. 948 949config ARM_ERRATA_430973 950 bool "ARM errata: Stale prediction on replaced interworking branch" 951 depends on CPU_V7 952 help 953 This option enables the workaround for the 430973 Cortex-A8 954 r1p* erratum. If a code sequence containing an ARM/Thumb 955 interworking branch is replaced with another code sequence at the 956 same virtual address, whether due to self-modifying code or virtual 957 to physical address re-mapping, Cortex-A8 does not recover from the 958 stale interworking branch prediction. This results in Cortex-A8 959 executing the new code sequence in the incorrect ARM or Thumb state. 960 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 961 and also flushes the branch target cache at every context switch. 962 Note that setting specific bits in the ACTLR register may not be 963 available in non-secure mode. 964 965config ARM_ERRATA_458693 966 bool "ARM errata: Processor deadlock when a false hazard is created" 967 depends on CPU_V7 968 depends on !ARCH_MULTIPLATFORM 969 help 970 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 971 erratum. For very specific sequences of memory operations, it is 972 possible for a hazard condition intended for a cache line to instead 973 be incorrectly associated with a different cache line. This false 974 hazard might then cause a processor deadlock. The workaround enables 975 the L1 caching of the NEON accesses and disables the PLD instruction 976 in the ACTLR register. Note that setting specific bits in the ACTLR 977 register may not be available in non-secure mode. 978 979config ARM_ERRATA_460075 980 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 981 depends on CPU_V7 982 depends on !ARCH_MULTIPLATFORM 983 help 984 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 985 erratum. Any asynchronous access to the L2 cache may encounter a 986 situation in which recent store transactions to the L2 cache are lost 987 and overwritten with stale memory contents from external memory. The 988 workaround disables the write-allocate mode for the L2 cache via the 989 ACTLR register. Note that setting specific bits in the ACTLR register 990 may not be available in non-secure mode. 991 992config ARM_ERRATA_742230 993 bool "ARM errata: DMB operation may be faulty" 994 depends on CPU_V7 && SMP 995 depends on !ARCH_MULTIPLATFORM 996 help 997 This option enables the workaround for the 742230 Cortex-A9 998 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 999 between two write operations may not ensure the correct visibility 1000 ordering of the two writes. This workaround sets a specific bit in 1001 the diagnostic register of the Cortex-A9 which causes the DMB 1002 instruction to behave as a DSB, ensuring the correct behaviour of 1003 the two writes. 1004 1005config ARM_ERRATA_742231 1006 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1007 depends on CPU_V7 && SMP 1008 depends on !ARCH_MULTIPLATFORM 1009 help 1010 This option enables the workaround for the 742231 Cortex-A9 1011 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1012 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1013 accessing some data located in the same cache line, may get corrupted 1014 data due to bad handling of the address hazard when the line gets 1015 replaced from one of the CPUs at the same time as another CPU is 1016 accessing it. This workaround sets specific bits in the diagnostic 1017 register of the Cortex-A9 which reduces the linefill issuing 1018 capabilities of the processor. 1019 1020config ARM_ERRATA_643719 1021 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1022 depends on CPU_V7 && SMP 1023 default y 1024 help 1025 This option enables the workaround for the 643719 Cortex-A9 (prior to 1026 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1027 register returns zero when it should return one. The workaround 1028 corrects this value, ensuring cache maintenance operations which use 1029 it behave as intended and avoiding data corruption. 1030 1031config ARM_ERRATA_720789 1032 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1033 depends on CPU_V7 1034 help 1035 This option enables the workaround for the 720789 Cortex-A9 (prior to 1036 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1037 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1038 As a consequence of this erratum, some TLB entries which should be 1039 invalidated are not, resulting in an incoherency in the system page 1040 tables. The workaround changes the TLB flushing routines to invalidate 1041 entries regardless of the ASID. 1042 1043config ARM_ERRATA_743622 1044 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1045 depends on CPU_V7 1046 depends on !ARCH_MULTIPLATFORM 1047 help 1048 This option enables the workaround for the 743622 Cortex-A9 1049 (r2p*) erratum. Under very rare conditions, a faulty 1050 optimisation in the Cortex-A9 Store Buffer may lead to data 1051 corruption. This workaround sets a specific bit in the diagnostic 1052 register of the Cortex-A9 which disables the Store Buffer 1053 optimisation, preventing the defect from occurring. This has no 1054 visible impact on the overall performance or power consumption of the 1055 processor. 1056 1057config ARM_ERRATA_751472 1058 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1059 depends on CPU_V7 1060 depends on !ARCH_MULTIPLATFORM 1061 help 1062 This option enables the workaround for the 751472 Cortex-A9 (prior 1063 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1064 completion of a following broadcasted operation if the second 1065 operation is received by a CPU before the ICIALLUIS has completed, 1066 potentially leading to corrupted entries in the cache or TLB. 1067 1068config ARM_ERRATA_754322 1069 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1070 depends on CPU_V7 1071 help 1072 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1073 r3p*) erratum. A speculative memory access may cause a page table walk 1074 which starts prior to an ASID switch but completes afterwards. This 1075 can populate the micro-TLB with a stale entry which may be hit with 1076 the new ASID. This workaround places two dsb instructions in the mm 1077 switching code so that no page table walks can cross the ASID switch. 1078 1079config ARM_ERRATA_754327 1080 bool "ARM errata: no automatic Store Buffer drain" 1081 depends on CPU_V7 && SMP 1082 help 1083 This option enables the workaround for the 754327 Cortex-A9 (prior to 1084 r2p0) erratum. The Store Buffer does not have any automatic draining 1085 mechanism and therefore a livelock may occur if an external agent 1086 continuously polls a memory location waiting to observe an update. 1087 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1088 written polling loops from denying visibility of updates to memory. 1089 1090config ARM_ERRATA_364296 1091 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1092 depends on CPU_V6 1093 help 1094 This options enables the workaround for the 364296 ARM1136 1095 r0p2 erratum (possible cache data corruption with 1096 hit-under-miss enabled). It sets the undocumented bit 31 in 1097 the auxiliary control register and the FI bit in the control 1098 register, thus disabling hit-under-miss without putting the 1099 processor into full low interrupt latency mode. ARM11MPCore 1100 is not affected. 1101 1102config ARM_ERRATA_764369 1103 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1104 depends on CPU_V7 && SMP 1105 help 1106 This option enables the workaround for erratum 764369 1107 affecting Cortex-A9 MPCore with two or more processors (all 1108 current revisions). Under certain timing circumstances, a data 1109 cache line maintenance operation by MVA targeting an Inner 1110 Shareable memory region may fail to proceed up to either the 1111 Point of Coherency or to the Point of Unification of the 1112 system. This workaround adds a DSB instruction before the 1113 relevant cache maintenance functions and sets a specific bit 1114 in the diagnostic control register of the SCU. 1115 1116config ARM_ERRATA_775420 1117 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1118 depends on CPU_V7 1119 help 1120 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1121 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1122 operation aborts with MMU exception, it might cause the processor 1123 to deadlock. This workaround puts DSB before executing ISB if 1124 an abort may occur on cache maintenance. 1125 1126config ARM_ERRATA_798181 1127 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1128 depends on CPU_V7 && SMP 1129 help 1130 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1131 adequately shooting down all use of the old entries. This 1132 option enables the Linux kernel workaround for this erratum 1133 which sends an IPI to the CPUs that are running the same ASID 1134 as the one being invalidated. 1135 1136config ARM_ERRATA_773022 1137 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1138 depends on CPU_V7 1139 help 1140 This option enables the workaround for the 773022 Cortex-A15 1141 (up to r0p4) erratum. In certain rare sequences of code, the 1142 loop buffer may deliver incorrect instructions. This 1143 workaround disables the loop buffer to avoid the erratum. 1144 1145config ARM_ERRATA_818325_852422 1146 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1147 depends on CPU_V7 1148 help 1149 This option enables the workaround for: 1150 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1151 instruction might deadlock. Fixed in r0p1. 1152 - Cortex-A12 852422: Execution of a sequence of instructions might 1153 lead to either a data corruption or a CPU deadlock. Not fixed in 1154 any Cortex-A12 cores yet. 1155 This workaround for all both errata involves setting bit[12] of the 1156 Feature Register. This bit disables an optimisation applied to a 1157 sequence of 2 instructions that use opposing condition codes. 1158 1159config ARM_ERRATA_821420 1160 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1161 depends on CPU_V7 1162 help 1163 This option enables the workaround for the 821420 Cortex-A12 1164 (all revs) erratum. In very rare timing conditions, a sequence 1165 of VMOV to Core registers instructions, for which the second 1166 one is in the shadow of a branch or abort, can lead to a 1167 deadlock when the VMOV instructions are issued out-of-order. 1168 1169config ARM_ERRATA_825619 1170 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1171 depends on CPU_V7 1172 help 1173 This option enables the workaround for the 825619 Cortex-A12 1174 (all revs) erratum. Within rare timing constraints, executing a 1175 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1176 and Device/Strongly-Ordered loads and stores might cause deadlock 1177 1178config ARM_ERRATA_852421 1179 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1180 depends on CPU_V7 1181 help 1182 This option enables the workaround for the 852421 Cortex-A17 1183 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1184 execution of a DMB ST instruction might fail to properly order 1185 stores from GroupA and stores from GroupB. 1186 1187config ARM_ERRATA_852423 1188 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1189 depends on CPU_V7 1190 help 1191 This option enables the workaround for: 1192 - Cortex-A17 852423: Execution of a sequence of instructions might 1193 lead to either a data corruption or a CPU deadlock. Not fixed in 1194 any Cortex-A17 cores yet. 1195 This is identical to Cortex-A12 erratum 852422. It is a separate 1196 config option from the A12 erratum due to the way errata are checked 1197 for and handled. 1198 1199endmenu 1200 1201source "arch/arm/common/Kconfig" 1202 1203menu "Bus support" 1204 1205config ISA 1206 bool 1207 help 1208 Find out whether you have ISA slots on your motherboard. ISA is the 1209 name of a bus system, i.e. the way the CPU talks to the other stuff 1210 inside your box. Other bus systems are PCI, EISA, MicroChannel 1211 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1212 newer boards don't support it. If you have ISA, say Y, otherwise N. 1213 1214# Select ISA DMA controller support 1215config ISA_DMA 1216 bool 1217 select ISA_DMA_API 1218 1219# Select ISA DMA interface 1220config ISA_DMA_API 1221 bool 1222 1223config PCI_NANOENGINE 1224 bool "BSE nanoEngine PCI support" 1225 depends on SA1100_NANOENGINE 1226 help 1227 Enable PCI on the BSE nanoEngine board. 1228 1229config PCI_HOST_ITE8152 1230 bool 1231 depends on PCI && MACH_ARMCORE 1232 default y 1233 select DMABOUNCE 1234 1235endmenu 1236 1237menu "Kernel Features" 1238 1239config HAVE_SMP 1240 bool 1241 help 1242 This option should be selected by machines which have an SMP- 1243 capable CPU. 1244 1245 The only effect of this option is to make the SMP-related 1246 options available to the user for configuration. 1247 1248config SMP 1249 bool "Symmetric Multi-Processing" 1250 depends on CPU_V6K || CPU_V7 1251 depends on GENERIC_CLOCKEVENTS 1252 depends on HAVE_SMP 1253 depends on MMU || ARM_MPU 1254 select IRQ_WORK 1255 help 1256 This enables support for systems with more than one CPU. If you have 1257 a system with only one CPU, say N. If you have a system with more 1258 than one CPU, say Y. 1259 1260 If you say N here, the kernel will run on uni- and multiprocessor 1261 machines, but will use only one CPU of a multiprocessor machine. If 1262 you say Y here, the kernel will run on many, but not all, 1263 uniprocessor machines. On a uniprocessor machine, the kernel 1264 will run faster if you say N here. 1265 1266 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1267 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1268 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1269 1270 If you don't know what to do here, say N. 1271 1272config SMP_ON_UP 1273 bool "Allow booting SMP kernel on uniprocessor systems" 1274 depends on SMP && !XIP_KERNEL && MMU 1275 default y 1276 help 1277 SMP kernels contain instructions which fail on non-SMP processors. 1278 Enabling this option allows the kernel to modify itself to make 1279 these instructions safe. Disabling it allows about 1K of space 1280 savings. 1281 1282 If you don't know what to do here, say Y. 1283 1284config ARM_CPU_TOPOLOGY 1285 bool "Support cpu topology definition" 1286 depends on SMP && CPU_V7 1287 default y 1288 help 1289 Support ARM cpu topology definition. The MPIDR register defines 1290 affinity between processors which is then used to describe the cpu 1291 topology of an ARM System. 1292 1293config SCHED_MC 1294 bool "Multi-core scheduler support" 1295 depends on ARM_CPU_TOPOLOGY 1296 help 1297 Multi-core scheduler support improves the CPU scheduler's decision 1298 making when dealing with multi-core CPU chips at a cost of slightly 1299 increased overhead in some places. If unsure say N here. 1300 1301config SCHED_SMT 1302 bool "SMT scheduler support" 1303 depends on ARM_CPU_TOPOLOGY 1304 help 1305 Improves the CPU scheduler's decision making when dealing with 1306 MultiThreading at a cost of slightly increased overhead in some 1307 places. If unsure say N here. 1308 1309config HAVE_ARM_SCU 1310 bool 1311 help 1312 This option enables support for the ARM snoop control unit 1313 1314config HAVE_ARM_ARCH_TIMER 1315 bool "Architected timer support" 1316 depends on CPU_V7 1317 select ARM_ARCH_TIMER 1318 select GENERIC_CLOCKEVENTS 1319 help 1320 This option enables support for the ARM architected timer 1321 1322config HAVE_ARM_TWD 1323 bool 1324 help 1325 This options enables support for the ARM timer and watchdog unit 1326 1327config MCPM 1328 bool "Multi-Cluster Power Management" 1329 depends on CPU_V7 && SMP 1330 help 1331 This option provides the common power management infrastructure 1332 for (multi-)cluster based systems, such as big.LITTLE based 1333 systems. 1334 1335config MCPM_QUAD_CLUSTER 1336 bool 1337 depends on MCPM 1338 help 1339 To avoid wasting resources unnecessarily, MCPM only supports up 1340 to 2 clusters by default. 1341 Platforms with 3 or 4 clusters that use MCPM must select this 1342 option to allow the additional clusters to be managed. 1343 1344config BIG_LITTLE 1345 bool "big.LITTLE support (Experimental)" 1346 depends on CPU_V7 && SMP 1347 select MCPM 1348 help 1349 This option enables support selections for the big.LITTLE 1350 system architecture. 1351 1352config BL_SWITCHER 1353 bool "big.LITTLE switcher support" 1354 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1355 select CPU_PM 1356 help 1357 The big.LITTLE "switcher" provides the core functionality to 1358 transparently handle transition between a cluster of A15's 1359 and a cluster of A7's in a big.LITTLE system. 1360 1361config BL_SWITCHER_DUMMY_IF 1362 tristate "Simple big.LITTLE switcher user interface" 1363 depends on BL_SWITCHER && DEBUG_KERNEL 1364 help 1365 This is a simple and dummy char dev interface to control 1366 the big.LITTLE switcher core code. It is meant for 1367 debugging purposes only. 1368 1369choice 1370 prompt "Memory split" 1371 depends on MMU 1372 default VMSPLIT_3G 1373 help 1374 Select the desired split between kernel and user memory. 1375 1376 If you are not absolutely sure what you are doing, leave this 1377 option alone! 1378 1379 config VMSPLIT_3G 1380 bool "3G/1G user/kernel split" 1381 config VMSPLIT_3G_OPT 1382 depends on !ARM_LPAE 1383 bool "3G/1G user/kernel split (for full 1G low memory)" 1384 config VMSPLIT_2G 1385 bool "2G/2G user/kernel split" 1386 config VMSPLIT_1G 1387 bool "1G/3G user/kernel split" 1388endchoice 1389 1390config PAGE_OFFSET 1391 hex 1392 default PHYS_OFFSET if !MMU 1393 default 0x40000000 if VMSPLIT_1G 1394 default 0x80000000 if VMSPLIT_2G 1395 default 0xB0000000 if VMSPLIT_3G_OPT 1396 default 0xC0000000 1397 1398config NR_CPUS 1399 int "Maximum number of CPUs (2-32)" 1400 range 2 32 1401 depends on SMP 1402 default "4" 1403 1404config HOTPLUG_CPU 1405 bool "Support for hot-pluggable CPUs" 1406 depends on SMP 1407 select GENERIC_IRQ_MIGRATION 1408 help 1409 Say Y here to experiment with turning CPUs off and on. CPUs 1410 can be controlled through /sys/devices/system/cpu. 1411 1412config ARM_PSCI 1413 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1414 depends on HAVE_ARM_SMCCC 1415 select ARM_PSCI_FW 1416 help 1417 Say Y here if you want Linux to communicate with system firmware 1418 implementing the PSCI specification for CPU-centric power 1419 management operations described in ARM document number ARM DEN 1420 0022A ("Power State Coordination Interface System Software on 1421 ARM processors"). 1422 1423# The GPIO number here must be sorted by descending number. In case of 1424# a multiplatform kernel, we just want the highest value required by the 1425# selected platforms. 1426config ARCH_NR_GPIO 1427 int 1428 default 2048 if ARCH_SOCFPGA 1429 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1430 ARCH_ZYNQ 1431 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1432 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1433 default 416 if ARCH_SUNXI 1434 default 392 if ARCH_U8500 1435 default 352 if ARCH_VT8500 1436 default 288 if ARCH_ROCKCHIP 1437 default 264 if MACH_H4700 1438 default 0 1439 help 1440 Maximum number of GPIOs in the system. 1441 1442 If unsure, leave the default value. 1443 1444config HZ_FIXED 1445 int 1446 default 200 if ARCH_EBSA110 1447 default 128 if SOC_AT91RM9200 1448 default 0 1449 1450choice 1451 depends on HZ_FIXED = 0 1452 prompt "Timer frequency" 1453 1454config HZ_100 1455 bool "100 Hz" 1456 1457config HZ_200 1458 bool "200 Hz" 1459 1460config HZ_250 1461 bool "250 Hz" 1462 1463config HZ_300 1464 bool "300 Hz" 1465 1466config HZ_500 1467 bool "500 Hz" 1468 1469config HZ_1000 1470 bool "1000 Hz" 1471 1472endchoice 1473 1474config HZ 1475 int 1476 default HZ_FIXED if HZ_FIXED != 0 1477 default 100 if HZ_100 1478 default 200 if HZ_200 1479 default 250 if HZ_250 1480 default 300 if HZ_300 1481 default 500 if HZ_500 1482 default 1000 1483 1484config SCHED_HRTICK 1485 def_bool HIGH_RES_TIMERS 1486 1487config THUMB2_KERNEL 1488 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1489 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1490 default y if CPU_THUMBONLY 1491 select ARM_UNWIND 1492 help 1493 By enabling this option, the kernel will be compiled in 1494 Thumb-2 mode. 1495 1496 If unsure, say N. 1497 1498config THUMB2_AVOID_R_ARM_THM_JUMP11 1499 bool "Work around buggy Thumb-2 short branch relocations in gas" 1500 depends on THUMB2_KERNEL && MODULES 1501 default y 1502 help 1503 Various binutils versions can resolve Thumb-2 branches to 1504 locally-defined, preemptible global symbols as short-range "b.n" 1505 branch instructions. 1506 1507 This is a problem, because there's no guarantee the final 1508 destination of the symbol, or any candidate locations for a 1509 trampoline, are within range of the branch. For this reason, the 1510 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1511 relocation in modules at all, and it makes little sense to add 1512 support. 1513 1514 The symptom is that the kernel fails with an "unsupported 1515 relocation" error when loading some modules. 1516 1517 Until fixed tools are available, passing 1518 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1519 code which hits this problem, at the cost of a bit of extra runtime 1520 stack usage in some cases. 1521 1522 The problem is described in more detail at: 1523 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1524 1525 Only Thumb-2 kernels are affected. 1526 1527 Unless you are sure your tools don't have this problem, say Y. 1528 1529config ARM_PATCH_IDIV 1530 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1531 depends on CPU_32v7 && !XIP_KERNEL 1532 default y 1533 help 1534 The ARM compiler inserts calls to __aeabi_idiv() and 1535 __aeabi_uidiv() when it needs to perform division on signed 1536 and unsigned integers. Some v7 CPUs have support for the sdiv 1537 and udiv instructions that can be used to implement those 1538 functions. 1539 1540 Enabling this option allows the kernel to modify itself to 1541 replace the first two instructions of these library functions 1542 with the sdiv or udiv plus "bx lr" instructions when the CPU 1543 it is running on supports them. Typically this will be faster 1544 and less power intensive than running the original library 1545 code to do integer division. 1546 1547config AEABI 1548 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1549 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1550 help 1551 This option allows for the kernel to be compiled using the latest 1552 ARM ABI (aka EABI). This is only useful if you are using a user 1553 space environment that is also compiled with EABI. 1554 1555 Since there are major incompatibilities between the legacy ABI and 1556 EABI, especially with regard to structure member alignment, this 1557 option also changes the kernel syscall calling convention to 1558 disambiguate both ABIs and allow for backward compatibility support 1559 (selected with CONFIG_OABI_COMPAT). 1560 1561 To use this you need GCC version 4.0.0 or later. 1562 1563config OABI_COMPAT 1564 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1565 depends on AEABI && !THUMB2_KERNEL 1566 help 1567 This option preserves the old syscall interface along with the 1568 new (ARM EABI) one. It also provides a compatibility layer to 1569 intercept syscalls that have structure arguments which layout 1570 in memory differs between the legacy ABI and the new ARM EABI 1571 (only for non "thumb" binaries). This option adds a tiny 1572 overhead to all syscalls and produces a slightly larger kernel. 1573 1574 The seccomp filter system will not be available when this is 1575 selected, since there is no way yet to sensibly distinguish 1576 between calling conventions during filtering. 1577 1578 If you know you'll be using only pure EABI user space then you 1579 can say N here. If this option is not selected and you attempt 1580 to execute a legacy ABI binary then the result will be 1581 UNPREDICTABLE (in fact it can be predicted that it won't work 1582 at all). If in doubt say N. 1583 1584config ARCH_HAS_HOLES_MEMORYMODEL 1585 bool 1586 1587config ARCH_SPARSEMEM_ENABLE 1588 bool 1589 1590config ARCH_SPARSEMEM_DEFAULT 1591 def_bool ARCH_SPARSEMEM_ENABLE 1592 1593config ARCH_SELECT_MEMORY_MODEL 1594 def_bool ARCH_SPARSEMEM_ENABLE 1595 1596config HAVE_ARCH_PFN_VALID 1597 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1598 1599config HAVE_GENERIC_GUP 1600 def_bool y 1601 depends on ARM_LPAE 1602 1603config HIGHMEM 1604 bool "High Memory Support" 1605 depends on MMU 1606 help 1607 The address space of ARM processors is only 4 Gigabytes large 1608 and it has to accommodate user address space, kernel address 1609 space as well as some memory mapped IO. That means that, if you 1610 have a large amount of physical memory and/or IO, not all of the 1611 memory can be "permanently mapped" by the kernel. The physical 1612 memory that is not permanently mapped is called "high memory". 1613 1614 Depending on the selected kernel/user memory split, minimum 1615 vmalloc space and actual amount of RAM, you may not need this 1616 option which should result in a slightly faster kernel. 1617 1618 If unsure, say n. 1619 1620config HIGHPTE 1621 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1622 depends on HIGHMEM 1623 default y 1624 help 1625 The VM uses one page of physical memory for each page table. 1626 For systems with a lot of processes, this can use a lot of 1627 precious low memory, eventually leading to low memory being 1628 consumed by page tables. Setting this option will allow 1629 user-space 2nd level page tables to reside in high memory. 1630 1631config CPU_SW_DOMAIN_PAN 1632 bool "Enable use of CPU domains to implement privileged no-access" 1633 depends on MMU && !ARM_LPAE 1634 default y 1635 help 1636 Increase kernel security by ensuring that normal kernel accesses 1637 are unable to access userspace addresses. This can help prevent 1638 use-after-free bugs becoming an exploitable privilege escalation 1639 by ensuring that magic values (such as LIST_POISON) will always 1640 fault when dereferenced. 1641 1642 CPUs with low-vector mappings use a best-efforts implementation. 1643 Their lower 1MB needs to remain accessible for the vectors, but 1644 the remainder of userspace will become appropriately inaccessible. 1645 1646config HW_PERF_EVENTS 1647 def_bool y 1648 depends on ARM_PMU 1649 1650config SYS_SUPPORTS_HUGETLBFS 1651 def_bool y 1652 depends on ARM_LPAE 1653 1654config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1655 def_bool y 1656 depends on ARM_LPAE 1657 1658config ARCH_WANT_GENERAL_HUGETLB 1659 def_bool y 1660 1661config ARM_MODULE_PLTS 1662 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1663 depends on MODULES 1664 default y 1665 help 1666 Allocate PLTs when loading modules so that jumps and calls whose 1667 targets are too far away for their relative offsets to be encoded 1668 in the instructions themselves can be bounced via veneers in the 1669 module's PLT. This allows modules to be allocated in the generic 1670 vmalloc area after the dedicated module memory area has been 1671 exhausted. The modules will use slightly more memory, but after 1672 rounding up to page size, the actual memory footprint is usually 1673 the same. 1674 1675 Disabling this is usually safe for small single-platform 1676 configurations. If unsure, say y. 1677 1678config FORCE_MAX_ZONEORDER 1679 int "Maximum zone order" 1680 default "12" if SOC_AM33XX 1681 default "9" if SA1111 || ARCH_EFM32 1682 default "11" 1683 help 1684 The kernel memory allocator divides physically contiguous memory 1685 blocks into "zones", where each zone is a power of two number of 1686 pages. This option selects the largest power of two that the kernel 1687 keeps in the memory allocator. If you need to allocate very large 1688 blocks of physically contiguous memory, then you may need to 1689 increase this value. 1690 1691 This config option is actually maximum order plus one. For example, 1692 a value of 11 means that the largest free memory block is 2^10 pages. 1693 1694config ALIGNMENT_TRAP 1695 bool 1696 depends on CPU_CP15_MMU 1697 default y if !ARCH_EBSA110 1698 select HAVE_PROC_CPU if PROC_FS 1699 help 1700 ARM processors cannot fetch/store information which is not 1701 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1702 address divisible by 4. On 32-bit ARM processors, these non-aligned 1703 fetch/store instructions will be emulated in software if you say 1704 here, which has a severe performance impact. This is necessary for 1705 correct operation of some network protocols. With an IP-only 1706 configuration it is safe to say N, otherwise say Y. 1707 1708config UACCESS_WITH_MEMCPY 1709 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1710 depends on MMU 1711 default y if CPU_FEROCEON 1712 help 1713 Implement faster copy_to_user and clear_user methods for CPU 1714 cores where a 8-word STM instruction give significantly higher 1715 memory write throughput than a sequence of individual 32bit stores. 1716 1717 A possible side effect is a slight increase in scheduling latency 1718 between threads sharing the same address space if they invoke 1719 such copy operations with large buffers. 1720 1721 However, if the CPU data cache is using a write-allocate mode, 1722 this option is unlikely to provide any performance gain. 1723 1724config SECCOMP 1725 bool 1726 prompt "Enable seccomp to safely compute untrusted bytecode" 1727 ---help--- 1728 This kernel feature is useful for number crunching applications 1729 that may need to compute untrusted bytecode during their 1730 execution. By using pipes or other transports made available to 1731 the process as file descriptors supporting the read/write 1732 syscalls, it's possible to isolate those applications in 1733 their own address space using seccomp. Once seccomp is 1734 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1735 and the task is only allowed to execute a few safe syscalls 1736 defined by each seccomp mode. 1737 1738config PARAVIRT 1739 bool "Enable paravirtualization code" 1740 help 1741 This changes the kernel so it can modify itself when it is run 1742 under a hypervisor, potentially improving performance significantly 1743 over full virtualization. 1744 1745config PARAVIRT_TIME_ACCOUNTING 1746 bool "Paravirtual steal time accounting" 1747 select PARAVIRT 1748 help 1749 Select this option to enable fine granularity task steal time 1750 accounting. Time spent executing other tasks in parallel with 1751 the current vCPU is discounted from the vCPU power. To account for 1752 that, there can be a small performance impact. 1753 1754 If in doubt, say N here. 1755 1756config XEN_DOM0 1757 def_bool y 1758 depends on XEN 1759 1760config XEN 1761 bool "Xen guest support on ARM" 1762 depends on ARM && AEABI && OF 1763 depends on CPU_V7 && !CPU_V6 1764 depends on !GENERIC_ATOMIC64 1765 depends on MMU 1766 select ARCH_DMA_ADDR_T_64BIT 1767 select ARM_PSCI 1768 select SWIOTLB 1769 select SWIOTLB_XEN 1770 select PARAVIRT 1771 help 1772 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1773 1774config STACKPROTECTOR_PER_TASK 1775 bool "Use a unique stack canary value for each task" 1776 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1777 select GCC_PLUGIN_ARM_SSP_PER_TASK 1778 default y 1779 help 1780 Due to the fact that GCC uses an ordinary symbol reference from 1781 which to load the value of the stack canary, this value can only 1782 change at reboot time on SMP systems, and all tasks running in the 1783 kernel's address space are forced to use the same canary value for 1784 the entire duration that the system is up. 1785 1786 Enable this option to switch to a different method that uses a 1787 different canary value for each task. 1788 1789endmenu 1790 1791menu "Boot options" 1792 1793config USE_OF 1794 bool "Flattened Device Tree support" 1795 select IRQ_DOMAIN 1796 select OF 1797 help 1798 Include support for flattened device tree machine descriptions. 1799 1800config ATAGS 1801 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1802 default y 1803 help 1804 This is the traditional way of passing data to the kernel at boot 1805 time. If you are solely relying on the flattened device tree (or 1806 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1807 to remove ATAGS support from your kernel binary. If unsure, 1808 leave this to y. 1809 1810config DEPRECATED_PARAM_STRUCT 1811 bool "Provide old way to pass kernel parameters" 1812 depends on ATAGS 1813 help 1814 This was deprecated in 2001 and announced to live on for 5 years. 1815 Some old boot loaders still use this way. 1816 1817# Compressed boot loader in ROM. Yes, we really want to ask about 1818# TEXT and BSS so we preserve their values in the config files. 1819config ZBOOT_ROM_TEXT 1820 hex "Compressed ROM boot loader base address" 1821 default "0" 1822 help 1823 The physical address at which the ROM-able zImage is to be 1824 placed in the target. Platforms which normally make use of 1825 ROM-able zImage formats normally set this to a suitable 1826 value in their defconfig file. 1827 1828 If ZBOOT_ROM is not enabled, this has no effect. 1829 1830config ZBOOT_ROM_BSS 1831 hex "Compressed ROM boot loader BSS address" 1832 default "0" 1833 help 1834 The base address of an area of read/write memory in the target 1835 for the ROM-able zImage which must be available while the 1836 decompressor is running. It must be large enough to hold the 1837 entire decompressed kernel plus an additional 128 KiB. 1838 Platforms which normally make use of ROM-able zImage formats 1839 normally set this to a suitable value in their defconfig file. 1840 1841 If ZBOOT_ROM is not enabled, this has no effect. 1842 1843config ZBOOT_ROM 1844 bool "Compressed boot loader in ROM/flash" 1845 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1846 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1847 help 1848 Say Y here if you intend to execute your compressed kernel image 1849 (zImage) directly from ROM or flash. If unsure, say N. 1850 1851config ARM_APPENDED_DTB 1852 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1853 depends on OF 1854 help 1855 With this option, the boot code will look for a device tree binary 1856 (DTB) appended to zImage 1857 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1858 1859 This is meant as a backward compatibility convenience for those 1860 systems with a bootloader that can't be upgraded to accommodate 1861 the documented boot protocol using a device tree. 1862 1863 Beware that there is very little in terms of protection against 1864 this option being confused by leftover garbage in memory that might 1865 look like a DTB header after a reboot if no actual DTB is appended 1866 to zImage. Do not leave this option active in a production kernel 1867 if you don't intend to always append a DTB. Proper passing of the 1868 location into r2 of a bootloader provided DTB is always preferable 1869 to this option. 1870 1871config ARM_ATAG_DTB_COMPAT 1872 bool "Supplement the appended DTB with traditional ATAG information" 1873 depends on ARM_APPENDED_DTB 1874 help 1875 Some old bootloaders can't be updated to a DTB capable one, yet 1876 they provide ATAGs with memory configuration, the ramdisk address, 1877 the kernel cmdline string, etc. Such information is dynamically 1878 provided by the bootloader and can't always be stored in a static 1879 DTB. To allow a device tree enabled kernel to be used with such 1880 bootloaders, this option allows zImage to extract the information 1881 from the ATAG list and store it at run time into the appended DTB. 1882 1883choice 1884 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1885 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1886 1887config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1888 bool "Use bootloader kernel arguments if available" 1889 help 1890 Uses the command-line options passed by the boot loader instead of 1891 the device tree bootargs property. If the boot loader doesn't provide 1892 any, the device tree bootargs property will be used. 1893 1894config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1895 bool "Extend with bootloader kernel arguments" 1896 help 1897 The command-line arguments provided by the boot loader will be 1898 appended to the the device tree bootargs property. 1899 1900endchoice 1901 1902config CMDLINE 1903 string "Default kernel command string" 1904 default "" 1905 help 1906 On some architectures (EBSA110 and CATS), there is currently no way 1907 for the boot loader to pass arguments to the kernel. For these 1908 architectures, you should supply some command-line options at build 1909 time by entering them here. As a minimum, you should specify the 1910 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1911 1912choice 1913 prompt "Kernel command line type" if CMDLINE != "" 1914 default CMDLINE_FROM_BOOTLOADER 1915 depends on ATAGS 1916 1917config CMDLINE_FROM_BOOTLOADER 1918 bool "Use bootloader kernel arguments if available" 1919 help 1920 Uses the command-line options passed by the boot loader. If 1921 the boot loader doesn't provide any, the default kernel command 1922 string provided in CMDLINE will be used. 1923 1924config CMDLINE_EXTEND 1925 bool "Extend bootloader kernel arguments" 1926 help 1927 The command-line arguments provided by the boot loader will be 1928 appended to the default kernel command string. 1929 1930config CMDLINE_FORCE 1931 bool "Always use the default kernel command string" 1932 help 1933 Always use the default kernel command string, even if the boot 1934 loader passes other arguments to the kernel. 1935 This is useful if you cannot or don't want to change the 1936 command-line options your boot loader passes to the kernel. 1937endchoice 1938 1939config XIP_KERNEL 1940 bool "Kernel Execute-In-Place from ROM" 1941 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1942 help 1943 Execute-In-Place allows the kernel to run from non-volatile storage 1944 directly addressable by the CPU, such as NOR flash. This saves RAM 1945 space since the text section of the kernel is not loaded from flash 1946 to RAM. Read-write sections, such as the data section and stack, 1947 are still copied to RAM. The XIP kernel is not compressed since 1948 it has to run directly from flash, so it will take more space to 1949 store it. The flash address used to link the kernel object files, 1950 and for storing it, is configuration dependent. Therefore, if you 1951 say Y here, you must know the proper physical address where to 1952 store the kernel image depending on your own flash memory usage. 1953 1954 Also note that the make target becomes "make xipImage" rather than 1955 "make zImage" or "make Image". The final kernel binary to put in 1956 ROM memory will be arch/arm/boot/xipImage. 1957 1958 If unsure, say N. 1959 1960config XIP_PHYS_ADDR 1961 hex "XIP Kernel Physical Location" 1962 depends on XIP_KERNEL 1963 default "0x00080000" 1964 help 1965 This is the physical address in your flash memory the kernel will 1966 be linked for and stored to. This address is dependent on your 1967 own flash usage. 1968 1969config XIP_DEFLATED_DATA 1970 bool "Store kernel .data section compressed in ROM" 1971 depends on XIP_KERNEL 1972 select ZLIB_INFLATE 1973 help 1974 Before the kernel is actually executed, its .data section has to be 1975 copied to RAM from ROM. This option allows for storing that data 1976 in compressed form and decompressed to RAM rather than merely being 1977 copied, saving some precious ROM space. A possible drawback is a 1978 slightly longer boot delay. 1979 1980config KEXEC 1981 bool "Kexec system call (EXPERIMENTAL)" 1982 depends on (!SMP || PM_SLEEP_SMP) 1983 depends on !CPU_V7M 1984 select KEXEC_CORE 1985 help 1986 kexec is a system call that implements the ability to shutdown your 1987 current kernel, and to start another kernel. It is like a reboot 1988 but it is independent of the system firmware. And like a reboot 1989 you can start any kernel with it, not just Linux. 1990 1991 It is an ongoing process to be certain the hardware in a machine 1992 is properly shutdown, so do not be surprised if this code does not 1993 initially work for you. 1994 1995config ATAGS_PROC 1996 bool "Export atags in procfs" 1997 depends on ATAGS && KEXEC 1998 default y 1999 help 2000 Should the atags used to boot the kernel be exported in an "atags" 2001 file in procfs. Useful with kexec. 2002 2003config CRASH_DUMP 2004 bool "Build kdump crash kernel (EXPERIMENTAL)" 2005 help 2006 Generate crash dump after being started by kexec. This should 2007 be normally only set in special crash dump kernels which are 2008 loaded in the main kernel with kexec-tools into a specially 2009 reserved region and then later executed after a crash by 2010 kdump/kexec. The crash dump kernel must be compiled to a 2011 memory address not used by the main kernel 2012 2013 For more details see Documentation/kdump/kdump.txt 2014 2015config AUTO_ZRELADDR 2016 bool "Auto calculation of the decompressed kernel image address" 2017 help 2018 ZRELADDR is the physical address where the decompressed kernel 2019 image will be placed. If AUTO_ZRELADDR is selected, the address 2020 will be determined at run-time by masking the current IP with 2021 0xf8000000. This assumes the zImage being placed in the first 128MB 2022 from start of memory. 2023 2024config EFI_STUB 2025 bool 2026 2027config EFI 2028 bool "UEFI runtime support" 2029 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2030 select UCS2_STRING 2031 select EFI_PARAMS_FROM_FDT 2032 select EFI_STUB 2033 select EFI_ARMSTUB 2034 select EFI_RUNTIME_WRAPPERS 2035 ---help--- 2036 This option provides support for runtime services provided 2037 by UEFI firmware (such as non-volatile variables, realtime 2038 clock, and platform reset). A UEFI stub is also provided to 2039 allow the kernel to be booted as an EFI application. This 2040 is only useful for kernels that may run on systems that have 2041 UEFI firmware. 2042 2043config DMI 2044 bool "Enable support for SMBIOS (DMI) tables" 2045 depends on EFI 2046 default y 2047 help 2048 This enables SMBIOS/DMI feature for systems. 2049 2050 This option is only useful on systems that have UEFI firmware. 2051 However, even with this option, the resultant kernel should 2052 continue to boot on existing non-UEFI platforms. 2053 2054 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2055 i.e., the the practice of identifying the platform via DMI to 2056 decide whether certain workarounds for buggy hardware and/or 2057 firmware need to be enabled. This would require the DMI subsystem 2058 to be enabled much earlier than we do on ARM, which is non-trivial. 2059 2060endmenu 2061 2062menu "CPU Power Management" 2063 2064source "drivers/cpufreq/Kconfig" 2065 2066source "drivers/cpuidle/Kconfig" 2067 2068endmenu 2069 2070menu "Floating point emulation" 2071 2072comment "At least one emulation must be selected" 2073 2074config FPE_NWFPE 2075 bool "NWFPE math emulation" 2076 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2077 ---help--- 2078 Say Y to include the NWFPE floating point emulator in the kernel. 2079 This is necessary to run most binaries. Linux does not currently 2080 support floating point hardware so you need to say Y here even if 2081 your machine has an FPA or floating point co-processor podule. 2082 2083 You may say N here if you are going to load the Acorn FPEmulator 2084 early in the bootup. 2085 2086config FPE_NWFPE_XP 2087 bool "Support extended precision" 2088 depends on FPE_NWFPE 2089 help 2090 Say Y to include 80-bit support in the kernel floating-point 2091 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2092 Note that gcc does not generate 80-bit operations by default, 2093 so in most cases this option only enlarges the size of the 2094 floating point emulator without any good reason. 2095 2096 You almost surely want to say N here. 2097 2098config FPE_FASTFPE 2099 bool "FastFPE math emulation (EXPERIMENTAL)" 2100 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2101 ---help--- 2102 Say Y here to include the FAST floating point emulator in the kernel. 2103 This is an experimental much faster emulator which now also has full 2104 precision for the mantissa. It does not support any exceptions. 2105 It is very simple, and approximately 3-6 times faster than NWFPE. 2106 2107 It should be sufficient for most programs. It may be not suitable 2108 for scientific calculations, but you have to check this for yourself. 2109 If you do not feel you need a faster FP emulation you should better 2110 choose NWFPE. 2111 2112config VFP 2113 bool "VFP-format floating point maths" 2114 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2115 help 2116 Say Y to include VFP support code in the kernel. This is needed 2117 if your hardware includes a VFP unit. 2118 2119 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2120 release notes and additional status information. 2121 2122 Say N if your target does not have VFP hardware. 2123 2124config VFPv3 2125 bool 2126 depends on VFP 2127 default y if CPU_V7 2128 2129config NEON 2130 bool "Advanced SIMD (NEON) Extension support" 2131 depends on VFPv3 && CPU_V7 2132 help 2133 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2134 Extension. 2135 2136config KERNEL_MODE_NEON 2137 bool "Support for NEON in kernel mode" 2138 depends on NEON && AEABI 2139 help 2140 Say Y to include support for NEON in kernel mode. 2141 2142endmenu 2143 2144menu "Power management options" 2145 2146source "kernel/power/Kconfig" 2147 2148config ARCH_SUSPEND_POSSIBLE 2149 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2150 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2151 def_bool y 2152 2153config ARM_CPU_SUSPEND 2154 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2155 depends on ARCH_SUSPEND_POSSIBLE 2156 2157config ARCH_HIBERNATION_POSSIBLE 2158 bool 2159 depends on MMU 2160 default y if ARCH_SUSPEND_POSSIBLE 2161 2162endmenu 2163 2164source "drivers/firmware/Kconfig" 2165 2166if CRYPTO 2167source "arch/arm/crypto/Kconfig" 2168endif 2169 2170source "arch/arm/kvm/Kconfig" 2171