1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_USE_MEMTEST 37 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 38 select ARCH_WANT_IPC_PARSE_VERSION 39 select ARCH_WANT_LD_ORPHAN_WARN 40 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 41 select BUILDTIME_TABLE_SORT if MMU 42 select CLONE_BACKWARDS 43 select CPU_PM if SUSPEND || CPU_IDLE 44 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 45 select DMA_DECLARE_COHERENT 46 select DMA_OPS 47 select DMA_REMAP if MMU 48 select EDAC_SUPPORT 49 select EDAC_ATOMIC_SCRUB 50 select GENERIC_ALLOCATOR 51 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 52 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 53 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 54 select GENERIC_IRQ_IPI if SMP 55 select GENERIC_CPU_AUTOPROBE 56 select GENERIC_EARLY_IOREMAP 57 select GENERIC_IDLE_POLL_SETUP 58 select GENERIC_IRQ_PROBE 59 select GENERIC_IRQ_SHOW 60 select GENERIC_IRQ_SHOW_LEVEL 61 select GENERIC_LIB_DEVMEM_IS_ALLOWED 62 select GENERIC_PCI_IOMAP 63 select GENERIC_SCHED_CLOCK 64 select GENERIC_SMP_IDLE_THREAD 65 select GENERIC_STRNCPY_FROM_USER 66 select GENERIC_STRNLEN_USER 67 select HANDLE_DOMAIN_IRQ 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 74 select HAVE_ARCH_MMAP_RND_BITS if MMU 75 select HAVE_ARCH_PFN_VALID 76 select HAVE_ARCH_SECCOMP 77 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 78 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 79 select HAVE_ARCH_TRACEHOOK 80 select HAVE_ARM_SMCCC if CPU_V7 81 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 82 select HAVE_CONTEXT_TRACKING 83 select HAVE_C_RECORDMCOUNT 84 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 85 select HAVE_DMA_CONTIGUOUS if MMU 86 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 87 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 88 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 89 select HAVE_EXIT_THREAD 90 select HAVE_FAST_GUP if ARM_LPAE 91 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 92 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 93 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 94 select HAVE_GCC_PLUGINS 95 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 96 select HAVE_IDE if PCI || ISA || PCMCIA 97 select HAVE_IRQ_TIME_ACCOUNTING 98 select HAVE_KERNEL_GZIP 99 select HAVE_KERNEL_LZ4 100 select HAVE_KERNEL_LZMA 101 select HAVE_KERNEL_LZO 102 select HAVE_KERNEL_XZ 103 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 104 select HAVE_KRETPROBES if HAVE_KPROBES 105 select HAVE_MOD_ARCH_SPECIFIC 106 select HAVE_NMI 107 select HAVE_OPTPROBES if !THUMB2_KERNEL 108 select HAVE_PERF_EVENTS 109 select HAVE_PERF_REGS 110 select HAVE_PERF_USER_STACK_DUMP 111 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 112 select HAVE_REGS_AND_STACK_ACCESS_API 113 select HAVE_RSEQ 114 select HAVE_STACKPROTECTOR 115 select HAVE_SYSCALL_TRACEPOINTS 116 select HAVE_UID16 117 select HAVE_VIRT_CPU_ACCOUNTING_GEN 118 select IRQ_FORCED_THREADING 119 select MODULES_USE_ELF_REL 120 select NEED_DMA_MAP_STATE 121 select OF_EARLY_FLATTREE if OF 122 select OLD_SIGACTION 123 select OLD_SIGSUSPEND3 124 select PCI_SYSCALL if PCI 125 select PERF_USE_VMALLOC 126 select RTC_LIB 127 select SET_FS 128 select SYS_SUPPORTS_APM_EMULATION 129 # Above selects are sorted alphabetically; please add new ones 130 # according to that. Thanks. 131 help 132 The ARM series is a line of low-power-consumption RISC chip designs 133 licensed by ARM Ltd and targeted at embedded applications and 134 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 135 manufactured, but legacy ARM-based PC hardware remains popular in 136 Europe. There is an ARM Linux project with a web page at 137 <http://www.arm.linux.org.uk/>. 138 139config ARM_HAS_SG_CHAIN 140 bool 141 142config ARM_DMA_USE_IOMMU 143 bool 144 select ARM_HAS_SG_CHAIN 145 select NEED_SG_DMA_LENGTH 146 147if ARM_DMA_USE_IOMMU 148 149config ARM_DMA_IOMMU_ALIGNMENT 150 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 151 range 4 9 152 default 8 153 help 154 DMA mapping framework by default aligns all buffers to the smallest 155 PAGE_SIZE order which is greater than or equal to the requested buffer 156 size. This works well for buffers up to a few hundreds kilobytes, but 157 for larger buffers it just a waste of address space. Drivers which has 158 relatively small addressing window (like 64Mib) might run out of 159 virtual space with just a few allocations. 160 161 With this parameter you can specify the maximum PAGE_SIZE order for 162 DMA IOMMU buffers. Larger buffers will be aligned only to this 163 specified order. The order is expressed as a power of two multiplied 164 by the PAGE_SIZE. 165 166endif 167 168config SYS_SUPPORTS_APM_EMULATION 169 bool 170 171config HAVE_TCM 172 bool 173 select GENERIC_ALLOCATOR 174 175config HAVE_PROC_CPU 176 bool 177 178config NO_IOPORT_MAP 179 bool 180 181config SBUS 182 bool 183 184config STACKTRACE_SUPPORT 185 bool 186 default y 187 188config LOCKDEP_SUPPORT 189 bool 190 default y 191 192config TRACE_IRQFLAGS_SUPPORT 193 bool 194 default !CPU_V7M 195 196config ARCH_HAS_ILOG2_U32 197 bool 198 199config ARCH_HAS_ILOG2_U64 200 bool 201 202config ARCH_HAS_BANDGAP 203 bool 204 205config FIX_EARLYCON_MEM 206 def_bool y if MMU 207 208config GENERIC_HWEIGHT 209 bool 210 default y 211 212config GENERIC_CALIBRATE_DELAY 213 bool 214 default y 215 216config ARCH_MAY_HAVE_PC_FDC 217 bool 218 219config ZONE_DMA 220 bool 221 222config ARCH_SUPPORTS_UPROBES 223 def_bool y 224 225config ARCH_HAS_DMA_SET_COHERENT_MASK 226 bool 227 228config GENERIC_ISA_DMA 229 bool 230 231config FIQ 232 bool 233 234config NEED_RET_TO_USER 235 bool 236 237config ARCH_MTD_XIP 238 bool 239 240config ARM_PATCH_PHYS_VIRT 241 bool "Patch physical to virtual translations at runtime" if EMBEDDED 242 default y 243 depends on !XIP_KERNEL && MMU 244 help 245 Patch phys-to-virt and virt-to-phys translation functions at 246 boot and module load time according to the position of the 247 kernel in system memory. 248 249 This can only be used with non-XIP MMU kernels where the base 250 of physical memory is at a 2 MiB boundary. 251 252 Only disable this option if you know that you do not require 253 this feature (eg, building a kernel for a single machine) and 254 you need to shrink the kernel to the minimal size. 255 256config NEED_MACH_IO_H 257 bool 258 help 259 Select this when mach/io.h is required to provide special 260 definitions for this platform. The need for mach/io.h should 261 be avoided when possible. 262 263config NEED_MACH_MEMORY_H 264 bool 265 help 266 Select this when mach/memory.h is required to provide special 267 definitions for this platform. The need for mach/memory.h should 268 be avoided when possible. 269 270config PHYS_OFFSET 271 hex "Physical address of main memory" if MMU 272 depends on !ARM_PATCH_PHYS_VIRT 273 default DRAM_BASE if !MMU 274 default 0x00000000 if ARCH_FOOTBRIDGE 275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 276 default 0x20000000 if ARCH_S5PV210 277 default 0xc0000000 if ARCH_SA1100 278 help 279 Please provide the physical address corresponding to the 280 location of main memory in your system. 281 282config GENERIC_BUG 283 def_bool y 284 depends on BUG 285 286config PGTABLE_LEVELS 287 int 288 default 3 if ARM_LPAE 289 default 2 290 291menu "System Type" 292 293config MMU 294 bool "MMU-based Paged Memory Management Support" 295 default y 296 help 297 Select if you want MMU-based virtualised addressing space 298 support by paged memory management. If unsure, say 'Y'. 299 300config ARCH_MMAP_RND_BITS_MIN 301 default 8 302 303config ARCH_MMAP_RND_BITS_MAX 304 default 14 if PAGE_OFFSET=0x40000000 305 default 15 if PAGE_OFFSET=0x80000000 306 default 16 307 308# 309# The "ARM system type" choice list is ordered alphabetically by option 310# text. Please add new entries in the option alphabetic order. 311# 312choice 313 prompt "ARM system type" 314 default ARM_SINGLE_ARMV7M if !MMU 315 default ARCH_MULTIPLATFORM if MMU 316 317config ARCH_MULTIPLATFORM 318 bool "Allow multiple platforms to be selected" 319 depends on MMU 320 select ARCH_FLATMEM_ENABLE 321 select ARCH_SPARSEMEM_ENABLE 322 select ARCH_SELECT_MEMORY_MODEL 323 select ARM_HAS_SG_CHAIN 324 select ARM_PATCH_PHYS_VIRT 325 select AUTO_ZRELADDR 326 select TIMER_OF 327 select COMMON_CLK 328 select GENERIC_IRQ_MULTI_HANDLER 329 select HAVE_PCI 330 select PCI_DOMAINS_GENERIC if PCI 331 select SPARSE_IRQ 332 select USE_OF 333 334config ARM_SINGLE_ARMV7M 335 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 336 depends on !MMU 337 select ARM_NVIC 338 select AUTO_ZRELADDR 339 select TIMER_OF 340 select COMMON_CLK 341 select CPU_V7M 342 select NO_IOPORT_MAP 343 select SPARSE_IRQ 344 select USE_OF 345 346config ARCH_EP93XX 347 bool "EP93xx-based" 348 select ARCH_SPARSEMEM_ENABLE 349 select ARM_AMBA 350 imply ARM_PATCH_PHYS_VIRT 351 select ARM_VIC 352 select GENERIC_IRQ_MULTI_HANDLER 353 select AUTO_ZRELADDR 354 select CLKDEV_LOOKUP 355 select CLKSRC_MMIO 356 select CPU_ARM920T 357 select GPIOLIB 358 select HAVE_LEGACY_CLK 359 help 360 This enables support for the Cirrus EP93xx series of CPUs. 361 362config ARCH_FOOTBRIDGE 363 bool "FootBridge" 364 select CPU_SA110 365 select FOOTBRIDGE 366 select HAVE_IDE 367 select NEED_MACH_IO_H if !MMU 368 select NEED_MACH_MEMORY_H 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_IOP32X 374 bool "IOP32x-based" 375 depends on MMU 376 select CPU_XSCALE 377 select GPIO_IOP 378 select GPIOLIB 379 select NEED_RET_TO_USER 380 select FORCE_PCI 381 select PLAT_IOP 382 help 383 Support for Intel's 80219 and IOP32X (XScale) family of 384 processors. 385 386config ARCH_IXP4XX 387 bool "IXP4xx-based" 388 depends on MMU 389 select ARCH_HAS_DMA_SET_COHERENT_MASK 390 select ARCH_SUPPORTS_BIG_ENDIAN 391 select CPU_XSCALE 392 select DMABOUNCE if PCI 393 select GENERIC_IRQ_MULTI_HANDLER 394 select GPIO_IXP4XX 395 select GPIOLIB 396 select HAVE_PCI 397 select IXP4XX_IRQ 398 select IXP4XX_TIMER 399 select NEED_MACH_IO_H 400 select USB_EHCI_BIG_ENDIAN_DESC 401 select USB_EHCI_BIG_ENDIAN_MMIO 402 help 403 Support for Intel's IXP4XX (XScale) family of processors. 404 405config ARCH_DOVE 406 bool "Marvell Dove" 407 select CPU_PJ4 408 select GENERIC_IRQ_MULTI_HANDLER 409 select GPIOLIB 410 select HAVE_PCI 411 select MVEBU_MBUS 412 select PINCTRL 413 select PINCTRL_DOVE 414 select PLAT_ORION_LEGACY 415 select SPARSE_IRQ 416 select PM_GENERIC_DOMAINS if PM 417 help 418 Support for the Marvell Dove SoC 88AP510 419 420config ARCH_PXA 421 bool "PXA2xx/PXA3xx-based" 422 depends on MMU 423 select ARCH_MTD_XIP 424 select ARM_CPU_SUSPEND if PM 425 select AUTO_ZRELADDR 426 select COMMON_CLK 427 select CLKSRC_PXA 428 select CLKSRC_MMIO 429 select TIMER_OF 430 select CPU_XSCALE if !CPU_XSC3 431 select GENERIC_IRQ_MULTI_HANDLER 432 select GPIO_PXA 433 select GPIOLIB 434 select HAVE_IDE 435 select IRQ_DOMAIN 436 select PLAT_PXA 437 select SPARSE_IRQ 438 help 439 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 440 441config ARCH_RPC 442 bool "RiscPC" 443 depends on MMU 444 select ARCH_ACORN 445 select ARCH_MAY_HAVE_PC_FDC 446 select ARCH_SPARSEMEM_ENABLE 447 select ARM_HAS_SG_CHAIN 448 select CPU_SA110 449 select FIQ 450 select HAVE_IDE 451 select HAVE_PATA_PLATFORM 452 select ISA_DMA_API 453 select LEGACY_TIMER_TICK 454 select NEED_MACH_IO_H 455 select NEED_MACH_MEMORY_H 456 select NO_IOPORT_MAP 457 help 458 On the Acorn Risc-PC, Linux can support the internal IDE disk and 459 CD-ROM interface, serial and parallel port, and the floppy drive. 460 461config ARCH_SA1100 462 bool "SA1100-based" 463 select ARCH_MTD_XIP 464 select ARCH_SPARSEMEM_ENABLE 465 select CLKSRC_MMIO 466 select CLKSRC_PXA 467 select TIMER_OF if OF 468 select COMMON_CLK 469 select CPU_FREQ 470 select CPU_SA1100 471 select GENERIC_IRQ_MULTI_HANDLER 472 select GPIOLIB 473 select HAVE_IDE 474 select IRQ_DOMAIN 475 select ISA 476 select NEED_MACH_MEMORY_H 477 select SPARSE_IRQ 478 help 479 Support for StrongARM 11x0 based boards. 480 481config ARCH_S3C24XX 482 bool "Samsung S3C24XX SoCs" 483 select ATAGS 484 select CLKSRC_SAMSUNG_PWM 485 select GPIO_SAMSUNG 486 select GPIOLIB 487 select GENERIC_IRQ_MULTI_HANDLER 488 select HAVE_S3C2410_I2C if I2C 489 select HAVE_S3C_RTC if RTC_CLASS 490 select NEED_MACH_IO_H 491 select S3C2410_WATCHDOG 492 select SAMSUNG_ATAGS 493 select USE_OF 494 select WATCHDOG 495 help 496 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 497 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 498 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 499 Samsung SMDK2410 development board (and derivatives). 500 501config ARCH_OMAP1 502 bool "TI OMAP1" 503 depends on MMU 504 select ARCH_OMAP 505 select CLKDEV_LOOKUP 506 select CLKSRC_MMIO 507 select GENERIC_IRQ_CHIP 508 select GENERIC_IRQ_MULTI_HANDLER 509 select GPIOLIB 510 select HAVE_IDE 511 select HAVE_LEGACY_CLK 512 select IRQ_DOMAIN 513 select NEED_MACH_IO_H if PCCARD 514 select NEED_MACH_MEMORY_H 515 select SPARSE_IRQ 516 help 517 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 518 519endchoice 520 521menu "Multiple platform selection" 522 depends on ARCH_MULTIPLATFORM 523 524comment "CPU Core family selection" 525 526config ARCH_MULTI_V4 527 bool "ARMv4 based platforms (FA526)" 528 depends on !ARCH_MULTI_V6_V7 529 select ARCH_MULTI_V4_V5 530 select CPU_FA526 531 532config ARCH_MULTI_V4T 533 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 534 depends on !ARCH_MULTI_V6_V7 535 select ARCH_MULTI_V4_V5 536 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 537 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 538 CPU_ARM925T || CPU_ARM940T) 539 540config ARCH_MULTI_V5 541 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 542 depends on !ARCH_MULTI_V6_V7 543 select ARCH_MULTI_V4_V5 544 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 545 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 546 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 547 548config ARCH_MULTI_V4_V5 549 bool 550 551config ARCH_MULTI_V6 552 bool "ARMv6 based platforms (ARM11)" 553 select ARCH_MULTI_V6_V7 554 select CPU_V6K 555 556config ARCH_MULTI_V7 557 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 558 default y 559 select ARCH_MULTI_V6_V7 560 select CPU_V7 561 select HAVE_SMP 562 563config ARCH_MULTI_V6_V7 564 bool 565 select MIGHT_HAVE_CACHE_L2X0 566 567config ARCH_MULTI_CPU_AUTO 568 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 569 select ARCH_MULTI_V5 570 571endmenu 572 573config ARCH_VIRT 574 bool "Dummy Virtual Machine" 575 depends on ARCH_MULTI_V7 576 select ARM_AMBA 577 select ARM_GIC 578 select ARM_GIC_V2M if PCI 579 select ARM_GIC_V3 580 select ARM_GIC_V3_ITS if PCI 581 select ARM_PSCI 582 select HAVE_ARM_ARCH_TIMER 583 select ARCH_SUPPORTS_BIG_ENDIAN 584 585# 586# This is sorted alphabetically by mach-* pathname. However, plat-* 587# Kconfigs may be included either alphabetically (according to the 588# plat- suffix) or along side the corresponding mach-* source. 589# 590source "arch/arm/mach-actions/Kconfig" 591 592source "arch/arm/mach-alpine/Kconfig" 593 594source "arch/arm/mach-artpec/Kconfig" 595 596source "arch/arm/mach-asm9260/Kconfig" 597 598source "arch/arm/mach-aspeed/Kconfig" 599 600source "arch/arm/mach-at91/Kconfig" 601 602source "arch/arm/mach-axxia/Kconfig" 603 604source "arch/arm/mach-bcm/Kconfig" 605 606source "arch/arm/mach-berlin/Kconfig" 607 608source "arch/arm/mach-clps711x/Kconfig" 609 610source "arch/arm/mach-cns3xxx/Kconfig" 611 612source "arch/arm/mach-davinci/Kconfig" 613 614source "arch/arm/mach-digicolor/Kconfig" 615 616source "arch/arm/mach-dove/Kconfig" 617 618source "arch/arm/mach-ep93xx/Kconfig" 619 620source "arch/arm/mach-exynos/Kconfig" 621 622source "arch/arm/mach-footbridge/Kconfig" 623 624source "arch/arm/mach-gemini/Kconfig" 625 626source "arch/arm/mach-highbank/Kconfig" 627 628source "arch/arm/mach-hisi/Kconfig" 629 630source "arch/arm/mach-imx/Kconfig" 631 632source "arch/arm/mach-integrator/Kconfig" 633 634source "arch/arm/mach-iop32x/Kconfig" 635 636source "arch/arm/mach-ixp4xx/Kconfig" 637 638source "arch/arm/mach-keystone/Kconfig" 639 640source "arch/arm/mach-lpc32xx/Kconfig" 641 642source "arch/arm/mach-mediatek/Kconfig" 643 644source "arch/arm/mach-meson/Kconfig" 645 646source "arch/arm/mach-milbeaut/Kconfig" 647 648source "arch/arm/mach-mmp/Kconfig" 649 650source "arch/arm/mach-moxart/Kconfig" 651 652source "arch/arm/mach-mstar/Kconfig" 653 654source "arch/arm/mach-mv78xx0/Kconfig" 655 656source "arch/arm/mach-mvebu/Kconfig" 657 658source "arch/arm/mach-mxs/Kconfig" 659 660source "arch/arm/mach-nomadik/Kconfig" 661 662source "arch/arm/mach-npcm/Kconfig" 663 664source "arch/arm/mach-nspire/Kconfig" 665 666source "arch/arm/plat-omap/Kconfig" 667 668source "arch/arm/mach-omap1/Kconfig" 669 670source "arch/arm/mach-omap2/Kconfig" 671 672source "arch/arm/mach-orion5x/Kconfig" 673 674source "arch/arm/mach-oxnas/Kconfig" 675 676source "arch/arm/mach-pxa/Kconfig" 677source "arch/arm/plat-pxa/Kconfig" 678 679source "arch/arm/mach-qcom/Kconfig" 680 681source "arch/arm/mach-rda/Kconfig" 682 683source "arch/arm/mach-realtek/Kconfig" 684 685source "arch/arm/mach-realview/Kconfig" 686 687source "arch/arm/mach-rockchip/Kconfig" 688 689source "arch/arm/mach-s3c/Kconfig" 690 691source "arch/arm/mach-s5pv210/Kconfig" 692 693source "arch/arm/mach-sa1100/Kconfig" 694 695source "arch/arm/mach-shmobile/Kconfig" 696 697source "arch/arm/mach-socfpga/Kconfig" 698 699source "arch/arm/mach-spear/Kconfig" 700 701source "arch/arm/mach-sti/Kconfig" 702 703source "arch/arm/mach-stm32/Kconfig" 704 705source "arch/arm/mach-sunxi/Kconfig" 706 707source "arch/arm/mach-tegra/Kconfig" 708 709source "arch/arm/mach-uniphier/Kconfig" 710 711source "arch/arm/mach-ux500/Kconfig" 712 713source "arch/arm/mach-versatile/Kconfig" 714 715source "arch/arm/mach-vexpress/Kconfig" 716 717source "arch/arm/mach-vt8500/Kconfig" 718 719source "arch/arm/mach-zynq/Kconfig" 720 721# ARMv7-M architecture 722config ARCH_LPC18XX 723 bool "NXP LPC18xx/LPC43xx" 724 depends on ARM_SINGLE_ARMV7M 725 select ARCH_HAS_RESET_CONTROLLER 726 select ARM_AMBA 727 select CLKSRC_LPC32XX 728 select PINCTRL 729 help 730 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 731 high performance microcontrollers. 732 733config ARCH_MPS2 734 bool "ARM MPS2 platform" 735 depends on ARM_SINGLE_ARMV7M 736 select ARM_AMBA 737 select CLKSRC_MPS2 738 help 739 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 740 with a range of available cores like Cortex-M3/M4/M7. 741 742 Please, note that depends which Application Note is used memory map 743 for the platform may vary, so adjustment of RAM base might be needed. 744 745# Definitions to make life easier 746config ARCH_ACORN 747 bool 748 749config PLAT_IOP 750 bool 751 752config PLAT_ORION 753 bool 754 select CLKSRC_MMIO 755 select COMMON_CLK 756 select GENERIC_IRQ_CHIP 757 select IRQ_DOMAIN 758 759config PLAT_ORION_LEGACY 760 bool 761 select PLAT_ORION 762 763config PLAT_PXA 764 bool 765 766config PLAT_VERSATILE 767 bool 768 769source "arch/arm/mm/Kconfig" 770 771config IWMMXT 772 bool "Enable iWMMXt support" 773 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 774 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 775 help 776 Enable support for iWMMXt context switching at run time if 777 running on a CPU that supports it. 778 779if !MMU 780source "arch/arm/Kconfig-nommu" 781endif 782 783config PJ4B_ERRATA_4742 784 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 785 depends on CPU_PJ4B && MACH_ARMADA_370 786 default y 787 help 788 When coming out of either a Wait for Interrupt (WFI) or a Wait for 789 Event (WFE) IDLE states, a specific timing sensitivity exists between 790 the retiring WFI/WFE instructions and the newly issued subsequent 791 instructions. This sensitivity can result in a CPU hang scenario. 792 Workaround: 793 The software must insert either a Data Synchronization Barrier (DSB) 794 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 795 instruction 796 797config ARM_ERRATA_326103 798 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 799 depends on CPU_V6 800 help 801 Executing a SWP instruction to read-only memory does not set bit 11 802 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 803 treat the access as a read, preventing a COW from occurring and 804 causing the faulting task to livelock. 805 806config ARM_ERRATA_411920 807 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 808 depends on CPU_V6 || CPU_V6K 809 help 810 Invalidation of the Instruction Cache operation can 811 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 812 It does not affect the MPCore. This option enables the ARM Ltd. 813 recommended workaround. 814 815config ARM_ERRATA_430973 816 bool "ARM errata: Stale prediction on replaced interworking branch" 817 depends on CPU_V7 818 help 819 This option enables the workaround for the 430973 Cortex-A8 820 r1p* erratum. If a code sequence containing an ARM/Thumb 821 interworking branch is replaced with another code sequence at the 822 same virtual address, whether due to self-modifying code or virtual 823 to physical address re-mapping, Cortex-A8 does not recover from the 824 stale interworking branch prediction. This results in Cortex-A8 825 executing the new code sequence in the incorrect ARM or Thumb state. 826 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 827 and also flushes the branch target cache at every context switch. 828 Note that setting specific bits in the ACTLR register may not be 829 available in non-secure mode. 830 831config ARM_ERRATA_458693 832 bool "ARM errata: Processor deadlock when a false hazard is created" 833 depends on CPU_V7 834 depends on !ARCH_MULTIPLATFORM 835 help 836 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 837 erratum. For very specific sequences of memory operations, it is 838 possible for a hazard condition intended for a cache line to instead 839 be incorrectly associated with a different cache line. This false 840 hazard might then cause a processor deadlock. The workaround enables 841 the L1 caching of the NEON accesses and disables the PLD instruction 842 in the ACTLR register. Note that setting specific bits in the ACTLR 843 register may not be available in non-secure mode. 844 845config ARM_ERRATA_460075 846 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 847 depends on CPU_V7 848 depends on !ARCH_MULTIPLATFORM 849 help 850 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 851 erratum. Any asynchronous access to the L2 cache may encounter a 852 situation in which recent store transactions to the L2 cache are lost 853 and overwritten with stale memory contents from external memory. The 854 workaround disables the write-allocate mode for the L2 cache via the 855 ACTLR register. Note that setting specific bits in the ACTLR register 856 may not be available in non-secure mode. 857 858config ARM_ERRATA_742230 859 bool "ARM errata: DMB operation may be faulty" 860 depends on CPU_V7 && SMP 861 depends on !ARCH_MULTIPLATFORM 862 help 863 This option enables the workaround for the 742230 Cortex-A9 864 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 865 between two write operations may not ensure the correct visibility 866 ordering of the two writes. This workaround sets a specific bit in 867 the diagnostic register of the Cortex-A9 which causes the DMB 868 instruction to behave as a DSB, ensuring the correct behaviour of 869 the two writes. 870 871config ARM_ERRATA_742231 872 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 873 depends on CPU_V7 && SMP 874 depends on !ARCH_MULTIPLATFORM 875 help 876 This option enables the workaround for the 742231 Cortex-A9 877 (r2p0..r2p2) erratum. Under certain conditions, specific to the 878 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 879 accessing some data located in the same cache line, may get corrupted 880 data due to bad handling of the address hazard when the line gets 881 replaced from one of the CPUs at the same time as another CPU is 882 accessing it. This workaround sets specific bits in the diagnostic 883 register of the Cortex-A9 which reduces the linefill issuing 884 capabilities of the processor. 885 886config ARM_ERRATA_643719 887 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 888 depends on CPU_V7 && SMP 889 default y 890 help 891 This option enables the workaround for the 643719 Cortex-A9 (prior to 892 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 893 register returns zero when it should return one. The workaround 894 corrects this value, ensuring cache maintenance operations which use 895 it behave as intended and avoiding data corruption. 896 897config ARM_ERRATA_720789 898 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 899 depends on CPU_V7 900 help 901 This option enables the workaround for the 720789 Cortex-A9 (prior to 902 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 903 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 904 As a consequence of this erratum, some TLB entries which should be 905 invalidated are not, resulting in an incoherency in the system page 906 tables. The workaround changes the TLB flushing routines to invalidate 907 entries regardless of the ASID. 908 909config ARM_ERRATA_743622 910 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 911 depends on CPU_V7 912 depends on !ARCH_MULTIPLATFORM 913 help 914 This option enables the workaround for the 743622 Cortex-A9 915 (r2p*) erratum. Under very rare conditions, a faulty 916 optimisation in the Cortex-A9 Store Buffer may lead to data 917 corruption. This workaround sets a specific bit in the diagnostic 918 register of the Cortex-A9 which disables the Store Buffer 919 optimisation, preventing the defect from occurring. This has no 920 visible impact on the overall performance or power consumption of the 921 processor. 922 923config ARM_ERRATA_751472 924 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 925 depends on CPU_V7 926 depends on !ARCH_MULTIPLATFORM 927 help 928 This option enables the workaround for the 751472 Cortex-A9 (prior 929 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 930 completion of a following broadcasted operation if the second 931 operation is received by a CPU before the ICIALLUIS has completed, 932 potentially leading to corrupted entries in the cache or TLB. 933 934config ARM_ERRATA_754322 935 bool "ARM errata: possible faulty MMU translations following an ASID switch" 936 depends on CPU_V7 937 help 938 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 939 r3p*) erratum. A speculative memory access may cause a page table walk 940 which starts prior to an ASID switch but completes afterwards. This 941 can populate the micro-TLB with a stale entry which may be hit with 942 the new ASID. This workaround places two dsb instructions in the mm 943 switching code so that no page table walks can cross the ASID switch. 944 945config ARM_ERRATA_754327 946 bool "ARM errata: no automatic Store Buffer drain" 947 depends on CPU_V7 && SMP 948 help 949 This option enables the workaround for the 754327 Cortex-A9 (prior to 950 r2p0) erratum. The Store Buffer does not have any automatic draining 951 mechanism and therefore a livelock may occur if an external agent 952 continuously polls a memory location waiting to observe an update. 953 This workaround defines cpu_relax() as smp_mb(), preventing correctly 954 written polling loops from denying visibility of updates to memory. 955 956config ARM_ERRATA_364296 957 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 958 depends on CPU_V6 959 help 960 This options enables the workaround for the 364296 ARM1136 961 r0p2 erratum (possible cache data corruption with 962 hit-under-miss enabled). It sets the undocumented bit 31 in 963 the auxiliary control register and the FI bit in the control 964 register, thus disabling hit-under-miss without putting the 965 processor into full low interrupt latency mode. ARM11MPCore 966 is not affected. 967 968config ARM_ERRATA_764369 969 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 970 depends on CPU_V7 && SMP 971 help 972 This option enables the workaround for erratum 764369 973 affecting Cortex-A9 MPCore with two or more processors (all 974 current revisions). Under certain timing circumstances, a data 975 cache line maintenance operation by MVA targeting an Inner 976 Shareable memory region may fail to proceed up to either the 977 Point of Coherency or to the Point of Unification of the 978 system. This workaround adds a DSB instruction before the 979 relevant cache maintenance functions and sets a specific bit 980 in the diagnostic control register of the SCU. 981 982config ARM_ERRATA_775420 983 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 984 depends on CPU_V7 985 help 986 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 987 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 988 operation aborts with MMU exception, it might cause the processor 989 to deadlock. This workaround puts DSB before executing ISB if 990 an abort may occur on cache maintenance. 991 992config ARM_ERRATA_798181 993 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 994 depends on CPU_V7 && SMP 995 help 996 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 997 adequately shooting down all use of the old entries. This 998 option enables the Linux kernel workaround for this erratum 999 which sends an IPI to the CPUs that are running the same ASID 1000 as the one being invalidated. 1001 1002config ARM_ERRATA_773022 1003 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1004 depends on CPU_V7 1005 help 1006 This option enables the workaround for the 773022 Cortex-A15 1007 (up to r0p4) erratum. In certain rare sequences of code, the 1008 loop buffer may deliver incorrect instructions. This 1009 workaround disables the loop buffer to avoid the erratum. 1010 1011config ARM_ERRATA_818325_852422 1012 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1013 depends on CPU_V7 1014 help 1015 This option enables the workaround for: 1016 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1017 instruction might deadlock. Fixed in r0p1. 1018 - Cortex-A12 852422: Execution of a sequence of instructions might 1019 lead to either a data corruption or a CPU deadlock. Not fixed in 1020 any Cortex-A12 cores yet. 1021 This workaround for all both errata involves setting bit[12] of the 1022 Feature Register. This bit disables an optimisation applied to a 1023 sequence of 2 instructions that use opposing condition codes. 1024 1025config ARM_ERRATA_821420 1026 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1027 depends on CPU_V7 1028 help 1029 This option enables the workaround for the 821420 Cortex-A12 1030 (all revs) erratum. In very rare timing conditions, a sequence 1031 of VMOV to Core registers instructions, for which the second 1032 one is in the shadow of a branch or abort, can lead to a 1033 deadlock when the VMOV instructions are issued out-of-order. 1034 1035config ARM_ERRATA_825619 1036 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1037 depends on CPU_V7 1038 help 1039 This option enables the workaround for the 825619 Cortex-A12 1040 (all revs) erratum. Within rare timing constraints, executing a 1041 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1042 and Device/Strongly-Ordered loads and stores might cause deadlock 1043 1044config ARM_ERRATA_857271 1045 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1046 depends on CPU_V7 1047 help 1048 This option enables the workaround for the 857271 Cortex-A12 1049 (all revs) erratum. Under very rare timing conditions, the CPU might 1050 hang. The workaround is expected to have a < 1% performance impact. 1051 1052config ARM_ERRATA_852421 1053 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1054 depends on CPU_V7 1055 help 1056 This option enables the workaround for the 852421 Cortex-A17 1057 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1058 execution of a DMB ST instruction might fail to properly order 1059 stores from GroupA and stores from GroupB. 1060 1061config ARM_ERRATA_852423 1062 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1063 depends on CPU_V7 1064 help 1065 This option enables the workaround for: 1066 - Cortex-A17 852423: Execution of a sequence of instructions might 1067 lead to either a data corruption or a CPU deadlock. Not fixed in 1068 any Cortex-A17 cores yet. 1069 This is identical to Cortex-A12 erratum 852422. It is a separate 1070 config option from the A12 erratum due to the way errata are checked 1071 for and handled. 1072 1073config ARM_ERRATA_857272 1074 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1075 depends on CPU_V7 1076 help 1077 This option enables the workaround for the 857272 Cortex-A17 erratum. 1078 This erratum is not known to be fixed in any A17 revision. 1079 This is identical to Cortex-A12 erratum 857271. It is a separate 1080 config option from the A12 erratum due to the way errata are checked 1081 for and handled. 1082 1083endmenu 1084 1085source "arch/arm/common/Kconfig" 1086 1087menu "Bus support" 1088 1089config ISA 1090 bool 1091 help 1092 Find out whether you have ISA slots on your motherboard. ISA is the 1093 name of a bus system, i.e. the way the CPU talks to the other stuff 1094 inside your box. Other bus systems are PCI, EISA, MicroChannel 1095 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1096 newer boards don't support it. If you have ISA, say Y, otherwise N. 1097 1098# Select ISA DMA controller support 1099config ISA_DMA 1100 bool 1101 select ISA_DMA_API 1102 1103# Select ISA DMA interface 1104config ISA_DMA_API 1105 bool 1106 1107config PCI_NANOENGINE 1108 bool "BSE nanoEngine PCI support" 1109 depends on SA1100_NANOENGINE 1110 help 1111 Enable PCI on the BSE nanoEngine board. 1112 1113config ARM_ERRATA_814220 1114 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1115 depends on CPU_V7 1116 help 1117 The v7 ARM states that all cache and branch predictor maintenance 1118 operations that do not specify an address execute, relative to 1119 each other, in program order. 1120 However, because of this erratum, an L2 set/way cache maintenance 1121 operation can overtake an L1 set/way cache maintenance operation. 1122 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1123 r0p4, r0p5. 1124 1125endmenu 1126 1127menu "Kernel Features" 1128 1129config HAVE_SMP 1130 bool 1131 help 1132 This option should be selected by machines which have an SMP- 1133 capable CPU. 1134 1135 The only effect of this option is to make the SMP-related 1136 options available to the user for configuration. 1137 1138config SMP 1139 bool "Symmetric Multi-Processing" 1140 depends on CPU_V6K || CPU_V7 1141 depends on HAVE_SMP 1142 depends on MMU || ARM_MPU 1143 select IRQ_WORK 1144 help 1145 This enables support for systems with more than one CPU. If you have 1146 a system with only one CPU, say N. If you have a system with more 1147 than one CPU, say Y. 1148 1149 If you say N here, the kernel will run on uni- and multiprocessor 1150 machines, but will use only one CPU of a multiprocessor machine. If 1151 you say Y here, the kernel will run on many, but not all, 1152 uniprocessor machines. On a uniprocessor machine, the kernel 1153 will run faster if you say N here. 1154 1155 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1156 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1157 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1158 1159 If you don't know what to do here, say N. 1160 1161config SMP_ON_UP 1162 bool "Allow booting SMP kernel on uniprocessor systems" 1163 depends on SMP && !XIP_KERNEL && MMU 1164 default y 1165 help 1166 SMP kernels contain instructions which fail on non-SMP processors. 1167 Enabling this option allows the kernel to modify itself to make 1168 these instructions safe. Disabling it allows about 1K of space 1169 savings. 1170 1171 If you don't know what to do here, say Y. 1172 1173config ARM_CPU_TOPOLOGY 1174 bool "Support cpu topology definition" 1175 depends on SMP && CPU_V7 1176 default y 1177 help 1178 Support ARM cpu topology definition. The MPIDR register defines 1179 affinity between processors which is then used to describe the cpu 1180 topology of an ARM System. 1181 1182config SCHED_MC 1183 bool "Multi-core scheduler support" 1184 depends on ARM_CPU_TOPOLOGY 1185 help 1186 Multi-core scheduler support improves the CPU scheduler's decision 1187 making when dealing with multi-core CPU chips at a cost of slightly 1188 increased overhead in some places. If unsure say N here. 1189 1190config SCHED_SMT 1191 bool "SMT scheduler support" 1192 depends on ARM_CPU_TOPOLOGY 1193 help 1194 Improves the CPU scheduler's decision making when dealing with 1195 MultiThreading at a cost of slightly increased overhead in some 1196 places. If unsure say N here. 1197 1198config HAVE_ARM_SCU 1199 bool 1200 help 1201 This option enables support for the ARM snoop control unit 1202 1203config HAVE_ARM_ARCH_TIMER 1204 bool "Architected timer support" 1205 depends on CPU_V7 1206 select ARM_ARCH_TIMER 1207 help 1208 This option enables support for the ARM architected timer 1209 1210config HAVE_ARM_TWD 1211 bool 1212 help 1213 This options enables support for the ARM timer and watchdog unit 1214 1215config MCPM 1216 bool "Multi-Cluster Power Management" 1217 depends on CPU_V7 && SMP 1218 help 1219 This option provides the common power management infrastructure 1220 for (multi-)cluster based systems, such as big.LITTLE based 1221 systems. 1222 1223config MCPM_QUAD_CLUSTER 1224 bool 1225 depends on MCPM 1226 help 1227 To avoid wasting resources unnecessarily, MCPM only supports up 1228 to 2 clusters by default. 1229 Platforms with 3 or 4 clusters that use MCPM must select this 1230 option to allow the additional clusters to be managed. 1231 1232config BIG_LITTLE 1233 bool "big.LITTLE support (Experimental)" 1234 depends on CPU_V7 && SMP 1235 select MCPM 1236 help 1237 This option enables support selections for the big.LITTLE 1238 system architecture. 1239 1240config BL_SWITCHER 1241 bool "big.LITTLE switcher support" 1242 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1243 select CPU_PM 1244 help 1245 The big.LITTLE "switcher" provides the core functionality to 1246 transparently handle transition between a cluster of A15's 1247 and a cluster of A7's in a big.LITTLE system. 1248 1249config BL_SWITCHER_DUMMY_IF 1250 tristate "Simple big.LITTLE switcher user interface" 1251 depends on BL_SWITCHER && DEBUG_KERNEL 1252 help 1253 This is a simple and dummy char dev interface to control 1254 the big.LITTLE switcher core code. It is meant for 1255 debugging purposes only. 1256 1257choice 1258 prompt "Memory split" 1259 depends on MMU 1260 default VMSPLIT_3G 1261 help 1262 Select the desired split between kernel and user memory. 1263 1264 If you are not absolutely sure what you are doing, leave this 1265 option alone! 1266 1267 config VMSPLIT_3G 1268 bool "3G/1G user/kernel split" 1269 config VMSPLIT_3G_OPT 1270 depends on !ARM_LPAE 1271 bool "3G/1G user/kernel split (for full 1G low memory)" 1272 config VMSPLIT_2G 1273 bool "2G/2G user/kernel split" 1274 config VMSPLIT_1G 1275 bool "1G/3G user/kernel split" 1276endchoice 1277 1278config PAGE_OFFSET 1279 hex 1280 default PHYS_OFFSET if !MMU 1281 default 0x40000000 if VMSPLIT_1G 1282 default 0x80000000 if VMSPLIT_2G 1283 default 0xB0000000 if VMSPLIT_3G_OPT 1284 default 0xC0000000 1285 1286config KASAN_SHADOW_OFFSET 1287 hex 1288 depends on KASAN 1289 default 0x1f000000 if PAGE_OFFSET=0x40000000 1290 default 0x5f000000 if PAGE_OFFSET=0x80000000 1291 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1292 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1293 default 0xffffffff 1294 1295config NR_CPUS 1296 int "Maximum number of CPUs (2-32)" 1297 range 2 16 if DEBUG_KMAP_LOCAL 1298 range 2 32 if !DEBUG_KMAP_LOCAL 1299 depends on SMP 1300 default "4" 1301 help 1302 The maximum number of CPUs that the kernel can support. 1303 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1304 debugging is enabled, which uses half of the per-CPU fixmap 1305 slots as guard regions. 1306 1307config HOTPLUG_CPU 1308 bool "Support for hot-pluggable CPUs" 1309 depends on SMP 1310 select GENERIC_IRQ_MIGRATION 1311 help 1312 Say Y here to experiment with turning CPUs off and on. CPUs 1313 can be controlled through /sys/devices/system/cpu. 1314 1315config ARM_PSCI 1316 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1317 depends on HAVE_ARM_SMCCC 1318 select ARM_PSCI_FW 1319 help 1320 Say Y here if you want Linux to communicate with system firmware 1321 implementing the PSCI specification for CPU-centric power 1322 management operations described in ARM document number ARM DEN 1323 0022A ("Power State Coordination Interface System Software on 1324 ARM processors"). 1325 1326# The GPIO number here must be sorted by descending number. In case of 1327# a multiplatform kernel, we just want the highest value required by the 1328# selected platforms. 1329config ARCH_NR_GPIO 1330 int 1331 default 2048 if ARCH_INTEL_SOCFPGA 1332 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1333 ARCH_ZYNQ || ARCH_ASPEED 1334 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1335 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1336 default 416 if ARCH_SUNXI 1337 default 392 if ARCH_U8500 1338 default 352 if ARCH_VT8500 1339 default 288 if ARCH_ROCKCHIP 1340 default 264 if MACH_H4700 1341 default 0 1342 help 1343 Maximum number of GPIOs in the system. 1344 1345 If unsure, leave the default value. 1346 1347config HZ_FIXED 1348 int 1349 default 128 if SOC_AT91RM9200 1350 default 0 1351 1352choice 1353 depends on HZ_FIXED = 0 1354 prompt "Timer frequency" 1355 1356config HZ_100 1357 bool "100 Hz" 1358 1359config HZ_200 1360 bool "200 Hz" 1361 1362config HZ_250 1363 bool "250 Hz" 1364 1365config HZ_300 1366 bool "300 Hz" 1367 1368config HZ_500 1369 bool "500 Hz" 1370 1371config HZ_1000 1372 bool "1000 Hz" 1373 1374endchoice 1375 1376config HZ 1377 int 1378 default HZ_FIXED if HZ_FIXED != 0 1379 default 100 if HZ_100 1380 default 200 if HZ_200 1381 default 250 if HZ_250 1382 default 300 if HZ_300 1383 default 500 if HZ_500 1384 default 1000 1385 1386config SCHED_HRTICK 1387 def_bool HIGH_RES_TIMERS 1388 1389config THUMB2_KERNEL 1390 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1391 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1392 default y if CPU_THUMBONLY 1393 select ARM_UNWIND 1394 help 1395 By enabling this option, the kernel will be compiled in 1396 Thumb-2 mode. 1397 1398 If unsure, say N. 1399 1400config ARM_PATCH_IDIV 1401 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1402 depends on CPU_32v7 && !XIP_KERNEL 1403 default y 1404 help 1405 The ARM compiler inserts calls to __aeabi_idiv() and 1406 __aeabi_uidiv() when it needs to perform division on signed 1407 and unsigned integers. Some v7 CPUs have support for the sdiv 1408 and udiv instructions that can be used to implement those 1409 functions. 1410 1411 Enabling this option allows the kernel to modify itself to 1412 replace the first two instructions of these library functions 1413 with the sdiv or udiv plus "bx lr" instructions when the CPU 1414 it is running on supports them. Typically this will be faster 1415 and less power intensive than running the original library 1416 code to do integer division. 1417 1418config AEABI 1419 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1420 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1421 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1422 help 1423 This option allows for the kernel to be compiled using the latest 1424 ARM ABI (aka EABI). This is only useful if you are using a user 1425 space environment that is also compiled with EABI. 1426 1427 Since there are major incompatibilities between the legacy ABI and 1428 EABI, especially with regard to structure member alignment, this 1429 option also changes the kernel syscall calling convention to 1430 disambiguate both ABIs and allow for backward compatibility support 1431 (selected with CONFIG_OABI_COMPAT). 1432 1433 To use this you need GCC version 4.0.0 or later. 1434 1435config OABI_COMPAT 1436 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1437 depends on AEABI && !THUMB2_KERNEL 1438 help 1439 This option preserves the old syscall interface along with the 1440 new (ARM EABI) one. It also provides a compatibility layer to 1441 intercept syscalls that have structure arguments which layout 1442 in memory differs between the legacy ABI and the new ARM EABI 1443 (only for non "thumb" binaries). This option adds a tiny 1444 overhead to all syscalls and produces a slightly larger kernel. 1445 1446 The seccomp filter system will not be available when this is 1447 selected, since there is no way yet to sensibly distinguish 1448 between calling conventions during filtering. 1449 1450 If you know you'll be using only pure EABI user space then you 1451 can say N here. If this option is not selected and you attempt 1452 to execute a legacy ABI binary then the result will be 1453 UNPREDICTABLE (in fact it can be predicted that it won't work 1454 at all). If in doubt say N. 1455 1456config ARCH_SELECT_MEMORY_MODEL 1457 bool 1458 1459config ARCH_FLATMEM_ENABLE 1460 bool 1461 1462config ARCH_SPARSEMEM_ENABLE 1463 bool 1464 select SPARSEMEM_STATIC if SPARSEMEM 1465 1466config HIGHMEM 1467 bool "High Memory Support" 1468 depends on MMU 1469 select KMAP_LOCAL 1470 help 1471 The address space of ARM processors is only 4 Gigabytes large 1472 and it has to accommodate user address space, kernel address 1473 space as well as some memory mapped IO. That means that, if you 1474 have a large amount of physical memory and/or IO, not all of the 1475 memory can be "permanently mapped" by the kernel. The physical 1476 memory that is not permanently mapped is called "high memory". 1477 1478 Depending on the selected kernel/user memory split, minimum 1479 vmalloc space and actual amount of RAM, you may not need this 1480 option which should result in a slightly faster kernel. 1481 1482 If unsure, say n. 1483 1484config HIGHPTE 1485 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1486 depends on HIGHMEM 1487 default y 1488 help 1489 The VM uses one page of physical memory for each page table. 1490 For systems with a lot of processes, this can use a lot of 1491 precious low memory, eventually leading to low memory being 1492 consumed by page tables. Setting this option will allow 1493 user-space 2nd level page tables to reside in high memory. 1494 1495config CPU_SW_DOMAIN_PAN 1496 bool "Enable use of CPU domains to implement privileged no-access" 1497 depends on MMU && !ARM_LPAE 1498 default y 1499 help 1500 Increase kernel security by ensuring that normal kernel accesses 1501 are unable to access userspace addresses. This can help prevent 1502 use-after-free bugs becoming an exploitable privilege escalation 1503 by ensuring that magic values (such as LIST_POISON) will always 1504 fault when dereferenced. 1505 1506 CPUs with low-vector mappings use a best-efforts implementation. 1507 Their lower 1MB needs to remain accessible for the vectors, but 1508 the remainder of userspace will become appropriately inaccessible. 1509 1510config HW_PERF_EVENTS 1511 def_bool y 1512 depends on ARM_PMU 1513 1514config SYS_SUPPORTS_HUGETLBFS 1515 def_bool y 1516 depends on ARM_LPAE 1517 1518config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1519 def_bool y 1520 depends on ARM_LPAE 1521 1522config ARCH_WANT_GENERAL_HUGETLB 1523 def_bool y 1524 1525config ARM_MODULE_PLTS 1526 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1527 depends on MODULES 1528 default y 1529 help 1530 Allocate PLTs when loading modules so that jumps and calls whose 1531 targets are too far away for their relative offsets to be encoded 1532 in the instructions themselves can be bounced via veneers in the 1533 module's PLT. This allows modules to be allocated in the generic 1534 vmalloc area after the dedicated module memory area has been 1535 exhausted. The modules will use slightly more memory, but after 1536 rounding up to page size, the actual memory footprint is usually 1537 the same. 1538 1539 Disabling this is usually safe for small single-platform 1540 configurations. If unsure, say y. 1541 1542config FORCE_MAX_ZONEORDER 1543 int "Maximum zone order" 1544 default "12" if SOC_AM33XX 1545 default "9" if SA1111 1546 default "11" 1547 help 1548 The kernel memory allocator divides physically contiguous memory 1549 blocks into "zones", where each zone is a power of two number of 1550 pages. This option selects the largest power of two that the kernel 1551 keeps in the memory allocator. If you need to allocate very large 1552 blocks of physically contiguous memory, then you may need to 1553 increase this value. 1554 1555 This config option is actually maximum order plus one. For example, 1556 a value of 11 means that the largest free memory block is 2^10 pages. 1557 1558config ALIGNMENT_TRAP 1559 def_bool CPU_CP15_MMU 1560 select HAVE_PROC_CPU if PROC_FS 1561 help 1562 ARM processors cannot fetch/store information which is not 1563 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1564 address divisible by 4. On 32-bit ARM processors, these non-aligned 1565 fetch/store instructions will be emulated in software if you say 1566 here, which has a severe performance impact. This is necessary for 1567 correct operation of some network protocols. With an IP-only 1568 configuration it is safe to say N, otherwise say Y. 1569 1570config UACCESS_WITH_MEMCPY 1571 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1572 depends on MMU 1573 default y if CPU_FEROCEON 1574 help 1575 Implement faster copy_to_user and clear_user methods for CPU 1576 cores where a 8-word STM instruction give significantly higher 1577 memory write throughput than a sequence of individual 32bit stores. 1578 1579 A possible side effect is a slight increase in scheduling latency 1580 between threads sharing the same address space if they invoke 1581 such copy operations with large buffers. 1582 1583 However, if the CPU data cache is using a write-allocate mode, 1584 this option is unlikely to provide any performance gain. 1585 1586config PARAVIRT 1587 bool "Enable paravirtualization code" 1588 help 1589 This changes the kernel so it can modify itself when it is run 1590 under a hypervisor, potentially improving performance significantly 1591 over full virtualization. 1592 1593config PARAVIRT_TIME_ACCOUNTING 1594 bool "Paravirtual steal time accounting" 1595 select PARAVIRT 1596 help 1597 Select this option to enable fine granularity task steal time 1598 accounting. Time spent executing other tasks in parallel with 1599 the current vCPU is discounted from the vCPU power. To account for 1600 that, there can be a small performance impact. 1601 1602 If in doubt, say N here. 1603 1604config XEN_DOM0 1605 def_bool y 1606 depends on XEN 1607 1608config XEN 1609 bool "Xen guest support on ARM" 1610 depends on ARM && AEABI && OF 1611 depends on CPU_V7 && !CPU_V6 1612 depends on !GENERIC_ATOMIC64 1613 depends on MMU 1614 select ARCH_DMA_ADDR_T_64BIT 1615 select ARM_PSCI 1616 select SWIOTLB 1617 select SWIOTLB_XEN 1618 select PARAVIRT 1619 help 1620 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1621 1622config STACKPROTECTOR_PER_TASK 1623 bool "Use a unique stack canary value for each task" 1624 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1625 select GCC_PLUGIN_ARM_SSP_PER_TASK 1626 default y 1627 help 1628 Due to the fact that GCC uses an ordinary symbol reference from 1629 which to load the value of the stack canary, this value can only 1630 change at reboot time on SMP systems, and all tasks running in the 1631 kernel's address space are forced to use the same canary value for 1632 the entire duration that the system is up. 1633 1634 Enable this option to switch to a different method that uses a 1635 different canary value for each task. 1636 1637endmenu 1638 1639menu "Boot options" 1640 1641config USE_OF 1642 bool "Flattened Device Tree support" 1643 select IRQ_DOMAIN 1644 select OF 1645 help 1646 Include support for flattened device tree machine descriptions. 1647 1648config ATAGS 1649 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1650 default y 1651 help 1652 This is the traditional way of passing data to the kernel at boot 1653 time. If you are solely relying on the flattened device tree (or 1654 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1655 to remove ATAGS support from your kernel binary. If unsure, 1656 leave this to y. 1657 1658config DEPRECATED_PARAM_STRUCT 1659 bool "Provide old way to pass kernel parameters" 1660 depends on ATAGS 1661 help 1662 This was deprecated in 2001 and announced to live on for 5 years. 1663 Some old boot loaders still use this way. 1664 1665# Compressed boot loader in ROM. Yes, we really want to ask about 1666# TEXT and BSS so we preserve their values in the config files. 1667config ZBOOT_ROM_TEXT 1668 hex "Compressed ROM boot loader base address" 1669 default 0x0 1670 help 1671 The physical address at which the ROM-able zImage is to be 1672 placed in the target. Platforms which normally make use of 1673 ROM-able zImage formats normally set this to a suitable 1674 value in their defconfig file. 1675 1676 If ZBOOT_ROM is not enabled, this has no effect. 1677 1678config ZBOOT_ROM_BSS 1679 hex "Compressed ROM boot loader BSS address" 1680 default 0x0 1681 help 1682 The base address of an area of read/write memory in the target 1683 for the ROM-able zImage which must be available while the 1684 decompressor is running. It must be large enough to hold the 1685 entire decompressed kernel plus an additional 128 KiB. 1686 Platforms which normally make use of ROM-able zImage formats 1687 normally set this to a suitable value in their defconfig file. 1688 1689 If ZBOOT_ROM is not enabled, this has no effect. 1690 1691config ZBOOT_ROM 1692 bool "Compressed boot loader in ROM/flash" 1693 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1694 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1695 help 1696 Say Y here if you intend to execute your compressed kernel image 1697 (zImage) directly from ROM or flash. If unsure, say N. 1698 1699config ARM_APPENDED_DTB 1700 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1701 depends on OF 1702 help 1703 With this option, the boot code will look for a device tree binary 1704 (DTB) appended to zImage 1705 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1706 1707 This is meant as a backward compatibility convenience for those 1708 systems with a bootloader that can't be upgraded to accommodate 1709 the documented boot protocol using a device tree. 1710 1711 Beware that there is very little in terms of protection against 1712 this option being confused by leftover garbage in memory that might 1713 look like a DTB header after a reboot if no actual DTB is appended 1714 to zImage. Do not leave this option active in a production kernel 1715 if you don't intend to always append a DTB. Proper passing of the 1716 location into r2 of a bootloader provided DTB is always preferable 1717 to this option. 1718 1719config ARM_ATAG_DTB_COMPAT 1720 bool "Supplement the appended DTB with traditional ATAG information" 1721 depends on ARM_APPENDED_DTB 1722 help 1723 Some old bootloaders can't be updated to a DTB capable one, yet 1724 they provide ATAGs with memory configuration, the ramdisk address, 1725 the kernel cmdline string, etc. Such information is dynamically 1726 provided by the bootloader and can't always be stored in a static 1727 DTB. To allow a device tree enabled kernel to be used with such 1728 bootloaders, this option allows zImage to extract the information 1729 from the ATAG list and store it at run time into the appended DTB. 1730 1731choice 1732 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1733 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1734 1735config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1736 bool "Use bootloader kernel arguments if available" 1737 help 1738 Uses the command-line options passed by the boot loader instead of 1739 the device tree bootargs property. If the boot loader doesn't provide 1740 any, the device tree bootargs property will be used. 1741 1742config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1743 bool "Extend with bootloader kernel arguments" 1744 help 1745 The command-line arguments provided by the boot loader will be 1746 appended to the the device tree bootargs property. 1747 1748endchoice 1749 1750config CMDLINE 1751 string "Default kernel command string" 1752 default "" 1753 help 1754 On some architectures (e.g. CATS), there is currently no way 1755 for the boot loader to pass arguments to the kernel. For these 1756 architectures, you should supply some command-line options at build 1757 time by entering them here. As a minimum, you should specify the 1758 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1759 1760choice 1761 prompt "Kernel command line type" if CMDLINE != "" 1762 default CMDLINE_FROM_BOOTLOADER 1763 depends on ATAGS 1764 1765config CMDLINE_FROM_BOOTLOADER 1766 bool "Use bootloader kernel arguments if available" 1767 help 1768 Uses the command-line options passed by the boot loader. If 1769 the boot loader doesn't provide any, the default kernel command 1770 string provided in CMDLINE will be used. 1771 1772config CMDLINE_EXTEND 1773 bool "Extend bootloader kernel arguments" 1774 help 1775 The command-line arguments provided by the boot loader will be 1776 appended to the default kernel command string. 1777 1778config CMDLINE_FORCE 1779 bool "Always use the default kernel command string" 1780 help 1781 Always use the default kernel command string, even if the boot 1782 loader passes other arguments to the kernel. 1783 This is useful if you cannot or don't want to change the 1784 command-line options your boot loader passes to the kernel. 1785endchoice 1786 1787config XIP_KERNEL 1788 bool "Kernel Execute-In-Place from ROM" 1789 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1790 help 1791 Execute-In-Place allows the kernel to run from non-volatile storage 1792 directly addressable by the CPU, such as NOR flash. This saves RAM 1793 space since the text section of the kernel is not loaded from flash 1794 to RAM. Read-write sections, such as the data section and stack, 1795 are still copied to RAM. The XIP kernel is not compressed since 1796 it has to run directly from flash, so it will take more space to 1797 store it. The flash address used to link the kernel object files, 1798 and for storing it, is configuration dependent. Therefore, if you 1799 say Y here, you must know the proper physical address where to 1800 store the kernel image depending on your own flash memory usage. 1801 1802 Also note that the make target becomes "make xipImage" rather than 1803 "make zImage" or "make Image". The final kernel binary to put in 1804 ROM memory will be arch/arm/boot/xipImage. 1805 1806 If unsure, say N. 1807 1808config XIP_PHYS_ADDR 1809 hex "XIP Kernel Physical Location" 1810 depends on XIP_KERNEL 1811 default "0x00080000" 1812 help 1813 This is the physical address in your flash memory the kernel will 1814 be linked for and stored to. This address is dependent on your 1815 own flash usage. 1816 1817config XIP_DEFLATED_DATA 1818 bool "Store kernel .data section compressed in ROM" 1819 depends on XIP_KERNEL 1820 select ZLIB_INFLATE 1821 help 1822 Before the kernel is actually executed, its .data section has to be 1823 copied to RAM from ROM. This option allows for storing that data 1824 in compressed form and decompressed to RAM rather than merely being 1825 copied, saving some precious ROM space. A possible drawback is a 1826 slightly longer boot delay. 1827 1828config KEXEC 1829 bool "Kexec system call (EXPERIMENTAL)" 1830 depends on (!SMP || PM_SLEEP_SMP) 1831 depends on MMU 1832 select KEXEC_CORE 1833 help 1834 kexec is a system call that implements the ability to shutdown your 1835 current kernel, and to start another kernel. It is like a reboot 1836 but it is independent of the system firmware. And like a reboot 1837 you can start any kernel with it, not just Linux. 1838 1839 It is an ongoing process to be certain the hardware in a machine 1840 is properly shutdown, so do not be surprised if this code does not 1841 initially work for you. 1842 1843config ATAGS_PROC 1844 bool "Export atags in procfs" 1845 depends on ATAGS && KEXEC 1846 default y 1847 help 1848 Should the atags used to boot the kernel be exported in an "atags" 1849 file in procfs. Useful with kexec. 1850 1851config CRASH_DUMP 1852 bool "Build kdump crash kernel (EXPERIMENTAL)" 1853 help 1854 Generate crash dump after being started by kexec. This should 1855 be normally only set in special crash dump kernels which are 1856 loaded in the main kernel with kexec-tools into a specially 1857 reserved region and then later executed after a crash by 1858 kdump/kexec. The crash dump kernel must be compiled to a 1859 memory address not used by the main kernel 1860 1861 For more details see Documentation/admin-guide/kdump/kdump.rst 1862 1863config AUTO_ZRELADDR 1864 bool "Auto calculation of the decompressed kernel image address" 1865 help 1866 ZRELADDR is the physical address where the decompressed kernel 1867 image will be placed. If AUTO_ZRELADDR is selected, the address 1868 will be determined at run-time, either by masking the current IP 1869 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1870 This assumes the zImage being placed in the first 128MB from 1871 start of memory. 1872 1873config EFI_STUB 1874 bool 1875 1876config EFI 1877 bool "UEFI runtime support" 1878 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1879 select UCS2_STRING 1880 select EFI_PARAMS_FROM_FDT 1881 select EFI_STUB 1882 select EFI_GENERIC_STUB 1883 select EFI_RUNTIME_WRAPPERS 1884 help 1885 This option provides support for runtime services provided 1886 by UEFI firmware (such as non-volatile variables, realtime 1887 clock, and platform reset). A UEFI stub is also provided to 1888 allow the kernel to be booted as an EFI application. This 1889 is only useful for kernels that may run on systems that have 1890 UEFI firmware. 1891 1892config DMI 1893 bool "Enable support for SMBIOS (DMI) tables" 1894 depends on EFI 1895 default y 1896 help 1897 This enables SMBIOS/DMI feature for systems. 1898 1899 This option is only useful on systems that have UEFI firmware. 1900 However, even with this option, the resultant kernel should 1901 continue to boot on existing non-UEFI platforms. 1902 1903 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1904 i.e., the the practice of identifying the platform via DMI to 1905 decide whether certain workarounds for buggy hardware and/or 1906 firmware need to be enabled. This would require the DMI subsystem 1907 to be enabled much earlier than we do on ARM, which is non-trivial. 1908 1909endmenu 1910 1911menu "CPU Power Management" 1912 1913source "drivers/cpufreq/Kconfig" 1914 1915source "drivers/cpuidle/Kconfig" 1916 1917endmenu 1918 1919menu "Floating point emulation" 1920 1921comment "At least one emulation must be selected" 1922 1923config FPE_NWFPE 1924 bool "NWFPE math emulation" 1925 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1926 help 1927 Say Y to include the NWFPE floating point emulator in the kernel. 1928 This is necessary to run most binaries. Linux does not currently 1929 support floating point hardware so you need to say Y here even if 1930 your machine has an FPA or floating point co-processor podule. 1931 1932 You may say N here if you are going to load the Acorn FPEmulator 1933 early in the bootup. 1934 1935config FPE_NWFPE_XP 1936 bool "Support extended precision" 1937 depends on FPE_NWFPE 1938 help 1939 Say Y to include 80-bit support in the kernel floating-point 1940 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1941 Note that gcc does not generate 80-bit operations by default, 1942 so in most cases this option only enlarges the size of the 1943 floating point emulator without any good reason. 1944 1945 You almost surely want to say N here. 1946 1947config FPE_FASTFPE 1948 bool "FastFPE math emulation (EXPERIMENTAL)" 1949 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1950 help 1951 Say Y here to include the FAST floating point emulator in the kernel. 1952 This is an experimental much faster emulator which now also has full 1953 precision for the mantissa. It does not support any exceptions. 1954 It is very simple, and approximately 3-6 times faster than NWFPE. 1955 1956 It should be sufficient for most programs. It may be not suitable 1957 for scientific calculations, but you have to check this for yourself. 1958 If you do not feel you need a faster FP emulation you should better 1959 choose NWFPE. 1960 1961config VFP 1962 bool "VFP-format floating point maths" 1963 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1964 help 1965 Say Y to include VFP support code in the kernel. This is needed 1966 if your hardware includes a VFP unit. 1967 1968 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1969 release notes and additional status information. 1970 1971 Say N if your target does not have VFP hardware. 1972 1973config VFPv3 1974 bool 1975 depends on VFP 1976 default y if CPU_V7 1977 1978config NEON 1979 bool "Advanced SIMD (NEON) Extension support" 1980 depends on VFPv3 && CPU_V7 1981 help 1982 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1983 Extension. 1984 1985config KERNEL_MODE_NEON 1986 bool "Support for NEON in kernel mode" 1987 depends on NEON && AEABI 1988 help 1989 Say Y to include support for NEON in kernel mode. 1990 1991endmenu 1992 1993menu "Power management options" 1994 1995source "kernel/power/Kconfig" 1996 1997config ARCH_SUSPEND_POSSIBLE 1998 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1999 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2000 def_bool y 2001 2002config ARM_CPU_SUSPEND 2003 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2004 depends on ARCH_SUSPEND_POSSIBLE 2005 2006config ARCH_HIBERNATION_POSSIBLE 2007 bool 2008 depends on MMU 2009 default y if ARCH_SUSPEND_POSSIBLE 2010 2011endmenu 2012 2013source "drivers/firmware/Kconfig" 2014 2015if CRYPTO 2016source "arch/arm/crypto/Kconfig" 2017endif 2018 2019source "arch/arm/Kconfig.assembler" 2020