1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_ELF_RANDOMIZE 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_HAVE_CUSTOM_GPIO_H 8 select ARCH_HAS_GCOV_PROFILE_ALL 9 select ARCH_MIGHT_HAVE_PC_PARPORT 10 select ARCH_SUPPORTS_ATOMIC_RMW 11 select ARCH_USE_BUILTIN_BSWAP 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_EXTABLE_SORT if MMU 15 select CLONE_BACKWARDS 16 select CPU_PM if (SUSPEND || CPU_IDLE) 17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 18 select EDAC_SUPPORT 19 select EDAC_ATOMIC_SCRUB 20 select GENERIC_ALLOCATOR 21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 23 select GENERIC_IDLE_POLL_SETUP 24 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW_LEVEL 27 select GENERIC_PCI_IOMAP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select HANDLE_DOMAIN_IRQ 33 select HARDIRQS_SW_RESEND 34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 39 select HAVE_ARCH_TRACEHOOK 40 select HAVE_BPF_JIT 41 select HAVE_CC_STACKPROTECTOR 42 select HAVE_CONTEXT_TRACKING 43 select HAVE_C_RECORDMCOUNT 44 select HAVE_DEBUG_KMEMLEAK 45 select HAVE_DMA_API_DEBUG 46 select HAVE_DMA_ATTRS 47 select HAVE_DMA_CONTIGUOUS if MMU 48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 53 select HAVE_GENERIC_DMA_COHERENT 54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 55 select HAVE_IDE if PCI || ISA || PCMCIA 56 select HAVE_IRQ_TIME_ACCOUNTING 57 select HAVE_KERNEL_GZIP 58 select HAVE_KERNEL_LZ4 59 select HAVE_KERNEL_LZMA 60 select HAVE_KERNEL_LZO 61 select HAVE_KERNEL_XZ 62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 63 select HAVE_KRETPROBES if (HAVE_KPROBES) 64 select HAVE_MEMBLOCK 65 select HAVE_MOD_ARCH_SPECIFIC 66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 67 select HAVE_OPTPROBES if !THUMB2_KERNEL 68 select HAVE_PERF_EVENTS 69 select HAVE_PERF_REGS 70 select HAVE_PERF_USER_STACK_DUMP 71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 72 select HAVE_REGS_AND_STACK_ACCESS_API 73 select HAVE_SYSCALL_TRACEPOINTS 74 select HAVE_UID16 75 select HAVE_VIRT_CPU_ACCOUNTING_GEN 76 select IRQ_FORCED_THREADING 77 select MODULES_USE_ELF_REL 78 select NO_BOOTMEM 79 select OF_EARLY_FLATTREE if OF 80 select OF_RESERVED_MEM if OF 81 select OLD_SIGACTION 82 select OLD_SIGSUSPEND3 83 select PERF_USE_VMALLOC 84 select RTC_LIB 85 select SYS_SUPPORTS_APM_EMULATION 86 # Above selects are sorted alphabetically; please add new ones 87 # according to that. Thanks. 88 help 89 The ARM series is a line of low-power-consumption RISC chip designs 90 licensed by ARM Ltd and targeted at embedded applications and 91 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 92 manufactured, but legacy ARM-based PC hardware remains popular in 93 Europe. There is an ARM Linux project with a web page at 94 <http://www.arm.linux.org.uk/>. 95 96config ARM_HAS_SG_CHAIN 97 select ARCH_HAS_SG_CHAIN 98 bool 99 100config NEED_SG_DMA_LENGTH 101 bool 102 103config ARM_DMA_USE_IOMMU 104 bool 105 select ARM_HAS_SG_CHAIN 106 select NEED_SG_DMA_LENGTH 107 108if ARM_DMA_USE_IOMMU 109 110config ARM_DMA_IOMMU_ALIGNMENT 111 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 112 range 4 9 113 default 8 114 help 115 DMA mapping framework by default aligns all buffers to the smallest 116 PAGE_SIZE order which is greater than or equal to the requested buffer 117 size. This works well for buffers up to a few hundreds kilobytes, but 118 for larger buffers it just a waste of address space. Drivers which has 119 relatively small addressing window (like 64Mib) might run out of 120 virtual space with just a few allocations. 121 122 With this parameter you can specify the maximum PAGE_SIZE order for 123 DMA IOMMU buffers. Larger buffers will be aligned only to this 124 specified order. The order is expressed as a power of two multiplied 125 by the PAGE_SIZE. 126 127endif 128 129config MIGHT_HAVE_PCI 130 bool 131 132config SYS_SUPPORTS_APM_EMULATION 133 bool 134 135config HAVE_TCM 136 bool 137 select GENERIC_ALLOCATOR 138 139config HAVE_PROC_CPU 140 bool 141 142config NO_IOPORT_MAP 143 bool 144 145config EISA 146 bool 147 ---help--- 148 The Extended Industry Standard Architecture (EISA) bus was 149 developed as an open alternative to the IBM MicroChannel bus. 150 151 The EISA bus provided some of the features of the IBM MicroChannel 152 bus while maintaining backward compatibility with cards made for 153 the older ISA bus. The EISA bus saw limited use between 1988 and 154 1995 when it was made obsolete by the PCI bus. 155 156 Say Y here if you are building a kernel for an EISA-based machine. 157 158 Otherwise, say N. 159 160config SBUS 161 bool 162 163config STACKTRACE_SUPPORT 164 bool 165 default y 166 167config HAVE_LATENCYTOP_SUPPORT 168 bool 169 depends on !SMP 170 default y 171 172config LOCKDEP_SUPPORT 173 bool 174 default y 175 176config TRACE_IRQFLAGS_SUPPORT 177 bool 178 default !CPU_V7M 179 180config RWSEM_XCHGADD_ALGORITHM 181 bool 182 default y 183 184config ARCH_HAS_ILOG2_U32 185 bool 186 187config ARCH_HAS_ILOG2_U64 188 bool 189 190config ARCH_HAS_BANDGAP 191 bool 192 193config FIX_EARLYCON_MEM 194 def_bool y if MMU 195 196config GENERIC_HWEIGHT 197 bool 198 default y 199 200config GENERIC_CALIBRATE_DELAY 201 bool 202 default y 203 204config ARCH_MAY_HAVE_PC_FDC 205 bool 206 207config ZONE_DMA 208 bool 209 210config NEED_DMA_MAP_STATE 211 def_bool y 212 213config ARCH_SUPPORTS_UPROBES 214 def_bool y 215 216config ARCH_HAS_DMA_SET_COHERENT_MASK 217 bool 218 219config GENERIC_ISA_DMA 220 bool 221 222config FIQ 223 bool 224 225config NEED_RET_TO_USER 226 bool 227 228config ARCH_MTD_XIP 229 bool 230 231config VECTORS_BASE 232 hex 233 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 234 default DRAM_BASE if REMAP_VECTORS_TO_RAM 235 default 0x00000000 236 help 237 The base address of exception vectors. This must be two pages 238 in size. 239 240config ARM_PATCH_PHYS_VIRT 241 bool "Patch physical to virtual translations at runtime" if EMBEDDED 242 default y 243 depends on !XIP_KERNEL && MMU 244 depends on !ARCH_REALVIEW || !SPARSEMEM 245 help 246 Patch phys-to-virt and virt-to-phys translation functions at 247 boot and module load time according to the position of the 248 kernel in system memory. 249 250 This can only be used with non-XIP MMU kernels where the base 251 of physical memory is at a 16MB boundary. 252 253 Only disable this option if you know that you do not require 254 this feature (eg, building a kernel for a single machine) and 255 you need to shrink the kernel to the minimal size. 256 257config NEED_MACH_IO_H 258 bool 259 help 260 Select this when mach/io.h is required to provide special 261 definitions for this platform. The need for mach/io.h should 262 be avoided when possible. 263 264config NEED_MACH_MEMORY_H 265 bool 266 help 267 Select this when mach/memory.h is required to provide special 268 definitions for this platform. The need for mach/memory.h should 269 be avoided when possible. 270 271config PHYS_OFFSET 272 hex "Physical address of main memory" if MMU 273 depends on !ARM_PATCH_PHYS_VIRT 274 default DRAM_BASE if !MMU 275 default 0x00000000 if ARCH_EBSA110 || \ 276 ARCH_FOOTBRIDGE || \ 277 ARCH_INTEGRATOR || \ 278 ARCH_IOP13XX || \ 279 ARCH_KS8695 || \ 280 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 282 default 0x20000000 if ARCH_S5PV210 283 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 284 default 0xc0000000 if ARCH_SA1100 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298source "init/Kconfig" 299 300source "kernel/Kconfig.freezer" 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311# 312# The "ARM system type" choice list is ordered alphabetically by option 313# text. Please add new entries in the option alphabetic order. 314# 315choice 316 prompt "ARM system type" 317 default ARCH_VERSATILE if !MMU 318 default ARCH_MULTIPLATFORM if MMU 319 320config ARCH_MULTIPLATFORM 321 bool "Allow multiple platforms to be selected" 322 depends on MMU 323 select ARCH_WANT_OPTIONAL_GPIOLIB 324 select ARM_HAS_SG_CHAIN 325 select ARM_PATCH_PHYS_VIRT 326 select AUTO_ZRELADDR 327 select CLKSRC_OF 328 select COMMON_CLK 329 select GENERIC_CLOCKEVENTS 330 select MIGHT_HAVE_PCI 331 select MULTI_IRQ_HANDLER 332 select SPARSE_IRQ 333 select USE_OF 334 335config ARM_SINGLE_ARMV7M 336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 337 depends on !MMU 338 select ARCH_WANT_OPTIONAL_GPIOLIB 339 select ARM_NVIC 340 select AUTO_ZRELADDR 341 select CLKSRC_OF 342 select COMMON_CLK 343 select CPU_V7M 344 select GENERIC_CLOCKEVENTS 345 select NO_IOPORT_MAP 346 select SPARSE_IRQ 347 select USE_OF 348 349config ARCH_REALVIEW 350 bool "ARM Ltd. RealView family" 351 select ARCH_WANT_OPTIONAL_GPIOLIB 352 select ARM_AMBA 353 select ARM_TIMER_SP804 354 select COMMON_CLK 355 select COMMON_CLK_VERSATILE 356 select GENERIC_CLOCKEVENTS 357 select GPIO_PL061 if GPIOLIB 358 select ICST 359 select NEED_MACH_MEMORY_H 360 select PLAT_VERSATILE 361 select PLAT_VERSATILE_SCHED_CLOCK 362 help 363 This enables support for ARM Ltd RealView boards. 364 365config ARCH_CLPS711X 366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 367 select ARCH_REQUIRE_GPIOLIB 368 select AUTO_ZRELADDR 369 select CLKSRC_MMIO 370 select COMMON_CLK 371 select CPU_ARM720T 372 select GENERIC_CLOCKEVENTS 373 select MFD_SYSCON 374 select SOC_BUS 375 help 376 Support for Cirrus Logic 711x/721x/731x based boards. 377 378config ARCH_GEMINI 379 bool "Cortina Systems Gemini" 380 select ARCH_REQUIRE_GPIOLIB 381 select CLKSRC_MMIO 382 select CPU_FA526 383 select GENERIC_CLOCKEVENTS 384 help 385 Support for the Cortina Systems Gemini family SoCs 386 387config ARCH_EBSA110 388 bool "EBSA-110" 389 select ARCH_USES_GETTIMEOFFSET 390 select CPU_SA110 391 select ISA 392 select NEED_MACH_IO_H 393 select NEED_MACH_MEMORY_H 394 select NO_IOPORT_MAP 395 help 396 This is an evaluation board for the StrongARM processor available 397 from Digital. It has limited hardware on-board, including an 398 Ethernet interface, two PCMCIA sockets, two serial ports and a 399 parallel port. 400 401config ARCH_EP93XX 402 bool "EP93xx-based" 403 select ARCH_HAS_HOLES_MEMORYMODEL 404 select ARCH_REQUIRE_GPIOLIB 405 select ARM_AMBA 406 select ARM_PATCH_PHYS_VIRT 407 select ARM_VIC 408 select AUTO_ZRELADDR 409 select CLKDEV_LOOKUP 410 select CLKSRC_MMIO 411 select CPU_ARM920T 412 select GENERIC_CLOCKEVENTS 413 help 414 This enables support for the Cirrus EP93xx series of CPUs. 415 416config ARCH_FOOTBRIDGE 417 bool "FootBridge" 418 select CPU_SA110 419 select FOOTBRIDGE 420 select GENERIC_CLOCKEVENTS 421 select HAVE_IDE 422 select NEED_MACH_IO_H if !MMU 423 select NEED_MACH_MEMORY_H 424 help 425 Support for systems based on the DC21285 companion chip 426 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 427 428config ARCH_NETX 429 bool "Hilscher NetX based" 430 select ARM_VIC 431 select CLKSRC_MMIO 432 select CPU_ARM926T 433 select GENERIC_CLOCKEVENTS 434 help 435 This enables support for systems based on the Hilscher NetX Soc 436 437config ARCH_IOP13XX 438 bool "IOP13xx-based" 439 depends on MMU 440 select CPU_XSC3 441 select NEED_MACH_MEMORY_H 442 select NEED_RET_TO_USER 443 select PCI 444 select PLAT_IOP 445 select VMSPLIT_1G 446 select SPARSE_IRQ 447 help 448 Support for Intel's IOP13XX (XScale) family of processors. 449 450config ARCH_IOP32X 451 bool "IOP32x-based" 452 depends on MMU 453 select ARCH_REQUIRE_GPIOLIB 454 select CPU_XSCALE 455 select GPIO_IOP 456 select NEED_RET_TO_USER 457 select PCI 458 select PLAT_IOP 459 help 460 Support for Intel's 80219 and IOP32X (XScale) family of 461 processors. 462 463config ARCH_IOP33X 464 bool "IOP33x-based" 465 depends on MMU 466 select ARCH_REQUIRE_GPIOLIB 467 select CPU_XSCALE 468 select GPIO_IOP 469 select NEED_RET_TO_USER 470 select PCI 471 select PLAT_IOP 472 help 473 Support for Intel's IOP33X (XScale) family of processors. 474 475config ARCH_IXP4XX 476 bool "IXP4xx-based" 477 depends on MMU 478 select ARCH_HAS_DMA_SET_COHERENT_MASK 479 select ARCH_REQUIRE_GPIOLIB 480 select ARCH_SUPPORTS_BIG_ENDIAN 481 select CLKSRC_MMIO 482 select CPU_XSCALE 483 select DMABOUNCE if PCI 484 select GENERIC_CLOCKEVENTS 485 select MIGHT_HAVE_PCI 486 select NEED_MACH_IO_H 487 select USB_EHCI_BIG_ENDIAN_DESC 488 select USB_EHCI_BIG_ENDIAN_MMIO 489 help 490 Support for Intel's IXP4XX (XScale) family of processors. 491 492config ARCH_DOVE 493 bool "Marvell Dove" 494 select ARCH_REQUIRE_GPIOLIB 495 select CPU_PJ4 496 select GENERIC_CLOCKEVENTS 497 select MIGHT_HAVE_PCI 498 select MVEBU_MBUS 499 select PINCTRL 500 select PINCTRL_DOVE 501 select PLAT_ORION_LEGACY 502 help 503 Support for the Marvell Dove SoC 88AP510 504 505config ARCH_MV78XX0 506 bool "Marvell MV78xx0" 507 select ARCH_REQUIRE_GPIOLIB 508 select CPU_FEROCEON 509 select GENERIC_CLOCKEVENTS 510 select MVEBU_MBUS 511 select PCI 512 select PLAT_ORION_LEGACY 513 help 514 Support for the following Marvell MV78xx0 series SoCs: 515 MV781x0, MV782x0. 516 517config ARCH_ORION5X 518 bool "Marvell Orion" 519 depends on MMU 520 select ARCH_REQUIRE_GPIOLIB 521 select CPU_FEROCEON 522 select GENERIC_CLOCKEVENTS 523 select MVEBU_MBUS 524 select PCI 525 select PLAT_ORION_LEGACY 526 select MULTI_IRQ_HANDLER 527 help 528 Support for the following Marvell Orion 5x series SoCs: 529 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 530 Orion-2 (5281), Orion-1-90 (6183). 531 532config ARCH_MMP 533 bool "Marvell PXA168/910/MMP2" 534 depends on MMU 535 select ARCH_REQUIRE_GPIOLIB 536 select CLKDEV_LOOKUP 537 select GENERIC_ALLOCATOR 538 select GENERIC_CLOCKEVENTS 539 select GPIO_PXA 540 select IRQ_DOMAIN 541 select MULTI_IRQ_HANDLER 542 select PINCTRL 543 select PLAT_PXA 544 select SPARSE_IRQ 545 help 546 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 547 548config ARCH_KS8695 549 bool "Micrel/Kendin KS8695" 550 select ARCH_REQUIRE_GPIOLIB 551 select CLKSRC_MMIO 552 select CPU_ARM922T 553 select GENERIC_CLOCKEVENTS 554 select NEED_MACH_MEMORY_H 555 help 556 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 557 System-on-Chip devices. 558 559config ARCH_W90X900 560 bool "Nuvoton W90X900 CPU" 561 select ARCH_REQUIRE_GPIOLIB 562 select CLKDEV_LOOKUP 563 select CLKSRC_MMIO 564 select CPU_ARM926T 565 select GENERIC_CLOCKEVENTS 566 help 567 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 568 At present, the w90x900 has been renamed nuc900, regarding 569 the ARM series product line, you can login the following 570 link address to know more. 571 572 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 573 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 574 575config ARCH_LPC32XX 576 bool "NXP LPC32XX" 577 select ARCH_REQUIRE_GPIOLIB 578 select ARM_AMBA 579 select CLKDEV_LOOKUP 580 select CLKSRC_MMIO 581 select CPU_ARM926T 582 select GENERIC_CLOCKEVENTS 583 select HAVE_IDE 584 select USE_OF 585 help 586 Support for the NXP LPC32XX family of processors 587 588config ARCH_PXA 589 bool "PXA2xx/PXA3xx-based" 590 depends on MMU 591 select ARCH_MTD_XIP 592 select ARCH_REQUIRE_GPIOLIB 593 select ARM_CPU_SUSPEND if PM 594 select AUTO_ZRELADDR 595 select COMMON_CLK 596 select CLKDEV_LOOKUP 597 select CLKSRC_MMIO 598 select CLKSRC_OF 599 select GENERIC_CLOCKEVENTS 600 select GPIO_PXA 601 select HAVE_IDE 602 select IRQ_DOMAIN 603 select MULTI_IRQ_HANDLER 604 select PLAT_PXA 605 select SPARSE_IRQ 606 help 607 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 608 609config ARCH_RPC 610 bool "RiscPC" 611 depends on MMU 612 select ARCH_ACORN 613 select ARCH_MAY_HAVE_PC_FDC 614 select ARCH_SPARSEMEM_ENABLE 615 select ARCH_USES_GETTIMEOFFSET 616 select CPU_SA110 617 select FIQ 618 select HAVE_IDE 619 select HAVE_PATA_PLATFORM 620 select ISA_DMA_API 621 select NEED_MACH_IO_H 622 select NEED_MACH_MEMORY_H 623 select NO_IOPORT_MAP 624 select VIRT_TO_BUS 625 help 626 On the Acorn Risc-PC, Linux can support the internal IDE disk and 627 CD-ROM interface, serial and parallel port, and the floppy drive. 628 629config ARCH_SA1100 630 bool "SA1100-based" 631 select ARCH_MTD_XIP 632 select ARCH_REQUIRE_GPIOLIB 633 select ARCH_SPARSEMEM_ENABLE 634 select CLKDEV_LOOKUP 635 select CLKSRC_MMIO 636 select CPU_FREQ 637 select CPU_SA1100 638 select GENERIC_CLOCKEVENTS 639 select HAVE_IDE 640 select IRQ_DOMAIN 641 select ISA 642 select MULTI_IRQ_HANDLER 643 select NEED_MACH_MEMORY_H 644 select SPARSE_IRQ 645 help 646 Support for StrongARM 11x0 based boards. 647 648config ARCH_S3C24XX 649 bool "Samsung S3C24XX SoCs" 650 select ARCH_REQUIRE_GPIOLIB 651 select ATAGS 652 select CLKDEV_LOOKUP 653 select CLKSRC_SAMSUNG_PWM 654 select GENERIC_CLOCKEVENTS 655 select GPIO_SAMSUNG 656 select HAVE_S3C2410_I2C if I2C 657 select HAVE_S3C2410_WATCHDOG if WATCHDOG 658 select HAVE_S3C_RTC if RTC_CLASS 659 select MULTI_IRQ_HANDLER 660 select NEED_MACH_IO_H 661 select SAMSUNG_ATAGS 662 help 663 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 664 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 665 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 666 Samsung SMDK2410 development board (and derivatives). 667 668config ARCH_S3C64XX 669 bool "Samsung S3C64XX" 670 select ARCH_REQUIRE_GPIOLIB 671 select ARM_AMBA 672 select ARM_VIC 673 select ATAGS 674 select CLKDEV_LOOKUP 675 select CLKSRC_SAMSUNG_PWM 676 select COMMON_CLK_SAMSUNG 677 select CPU_V6K 678 select GENERIC_CLOCKEVENTS 679 select GPIO_SAMSUNG 680 select HAVE_S3C2410_I2C if I2C 681 select HAVE_S3C2410_WATCHDOG if WATCHDOG 682 select HAVE_TCM 683 select NO_IOPORT_MAP 684 select PLAT_SAMSUNG 685 select PM_GENERIC_DOMAINS if PM 686 select S3C_DEV_NAND 687 select S3C_GPIO_TRACK 688 select SAMSUNG_ATAGS 689 select SAMSUNG_WAKEMASK 690 select SAMSUNG_WDT_RESET 691 help 692 Samsung S3C64XX series based systems 693 694config ARCH_DAVINCI 695 bool "TI DaVinci" 696 select ARCH_HAS_HOLES_MEMORYMODEL 697 select ARCH_REQUIRE_GPIOLIB 698 select CLKDEV_LOOKUP 699 select GENERIC_ALLOCATOR 700 select GENERIC_CLOCKEVENTS 701 select GENERIC_IRQ_CHIP 702 select HAVE_IDE 703 select USE_OF 704 select ZONE_DMA 705 help 706 Support for TI's DaVinci platform. 707 708config ARCH_OMAP1 709 bool "TI OMAP1" 710 depends on MMU 711 select ARCH_HAS_HOLES_MEMORYMODEL 712 select ARCH_OMAP 713 select ARCH_REQUIRE_GPIOLIB 714 select CLKDEV_LOOKUP 715 select CLKSRC_MMIO 716 select GENERIC_CLOCKEVENTS 717 select GENERIC_IRQ_CHIP 718 select HAVE_IDE 719 select IRQ_DOMAIN 720 select MULTI_IRQ_HANDLER 721 select NEED_MACH_IO_H if PCCARD 722 select NEED_MACH_MEMORY_H 723 select SPARSE_IRQ 724 help 725 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 726 727endchoice 728 729menu "Multiple platform selection" 730 depends on ARCH_MULTIPLATFORM 731 732comment "CPU Core family selection" 733 734config ARCH_MULTI_V4 735 bool "ARMv4 based platforms (FA526)" 736 depends on !ARCH_MULTI_V6_V7 737 select ARCH_MULTI_V4_V5 738 select CPU_FA526 739 740config ARCH_MULTI_V4T 741 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 742 depends on !ARCH_MULTI_V6_V7 743 select ARCH_MULTI_V4_V5 744 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 745 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 746 CPU_ARM925T || CPU_ARM940T) 747 748config ARCH_MULTI_V5 749 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 750 depends on !ARCH_MULTI_V6_V7 751 select ARCH_MULTI_V4_V5 752 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 753 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 754 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 755 756config ARCH_MULTI_V4_V5 757 bool 758 759config ARCH_MULTI_V6 760 bool "ARMv6 based platforms (ARM11)" 761 select ARCH_MULTI_V6_V7 762 select CPU_V6K 763 764config ARCH_MULTI_V7 765 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 766 default y 767 select ARCH_MULTI_V6_V7 768 select CPU_V7 769 select HAVE_SMP 770 771config ARCH_MULTI_V6_V7 772 bool 773 select MIGHT_HAVE_CACHE_L2X0 774 775config ARCH_MULTI_CPU_AUTO 776 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 777 select ARCH_MULTI_V5 778 779endmenu 780 781config ARCH_VIRT 782 bool "Dummy Virtual Machine" if ARCH_MULTI_V7 783 select ARM_AMBA 784 select ARM_GIC 785 select ARM_GIC_V3 786 select ARM_PSCI 787 select HAVE_ARM_ARCH_TIMER 788 789# 790# This is sorted alphabetically by mach-* pathname. However, plat-* 791# Kconfigs may be included either alphabetically (according to the 792# plat- suffix) or along side the corresponding mach-* source. 793# 794source "arch/arm/mach-mvebu/Kconfig" 795 796source "arch/arm/mach-alpine/Kconfig" 797 798source "arch/arm/mach-asm9260/Kconfig" 799 800source "arch/arm/mach-at91/Kconfig" 801 802source "arch/arm/mach-axxia/Kconfig" 803 804source "arch/arm/mach-bcm/Kconfig" 805 806source "arch/arm/mach-berlin/Kconfig" 807 808source "arch/arm/mach-clps711x/Kconfig" 809 810source "arch/arm/mach-cns3xxx/Kconfig" 811 812source "arch/arm/mach-davinci/Kconfig" 813 814source "arch/arm/mach-digicolor/Kconfig" 815 816source "arch/arm/mach-dove/Kconfig" 817 818source "arch/arm/mach-ep93xx/Kconfig" 819 820source "arch/arm/mach-footbridge/Kconfig" 821 822source "arch/arm/mach-gemini/Kconfig" 823 824source "arch/arm/mach-highbank/Kconfig" 825 826source "arch/arm/mach-hisi/Kconfig" 827 828source "arch/arm/mach-integrator/Kconfig" 829 830source "arch/arm/mach-iop32x/Kconfig" 831 832source "arch/arm/mach-iop33x/Kconfig" 833 834source "arch/arm/mach-iop13xx/Kconfig" 835 836source "arch/arm/mach-ixp4xx/Kconfig" 837 838source "arch/arm/mach-keystone/Kconfig" 839 840source "arch/arm/mach-ks8695/Kconfig" 841 842source "arch/arm/mach-meson/Kconfig" 843 844source "arch/arm/mach-moxart/Kconfig" 845 846source "arch/arm/mach-mv78xx0/Kconfig" 847 848source "arch/arm/mach-imx/Kconfig" 849 850source "arch/arm/mach-mediatek/Kconfig" 851 852source "arch/arm/mach-mxs/Kconfig" 853 854source "arch/arm/mach-netx/Kconfig" 855 856source "arch/arm/mach-nomadik/Kconfig" 857 858source "arch/arm/mach-nspire/Kconfig" 859 860source "arch/arm/plat-omap/Kconfig" 861 862source "arch/arm/mach-omap1/Kconfig" 863 864source "arch/arm/mach-omap2/Kconfig" 865 866source "arch/arm/mach-orion5x/Kconfig" 867 868source "arch/arm/mach-picoxcell/Kconfig" 869 870source "arch/arm/mach-pxa/Kconfig" 871source "arch/arm/plat-pxa/Kconfig" 872 873source "arch/arm/mach-mmp/Kconfig" 874 875source "arch/arm/mach-qcom/Kconfig" 876 877source "arch/arm/mach-realview/Kconfig" 878 879source "arch/arm/mach-rockchip/Kconfig" 880 881source "arch/arm/mach-sa1100/Kconfig" 882 883source "arch/arm/mach-socfpga/Kconfig" 884 885source "arch/arm/mach-spear/Kconfig" 886 887source "arch/arm/mach-sti/Kconfig" 888 889source "arch/arm/mach-s3c24xx/Kconfig" 890 891source "arch/arm/mach-s3c64xx/Kconfig" 892 893source "arch/arm/mach-s5pv210/Kconfig" 894 895source "arch/arm/mach-exynos/Kconfig" 896source "arch/arm/plat-samsung/Kconfig" 897 898source "arch/arm/mach-shmobile/Kconfig" 899 900source "arch/arm/mach-sunxi/Kconfig" 901 902source "arch/arm/mach-prima2/Kconfig" 903 904source "arch/arm/mach-tegra/Kconfig" 905 906source "arch/arm/mach-u300/Kconfig" 907 908source "arch/arm/mach-uniphier/Kconfig" 909 910source "arch/arm/mach-ux500/Kconfig" 911 912source "arch/arm/mach-versatile/Kconfig" 913 914source "arch/arm/mach-vexpress/Kconfig" 915source "arch/arm/plat-versatile/Kconfig" 916 917source "arch/arm/mach-vt8500/Kconfig" 918 919source "arch/arm/mach-w90x900/Kconfig" 920 921source "arch/arm/mach-zx/Kconfig" 922 923source "arch/arm/mach-zynq/Kconfig" 924 925# ARMv7-M architecture 926config ARCH_EFM32 927 bool "Energy Micro efm32" 928 depends on ARM_SINGLE_ARMV7M 929 select ARCH_REQUIRE_GPIOLIB 930 help 931 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 932 processors. 933 934config ARCH_LPC18XX 935 bool "NXP LPC18xx/LPC43xx" 936 depends on ARM_SINGLE_ARMV7M 937 select ARCH_HAS_RESET_CONTROLLER 938 select ARM_AMBA 939 select CLKSRC_LPC32XX 940 select PINCTRL 941 help 942 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 943 high performance microcontrollers. 944 945config ARCH_STM32 946 bool "STMicrolectronics STM32" 947 depends on ARM_SINGLE_ARMV7M 948 select ARCH_HAS_RESET_CONTROLLER 949 select ARMV7M_SYSTICK 950 select CLKSRC_STM32 951 select RESET_CONTROLLER 952 help 953 Support for STMicroelectronics STM32 processors. 954 955# Definitions to make life easier 956config ARCH_ACORN 957 bool 958 959config PLAT_IOP 960 bool 961 select GENERIC_CLOCKEVENTS 962 963config PLAT_ORION 964 bool 965 select CLKSRC_MMIO 966 select COMMON_CLK 967 select GENERIC_IRQ_CHIP 968 select IRQ_DOMAIN 969 970config PLAT_ORION_LEGACY 971 bool 972 select PLAT_ORION 973 974config PLAT_PXA 975 bool 976 977config PLAT_VERSATILE 978 bool 979 980source "arch/arm/firmware/Kconfig" 981 982source arch/arm/mm/Kconfig 983 984config IWMMXT 985 bool "Enable iWMMXt support" 986 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 987 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 988 help 989 Enable support for iWMMXt context switching at run time if 990 running on a CPU that supports it. 991 992config MULTI_IRQ_HANDLER 993 bool 994 help 995 Allow each machine to specify it's own IRQ handler at run time. 996 997if !MMU 998source "arch/arm/Kconfig-nommu" 999endif 1000 1001config PJ4B_ERRATA_4742 1002 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 1003 depends on CPU_PJ4B && MACH_ARMADA_370 1004 default y 1005 help 1006 When coming out of either a Wait for Interrupt (WFI) or a Wait for 1007 Event (WFE) IDLE states, a specific timing sensitivity exists between 1008 the retiring WFI/WFE instructions and the newly issued subsequent 1009 instructions. This sensitivity can result in a CPU hang scenario. 1010 Workaround: 1011 The software must insert either a Data Synchronization Barrier (DSB) 1012 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 1013 instruction 1014 1015config ARM_ERRATA_326103 1016 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1017 depends on CPU_V6 1018 help 1019 Executing a SWP instruction to read-only memory does not set bit 11 1020 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1021 treat the access as a read, preventing a COW from occurring and 1022 causing the faulting task to livelock. 1023 1024config ARM_ERRATA_411920 1025 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1026 depends on CPU_V6 || CPU_V6K 1027 help 1028 Invalidation of the Instruction Cache operation can 1029 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1030 It does not affect the MPCore. This option enables the ARM Ltd. 1031 recommended workaround. 1032 1033config ARM_ERRATA_430973 1034 bool "ARM errata: Stale prediction on replaced interworking branch" 1035 depends on CPU_V7 1036 help 1037 This option enables the workaround for the 430973 Cortex-A8 1038 r1p* erratum. If a code sequence containing an ARM/Thumb 1039 interworking branch is replaced with another code sequence at the 1040 same virtual address, whether due to self-modifying code or virtual 1041 to physical address re-mapping, Cortex-A8 does not recover from the 1042 stale interworking branch prediction. This results in Cortex-A8 1043 executing the new code sequence in the incorrect ARM or Thumb state. 1044 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1045 and also flushes the branch target cache at every context switch. 1046 Note that setting specific bits in the ACTLR register may not be 1047 available in non-secure mode. 1048 1049config ARM_ERRATA_458693 1050 bool "ARM errata: Processor deadlock when a false hazard is created" 1051 depends on CPU_V7 1052 depends on !ARCH_MULTIPLATFORM 1053 help 1054 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1055 erratum. For very specific sequences of memory operations, it is 1056 possible for a hazard condition intended for a cache line to instead 1057 be incorrectly associated with a different cache line. This false 1058 hazard might then cause a processor deadlock. The workaround enables 1059 the L1 caching of the NEON accesses and disables the PLD instruction 1060 in the ACTLR register. Note that setting specific bits in the ACTLR 1061 register may not be available in non-secure mode. 1062 1063config ARM_ERRATA_460075 1064 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1065 depends on CPU_V7 1066 depends on !ARCH_MULTIPLATFORM 1067 help 1068 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1069 erratum. Any asynchronous access to the L2 cache may encounter a 1070 situation in which recent store transactions to the L2 cache are lost 1071 and overwritten with stale memory contents from external memory. The 1072 workaround disables the write-allocate mode for the L2 cache via the 1073 ACTLR register. Note that setting specific bits in the ACTLR register 1074 may not be available in non-secure mode. 1075 1076config ARM_ERRATA_742230 1077 bool "ARM errata: DMB operation may be faulty" 1078 depends on CPU_V7 && SMP 1079 depends on !ARCH_MULTIPLATFORM 1080 help 1081 This option enables the workaround for the 742230 Cortex-A9 1082 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1083 between two write operations may not ensure the correct visibility 1084 ordering of the two writes. This workaround sets a specific bit in 1085 the diagnostic register of the Cortex-A9 which causes the DMB 1086 instruction to behave as a DSB, ensuring the correct behaviour of 1087 the two writes. 1088 1089config ARM_ERRATA_742231 1090 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1091 depends on CPU_V7 && SMP 1092 depends on !ARCH_MULTIPLATFORM 1093 help 1094 This option enables the workaround for the 742231 Cortex-A9 1095 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1096 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1097 accessing some data located in the same cache line, may get corrupted 1098 data due to bad handling of the address hazard when the line gets 1099 replaced from one of the CPUs at the same time as another CPU is 1100 accessing it. This workaround sets specific bits in the diagnostic 1101 register of the Cortex-A9 which reduces the linefill issuing 1102 capabilities of the processor. 1103 1104config ARM_ERRATA_643719 1105 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1106 depends on CPU_V7 && SMP 1107 default y 1108 help 1109 This option enables the workaround for the 643719 Cortex-A9 (prior to 1110 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1111 register returns zero when it should return one. The workaround 1112 corrects this value, ensuring cache maintenance operations which use 1113 it behave as intended and avoiding data corruption. 1114 1115config ARM_ERRATA_720789 1116 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1117 depends on CPU_V7 1118 help 1119 This option enables the workaround for the 720789 Cortex-A9 (prior to 1120 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1121 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1122 As a consequence of this erratum, some TLB entries which should be 1123 invalidated are not, resulting in an incoherency in the system page 1124 tables. The workaround changes the TLB flushing routines to invalidate 1125 entries regardless of the ASID. 1126 1127config ARM_ERRATA_743622 1128 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1129 depends on CPU_V7 1130 depends on !ARCH_MULTIPLATFORM 1131 help 1132 This option enables the workaround for the 743622 Cortex-A9 1133 (r2p*) erratum. Under very rare conditions, a faulty 1134 optimisation in the Cortex-A9 Store Buffer may lead to data 1135 corruption. This workaround sets a specific bit in the diagnostic 1136 register of the Cortex-A9 which disables the Store Buffer 1137 optimisation, preventing the defect from occurring. This has no 1138 visible impact on the overall performance or power consumption of the 1139 processor. 1140 1141config ARM_ERRATA_751472 1142 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1143 depends on CPU_V7 1144 depends on !ARCH_MULTIPLATFORM 1145 help 1146 This option enables the workaround for the 751472 Cortex-A9 (prior 1147 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1148 completion of a following broadcasted operation if the second 1149 operation is received by a CPU before the ICIALLUIS has completed, 1150 potentially leading to corrupted entries in the cache or TLB. 1151 1152config ARM_ERRATA_754322 1153 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1154 depends on CPU_V7 1155 help 1156 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1157 r3p*) erratum. A speculative memory access may cause a page table walk 1158 which starts prior to an ASID switch but completes afterwards. This 1159 can populate the micro-TLB with a stale entry which may be hit with 1160 the new ASID. This workaround places two dsb instructions in the mm 1161 switching code so that no page table walks can cross the ASID switch. 1162 1163config ARM_ERRATA_754327 1164 bool "ARM errata: no automatic Store Buffer drain" 1165 depends on CPU_V7 && SMP 1166 help 1167 This option enables the workaround for the 754327 Cortex-A9 (prior to 1168 r2p0) erratum. The Store Buffer does not have any automatic draining 1169 mechanism and therefore a livelock may occur if an external agent 1170 continuously polls a memory location waiting to observe an update. 1171 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1172 written polling loops from denying visibility of updates to memory. 1173 1174config ARM_ERRATA_364296 1175 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1176 depends on CPU_V6 1177 help 1178 This options enables the workaround for the 364296 ARM1136 1179 r0p2 erratum (possible cache data corruption with 1180 hit-under-miss enabled). It sets the undocumented bit 31 in 1181 the auxiliary control register and the FI bit in the control 1182 register, thus disabling hit-under-miss without putting the 1183 processor into full low interrupt latency mode. ARM11MPCore 1184 is not affected. 1185 1186config ARM_ERRATA_764369 1187 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1188 depends on CPU_V7 && SMP 1189 help 1190 This option enables the workaround for erratum 764369 1191 affecting Cortex-A9 MPCore with two or more processors (all 1192 current revisions). Under certain timing circumstances, a data 1193 cache line maintenance operation by MVA targeting an Inner 1194 Shareable memory region may fail to proceed up to either the 1195 Point of Coherency or to the Point of Unification of the 1196 system. This workaround adds a DSB instruction before the 1197 relevant cache maintenance functions and sets a specific bit 1198 in the diagnostic control register of the SCU. 1199 1200config ARM_ERRATA_775420 1201 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1202 depends on CPU_V7 1203 help 1204 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1205 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1206 operation aborts with MMU exception, it might cause the processor 1207 to deadlock. This workaround puts DSB before executing ISB if 1208 an abort may occur on cache maintenance. 1209 1210config ARM_ERRATA_798181 1211 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1212 depends on CPU_V7 && SMP 1213 help 1214 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1215 adequately shooting down all use of the old entries. This 1216 option enables the Linux kernel workaround for this erratum 1217 which sends an IPI to the CPUs that are running the same ASID 1218 as the one being invalidated. 1219 1220config ARM_ERRATA_773022 1221 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1222 depends on CPU_V7 1223 help 1224 This option enables the workaround for the 773022 Cortex-A15 1225 (up to r0p4) erratum. In certain rare sequences of code, the 1226 loop buffer may deliver incorrect instructions. This 1227 workaround disables the loop buffer to avoid the erratum. 1228 1229endmenu 1230 1231source "arch/arm/common/Kconfig" 1232 1233menu "Bus support" 1234 1235config ISA 1236 bool 1237 help 1238 Find out whether you have ISA slots on your motherboard. ISA is the 1239 name of a bus system, i.e. the way the CPU talks to the other stuff 1240 inside your box. Other bus systems are PCI, EISA, MicroChannel 1241 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1242 newer boards don't support it. If you have ISA, say Y, otherwise N. 1243 1244# Select ISA DMA controller support 1245config ISA_DMA 1246 bool 1247 select ISA_DMA_API 1248 1249# Select ISA DMA interface 1250config ISA_DMA_API 1251 bool 1252 1253config PCI 1254 bool "PCI support" if MIGHT_HAVE_PCI 1255 help 1256 Find out whether you have a PCI motherboard. PCI is the name of a 1257 bus system, i.e. the way the CPU talks to the other stuff inside 1258 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1259 VESA. If you have PCI, say Y, otherwise N. 1260 1261config PCI_DOMAINS 1262 bool 1263 depends on PCI 1264 1265config PCI_DOMAINS_GENERIC 1266 def_bool PCI_DOMAINS 1267 1268config PCI_NANOENGINE 1269 bool "BSE nanoEngine PCI support" 1270 depends on SA1100_NANOENGINE 1271 help 1272 Enable PCI on the BSE nanoEngine board. 1273 1274config PCI_SYSCALL 1275 def_bool PCI 1276 1277config PCI_HOST_ITE8152 1278 bool 1279 depends on PCI && MACH_ARMCORE 1280 default y 1281 select DMABOUNCE 1282 1283source "drivers/pci/Kconfig" 1284source "drivers/pci/pcie/Kconfig" 1285 1286source "drivers/pcmcia/Kconfig" 1287 1288endmenu 1289 1290menu "Kernel Features" 1291 1292config HAVE_SMP 1293 bool 1294 help 1295 This option should be selected by machines which have an SMP- 1296 capable CPU. 1297 1298 The only effect of this option is to make the SMP-related 1299 options available to the user for configuration. 1300 1301config SMP 1302 bool "Symmetric Multi-Processing" 1303 depends on CPU_V6K || CPU_V7 1304 depends on GENERIC_CLOCKEVENTS 1305 depends on HAVE_SMP 1306 depends on MMU || ARM_MPU 1307 select IRQ_WORK 1308 help 1309 This enables support for systems with more than one CPU. If you have 1310 a system with only one CPU, say N. If you have a system with more 1311 than one CPU, say Y. 1312 1313 If you say N here, the kernel will run on uni- and multiprocessor 1314 machines, but will use only one CPU of a multiprocessor machine. If 1315 you say Y here, the kernel will run on many, but not all, 1316 uniprocessor machines. On a uniprocessor machine, the kernel 1317 will run faster if you say N here. 1318 1319 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1320 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1321 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1322 1323 If you don't know what to do here, say N. 1324 1325config SMP_ON_UP 1326 bool "Allow booting SMP kernel on uniprocessor systems" 1327 depends on SMP && !XIP_KERNEL && MMU 1328 default y 1329 help 1330 SMP kernels contain instructions which fail on non-SMP processors. 1331 Enabling this option allows the kernel to modify itself to make 1332 these instructions safe. Disabling it allows about 1K of space 1333 savings. 1334 1335 If you don't know what to do here, say Y. 1336 1337config ARM_CPU_TOPOLOGY 1338 bool "Support cpu topology definition" 1339 depends on SMP && CPU_V7 1340 default y 1341 help 1342 Support ARM cpu topology definition. The MPIDR register defines 1343 affinity between processors which is then used to describe the cpu 1344 topology of an ARM System. 1345 1346config SCHED_MC 1347 bool "Multi-core scheduler support" 1348 depends on ARM_CPU_TOPOLOGY 1349 help 1350 Multi-core scheduler support improves the CPU scheduler's decision 1351 making when dealing with multi-core CPU chips at a cost of slightly 1352 increased overhead in some places. If unsure say N here. 1353 1354config SCHED_SMT 1355 bool "SMT scheduler support" 1356 depends on ARM_CPU_TOPOLOGY 1357 help 1358 Improves the CPU scheduler's decision making when dealing with 1359 MultiThreading at a cost of slightly increased overhead in some 1360 places. If unsure say N here. 1361 1362config HAVE_ARM_SCU 1363 bool 1364 help 1365 This option enables support for the ARM system coherency unit 1366 1367config HAVE_ARM_ARCH_TIMER 1368 bool "Architected timer support" 1369 depends on CPU_V7 1370 select ARM_ARCH_TIMER 1371 select GENERIC_CLOCKEVENTS 1372 help 1373 This option enables support for the ARM architected timer 1374 1375config HAVE_ARM_TWD 1376 bool 1377 select CLKSRC_OF if OF 1378 help 1379 This options enables support for the ARM timer and watchdog unit 1380 1381config MCPM 1382 bool "Multi-Cluster Power Management" 1383 depends on CPU_V7 && SMP 1384 help 1385 This option provides the common power management infrastructure 1386 for (multi-)cluster based systems, such as big.LITTLE based 1387 systems. 1388 1389config MCPM_QUAD_CLUSTER 1390 bool 1391 depends on MCPM 1392 help 1393 To avoid wasting resources unnecessarily, MCPM only supports up 1394 to 2 clusters by default. 1395 Platforms with 3 or 4 clusters that use MCPM must select this 1396 option to allow the additional clusters to be managed. 1397 1398config BIG_LITTLE 1399 bool "big.LITTLE support (Experimental)" 1400 depends on CPU_V7 && SMP 1401 select MCPM 1402 help 1403 This option enables support selections for the big.LITTLE 1404 system architecture. 1405 1406config BL_SWITCHER 1407 bool "big.LITTLE switcher support" 1408 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU 1409 select ARM_CPU_SUSPEND 1410 select CPU_PM 1411 help 1412 The big.LITTLE "switcher" provides the core functionality to 1413 transparently handle transition between a cluster of A15's 1414 and a cluster of A7's in a big.LITTLE system. 1415 1416config BL_SWITCHER_DUMMY_IF 1417 tristate "Simple big.LITTLE switcher user interface" 1418 depends on BL_SWITCHER && DEBUG_KERNEL 1419 help 1420 This is a simple and dummy char dev interface to control 1421 the big.LITTLE switcher core code. It is meant for 1422 debugging purposes only. 1423 1424choice 1425 prompt "Memory split" 1426 depends on MMU 1427 default VMSPLIT_3G 1428 help 1429 Select the desired split between kernel and user memory. 1430 1431 If you are not absolutely sure what you are doing, leave this 1432 option alone! 1433 1434 config VMSPLIT_3G 1435 bool "3G/1G user/kernel split" 1436 config VMSPLIT_3G_OPT 1437 bool "3G/1G user/kernel split (for full 1G low memory)" 1438 config VMSPLIT_2G 1439 bool "2G/2G user/kernel split" 1440 config VMSPLIT_1G 1441 bool "1G/3G user/kernel split" 1442endchoice 1443 1444config PAGE_OFFSET 1445 hex 1446 default PHYS_OFFSET if !MMU 1447 default 0x40000000 if VMSPLIT_1G 1448 default 0x80000000 if VMSPLIT_2G 1449 default 0xB0000000 if VMSPLIT_3G_OPT 1450 default 0xC0000000 1451 1452config NR_CPUS 1453 int "Maximum number of CPUs (2-32)" 1454 range 2 32 1455 depends on SMP 1456 default "4" 1457 1458config HOTPLUG_CPU 1459 bool "Support for hot-pluggable CPUs" 1460 depends on SMP 1461 help 1462 Say Y here to experiment with turning CPUs off and on. CPUs 1463 can be controlled through /sys/devices/system/cpu. 1464 1465config ARM_PSCI 1466 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1467 depends on CPU_V7 1468 select ARM_PSCI_FW 1469 help 1470 Say Y here if you want Linux to communicate with system firmware 1471 implementing the PSCI specification for CPU-centric power 1472 management operations described in ARM document number ARM DEN 1473 0022A ("Power State Coordination Interface System Software on 1474 ARM processors"). 1475 1476# The GPIO number here must be sorted by descending number. In case of 1477# a multiplatform kernel, we just want the highest value required by the 1478# selected platforms. 1479config ARCH_NR_GPIO 1480 int 1481 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1482 ARCH_ZYNQ 1483 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1484 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1485 default 416 if ARCH_SUNXI 1486 default 392 if ARCH_U8500 1487 default 352 if ARCH_VT8500 1488 default 288 if ARCH_ROCKCHIP 1489 default 264 if MACH_H4700 1490 default 0 1491 help 1492 Maximum number of GPIOs in the system. 1493 1494 If unsure, leave the default value. 1495 1496source kernel/Kconfig.preempt 1497 1498config HZ_FIXED 1499 int 1500 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1501 ARCH_S5PV210 || ARCH_EXYNOS4 1502 default 128 if SOC_AT91RM9200 1503 default 0 1504 1505choice 1506 depends on HZ_FIXED = 0 1507 prompt "Timer frequency" 1508 1509config HZ_100 1510 bool "100 Hz" 1511 1512config HZ_200 1513 bool "200 Hz" 1514 1515config HZ_250 1516 bool "250 Hz" 1517 1518config HZ_300 1519 bool "300 Hz" 1520 1521config HZ_500 1522 bool "500 Hz" 1523 1524config HZ_1000 1525 bool "1000 Hz" 1526 1527endchoice 1528 1529config HZ 1530 int 1531 default HZ_FIXED if HZ_FIXED != 0 1532 default 100 if HZ_100 1533 default 200 if HZ_200 1534 default 250 if HZ_250 1535 default 300 if HZ_300 1536 default 500 if HZ_500 1537 default 1000 1538 1539config SCHED_HRTICK 1540 def_bool HIGH_RES_TIMERS 1541 1542config THUMB2_KERNEL 1543 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1544 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1545 default y if CPU_THUMBONLY 1546 select AEABI 1547 select ARM_ASM_UNIFIED 1548 select ARM_UNWIND 1549 help 1550 By enabling this option, the kernel will be compiled in 1551 Thumb-2 mode. A compiler/assembler that understand the unified 1552 ARM-Thumb syntax is needed. 1553 1554 If unsure, say N. 1555 1556config THUMB2_AVOID_R_ARM_THM_JUMP11 1557 bool "Work around buggy Thumb-2 short branch relocations in gas" 1558 depends on THUMB2_KERNEL && MODULES 1559 default y 1560 help 1561 Various binutils versions can resolve Thumb-2 branches to 1562 locally-defined, preemptible global symbols as short-range "b.n" 1563 branch instructions. 1564 1565 This is a problem, because there's no guarantee the final 1566 destination of the symbol, or any candidate locations for a 1567 trampoline, are within range of the branch. For this reason, the 1568 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1569 relocation in modules at all, and it makes little sense to add 1570 support. 1571 1572 The symptom is that the kernel fails with an "unsupported 1573 relocation" error when loading some modules. 1574 1575 Until fixed tools are available, passing 1576 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1577 code which hits this problem, at the cost of a bit of extra runtime 1578 stack usage in some cases. 1579 1580 The problem is described in more detail at: 1581 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1582 1583 Only Thumb-2 kernels are affected. 1584 1585 Unless you are sure your tools don't have this problem, say Y. 1586 1587config ARM_ASM_UNIFIED 1588 bool 1589 1590config AEABI 1591 bool "Use the ARM EABI to compile the kernel" 1592 help 1593 This option allows for the kernel to be compiled using the latest 1594 ARM ABI (aka EABI). This is only useful if you are using a user 1595 space environment that is also compiled with EABI. 1596 1597 Since there are major incompatibilities between the legacy ABI and 1598 EABI, especially with regard to structure member alignment, this 1599 option also changes the kernel syscall calling convention to 1600 disambiguate both ABIs and allow for backward compatibility support 1601 (selected with CONFIG_OABI_COMPAT). 1602 1603 To use this you need GCC version 4.0.0 or later. 1604 1605config OABI_COMPAT 1606 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1607 depends on AEABI && !THUMB2_KERNEL 1608 help 1609 This option preserves the old syscall interface along with the 1610 new (ARM EABI) one. It also provides a compatibility layer to 1611 intercept syscalls that have structure arguments which layout 1612 in memory differs between the legacy ABI and the new ARM EABI 1613 (only for non "thumb" binaries). This option adds a tiny 1614 overhead to all syscalls and produces a slightly larger kernel. 1615 1616 The seccomp filter system will not be available when this is 1617 selected, since there is no way yet to sensibly distinguish 1618 between calling conventions during filtering. 1619 1620 If you know you'll be using only pure EABI user space then you 1621 can say N here. If this option is not selected and you attempt 1622 to execute a legacy ABI binary then the result will be 1623 UNPREDICTABLE (in fact it can be predicted that it won't work 1624 at all). If in doubt say N. 1625 1626config ARCH_HAS_HOLES_MEMORYMODEL 1627 bool 1628 1629config ARCH_SPARSEMEM_ENABLE 1630 bool 1631 1632config ARCH_SPARSEMEM_DEFAULT 1633 def_bool ARCH_SPARSEMEM_ENABLE 1634 1635config ARCH_SELECT_MEMORY_MODEL 1636 def_bool ARCH_SPARSEMEM_ENABLE 1637 1638config HAVE_ARCH_PFN_VALID 1639 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1640 1641config HAVE_GENERIC_RCU_GUP 1642 def_bool y 1643 depends on ARM_LPAE 1644 1645config HIGHMEM 1646 bool "High Memory Support" 1647 depends on MMU 1648 help 1649 The address space of ARM processors is only 4 Gigabytes large 1650 and it has to accommodate user address space, kernel address 1651 space as well as some memory mapped IO. That means that, if you 1652 have a large amount of physical memory and/or IO, not all of the 1653 memory can be "permanently mapped" by the kernel. The physical 1654 memory that is not permanently mapped is called "high memory". 1655 1656 Depending on the selected kernel/user memory split, minimum 1657 vmalloc space and actual amount of RAM, you may not need this 1658 option which should result in a slightly faster kernel. 1659 1660 If unsure, say n. 1661 1662config HIGHPTE 1663 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1664 depends on HIGHMEM 1665 default y 1666 help 1667 The VM uses one page of physical memory for each page table. 1668 For systems with a lot of processes, this can use a lot of 1669 precious low memory, eventually leading to low memory being 1670 consumed by page tables. Setting this option will allow 1671 user-space 2nd level page tables to reside in high memory. 1672 1673config CPU_SW_DOMAIN_PAN 1674 bool "Enable use of CPU domains to implement privileged no-access" 1675 depends on MMU && !ARM_LPAE 1676 default y 1677 help 1678 Increase kernel security by ensuring that normal kernel accesses 1679 are unable to access userspace addresses. This can help prevent 1680 use-after-free bugs becoming an exploitable privilege escalation 1681 by ensuring that magic values (such as LIST_POISON) will always 1682 fault when dereferenced. 1683 1684 CPUs with low-vector mappings use a best-efforts implementation. 1685 Their lower 1MB needs to remain accessible for the vectors, but 1686 the remainder of userspace will become appropriately inaccessible. 1687 1688config HW_PERF_EVENTS 1689 def_bool y 1690 depends on ARM_PMU 1691 1692config SYS_SUPPORTS_HUGETLBFS 1693 def_bool y 1694 depends on ARM_LPAE 1695 1696config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1697 def_bool y 1698 depends on ARM_LPAE 1699 1700config ARCH_WANT_GENERAL_HUGETLB 1701 def_bool y 1702 1703config ARM_MODULE_PLTS 1704 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1705 depends on MODULES 1706 help 1707 Allocate PLTs when loading modules so that jumps and calls whose 1708 targets are too far away for their relative offsets to be encoded 1709 in the instructions themselves can be bounced via veneers in the 1710 module's PLT. This allows modules to be allocated in the generic 1711 vmalloc area after the dedicated module memory area has been 1712 exhausted. The modules will use slightly more memory, but after 1713 rounding up to page size, the actual memory footprint is usually 1714 the same. 1715 1716 Say y if you are getting out of memory errors while loading modules 1717 1718source "mm/Kconfig" 1719 1720config FORCE_MAX_ZONEORDER 1721 int "Maximum zone order" 1722 default "12" if SOC_AM33XX 1723 default "9" if SA1111 || ARCH_EFM32 1724 default "11" 1725 help 1726 The kernel memory allocator divides physically contiguous memory 1727 blocks into "zones", where each zone is a power of two number of 1728 pages. This option selects the largest power of two that the kernel 1729 keeps in the memory allocator. If you need to allocate very large 1730 blocks of physically contiguous memory, then you may need to 1731 increase this value. 1732 1733 This config option is actually maximum order plus one. For example, 1734 a value of 11 means that the largest free memory block is 2^10 pages. 1735 1736config ALIGNMENT_TRAP 1737 bool 1738 depends on CPU_CP15_MMU 1739 default y if !ARCH_EBSA110 1740 select HAVE_PROC_CPU if PROC_FS 1741 help 1742 ARM processors cannot fetch/store information which is not 1743 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1744 address divisible by 4. On 32-bit ARM processors, these non-aligned 1745 fetch/store instructions will be emulated in software if you say 1746 here, which has a severe performance impact. This is necessary for 1747 correct operation of some network protocols. With an IP-only 1748 configuration it is safe to say N, otherwise say Y. 1749 1750config UACCESS_WITH_MEMCPY 1751 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1752 depends on MMU 1753 default y if CPU_FEROCEON 1754 help 1755 Implement faster copy_to_user and clear_user methods for CPU 1756 cores where a 8-word STM instruction give significantly higher 1757 memory write throughput than a sequence of individual 32bit stores. 1758 1759 A possible side effect is a slight increase in scheduling latency 1760 between threads sharing the same address space if they invoke 1761 such copy operations with large buffers. 1762 1763 However, if the CPU data cache is using a write-allocate mode, 1764 this option is unlikely to provide any performance gain. 1765 1766config SECCOMP 1767 bool 1768 prompt "Enable seccomp to safely compute untrusted bytecode" 1769 ---help--- 1770 This kernel feature is useful for number crunching applications 1771 that may need to compute untrusted bytecode during their 1772 execution. By using pipes or other transports made available to 1773 the process as file descriptors supporting the read/write 1774 syscalls, it's possible to isolate those applications in 1775 their own address space using seccomp. Once seccomp is 1776 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1777 and the task is only allowed to execute a few safe syscalls 1778 defined by each seccomp mode. 1779 1780config SWIOTLB 1781 def_bool y 1782 1783config IOMMU_HELPER 1784 def_bool SWIOTLB 1785 1786config XEN_DOM0 1787 def_bool y 1788 depends on XEN 1789 1790config XEN 1791 bool "Xen guest support on ARM" 1792 depends on ARM && AEABI && OF 1793 depends on CPU_V7 && !CPU_V6 1794 depends on !GENERIC_ATOMIC64 1795 depends on MMU 1796 select ARCH_DMA_ADDR_T_64BIT 1797 select ARM_PSCI 1798 select SWIOTLB_XEN 1799 help 1800 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1801 1802endmenu 1803 1804menu "Boot options" 1805 1806config USE_OF 1807 bool "Flattened Device Tree support" 1808 select IRQ_DOMAIN 1809 select OF 1810 help 1811 Include support for flattened device tree machine descriptions. 1812 1813config ATAGS 1814 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1815 default y 1816 help 1817 This is the traditional way of passing data to the kernel at boot 1818 time. If you are solely relying on the flattened device tree (or 1819 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1820 to remove ATAGS support from your kernel binary. If unsure, 1821 leave this to y. 1822 1823config DEPRECATED_PARAM_STRUCT 1824 bool "Provide old way to pass kernel parameters" 1825 depends on ATAGS 1826 help 1827 This was deprecated in 2001 and announced to live on for 5 years. 1828 Some old boot loaders still use this way. 1829 1830# Compressed boot loader in ROM. Yes, we really want to ask about 1831# TEXT and BSS so we preserve their values in the config files. 1832config ZBOOT_ROM_TEXT 1833 hex "Compressed ROM boot loader base address" 1834 default "0" 1835 help 1836 The physical address at which the ROM-able zImage is to be 1837 placed in the target. Platforms which normally make use of 1838 ROM-able zImage formats normally set this to a suitable 1839 value in their defconfig file. 1840 1841 If ZBOOT_ROM is not enabled, this has no effect. 1842 1843config ZBOOT_ROM_BSS 1844 hex "Compressed ROM boot loader BSS address" 1845 default "0" 1846 help 1847 The base address of an area of read/write memory in the target 1848 for the ROM-able zImage which must be available while the 1849 decompressor is running. It must be large enough to hold the 1850 entire decompressed kernel plus an additional 128 KiB. 1851 Platforms which normally make use of ROM-able zImage formats 1852 normally set this to a suitable value in their defconfig file. 1853 1854 If ZBOOT_ROM is not enabled, this has no effect. 1855 1856config ZBOOT_ROM 1857 bool "Compressed boot loader in ROM/flash" 1858 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1859 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1860 help 1861 Say Y here if you intend to execute your compressed kernel image 1862 (zImage) directly from ROM or flash. If unsure, say N. 1863 1864config ARM_APPENDED_DTB 1865 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1866 depends on OF 1867 help 1868 With this option, the boot code will look for a device tree binary 1869 (DTB) appended to zImage 1870 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1871 1872 This is meant as a backward compatibility convenience for those 1873 systems with a bootloader that can't be upgraded to accommodate 1874 the documented boot protocol using a device tree. 1875 1876 Beware that there is very little in terms of protection against 1877 this option being confused by leftover garbage in memory that might 1878 look like a DTB header after a reboot if no actual DTB is appended 1879 to zImage. Do not leave this option active in a production kernel 1880 if you don't intend to always append a DTB. Proper passing of the 1881 location into r2 of a bootloader provided DTB is always preferable 1882 to this option. 1883 1884config ARM_ATAG_DTB_COMPAT 1885 bool "Supplement the appended DTB with traditional ATAG information" 1886 depends on ARM_APPENDED_DTB 1887 help 1888 Some old bootloaders can't be updated to a DTB capable one, yet 1889 they provide ATAGs with memory configuration, the ramdisk address, 1890 the kernel cmdline string, etc. Such information is dynamically 1891 provided by the bootloader and can't always be stored in a static 1892 DTB. To allow a device tree enabled kernel to be used with such 1893 bootloaders, this option allows zImage to extract the information 1894 from the ATAG list and store it at run time into the appended DTB. 1895 1896choice 1897 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1898 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1899 1900config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1901 bool "Use bootloader kernel arguments if available" 1902 help 1903 Uses the command-line options passed by the boot loader instead of 1904 the device tree bootargs property. If the boot loader doesn't provide 1905 any, the device tree bootargs property will be used. 1906 1907config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1908 bool "Extend with bootloader kernel arguments" 1909 help 1910 The command-line arguments provided by the boot loader will be 1911 appended to the the device tree bootargs property. 1912 1913endchoice 1914 1915config CMDLINE 1916 string "Default kernel command string" 1917 default "" 1918 help 1919 On some architectures (EBSA110 and CATS), there is currently no way 1920 for the boot loader to pass arguments to the kernel. For these 1921 architectures, you should supply some command-line options at build 1922 time by entering them here. As a minimum, you should specify the 1923 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1924 1925choice 1926 prompt "Kernel command line type" if CMDLINE != "" 1927 default CMDLINE_FROM_BOOTLOADER 1928 depends on ATAGS 1929 1930config CMDLINE_FROM_BOOTLOADER 1931 bool "Use bootloader kernel arguments if available" 1932 help 1933 Uses the command-line options passed by the boot loader. If 1934 the boot loader doesn't provide any, the default kernel command 1935 string provided in CMDLINE will be used. 1936 1937config CMDLINE_EXTEND 1938 bool "Extend bootloader kernel arguments" 1939 help 1940 The command-line arguments provided by the boot loader will be 1941 appended to the default kernel command string. 1942 1943config CMDLINE_FORCE 1944 bool "Always use the default kernel command string" 1945 help 1946 Always use the default kernel command string, even if the boot 1947 loader passes other arguments to the kernel. 1948 This is useful if you cannot or don't want to change the 1949 command-line options your boot loader passes to the kernel. 1950endchoice 1951 1952config XIP_KERNEL 1953 bool "Kernel Execute-In-Place from ROM" 1954 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1955 help 1956 Execute-In-Place allows the kernel to run from non-volatile storage 1957 directly addressable by the CPU, such as NOR flash. This saves RAM 1958 space since the text section of the kernel is not loaded from flash 1959 to RAM. Read-write sections, such as the data section and stack, 1960 are still copied to RAM. The XIP kernel is not compressed since 1961 it has to run directly from flash, so it will take more space to 1962 store it. The flash address used to link the kernel object files, 1963 and for storing it, is configuration dependent. Therefore, if you 1964 say Y here, you must know the proper physical address where to 1965 store the kernel image depending on your own flash memory usage. 1966 1967 Also note that the make target becomes "make xipImage" rather than 1968 "make zImage" or "make Image". The final kernel binary to put in 1969 ROM memory will be arch/arm/boot/xipImage. 1970 1971 If unsure, say N. 1972 1973config XIP_PHYS_ADDR 1974 hex "XIP Kernel Physical Location" 1975 depends on XIP_KERNEL 1976 default "0x00080000" 1977 help 1978 This is the physical address in your flash memory the kernel will 1979 be linked for and stored to. This address is dependent on your 1980 own flash usage. 1981 1982config KEXEC 1983 bool "Kexec system call (EXPERIMENTAL)" 1984 depends on (!SMP || PM_SLEEP_SMP) 1985 depends on !CPU_V7M 1986 select KEXEC_CORE 1987 help 1988 kexec is a system call that implements the ability to shutdown your 1989 current kernel, and to start another kernel. It is like a reboot 1990 but it is independent of the system firmware. And like a reboot 1991 you can start any kernel with it, not just Linux. 1992 1993 It is an ongoing process to be certain the hardware in a machine 1994 is properly shutdown, so do not be surprised if this code does not 1995 initially work for you. 1996 1997config ATAGS_PROC 1998 bool "Export atags in procfs" 1999 depends on ATAGS && KEXEC 2000 default y 2001 help 2002 Should the atags used to boot the kernel be exported in an "atags" 2003 file in procfs. Useful with kexec. 2004 2005config CRASH_DUMP 2006 bool "Build kdump crash kernel (EXPERIMENTAL)" 2007 help 2008 Generate crash dump after being started by kexec. This should 2009 be normally only set in special crash dump kernels which are 2010 loaded in the main kernel with kexec-tools into a specially 2011 reserved region and then later executed after a crash by 2012 kdump/kexec. The crash dump kernel must be compiled to a 2013 memory address not used by the main kernel 2014 2015 For more details see Documentation/kdump/kdump.txt 2016 2017config AUTO_ZRELADDR 2018 bool "Auto calculation of the decompressed kernel image address" 2019 help 2020 ZRELADDR is the physical address where the decompressed kernel 2021 image will be placed. If AUTO_ZRELADDR is selected, the address 2022 will be determined at run-time by masking the current IP with 2023 0xf8000000. This assumes the zImage being placed in the first 128MB 2024 from start of memory. 2025 2026endmenu 2027 2028menu "CPU Power Management" 2029 2030source "drivers/cpufreq/Kconfig" 2031 2032source "drivers/cpuidle/Kconfig" 2033 2034endmenu 2035 2036menu "Floating point emulation" 2037 2038comment "At least one emulation must be selected" 2039 2040config FPE_NWFPE 2041 bool "NWFPE math emulation" 2042 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2043 ---help--- 2044 Say Y to include the NWFPE floating point emulator in the kernel. 2045 This is necessary to run most binaries. Linux does not currently 2046 support floating point hardware so you need to say Y here even if 2047 your machine has an FPA or floating point co-processor podule. 2048 2049 You may say N here if you are going to load the Acorn FPEmulator 2050 early in the bootup. 2051 2052config FPE_NWFPE_XP 2053 bool "Support extended precision" 2054 depends on FPE_NWFPE 2055 help 2056 Say Y to include 80-bit support in the kernel floating-point 2057 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2058 Note that gcc does not generate 80-bit operations by default, 2059 so in most cases this option only enlarges the size of the 2060 floating point emulator without any good reason. 2061 2062 You almost surely want to say N here. 2063 2064config FPE_FASTFPE 2065 bool "FastFPE math emulation (EXPERIMENTAL)" 2066 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2067 ---help--- 2068 Say Y here to include the FAST floating point emulator in the kernel. 2069 This is an experimental much faster emulator which now also has full 2070 precision for the mantissa. It does not support any exceptions. 2071 It is very simple, and approximately 3-6 times faster than NWFPE. 2072 2073 It should be sufficient for most programs. It may be not suitable 2074 for scientific calculations, but you have to check this for yourself. 2075 If you do not feel you need a faster FP emulation you should better 2076 choose NWFPE. 2077 2078config VFP 2079 bool "VFP-format floating point maths" 2080 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2081 help 2082 Say Y to include VFP support code in the kernel. This is needed 2083 if your hardware includes a VFP unit. 2084 2085 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2086 release notes and additional status information. 2087 2088 Say N if your target does not have VFP hardware. 2089 2090config VFPv3 2091 bool 2092 depends on VFP 2093 default y if CPU_V7 2094 2095config NEON 2096 bool "Advanced SIMD (NEON) Extension support" 2097 depends on VFPv3 && CPU_V7 2098 help 2099 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2100 Extension. 2101 2102config KERNEL_MODE_NEON 2103 bool "Support for NEON in kernel mode" 2104 depends on NEON && AEABI 2105 help 2106 Say Y to include support for NEON in kernel mode. 2107 2108endmenu 2109 2110menu "Userspace binary formats" 2111 2112source "fs/Kconfig.binfmt" 2113 2114endmenu 2115 2116menu "Power management options" 2117 2118source "kernel/power/Kconfig" 2119 2120config ARCH_SUSPEND_POSSIBLE 2121 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2122 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2123 def_bool y 2124 2125config ARM_CPU_SUSPEND 2126 def_bool PM_SLEEP 2127 2128config ARCH_HIBERNATION_POSSIBLE 2129 bool 2130 depends on MMU 2131 default y if ARCH_SUSPEND_POSSIBLE 2132 2133endmenu 2134 2135source "net/Kconfig" 2136 2137source "drivers/Kconfig" 2138 2139source "drivers/firmware/Kconfig" 2140 2141source "fs/Kconfig" 2142 2143source "arch/arm/Kconfig.debug" 2144 2145source "security/Kconfig" 2146 2147source "crypto/Kconfig" 2148if CRYPTO 2149source "arch/arm/crypto/Kconfig" 2150endif 2151 2152source "lib/Kconfig" 2153 2154source "arch/arm/kvm/Kconfig" 2155