1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if !XIP_KERNEL 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select HAVE_GENERIC_DMA_COHERENT 20 select HAVE_KERNEL_GZIP 21 select HAVE_KERNEL_LZO 22 select HAVE_KERNEL_LZMA 23 select HAVE_IRQ_WORK 24 select HAVE_PERF_EVENTS 25 select PERF_USE_VMALLOC 26 select HAVE_REGS_AND_STACK_ACCESS_API 27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 28 select HAVE_C_RECORDMCOUNT 29 select HAVE_GENERIC_HARDIRQS 30 select HAVE_SPARSE_IRQ 31 select GENERIC_IRQ_SHOW 32 select CPU_PM if (SUSPEND || CPU_IDLE) 33 help 34 The ARM series is a line of low-power-consumption RISC chip designs 35 licensed by ARM Ltd and targeted at embedded applications and 36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 37 manufactured, but legacy ARM-based PC hardware remains popular in 38 Europe. There is an ARM Linux project with a web page at 39 <http://www.arm.linux.org.uk/>. 40 41config ARM_HAS_SG_CHAIN 42 bool 43 44config HAVE_PWM 45 bool 46 47config MIGHT_HAVE_PCI 48 bool 49 50config SYS_SUPPORTS_APM_EMULATION 51 bool 52 53config HAVE_SCHED_CLOCK 54 bool 55 56config GENERIC_GPIO 57 bool 58 59config ARCH_USES_GETTIMEOFFSET 60 bool 61 default n 62 63config GENERIC_CLOCKEVENTS 64 bool 65 66config GENERIC_CLOCKEVENTS_BROADCAST 67 bool 68 depends on GENERIC_CLOCKEVENTS 69 default y if SMP 70 71config KTIME_SCALAR 72 bool 73 default y 74 75config HAVE_TCM 76 bool 77 select GENERIC_ALLOCATOR 78 79config HAVE_PROC_CPU 80 bool 81 82config NO_IOPORT 83 bool 84 85config EISA 86 bool 87 ---help--- 88 The Extended Industry Standard Architecture (EISA) bus was 89 developed as an open alternative to the IBM MicroChannel bus. 90 91 The EISA bus provided some of the features of the IBM MicroChannel 92 bus while maintaining backward compatibility with cards made for 93 the older ISA bus. The EISA bus saw limited use between 1988 and 94 1995 when it was made obsolete by the PCI bus. 95 96 Say Y here if you are building a kernel for an EISA-based machine. 97 98 Otherwise, say N. 99 100config SBUS 101 bool 102 103config MCA 104 bool 105 help 106 MicroChannel Architecture is found in some IBM PS/2 machines and 107 laptops. It is a bus system similar to PCI or ISA. See 108 <file:Documentation/mca.txt> (and especially the web page given 109 there) before attempting to build an MCA bus kernel. 110 111config STACKTRACE_SUPPORT 112 bool 113 default y 114 115config HAVE_LATENCYTOP_SUPPORT 116 bool 117 depends on !SMP 118 default y 119 120config LOCKDEP_SUPPORT 121 bool 122 default y 123 124config TRACE_IRQFLAGS_SUPPORT 125 bool 126 default y 127 128config HARDIRQS_SW_RESEND 129 bool 130 default y 131 132config GENERIC_IRQ_PROBE 133 bool 134 default y 135 136config GENERIC_LOCKBREAK 137 bool 138 default y 139 depends on SMP && PREEMPT 140 141config RWSEM_GENERIC_SPINLOCK 142 bool 143 default y 144 145config RWSEM_XCHGADD_ALGORITHM 146 bool 147 148config ARCH_HAS_ILOG2_U32 149 bool 150 151config ARCH_HAS_ILOG2_U64 152 bool 153 154config ARCH_HAS_CPUFREQ 155 bool 156 help 157 Internal node to signify that the ARCH has CPUFREQ support 158 and that the relevant menu configurations are displayed for 159 it. 160 161config ARCH_HAS_CPU_IDLE_WAIT 162 def_bool y 163 164config GENERIC_HWEIGHT 165 bool 166 default y 167 168config GENERIC_CALIBRATE_DELAY 169 bool 170 default y 171 172config ARCH_MAY_HAVE_PC_FDC 173 bool 174 175config ZONE_DMA 176 bool 177 178config NEED_DMA_MAP_STATE 179 def_bool y 180 181config GENERIC_ISA_DMA 182 bool 183 184config FIQ 185 bool 186 187config ARCH_MTD_XIP 188 bool 189 190config VECTORS_BASE 191 hex 192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 193 default DRAM_BASE if REMAP_VECTORS_TO_RAM 194 default 0x00000000 195 help 196 The base address of exception vectors. 197 198config ARM_PATCH_PHYS_VIRT 199 bool "Patch physical to virtual translations at runtime" if EMBEDDED 200 default y 201 depends on !XIP_KERNEL && MMU 202 depends on !ARCH_REALVIEW || !SPARSEMEM 203 help 204 Patch phys-to-virt and virt-to-phys translation functions at 205 boot and module load time according to the position of the 206 kernel in system memory. 207 208 This can only be used with non-XIP MMU kernels where the base 209 of physical memory is at a 16MB boundary. 210 211 Only disable this option if you know that you do not require 212 this feature (eg, building a kernel for a single machine) and 213 you need to shrink the kernel to the minimal size. 214 215config NEED_MACH_MEMORY_H 216 bool 217 help 218 Select this when mach/memory.h is required to provide special 219 definitions for this platform. The need for mach/memory.h should 220 be avoided when possible. 221 222config PHYS_OFFSET 223 hex "Physical address of main memory" 224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 225 help 226 Please provide the physical address corresponding to the 227 location of main memory in your system. 228 229config GENERIC_BUG 230 def_bool y 231 depends on BUG 232 233source "init/Kconfig" 234 235source "kernel/Kconfig.freezer" 236 237menu "System Type" 238 239config MMU 240 bool "MMU-based Paged Memory Management Support" 241 default y 242 help 243 Select if you want MMU-based virtualised addressing space 244 support by paged memory management. If unsure, say 'Y'. 245 246# 247# The "ARM system type" choice list is ordered alphabetically by option 248# text. Please add new entries in the option alphabetic order. 249# 250choice 251 prompt "ARM system type" 252 default ARCH_VERSATILE 253 254config ARCH_INTEGRATOR 255 bool "ARM Ltd. Integrator family" 256 select ARM_AMBA 257 select ARCH_HAS_CPUFREQ 258 select CLKDEV_LOOKUP 259 select HAVE_MACH_CLKDEV 260 select ICST 261 select GENERIC_CLOCKEVENTS 262 select PLAT_VERSATILE 263 select PLAT_VERSATILE_FPGA_IRQ 264 select NEED_MACH_MEMORY_H 265 help 266 Support for ARM's Integrator platform. 267 268config ARCH_REALVIEW 269 bool "ARM Ltd. RealView family" 270 select ARM_AMBA 271 select CLKDEV_LOOKUP 272 select HAVE_MACH_CLKDEV 273 select ICST 274 select GENERIC_CLOCKEVENTS 275 select ARCH_WANT_OPTIONAL_GPIOLIB 276 select PLAT_VERSATILE 277 select PLAT_VERSATILE_CLCD 278 select ARM_TIMER_SP804 279 select GPIO_PL061 if GPIOLIB 280 select NEED_MACH_MEMORY_H 281 help 282 This enables support for ARM Ltd RealView boards. 283 284config ARCH_VERSATILE 285 bool "ARM Ltd. Versatile family" 286 select ARM_AMBA 287 select ARM_VIC 288 select CLKDEV_LOOKUP 289 select HAVE_MACH_CLKDEV 290 select ICST 291 select GENERIC_CLOCKEVENTS 292 select ARCH_WANT_OPTIONAL_GPIOLIB 293 select PLAT_VERSATILE 294 select PLAT_VERSATILE_CLCD 295 select PLAT_VERSATILE_FPGA_IRQ 296 select ARM_TIMER_SP804 297 help 298 This enables support for ARM Ltd Versatile board. 299 300config ARCH_VEXPRESS 301 bool "ARM Ltd. Versatile Express family" 302 select ARCH_WANT_OPTIONAL_GPIOLIB 303 select ARM_AMBA 304 select ARM_TIMER_SP804 305 select CLKDEV_LOOKUP 306 select HAVE_MACH_CLKDEV 307 select GENERIC_CLOCKEVENTS 308 select HAVE_CLK 309 select HAVE_PATA_PLATFORM 310 select ICST 311 select PLAT_VERSATILE 312 select PLAT_VERSATILE_CLCD 313 help 314 This enables support for the ARM Ltd Versatile Express boards. 315 316config ARCH_AT91 317 bool "Atmel AT91" 318 select ARCH_REQUIRE_GPIOLIB 319 select HAVE_CLK 320 select CLKDEV_LOOKUP 321 help 322 This enables support for systems based on the Atmel AT91RM9200, 323 AT91SAM9 and AT91CAP9 processors. 324 325config ARCH_BCMRING 326 bool "Broadcom BCMRING" 327 depends on MMU 328 select CPU_V6 329 select ARM_AMBA 330 select ARM_TIMER_SP804 331 select CLKDEV_LOOKUP 332 select GENERIC_CLOCKEVENTS 333 select ARCH_WANT_OPTIONAL_GPIOLIB 334 help 335 Support for Broadcom's BCMRing platform. 336 337config ARCH_HIGHBANK 338 bool "Calxeda Highbank-based" 339 select ARCH_WANT_OPTIONAL_GPIOLIB 340 select ARM_AMBA 341 select ARM_GIC 342 select ARM_TIMER_SP804 343 select CLKDEV_LOOKUP 344 select CPU_V7 345 select GENERIC_CLOCKEVENTS 346 select HAVE_ARM_SCU 347 select USE_OF 348 help 349 Support for the Calxeda Highbank SoC based boards. 350 351config ARCH_CLPS711X 352 bool "Cirrus Logic CLPS711x/EP721x-based" 353 select CPU_ARM720T 354 select ARCH_USES_GETTIMEOFFSET 355 select NEED_MACH_MEMORY_H 356 help 357 Support for Cirrus Logic 711x/721x based boards. 358 359config ARCH_CNS3XXX 360 bool "Cavium Networks CNS3XXX family" 361 select CPU_V6K 362 select GENERIC_CLOCKEVENTS 363 select ARM_GIC 364 select MIGHT_HAVE_PCI 365 select PCI_DOMAINS if PCI 366 help 367 Support for Cavium Networks CNS3XXX platform. 368 369config ARCH_GEMINI 370 bool "Cortina Systems Gemini" 371 select CPU_FA526 372 select ARCH_REQUIRE_GPIOLIB 373 select ARCH_USES_GETTIMEOFFSET 374 help 375 Support for the Cortina Systems Gemini family SoCs 376 377config ARCH_PRIMA2 378 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 379 select CPU_V7 380 select NO_IOPORT 381 select GENERIC_CLOCKEVENTS 382 select CLKDEV_LOOKUP 383 select GENERIC_IRQ_CHIP 384 select USE_OF 385 select ZONE_DMA 386 help 387 Support for CSR SiRFSoC ARM Cortex A9 Platform 388 389config ARCH_EBSA110 390 bool "EBSA-110" 391 select CPU_SA110 392 select ISA 393 select NO_IOPORT 394 select ARCH_USES_GETTIMEOFFSET 395 select NEED_MACH_MEMORY_H 396 help 397 This is an evaluation board for the StrongARM processor available 398 from Digital. It has limited hardware on-board, including an 399 Ethernet interface, two PCMCIA sockets, two serial ports and a 400 parallel port. 401 402config ARCH_EP93XX 403 bool "EP93xx-based" 404 select CPU_ARM920T 405 select ARM_AMBA 406 select ARM_VIC 407 select CLKDEV_LOOKUP 408 select ARCH_REQUIRE_GPIOLIB 409 select ARCH_HAS_HOLES_MEMORYMODEL 410 select ARCH_USES_GETTIMEOFFSET 411 select NEED_MACH_MEMORY_H 412 help 413 This enables support for the Cirrus EP93xx series of CPUs. 414 415config ARCH_FOOTBRIDGE 416 bool "FootBridge" 417 select CPU_SA110 418 select FOOTBRIDGE 419 select GENERIC_CLOCKEVENTS 420 select HAVE_IDE 421 select NEED_MACH_MEMORY_H 422 help 423 Support for systems based on the DC21285 companion chip 424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 425 426config ARCH_MXC 427 bool "Freescale MXC/iMX-based" 428 select GENERIC_CLOCKEVENTS 429 select ARCH_REQUIRE_GPIOLIB 430 select CLKDEV_LOOKUP 431 select CLKSRC_MMIO 432 select GENERIC_IRQ_CHIP 433 select HAVE_SCHED_CLOCK 434 select MULTI_IRQ_HANDLER 435 help 436 Support for Freescale MXC/iMX-based family of processors 437 438config ARCH_MXS 439 bool "Freescale MXS-based" 440 select GENERIC_CLOCKEVENTS 441 select ARCH_REQUIRE_GPIOLIB 442 select CLKDEV_LOOKUP 443 select CLKSRC_MMIO 444 help 445 Support for Freescale MXS-based family of processors 446 447config ARCH_NETX 448 bool "Hilscher NetX based" 449 select CLKSRC_MMIO 450 select CPU_ARM926T 451 select ARM_VIC 452 select GENERIC_CLOCKEVENTS 453 help 454 This enables support for systems based on the Hilscher NetX Soc 455 456config ARCH_H720X 457 bool "Hynix HMS720x-based" 458 select CPU_ARM720T 459 select ISA_DMA_API 460 select ARCH_USES_GETTIMEOFFSET 461 help 462 This enables support for systems based on the Hynix HMS720x 463 464config ARCH_IOP13XX 465 bool "IOP13xx-based" 466 depends on MMU 467 select CPU_XSC3 468 select PLAT_IOP 469 select PCI 470 select ARCH_SUPPORTS_MSI 471 select VMSPLIT_1G 472 select NEED_MACH_MEMORY_H 473 help 474 Support for Intel's IOP13XX (XScale) family of processors. 475 476config ARCH_IOP32X 477 bool "IOP32x-based" 478 depends on MMU 479 select CPU_XSCALE 480 select PLAT_IOP 481 select PCI 482 select ARCH_REQUIRE_GPIOLIB 483 help 484 Support for Intel's 80219 and IOP32X (XScale) family of 485 processors. 486 487config ARCH_IOP33X 488 bool "IOP33x-based" 489 depends on MMU 490 select CPU_XSCALE 491 select PLAT_IOP 492 select PCI 493 select ARCH_REQUIRE_GPIOLIB 494 help 495 Support for Intel's IOP33X (XScale) family of processors. 496 497config ARCH_IXP23XX 498 bool "IXP23XX-based" 499 depends on MMU 500 select CPU_XSC3 501 select PCI 502 select ARCH_USES_GETTIMEOFFSET 503 select NEED_MACH_MEMORY_H 504 help 505 Support for Intel's IXP23xx (XScale) family of processors. 506 507config ARCH_IXP2000 508 bool "IXP2400/2800-based" 509 depends on MMU 510 select CPU_XSCALE 511 select PCI 512 select ARCH_USES_GETTIMEOFFSET 513 select NEED_MACH_MEMORY_H 514 help 515 Support for Intel's IXP2400/2800 (XScale) family of processors. 516 517config ARCH_IXP4XX 518 bool "IXP4xx-based" 519 depends on MMU 520 select CLKSRC_MMIO 521 select CPU_XSCALE 522 select GENERIC_GPIO 523 select GENERIC_CLOCKEVENTS 524 select HAVE_SCHED_CLOCK 525 select MIGHT_HAVE_PCI 526 select DMABOUNCE if PCI 527 help 528 Support for Intel's IXP4XX (XScale) family of processors. 529 530config ARCH_DOVE 531 bool "Marvell Dove" 532 select CPU_V7 533 select PCI 534 select ARCH_REQUIRE_GPIOLIB 535 select GENERIC_CLOCKEVENTS 536 select PLAT_ORION 537 help 538 Support for the Marvell Dove SoC 88AP510 539 540config ARCH_KIRKWOOD 541 bool "Marvell Kirkwood" 542 select CPU_FEROCEON 543 select PCI 544 select ARCH_REQUIRE_GPIOLIB 545 select GENERIC_CLOCKEVENTS 546 select PLAT_ORION 547 help 548 Support for the following Marvell Kirkwood series SoCs: 549 88F6180, 88F6192 and 88F6281. 550 551config ARCH_LPC32XX 552 bool "NXP LPC32XX" 553 select CLKSRC_MMIO 554 select CPU_ARM926T 555 select ARCH_REQUIRE_GPIOLIB 556 select HAVE_IDE 557 select ARM_AMBA 558 select USB_ARCH_HAS_OHCI 559 select CLKDEV_LOOKUP 560 select GENERIC_CLOCKEVENTS 561 help 562 Support for the NXP LPC32XX family of processors 563 564config ARCH_MV78XX0 565 bool "Marvell MV78xx0" 566 select CPU_FEROCEON 567 select PCI 568 select ARCH_REQUIRE_GPIOLIB 569 select GENERIC_CLOCKEVENTS 570 select PLAT_ORION 571 help 572 Support for the following Marvell MV78xx0 series SoCs: 573 MV781x0, MV782x0. 574 575config ARCH_ORION5X 576 bool "Marvell Orion" 577 depends on MMU 578 select CPU_FEROCEON 579 select PCI 580 select ARCH_REQUIRE_GPIOLIB 581 select GENERIC_CLOCKEVENTS 582 select PLAT_ORION 583 help 584 Support for the following Marvell Orion 5x series SoCs: 585 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 586 Orion-2 (5281), Orion-1-90 (6183). 587 588config ARCH_MMP 589 bool "Marvell PXA168/910/MMP2" 590 depends on MMU 591 select ARCH_REQUIRE_GPIOLIB 592 select CLKDEV_LOOKUP 593 select GENERIC_CLOCKEVENTS 594 select HAVE_SCHED_CLOCK 595 select TICK_ONESHOT 596 select PLAT_PXA 597 select SPARSE_IRQ 598 select GENERIC_ALLOCATOR 599 help 600 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 601 602config ARCH_KS8695 603 bool "Micrel/Kendin KS8695" 604 select CPU_ARM922T 605 select ARCH_REQUIRE_GPIOLIB 606 select ARCH_USES_GETTIMEOFFSET 607 select NEED_MACH_MEMORY_H 608 help 609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 610 System-on-Chip devices. 611 612config ARCH_W90X900 613 bool "Nuvoton W90X900 CPU" 614 select CPU_ARM926T 615 select ARCH_REQUIRE_GPIOLIB 616 select CLKDEV_LOOKUP 617 select CLKSRC_MMIO 618 select GENERIC_CLOCKEVENTS 619 help 620 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 621 At present, the w90x900 has been renamed nuc900, regarding 622 the ARM series product line, you can login the following 623 link address to know more. 624 625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 627 628config ARCH_TEGRA 629 bool "NVIDIA Tegra" 630 select CLKDEV_LOOKUP 631 select CLKSRC_MMIO 632 select GENERIC_CLOCKEVENTS 633 select GENERIC_GPIO 634 select HAVE_CLK 635 select HAVE_SCHED_CLOCK 636 select ARCH_HAS_CPUFREQ 637 help 638 This enables support for NVIDIA Tegra based systems (Tegra APX, 639 Tegra 6xx and Tegra 2 series). 640 641config ARCH_PICOXCELL 642 bool "Picochip picoXcell" 643 select ARCH_REQUIRE_GPIOLIB 644 select ARM_PATCH_PHYS_VIRT 645 select ARM_VIC 646 select CPU_V6K 647 select DW_APB_TIMER 648 select GENERIC_CLOCKEVENTS 649 select GENERIC_GPIO 650 select HAVE_SCHED_CLOCK 651 select HAVE_TCM 652 select NO_IOPORT 653 select USE_OF 654 help 655 This enables support for systems based on the Picochip picoXcell 656 family of Femtocell devices. The picoxcell support requires device tree 657 for all boards. 658 659config ARCH_PNX4008 660 bool "Philips Nexperia PNX4008 Mobile" 661 select CPU_ARM926T 662 select CLKDEV_LOOKUP 663 select ARCH_USES_GETTIMEOFFSET 664 help 665 This enables support for Philips PNX4008 mobile platform. 666 667config ARCH_PXA 668 bool "PXA2xx/PXA3xx-based" 669 depends on MMU 670 select ARCH_MTD_XIP 671 select ARCH_HAS_CPUFREQ 672 select CLKDEV_LOOKUP 673 select CLKSRC_MMIO 674 select ARCH_REQUIRE_GPIOLIB 675 select GENERIC_CLOCKEVENTS 676 select HAVE_SCHED_CLOCK 677 select TICK_ONESHOT 678 select PLAT_PXA 679 select SPARSE_IRQ 680 select AUTO_ZRELADDR 681 select MULTI_IRQ_HANDLER 682 select ARM_CPU_SUSPEND if PM 683 select HAVE_IDE 684 help 685 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 686 687config ARCH_MSM 688 bool "Qualcomm MSM" 689 select HAVE_CLK 690 select GENERIC_CLOCKEVENTS 691 select ARCH_REQUIRE_GPIOLIB 692 select CLKDEV_LOOKUP 693 help 694 Support for Qualcomm MSM/QSD based systems. This runs on the 695 apps processor of the MSM/QSD and depends on a shared memory 696 interface to the modem processor which runs the baseband 697 stack and controls some vital subsystems 698 (clock and power control, etc). 699 700config ARCH_SHMOBILE 701 bool "Renesas SH-Mobile / R-Mobile" 702 select HAVE_CLK 703 select CLKDEV_LOOKUP 704 select HAVE_MACH_CLKDEV 705 select GENERIC_CLOCKEVENTS 706 select NO_IOPORT 707 select SPARSE_IRQ 708 select MULTI_IRQ_HANDLER 709 select PM_GENERIC_DOMAINS if PM 710 select NEED_MACH_MEMORY_H 711 help 712 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 713 714config ARCH_RPC 715 bool "RiscPC" 716 select ARCH_ACORN 717 select FIQ 718 select TIMER_ACORN 719 select ARCH_MAY_HAVE_PC_FDC 720 select HAVE_PATA_PLATFORM 721 select ISA_DMA_API 722 select NO_IOPORT 723 select ARCH_SPARSEMEM_ENABLE 724 select ARCH_USES_GETTIMEOFFSET 725 select HAVE_IDE 726 select NEED_MACH_MEMORY_H 727 help 728 On the Acorn Risc-PC, Linux can support the internal IDE disk and 729 CD-ROM interface, serial and parallel port, and the floppy drive. 730 731config ARCH_SA1100 732 bool "SA1100-based" 733 select CLKSRC_MMIO 734 select CPU_SA1100 735 select ISA 736 select ARCH_SPARSEMEM_ENABLE 737 select ARCH_MTD_XIP 738 select ARCH_HAS_CPUFREQ 739 select CPU_FREQ 740 select GENERIC_CLOCKEVENTS 741 select HAVE_CLK 742 select HAVE_SCHED_CLOCK 743 select TICK_ONESHOT 744 select ARCH_REQUIRE_GPIOLIB 745 select HAVE_IDE 746 select NEED_MACH_MEMORY_H 747 help 748 Support for StrongARM 11x0 based boards. 749 750config ARCH_S3C2410 751 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 752 select GENERIC_GPIO 753 select ARCH_HAS_CPUFREQ 754 select HAVE_CLK 755 select CLKDEV_LOOKUP 756 select ARCH_USES_GETTIMEOFFSET 757 select HAVE_S3C2410_I2C if I2C 758 help 759 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 760 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 761 the Samsung SMDK2410 development board (and derivatives). 762 763 Note, the S3C2416 and the S3C2450 are so close that they even share 764 the same SoC ID code. This means that there is no separate machine 765 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 766 767config ARCH_S3C64XX 768 bool "Samsung S3C64XX" 769 select PLAT_SAMSUNG 770 select CPU_V6 771 select ARM_VIC 772 select HAVE_CLK 773 select HAVE_TCM 774 select CLKDEV_LOOKUP 775 select NO_IOPORT 776 select ARCH_USES_GETTIMEOFFSET 777 select ARCH_HAS_CPUFREQ 778 select ARCH_REQUIRE_GPIOLIB 779 select SAMSUNG_CLKSRC 780 select SAMSUNG_IRQ_VIC_TIMER 781 select S3C_GPIO_TRACK 782 select S3C_DEV_NAND 783 select USB_ARCH_HAS_OHCI 784 select SAMSUNG_GPIOLIB_4BIT 785 select HAVE_S3C2410_I2C if I2C 786 select HAVE_S3C2410_WATCHDOG if WATCHDOG 787 help 788 Samsung S3C64XX series based systems 789 790config ARCH_S5P64X0 791 bool "Samsung S5P6440 S5P6450" 792 select CPU_V6 793 select GENERIC_GPIO 794 select HAVE_CLK 795 select CLKDEV_LOOKUP 796 select CLKSRC_MMIO 797 select HAVE_S3C2410_WATCHDOG if WATCHDOG 798 select GENERIC_CLOCKEVENTS 799 select HAVE_SCHED_CLOCK 800 select HAVE_S3C2410_I2C if I2C 801 select HAVE_S3C_RTC if RTC_CLASS 802 help 803 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 804 SMDK6450. 805 806config ARCH_S5PC100 807 bool "Samsung S5PC100" 808 select GENERIC_GPIO 809 select HAVE_CLK 810 select CLKDEV_LOOKUP 811 select CPU_V7 812 select ARM_L1_CACHE_SHIFT_6 813 select ARCH_USES_GETTIMEOFFSET 814 select HAVE_S3C2410_I2C if I2C 815 select HAVE_S3C_RTC if RTC_CLASS 816 select HAVE_S3C2410_WATCHDOG if WATCHDOG 817 help 818 Samsung S5PC100 series based systems 819 820config ARCH_S5PV210 821 bool "Samsung S5PV210/S5PC110" 822 select CPU_V7 823 select ARCH_SPARSEMEM_ENABLE 824 select ARCH_HAS_HOLES_MEMORYMODEL 825 select GENERIC_GPIO 826 select HAVE_CLK 827 select CLKDEV_LOOKUP 828 select CLKSRC_MMIO 829 select ARM_L1_CACHE_SHIFT_6 830 select ARCH_HAS_CPUFREQ 831 select GENERIC_CLOCKEVENTS 832 select HAVE_SCHED_CLOCK 833 select HAVE_S3C2410_I2C if I2C 834 select HAVE_S3C_RTC if RTC_CLASS 835 select HAVE_S3C2410_WATCHDOG if WATCHDOG 836 select NEED_MACH_MEMORY_H 837 help 838 Samsung S5PV210/S5PC110 series based systems 839 840config ARCH_EXYNOS 841 bool "SAMSUNG EXYNOS" 842 select CPU_V7 843 select ARCH_SPARSEMEM_ENABLE 844 select ARCH_HAS_HOLES_MEMORYMODEL 845 select GENERIC_GPIO 846 select HAVE_CLK 847 select CLKDEV_LOOKUP 848 select ARCH_HAS_CPUFREQ 849 select GENERIC_CLOCKEVENTS 850 select HAVE_S3C_RTC if RTC_CLASS 851 select HAVE_S3C2410_I2C if I2C 852 select HAVE_S3C2410_WATCHDOG if WATCHDOG 853 select NEED_MACH_MEMORY_H 854 help 855 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 856 857config ARCH_SHARK 858 bool "Shark" 859 select CPU_SA110 860 select ISA 861 select ISA_DMA 862 select ZONE_DMA 863 select PCI 864 select ARCH_USES_GETTIMEOFFSET 865 select NEED_MACH_MEMORY_H 866 help 867 Support for the StrongARM based Digital DNARD machine, also known 868 as "Shark" (<http://www.shark-linux.de/shark.html>). 869 870config ARCH_TCC_926 871 bool "Telechips TCC ARM926-based systems" 872 select CLKSRC_MMIO 873 select CPU_ARM926T 874 select HAVE_CLK 875 select CLKDEV_LOOKUP 876 select GENERIC_CLOCKEVENTS 877 help 878 Support for Telechips TCC ARM926-based systems. 879 880config ARCH_U300 881 bool "ST-Ericsson U300 Series" 882 depends on MMU 883 select CLKSRC_MMIO 884 select CPU_ARM926T 885 select HAVE_SCHED_CLOCK 886 select HAVE_TCM 887 select ARM_AMBA 888 select ARM_PATCH_PHYS_VIRT 889 select ARM_VIC 890 select GENERIC_CLOCKEVENTS 891 select CLKDEV_LOOKUP 892 select HAVE_MACH_CLKDEV 893 select GENERIC_GPIO 894 select ARCH_REQUIRE_GPIOLIB 895 select NEED_MACH_MEMORY_H 896 help 897 Support for ST-Ericsson U300 series mobile platforms. 898 899config ARCH_U8500 900 bool "ST-Ericsson U8500 Series" 901 select CPU_V7 902 select ARM_AMBA 903 select GENERIC_CLOCKEVENTS 904 select CLKDEV_LOOKUP 905 select ARCH_REQUIRE_GPIOLIB 906 select ARCH_HAS_CPUFREQ 907 help 908 Support for ST-Ericsson's Ux500 architecture 909 910config ARCH_NOMADIK 911 bool "STMicroelectronics Nomadik" 912 select ARM_AMBA 913 select ARM_VIC 914 select CPU_ARM926T 915 select CLKDEV_LOOKUP 916 select GENERIC_CLOCKEVENTS 917 select ARCH_REQUIRE_GPIOLIB 918 help 919 Support for the Nomadik platform by ST-Ericsson 920 921config ARCH_DAVINCI 922 bool "TI DaVinci" 923 select GENERIC_CLOCKEVENTS 924 select ARCH_REQUIRE_GPIOLIB 925 select ZONE_DMA 926 select HAVE_IDE 927 select CLKDEV_LOOKUP 928 select GENERIC_ALLOCATOR 929 select GENERIC_IRQ_CHIP 930 select ARCH_HAS_HOLES_MEMORYMODEL 931 help 932 Support for TI's DaVinci platform. 933 934config ARCH_OMAP 935 bool "TI OMAP" 936 select HAVE_CLK 937 select ARCH_REQUIRE_GPIOLIB 938 select ARCH_HAS_CPUFREQ 939 select CLKSRC_MMIO 940 select GENERIC_CLOCKEVENTS 941 select HAVE_SCHED_CLOCK 942 select ARCH_HAS_HOLES_MEMORYMODEL 943 help 944 Support for TI's OMAP platform (OMAP1/2/3/4). 945 946config PLAT_SPEAR 947 bool "ST SPEAr" 948 select ARM_AMBA 949 select ARCH_REQUIRE_GPIOLIB 950 select CLKDEV_LOOKUP 951 select CLKSRC_MMIO 952 select GENERIC_CLOCKEVENTS 953 select HAVE_CLK 954 help 955 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 956 957config ARCH_VT8500 958 bool "VIA/WonderMedia 85xx" 959 select CPU_ARM926T 960 select GENERIC_GPIO 961 select ARCH_HAS_CPUFREQ 962 select GENERIC_CLOCKEVENTS 963 select ARCH_REQUIRE_GPIOLIB 964 select HAVE_PWM 965 help 966 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 967 968config ARCH_ZYNQ 969 bool "Xilinx Zynq ARM Cortex A9 Platform" 970 select CPU_V7 971 select GENERIC_CLOCKEVENTS 972 select CLKDEV_LOOKUP 973 select ARM_GIC 974 select ARM_AMBA 975 select ICST 976 select USE_OF 977 help 978 Support for Xilinx Zynq ARM Cortex A9 Platform 979endchoice 980 981# 982# This is sorted alphabetically by mach-* pathname. However, plat-* 983# Kconfigs may be included either alphabetically (according to the 984# plat- suffix) or along side the corresponding mach-* source. 985# 986source "arch/arm/mach-at91/Kconfig" 987 988source "arch/arm/mach-bcmring/Kconfig" 989 990source "arch/arm/mach-clps711x/Kconfig" 991 992source "arch/arm/mach-cns3xxx/Kconfig" 993 994source "arch/arm/mach-davinci/Kconfig" 995 996source "arch/arm/mach-dove/Kconfig" 997 998source "arch/arm/mach-ep93xx/Kconfig" 999 1000source "arch/arm/mach-footbridge/Kconfig" 1001 1002source "arch/arm/mach-gemini/Kconfig" 1003 1004source "arch/arm/mach-h720x/Kconfig" 1005 1006source "arch/arm/mach-integrator/Kconfig" 1007 1008source "arch/arm/mach-iop32x/Kconfig" 1009 1010source "arch/arm/mach-iop33x/Kconfig" 1011 1012source "arch/arm/mach-iop13xx/Kconfig" 1013 1014source "arch/arm/mach-ixp4xx/Kconfig" 1015 1016source "arch/arm/mach-ixp2000/Kconfig" 1017 1018source "arch/arm/mach-ixp23xx/Kconfig" 1019 1020source "arch/arm/mach-kirkwood/Kconfig" 1021 1022source "arch/arm/mach-ks8695/Kconfig" 1023 1024source "arch/arm/mach-lpc32xx/Kconfig" 1025 1026source "arch/arm/mach-msm/Kconfig" 1027 1028source "arch/arm/mach-mv78xx0/Kconfig" 1029 1030source "arch/arm/plat-mxc/Kconfig" 1031 1032source "arch/arm/mach-mxs/Kconfig" 1033 1034source "arch/arm/mach-netx/Kconfig" 1035 1036source "arch/arm/mach-nomadik/Kconfig" 1037source "arch/arm/plat-nomadik/Kconfig" 1038 1039source "arch/arm/plat-omap/Kconfig" 1040 1041source "arch/arm/mach-omap1/Kconfig" 1042 1043source "arch/arm/mach-omap2/Kconfig" 1044 1045source "arch/arm/mach-orion5x/Kconfig" 1046 1047source "arch/arm/mach-pxa/Kconfig" 1048source "arch/arm/plat-pxa/Kconfig" 1049 1050source "arch/arm/mach-mmp/Kconfig" 1051 1052source "arch/arm/mach-realview/Kconfig" 1053 1054source "arch/arm/mach-sa1100/Kconfig" 1055 1056source "arch/arm/plat-samsung/Kconfig" 1057source "arch/arm/plat-s3c24xx/Kconfig" 1058source "arch/arm/plat-s5p/Kconfig" 1059 1060source "arch/arm/plat-spear/Kconfig" 1061 1062source "arch/arm/plat-tcc/Kconfig" 1063 1064if ARCH_S3C2410 1065source "arch/arm/mach-s3c2410/Kconfig" 1066source "arch/arm/mach-s3c2412/Kconfig" 1067source "arch/arm/mach-s3c2416/Kconfig" 1068source "arch/arm/mach-s3c2440/Kconfig" 1069source "arch/arm/mach-s3c2443/Kconfig" 1070endif 1071 1072if ARCH_S3C64XX 1073source "arch/arm/mach-s3c64xx/Kconfig" 1074endif 1075 1076source "arch/arm/mach-s5p64x0/Kconfig" 1077 1078source "arch/arm/mach-s5pc100/Kconfig" 1079 1080source "arch/arm/mach-s5pv210/Kconfig" 1081 1082source "arch/arm/mach-exynos/Kconfig" 1083 1084source "arch/arm/mach-shmobile/Kconfig" 1085 1086source "arch/arm/mach-tegra/Kconfig" 1087 1088source "arch/arm/mach-u300/Kconfig" 1089 1090source "arch/arm/mach-ux500/Kconfig" 1091 1092source "arch/arm/mach-versatile/Kconfig" 1093 1094source "arch/arm/mach-vexpress/Kconfig" 1095source "arch/arm/plat-versatile/Kconfig" 1096 1097source "arch/arm/mach-vt8500/Kconfig" 1098 1099source "arch/arm/mach-w90x900/Kconfig" 1100 1101# Definitions to make life easier 1102config ARCH_ACORN 1103 bool 1104 1105config PLAT_IOP 1106 bool 1107 select GENERIC_CLOCKEVENTS 1108 select HAVE_SCHED_CLOCK 1109 1110config PLAT_ORION 1111 bool 1112 select CLKSRC_MMIO 1113 select GENERIC_IRQ_CHIP 1114 select HAVE_SCHED_CLOCK 1115 1116config PLAT_PXA 1117 bool 1118 1119config PLAT_VERSATILE 1120 bool 1121 1122config ARM_TIMER_SP804 1123 bool 1124 select CLKSRC_MMIO 1125 1126source arch/arm/mm/Kconfig 1127 1128config IWMMXT 1129 bool "Enable iWMMXt support" 1130 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1131 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1132 help 1133 Enable support for iWMMXt context switching at run time if 1134 running on a CPU that supports it. 1135 1136# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 1137config XSCALE_PMU 1138 bool 1139 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 1140 default y 1141 1142config CPU_HAS_PMU 1143 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1144 (!ARCH_OMAP3 || OMAP3_EMU) 1145 default y 1146 bool 1147 1148config MULTI_IRQ_HANDLER 1149 bool 1150 help 1151 Allow each machine to specify it's own IRQ handler at run time. 1152 1153if !MMU 1154source "arch/arm/Kconfig-nommu" 1155endif 1156 1157config ARM_ERRATA_411920 1158 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1159 depends on CPU_V6 || CPU_V6K 1160 help 1161 Invalidation of the Instruction Cache operation can 1162 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1163 It does not affect the MPCore. This option enables the ARM Ltd. 1164 recommended workaround. 1165 1166config ARM_ERRATA_430973 1167 bool "ARM errata: Stale prediction on replaced interworking branch" 1168 depends on CPU_V7 1169 help 1170 This option enables the workaround for the 430973 Cortex-A8 1171 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1172 interworking branch is replaced with another code sequence at the 1173 same virtual address, whether due to self-modifying code or virtual 1174 to physical address re-mapping, Cortex-A8 does not recover from the 1175 stale interworking branch prediction. This results in Cortex-A8 1176 executing the new code sequence in the incorrect ARM or Thumb state. 1177 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1178 and also flushes the branch target cache at every context switch. 1179 Note that setting specific bits in the ACTLR register may not be 1180 available in non-secure mode. 1181 1182config ARM_ERRATA_458693 1183 bool "ARM errata: Processor deadlock when a false hazard is created" 1184 depends on CPU_V7 1185 help 1186 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1187 erratum. For very specific sequences of memory operations, it is 1188 possible for a hazard condition intended for a cache line to instead 1189 be incorrectly associated with a different cache line. This false 1190 hazard might then cause a processor deadlock. The workaround enables 1191 the L1 caching of the NEON accesses and disables the PLD instruction 1192 in the ACTLR register. Note that setting specific bits in the ACTLR 1193 register may not be available in non-secure mode. 1194 1195config ARM_ERRATA_460075 1196 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1197 depends on CPU_V7 1198 help 1199 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1200 erratum. Any asynchronous access to the L2 cache may encounter a 1201 situation in which recent store transactions to the L2 cache are lost 1202 and overwritten with stale memory contents from external memory. The 1203 workaround disables the write-allocate mode for the L2 cache via the 1204 ACTLR register. Note that setting specific bits in the ACTLR register 1205 may not be available in non-secure mode. 1206 1207config ARM_ERRATA_742230 1208 bool "ARM errata: DMB operation may be faulty" 1209 depends on CPU_V7 && SMP 1210 help 1211 This option enables the workaround for the 742230 Cortex-A9 1212 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1213 between two write operations may not ensure the correct visibility 1214 ordering of the two writes. This workaround sets a specific bit in 1215 the diagnostic register of the Cortex-A9 which causes the DMB 1216 instruction to behave as a DSB, ensuring the correct behaviour of 1217 the two writes. 1218 1219config ARM_ERRATA_742231 1220 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1221 depends on CPU_V7 && SMP 1222 help 1223 This option enables the workaround for the 742231 Cortex-A9 1224 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1225 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1226 accessing some data located in the same cache line, may get corrupted 1227 data due to bad handling of the address hazard when the line gets 1228 replaced from one of the CPUs at the same time as another CPU is 1229 accessing it. This workaround sets specific bits in the diagnostic 1230 register of the Cortex-A9 which reduces the linefill issuing 1231 capabilities of the processor. 1232 1233config PL310_ERRATA_588369 1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1235 depends on CACHE_L2X0 1236 help 1237 The PL310 L2 cache controller implements three types of Clean & 1238 Invalidate maintenance operations: by Physical Address 1239 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1240 They are architecturally defined to behave as the execution of a 1241 clean operation followed immediately by an invalidate operation, 1242 both performing to the same memory location. This functionality 1243 is not correctly implemented in PL310 as clean lines are not 1244 invalidated as a result of these operations. 1245 1246config ARM_ERRATA_720789 1247 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1248 depends on CPU_V7 && SMP 1249 help 1250 This option enables the workaround for the 720789 Cortex-A9 (prior to 1251 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1252 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1253 As a consequence of this erratum, some TLB entries which should be 1254 invalidated are not, resulting in an incoherency in the system page 1255 tables. The workaround changes the TLB flushing routines to invalidate 1256 entries regardless of the ASID. 1257 1258config PL310_ERRATA_727915 1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1260 depends on CACHE_L2X0 1261 help 1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1263 operation (offset 0x7FC). This operation runs in background so that 1264 PL310 can handle normal accesses while it is in progress. Under very 1265 rare circumstances, due to this erratum, write data can be lost when 1266 PL310 treats a cacheable write transaction during a Clean & 1267 Invalidate by Way operation. 1268 1269config ARM_ERRATA_743622 1270 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1271 depends on CPU_V7 1272 help 1273 This option enables the workaround for the 743622 Cortex-A9 1274 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1275 optimisation in the Cortex-A9 Store Buffer may lead to data 1276 corruption. This workaround sets a specific bit in the diagnostic 1277 register of the Cortex-A9 which disables the Store Buffer 1278 optimisation, preventing the defect from occurring. This has no 1279 visible impact on the overall performance or power consumption of the 1280 processor. 1281 1282config ARM_ERRATA_751472 1283 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1284 depends on CPU_V7 && SMP 1285 help 1286 This option enables the workaround for the 751472 Cortex-A9 (prior 1287 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1288 completion of a following broadcasted operation if the second 1289 operation is received by a CPU before the ICIALLUIS has completed, 1290 potentially leading to corrupted entries in the cache or TLB. 1291 1292config PL310_ERRATA_753970 1293 bool "PL310 errata: cache sync operation may be faulty" 1294 depends on CACHE_PL310 1295 help 1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1297 1298 Under some condition the effect of cache sync operation on 1299 the store buffer still remains when the operation completes. 1300 This means that the store buffer is always asked to drain and 1301 this prevents it from merging any further writes. The workaround 1302 is to replace the normal offset of cache sync operation (0x730) 1303 by another offset targeting an unmapped PL310 register 0x740. 1304 This has the same effect as the cache sync operation: store buffer 1305 drain and waiting for all buffers empty. 1306 1307config ARM_ERRATA_754322 1308 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1309 depends on CPU_V7 1310 help 1311 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1312 r3p*) erratum. A speculative memory access may cause a page table walk 1313 which starts prior to an ASID switch but completes afterwards. This 1314 can populate the micro-TLB with a stale entry which may be hit with 1315 the new ASID. This workaround places two dsb instructions in the mm 1316 switching code so that no page table walks can cross the ASID switch. 1317 1318config ARM_ERRATA_754327 1319 bool "ARM errata: no automatic Store Buffer drain" 1320 depends on CPU_V7 && SMP 1321 help 1322 This option enables the workaround for the 754327 Cortex-A9 (prior to 1323 r2p0) erratum. The Store Buffer does not have any automatic draining 1324 mechanism and therefore a livelock may occur if an external agent 1325 continuously polls a memory location waiting to observe an update. 1326 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1327 written polling loops from denying visibility of updates to memory. 1328 1329config ARM_ERRATA_364296 1330 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1331 depends on CPU_V6 && !SMP 1332 help 1333 This options enables the workaround for the 364296 ARM1136 1334 r0p2 erratum (possible cache data corruption with 1335 hit-under-miss enabled). It sets the undocumented bit 31 in 1336 the auxiliary control register and the FI bit in the control 1337 register, thus disabling hit-under-miss without putting the 1338 processor into full low interrupt latency mode. ARM11MPCore 1339 is not affected. 1340 1341config ARM_ERRATA_764369 1342 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1343 depends on CPU_V7 && SMP 1344 help 1345 This option enables the workaround for erratum 764369 1346 affecting Cortex-A9 MPCore with two or more processors (all 1347 current revisions). Under certain timing circumstances, a data 1348 cache line maintenance operation by MVA targeting an Inner 1349 Shareable memory region may fail to proceed up to either the 1350 Point of Coherency or to the Point of Unification of the 1351 system. This workaround adds a DSB instruction before the 1352 relevant cache maintenance functions and sets a specific bit 1353 in the diagnostic control register of the SCU. 1354 1355config PL310_ERRATA_769419 1356 bool "PL310 errata: no automatic Store Buffer drain" 1357 depends on CACHE_L2X0 1358 help 1359 On revisions of the PL310 prior to r3p2, the Store Buffer does 1360 not automatically drain. This can cause normal, non-cacheable 1361 writes to be retained when the memory system is idle, leading 1362 to suboptimal I/O performance for drivers using coherent DMA. 1363 This option adds a write barrier to the cpu_idle loop so that, 1364 on systems with an outer cache, the store buffer is drained 1365 explicitly. 1366 1367endmenu 1368 1369source "arch/arm/common/Kconfig" 1370 1371menu "Bus support" 1372 1373config ARM_AMBA 1374 bool 1375 1376config ISA 1377 bool 1378 help 1379 Find out whether you have ISA slots on your motherboard. ISA is the 1380 name of a bus system, i.e. the way the CPU talks to the other stuff 1381 inside your box. Other bus systems are PCI, EISA, MicroChannel 1382 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1383 newer boards don't support it. If you have ISA, say Y, otherwise N. 1384 1385# Select ISA DMA controller support 1386config ISA_DMA 1387 bool 1388 select ISA_DMA_API 1389 1390# Select ISA DMA interface 1391config ISA_DMA_API 1392 bool 1393 1394config PCI 1395 bool "PCI support" if MIGHT_HAVE_PCI 1396 help 1397 Find out whether you have a PCI motherboard. PCI is the name of a 1398 bus system, i.e. the way the CPU talks to the other stuff inside 1399 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1400 VESA. If you have PCI, say Y, otherwise N. 1401 1402config PCI_DOMAINS 1403 bool 1404 depends on PCI 1405 1406config PCI_NANOENGINE 1407 bool "BSE nanoEngine PCI support" 1408 depends on SA1100_NANOENGINE 1409 help 1410 Enable PCI on the BSE nanoEngine board. 1411 1412config PCI_SYSCALL 1413 def_bool PCI 1414 1415# Select the host bridge type 1416config PCI_HOST_VIA82C505 1417 bool 1418 depends on PCI && ARCH_SHARK 1419 default y 1420 1421config PCI_HOST_ITE8152 1422 bool 1423 depends on PCI && MACH_ARMCORE 1424 default y 1425 select DMABOUNCE 1426 1427source "drivers/pci/Kconfig" 1428 1429source "drivers/pcmcia/Kconfig" 1430 1431endmenu 1432 1433menu "Kernel Features" 1434 1435source "kernel/time/Kconfig" 1436 1437config SMP 1438 bool "Symmetric Multi-Processing" 1439 depends on CPU_V6K || CPU_V7 1440 depends on GENERIC_CLOCKEVENTS 1441 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1442 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1443 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1444 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q 1445 depends on MMU 1446 select USE_GENERIC_SMP_HELPERS 1447 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1448 help 1449 This enables support for systems with more than one CPU. If you have 1450 a system with only one CPU, like most personal computers, say N. If 1451 you have a system with more than one CPU, say Y. 1452 1453 If you say N here, the kernel will run on single and multiprocessor 1454 machines, but will use only one CPU of a multiprocessor machine. If 1455 you say Y here, the kernel will run on many, but not all, single 1456 processor machines. On a single processor machine, the kernel will 1457 run faster if you say N here. 1458 1459 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1460 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1461 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1462 1463 If you don't know what to do here, say N. 1464 1465config SMP_ON_UP 1466 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1467 depends on EXPERIMENTAL 1468 depends on SMP && !XIP_KERNEL 1469 default y 1470 help 1471 SMP kernels contain instructions which fail on non-SMP processors. 1472 Enabling this option allows the kernel to modify itself to make 1473 these instructions safe. Disabling it allows about 1K of space 1474 savings. 1475 1476 If you don't know what to do here, say Y. 1477 1478config ARM_CPU_TOPOLOGY 1479 bool "Support cpu topology definition" 1480 depends on SMP && CPU_V7 1481 default y 1482 help 1483 Support ARM cpu topology definition. The MPIDR register defines 1484 affinity between processors which is then used to describe the cpu 1485 topology of an ARM System. 1486 1487config SCHED_MC 1488 bool "Multi-core scheduler support" 1489 depends on ARM_CPU_TOPOLOGY 1490 help 1491 Multi-core scheduler support improves the CPU scheduler's decision 1492 making when dealing with multi-core CPU chips at a cost of slightly 1493 increased overhead in some places. If unsure say N here. 1494 1495config SCHED_SMT 1496 bool "SMT scheduler support" 1497 depends on ARM_CPU_TOPOLOGY 1498 help 1499 Improves the CPU scheduler's decision making when dealing with 1500 MultiThreading at a cost of slightly increased overhead in some 1501 places. If unsure say N here. 1502 1503config HAVE_ARM_SCU 1504 bool 1505 help 1506 This option enables support for the ARM system coherency unit 1507 1508config HAVE_ARM_TWD 1509 bool 1510 depends on SMP 1511 select TICK_ONESHOT 1512 help 1513 This options enables support for the ARM timer and watchdog unit 1514 1515choice 1516 prompt "Memory split" 1517 default VMSPLIT_3G 1518 help 1519 Select the desired split between kernel and user memory. 1520 1521 If you are not absolutely sure what you are doing, leave this 1522 option alone! 1523 1524 config VMSPLIT_3G 1525 bool "3G/1G user/kernel split" 1526 config VMSPLIT_2G 1527 bool "2G/2G user/kernel split" 1528 config VMSPLIT_1G 1529 bool "1G/3G user/kernel split" 1530endchoice 1531 1532config PAGE_OFFSET 1533 hex 1534 default 0x40000000 if VMSPLIT_1G 1535 default 0x80000000 if VMSPLIT_2G 1536 default 0xC0000000 1537 1538config NR_CPUS 1539 int "Maximum number of CPUs (2-32)" 1540 range 2 32 1541 depends on SMP 1542 default "4" 1543 1544config HOTPLUG_CPU 1545 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1546 depends on SMP && HOTPLUG && EXPERIMENTAL 1547 help 1548 Say Y here to experiment with turning CPUs off and on. CPUs 1549 can be controlled through /sys/devices/system/cpu. 1550 1551config LOCAL_TIMERS 1552 bool "Use local timer interrupts" 1553 depends on SMP 1554 default y 1555 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1556 help 1557 Enable support for local timers on SMP platforms, rather then the 1558 legacy IPI broadcast method. Local timers allows the system 1559 accounting to be spread across the timer interval, preventing a 1560 "thundering herd" at every timer tick. 1561 1562source kernel/Kconfig.preempt 1563 1564config HZ 1565 int 1566 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1567 ARCH_S5PV210 || ARCH_EXYNOS4 1568 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1569 default AT91_TIMER_HZ if ARCH_AT91 1570 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1571 default 100 1572 1573config THUMB2_KERNEL 1574 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1575 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1576 select AEABI 1577 select ARM_ASM_UNIFIED 1578 select ARM_UNWIND 1579 help 1580 By enabling this option, the kernel will be compiled in 1581 Thumb-2 mode. A compiler/assembler that understand the unified 1582 ARM-Thumb syntax is needed. 1583 1584 If unsure, say N. 1585 1586config THUMB2_AVOID_R_ARM_THM_JUMP11 1587 bool "Work around buggy Thumb-2 short branch relocations in gas" 1588 depends on THUMB2_KERNEL && MODULES 1589 default y 1590 help 1591 Various binutils versions can resolve Thumb-2 branches to 1592 locally-defined, preemptible global symbols as short-range "b.n" 1593 branch instructions. 1594 1595 This is a problem, because there's no guarantee the final 1596 destination of the symbol, or any candidate locations for a 1597 trampoline, are within range of the branch. For this reason, the 1598 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1599 relocation in modules at all, and it makes little sense to add 1600 support. 1601 1602 The symptom is that the kernel fails with an "unsupported 1603 relocation" error when loading some modules. 1604 1605 Until fixed tools are available, passing 1606 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1607 code which hits this problem, at the cost of a bit of extra runtime 1608 stack usage in some cases. 1609 1610 The problem is described in more detail at: 1611 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1612 1613 Only Thumb-2 kernels are affected. 1614 1615 Unless you are sure your tools don't have this problem, say Y. 1616 1617config ARM_ASM_UNIFIED 1618 bool 1619 1620config AEABI 1621 bool "Use the ARM EABI to compile the kernel" 1622 help 1623 This option allows for the kernel to be compiled using the latest 1624 ARM ABI (aka EABI). This is only useful if you are using a user 1625 space environment that is also compiled with EABI. 1626 1627 Since there are major incompatibilities between the legacy ABI and 1628 EABI, especially with regard to structure member alignment, this 1629 option also changes the kernel syscall calling convention to 1630 disambiguate both ABIs and allow for backward compatibility support 1631 (selected with CONFIG_OABI_COMPAT). 1632 1633 To use this you need GCC version 4.0.0 or later. 1634 1635config OABI_COMPAT 1636 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1637 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1638 default y 1639 help 1640 This option preserves the old syscall interface along with the 1641 new (ARM EABI) one. It also provides a compatibility layer to 1642 intercept syscalls that have structure arguments which layout 1643 in memory differs between the legacy ABI and the new ARM EABI 1644 (only for non "thumb" binaries). This option adds a tiny 1645 overhead to all syscalls and produces a slightly larger kernel. 1646 If you know you'll be using only pure EABI user space then you 1647 can say N here. If this option is not selected and you attempt 1648 to execute a legacy ABI binary then the result will be 1649 UNPREDICTABLE (in fact it can be predicted that it won't work 1650 at all). If in doubt say Y. 1651 1652config ARCH_HAS_HOLES_MEMORYMODEL 1653 bool 1654 1655config ARCH_SPARSEMEM_ENABLE 1656 bool 1657 1658config ARCH_SPARSEMEM_DEFAULT 1659 def_bool ARCH_SPARSEMEM_ENABLE 1660 1661config ARCH_SELECT_MEMORY_MODEL 1662 def_bool ARCH_SPARSEMEM_ENABLE 1663 1664config HAVE_ARCH_PFN_VALID 1665 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1666 1667config HIGHMEM 1668 bool "High Memory Support" 1669 depends on MMU 1670 help 1671 The address space of ARM processors is only 4 Gigabytes large 1672 and it has to accommodate user address space, kernel address 1673 space as well as some memory mapped IO. That means that, if you 1674 have a large amount of physical memory and/or IO, not all of the 1675 memory can be "permanently mapped" by the kernel. The physical 1676 memory that is not permanently mapped is called "high memory". 1677 1678 Depending on the selected kernel/user memory split, minimum 1679 vmalloc space and actual amount of RAM, you may not need this 1680 option which should result in a slightly faster kernel. 1681 1682 If unsure, say n. 1683 1684config HIGHPTE 1685 bool "Allocate 2nd-level pagetables from highmem" 1686 depends on HIGHMEM 1687 1688config HW_PERF_EVENTS 1689 bool "Enable hardware performance counter support for perf events" 1690 depends on PERF_EVENTS && CPU_HAS_PMU 1691 default y 1692 help 1693 Enable hardware performance counter support for perf events. If 1694 disabled, perf events will use software events only. 1695 1696source "mm/Kconfig" 1697 1698config FORCE_MAX_ZONEORDER 1699 int "Maximum zone order" if ARCH_SHMOBILE 1700 range 11 64 if ARCH_SHMOBILE 1701 default "9" if SA1111 1702 default "11" 1703 help 1704 The kernel memory allocator divides physically contiguous memory 1705 blocks into "zones", where each zone is a power of two number of 1706 pages. This option selects the largest power of two that the kernel 1707 keeps in the memory allocator. If you need to allocate very large 1708 blocks of physically contiguous memory, then you may need to 1709 increase this value. 1710 1711 This config option is actually maximum order plus one. For example, 1712 a value of 11 means that the largest free memory block is 2^10 pages. 1713 1714config LEDS 1715 bool "Timer and CPU usage LEDs" 1716 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1717 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1718 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1719 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1720 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1721 ARCH_AT91 || ARCH_DAVINCI || \ 1722 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1723 help 1724 If you say Y here, the LEDs on your machine will be used 1725 to provide useful information about your current system status. 1726 1727 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1728 be able to select which LEDs are active using the options below. If 1729 you are compiling a kernel for the EBSA-110 or the LART however, the 1730 red LED will simply flash regularly to indicate that the system is 1731 still functional. It is safe to say Y here if you have a CATS 1732 system, but the driver will do nothing. 1733 1734config LEDS_TIMER 1735 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1736 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1737 || MACH_OMAP_PERSEUS2 1738 depends on LEDS 1739 depends on !GENERIC_CLOCKEVENTS 1740 default y if ARCH_EBSA110 1741 help 1742 If you say Y here, one of the system LEDs (the green one on the 1743 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1744 will flash regularly to indicate that the system is still 1745 operational. This is mainly useful to kernel hackers who are 1746 debugging unstable kernels. 1747 1748 The LART uses the same LED for both Timer LED and CPU usage LED 1749 functions. You may choose to use both, but the Timer LED function 1750 will overrule the CPU usage LED. 1751 1752config LEDS_CPU 1753 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1754 !ARCH_OMAP) \ 1755 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1756 || MACH_OMAP_PERSEUS2 1757 depends on LEDS 1758 help 1759 If you say Y here, the red LED will be used to give a good real 1760 time indication of CPU usage, by lighting whenever the idle task 1761 is not currently executing. 1762 1763 The LART uses the same LED for both Timer LED and CPU usage LED 1764 functions. You may choose to use both, but the Timer LED function 1765 will overrule the CPU usage LED. 1766 1767config ALIGNMENT_TRAP 1768 bool 1769 depends on CPU_CP15_MMU 1770 default y if !ARCH_EBSA110 1771 select HAVE_PROC_CPU if PROC_FS 1772 help 1773 ARM processors cannot fetch/store information which is not 1774 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1775 address divisible by 4. On 32-bit ARM processors, these non-aligned 1776 fetch/store instructions will be emulated in software if you say 1777 here, which has a severe performance impact. This is necessary for 1778 correct operation of some network protocols. With an IP-only 1779 configuration it is safe to say N, otherwise say Y. 1780 1781config UACCESS_WITH_MEMCPY 1782 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1783 depends on MMU && EXPERIMENTAL 1784 default y if CPU_FEROCEON 1785 help 1786 Implement faster copy_to_user and clear_user methods for CPU 1787 cores where a 8-word STM instruction give significantly higher 1788 memory write throughput than a sequence of individual 32bit stores. 1789 1790 A possible side effect is a slight increase in scheduling latency 1791 between threads sharing the same address space if they invoke 1792 such copy operations with large buffers. 1793 1794 However, if the CPU data cache is using a write-allocate mode, 1795 this option is unlikely to provide any performance gain. 1796 1797config SECCOMP 1798 bool 1799 prompt "Enable seccomp to safely compute untrusted bytecode" 1800 ---help--- 1801 This kernel feature is useful for number crunching applications 1802 that may need to compute untrusted bytecode during their 1803 execution. By using pipes or other transports made available to 1804 the process as file descriptors supporting the read/write 1805 syscalls, it's possible to isolate those applications in 1806 their own address space using seccomp. Once seccomp is 1807 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1808 and the task is only allowed to execute a few safe syscalls 1809 defined by each seccomp mode. 1810 1811config CC_STACKPROTECTOR 1812 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1813 depends on EXPERIMENTAL 1814 help 1815 This option turns on the -fstack-protector GCC feature. This 1816 feature puts, at the beginning of functions, a canary value on 1817 the stack just before the return address, and validates 1818 the value just before actually returning. Stack based buffer 1819 overflows (that need to overwrite this return address) now also 1820 overwrite the canary, which gets detected and the attack is then 1821 neutralized via a kernel panic. 1822 This feature requires gcc version 4.2 or above. 1823 1824config DEPRECATED_PARAM_STRUCT 1825 bool "Provide old way to pass kernel parameters" 1826 help 1827 This was deprecated in 2001 and announced to live on for 5 years. 1828 Some old boot loaders still use this way. 1829 1830endmenu 1831 1832menu "Boot options" 1833 1834config USE_OF 1835 bool "Flattened Device Tree support" 1836 select OF 1837 select OF_EARLY_FLATTREE 1838 select IRQ_DOMAIN 1839 help 1840 Include support for flattened device tree machine descriptions. 1841 1842# Compressed boot loader in ROM. Yes, we really want to ask about 1843# TEXT and BSS so we preserve their values in the config files. 1844config ZBOOT_ROM_TEXT 1845 hex "Compressed ROM boot loader base address" 1846 default "0" 1847 help 1848 The physical address at which the ROM-able zImage is to be 1849 placed in the target. Platforms which normally make use of 1850 ROM-able zImage formats normally set this to a suitable 1851 value in their defconfig file. 1852 1853 If ZBOOT_ROM is not enabled, this has no effect. 1854 1855config ZBOOT_ROM_BSS 1856 hex "Compressed ROM boot loader BSS address" 1857 default "0" 1858 help 1859 The base address of an area of read/write memory in the target 1860 for the ROM-able zImage which must be available while the 1861 decompressor is running. It must be large enough to hold the 1862 entire decompressed kernel plus an additional 128 KiB. 1863 Platforms which normally make use of ROM-able zImage formats 1864 normally set this to a suitable value in their defconfig file. 1865 1866 If ZBOOT_ROM is not enabled, this has no effect. 1867 1868config ZBOOT_ROM 1869 bool "Compressed boot loader in ROM/flash" 1870 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1871 help 1872 Say Y here if you intend to execute your compressed kernel image 1873 (zImage) directly from ROM or flash. If unsure, say N. 1874 1875choice 1876 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1877 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1878 default ZBOOT_ROM_NONE 1879 help 1880 Include experimental SD/MMC loading code in the ROM-able zImage. 1881 With this enabled it is possible to write the the ROM-able zImage 1882 kernel image to an MMC or SD card and boot the kernel straight 1883 from the reset vector. At reset the processor Mask ROM will load 1884 the first part of the the ROM-able zImage which in turn loads the 1885 rest the kernel image to RAM. 1886 1887config ZBOOT_ROM_NONE 1888 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1889 help 1890 Do not load image from SD or MMC 1891 1892config ZBOOT_ROM_MMCIF 1893 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1894 help 1895 Load image from MMCIF hardware block. 1896 1897config ZBOOT_ROM_SH_MOBILE_SDHI 1898 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1899 help 1900 Load image from SDHI hardware block 1901 1902endchoice 1903 1904config ARM_APPENDED_DTB 1905 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1906 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1907 help 1908 With this option, the boot code will look for a device tree binary 1909 (DTB) appended to zImage 1910 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1911 1912 This is meant as a backward compatibility convenience for those 1913 systems with a bootloader that can't be upgraded to accommodate 1914 the documented boot protocol using a device tree. 1915 1916 Beware that there is very little in terms of protection against 1917 this option being confused by leftover garbage in memory that might 1918 look like a DTB header after a reboot if no actual DTB is appended 1919 to zImage. Do not leave this option active in a production kernel 1920 if you don't intend to always append a DTB. Proper passing of the 1921 location into r2 of a bootloader provided DTB is always preferable 1922 to this option. 1923 1924config ARM_ATAG_DTB_COMPAT 1925 bool "Supplement the appended DTB with traditional ATAG information" 1926 depends on ARM_APPENDED_DTB 1927 help 1928 Some old bootloaders can't be updated to a DTB capable one, yet 1929 they provide ATAGs with memory configuration, the ramdisk address, 1930 the kernel cmdline string, etc. Such information is dynamically 1931 provided by the bootloader and can't always be stored in a static 1932 DTB. To allow a device tree enabled kernel to be used with such 1933 bootloaders, this option allows zImage to extract the information 1934 from the ATAG list and store it at run time into the appended DTB. 1935 1936config CMDLINE 1937 string "Default kernel command string" 1938 default "" 1939 help 1940 On some architectures (EBSA110 and CATS), there is currently no way 1941 for the boot loader to pass arguments to the kernel. For these 1942 architectures, you should supply some command-line options at build 1943 time by entering them here. As a minimum, you should specify the 1944 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1945 1946choice 1947 prompt "Kernel command line type" if CMDLINE != "" 1948 default CMDLINE_FROM_BOOTLOADER 1949 1950config CMDLINE_FROM_BOOTLOADER 1951 bool "Use bootloader kernel arguments if available" 1952 help 1953 Uses the command-line options passed by the boot loader. If 1954 the boot loader doesn't provide any, the default kernel command 1955 string provided in CMDLINE will be used. 1956 1957config CMDLINE_EXTEND 1958 bool "Extend bootloader kernel arguments" 1959 help 1960 The command-line arguments provided by the boot loader will be 1961 appended to the default kernel command string. 1962 1963config CMDLINE_FORCE 1964 bool "Always use the default kernel command string" 1965 help 1966 Always use the default kernel command string, even if the boot 1967 loader passes other arguments to the kernel. 1968 This is useful if you cannot or don't want to change the 1969 command-line options your boot loader passes to the kernel. 1970endchoice 1971 1972config XIP_KERNEL 1973 bool "Kernel Execute-In-Place from ROM" 1974 depends on !ZBOOT_ROM 1975 help 1976 Execute-In-Place allows the kernel to run from non-volatile storage 1977 directly addressable by the CPU, such as NOR flash. This saves RAM 1978 space since the text section of the kernel is not loaded from flash 1979 to RAM. Read-write sections, such as the data section and stack, 1980 are still copied to RAM. The XIP kernel is not compressed since 1981 it has to run directly from flash, so it will take more space to 1982 store it. The flash address used to link the kernel object files, 1983 and for storing it, is configuration dependent. Therefore, if you 1984 say Y here, you must know the proper physical address where to 1985 store the kernel image depending on your own flash memory usage. 1986 1987 Also note that the make target becomes "make xipImage" rather than 1988 "make zImage" or "make Image". The final kernel binary to put in 1989 ROM memory will be arch/arm/boot/xipImage. 1990 1991 If unsure, say N. 1992 1993config XIP_PHYS_ADDR 1994 hex "XIP Kernel Physical Location" 1995 depends on XIP_KERNEL 1996 default "0x00080000" 1997 help 1998 This is the physical address in your flash memory the kernel will 1999 be linked for and stored to. This address is dependent on your 2000 own flash usage. 2001 2002config KEXEC 2003 bool "Kexec system call (EXPERIMENTAL)" 2004 depends on EXPERIMENTAL 2005 help 2006 kexec is a system call that implements the ability to shutdown your 2007 current kernel, and to start another kernel. It is like a reboot 2008 but it is independent of the system firmware. And like a reboot 2009 you can start any kernel with it, not just Linux. 2010 2011 It is an ongoing process to be certain the hardware in a machine 2012 is properly shutdown, so do not be surprised if this code does not 2013 initially work for you. It may help to enable device hotplugging 2014 support. 2015 2016config ATAGS_PROC 2017 bool "Export atags in procfs" 2018 depends on KEXEC 2019 default y 2020 help 2021 Should the atags used to boot the kernel be exported in an "atags" 2022 file in procfs. Useful with kexec. 2023 2024config CRASH_DUMP 2025 bool "Build kdump crash kernel (EXPERIMENTAL)" 2026 depends on EXPERIMENTAL 2027 help 2028 Generate crash dump after being started by kexec. This should 2029 be normally only set in special crash dump kernels which are 2030 loaded in the main kernel with kexec-tools into a specially 2031 reserved region and then later executed after a crash by 2032 kdump/kexec. The crash dump kernel must be compiled to a 2033 memory address not used by the main kernel 2034 2035 For more details see Documentation/kdump/kdump.txt 2036 2037config AUTO_ZRELADDR 2038 bool "Auto calculation of the decompressed kernel image address" 2039 depends on !ZBOOT_ROM && !ARCH_U300 2040 help 2041 ZRELADDR is the physical address where the decompressed kernel 2042 image will be placed. If AUTO_ZRELADDR is selected, the address 2043 will be determined at run-time by masking the current IP with 2044 0xf8000000. This assumes the zImage being placed in the first 128MB 2045 from start of memory. 2046 2047endmenu 2048 2049menu "CPU Power Management" 2050 2051if ARCH_HAS_CPUFREQ 2052 2053source "drivers/cpufreq/Kconfig" 2054 2055config CPU_FREQ_IMX 2056 tristate "CPUfreq driver for i.MX CPUs" 2057 depends on ARCH_MXC && CPU_FREQ 2058 help 2059 This enables the CPUfreq driver for i.MX CPUs. 2060 2061config CPU_FREQ_SA1100 2062 bool 2063 2064config CPU_FREQ_SA1110 2065 bool 2066 2067config CPU_FREQ_INTEGRATOR 2068 tristate "CPUfreq driver for ARM Integrator CPUs" 2069 depends on ARCH_INTEGRATOR && CPU_FREQ 2070 default y 2071 help 2072 This enables the CPUfreq driver for ARM Integrator CPUs. 2073 2074 For details, take a look at <file:Documentation/cpu-freq>. 2075 2076 If in doubt, say Y. 2077 2078config CPU_FREQ_PXA 2079 bool 2080 depends on CPU_FREQ && ARCH_PXA && PXA25x 2081 default y 2082 select CPU_FREQ_TABLE 2083 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2084 2085config CPU_FREQ_S3C 2086 bool 2087 help 2088 Internal configuration node for common cpufreq on Samsung SoC 2089 2090config CPU_FREQ_S3C24XX 2091 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2092 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 2093 select CPU_FREQ_S3C 2094 help 2095 This enables the CPUfreq driver for the Samsung S3C24XX family 2096 of CPUs. 2097 2098 For details, take a look at <file:Documentation/cpu-freq>. 2099 2100 If in doubt, say N. 2101 2102config CPU_FREQ_S3C24XX_PLL 2103 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2104 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2105 help 2106 Compile in support for changing the PLL frequency from the 2107 S3C24XX series CPUfreq driver. The PLL takes time to settle 2108 after a frequency change, so by default it is not enabled. 2109 2110 This also means that the PLL tables for the selected CPU(s) will 2111 be built which may increase the size of the kernel image. 2112 2113config CPU_FREQ_S3C24XX_DEBUG 2114 bool "Debug CPUfreq Samsung driver core" 2115 depends on CPU_FREQ_S3C24XX 2116 help 2117 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2118 2119config CPU_FREQ_S3C24XX_IODEBUG 2120 bool "Debug CPUfreq Samsung driver IO timing" 2121 depends on CPU_FREQ_S3C24XX 2122 help 2123 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2124 2125config CPU_FREQ_S3C24XX_DEBUGFS 2126 bool "Export debugfs for CPUFreq" 2127 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2128 help 2129 Export status information via debugfs. 2130 2131endif 2132 2133source "drivers/cpuidle/Kconfig" 2134 2135endmenu 2136 2137menu "Floating point emulation" 2138 2139comment "At least one emulation must be selected" 2140 2141config FPE_NWFPE 2142 bool "NWFPE math emulation" 2143 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2144 ---help--- 2145 Say Y to include the NWFPE floating point emulator in the kernel. 2146 This is necessary to run most binaries. Linux does not currently 2147 support floating point hardware so you need to say Y here even if 2148 your machine has an FPA or floating point co-processor podule. 2149 2150 You may say N here if you are going to load the Acorn FPEmulator 2151 early in the bootup. 2152 2153config FPE_NWFPE_XP 2154 bool "Support extended precision" 2155 depends on FPE_NWFPE 2156 help 2157 Say Y to include 80-bit support in the kernel floating-point 2158 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2159 Note that gcc does not generate 80-bit operations by default, 2160 so in most cases this option only enlarges the size of the 2161 floating point emulator without any good reason. 2162 2163 You almost surely want to say N here. 2164 2165config FPE_FASTFPE 2166 bool "FastFPE math emulation (EXPERIMENTAL)" 2167 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2168 ---help--- 2169 Say Y here to include the FAST floating point emulator in the kernel. 2170 This is an experimental much faster emulator which now also has full 2171 precision for the mantissa. It does not support any exceptions. 2172 It is very simple, and approximately 3-6 times faster than NWFPE. 2173 2174 It should be sufficient for most programs. It may be not suitable 2175 for scientific calculations, but you have to check this for yourself. 2176 If you do not feel you need a faster FP emulation you should better 2177 choose NWFPE. 2178 2179config VFP 2180 bool "VFP-format floating point maths" 2181 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2182 help 2183 Say Y to include VFP support code in the kernel. This is needed 2184 if your hardware includes a VFP unit. 2185 2186 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2187 release notes and additional status information. 2188 2189 Say N if your target does not have VFP hardware. 2190 2191config VFPv3 2192 bool 2193 depends on VFP 2194 default y if CPU_V7 2195 2196config NEON 2197 bool "Advanced SIMD (NEON) Extension support" 2198 depends on VFPv3 && CPU_V7 2199 help 2200 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2201 Extension. 2202 2203endmenu 2204 2205menu "Userspace binary formats" 2206 2207source "fs/Kconfig.binfmt" 2208 2209config ARTHUR 2210 tristate "RISC OS personality" 2211 depends on !AEABI 2212 help 2213 Say Y here to include the kernel code necessary if you want to run 2214 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2215 experimental; if this sounds frightening, say N and sleep in peace. 2216 You can also say M here to compile this support as a module (which 2217 will be called arthur). 2218 2219endmenu 2220 2221menu "Power management options" 2222 2223source "kernel/power/Kconfig" 2224 2225config ARCH_SUSPEND_POSSIBLE 2226 depends on !ARCH_S5PC100 2227 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2228 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2229 def_bool y 2230 2231config ARM_CPU_SUSPEND 2232 def_bool PM_SLEEP 2233 2234endmenu 2235 2236source "net/Kconfig" 2237 2238source "drivers/Kconfig" 2239 2240source "fs/Kconfig" 2241 2242source "arch/arm/Kconfig.debug" 2243 2244source "security/Kconfig" 2245 2246source "crypto/Kconfig" 2247 2248source "lib/Kconfig" 2249