1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_STACKWALK 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 24 select ARCH_HAS_SYNC_DMA_FOR_CPU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 80 select HAVE_ARCH_MMAP_RND_BITS if MMU 81 select HAVE_ARCH_PFN_VALID 82 select HAVE_ARCH_SECCOMP 83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 85 select HAVE_ARCH_TRACEHOOK 86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 87 select HAVE_ARM_SMCCC if CPU_V7 88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 89 select HAVE_CONTEXT_TRACKING_USER 90 select HAVE_C_RECORDMCOUNT 91 select HAVE_BUILDTIME_MCOUNT_SORT 92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 93 select HAVE_DMA_CONTIGUOUS if MMU 94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 97 select HAVE_EXIT_THREAD 98 select HAVE_FAST_GUP if ARM_LPAE 99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 100 select HAVE_FUNCTION_ERROR_INJECTION 101 select HAVE_FUNCTION_GRAPH_TRACER 102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 103 select HAVE_GCC_PLUGINS 104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 105 select HAVE_IRQ_TIME_ACCOUNTING 106 select HAVE_KERNEL_GZIP 107 select HAVE_KERNEL_LZ4 108 select HAVE_KERNEL_LZMA 109 select HAVE_KERNEL_LZO 110 select HAVE_KERNEL_XZ 111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 112 select HAVE_KRETPROBES if HAVE_KPROBES 113 select HAVE_MOD_ARCH_SPECIFIC 114 select HAVE_NMI 115 select HAVE_OPTPROBES if !THUMB2_KERNEL 116 select HAVE_PCI if MMU 117 select HAVE_PERF_EVENTS 118 select HAVE_PERF_REGS 119 select HAVE_PERF_USER_STACK_DUMP 120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 121 select HAVE_REGS_AND_STACK_ACCESS_API 122 select HAVE_RSEQ 123 select HAVE_STACKPROTECTOR 124 select HAVE_SYSCALL_TRACEPOINTS 125 select HAVE_UID16 126 select HAVE_VIRT_CPU_ACCOUNTING_GEN 127 select IRQ_FORCED_THREADING 128 select MODULES_USE_ELF_REL 129 select NEED_DMA_MAP_STATE 130 select OF_EARLY_FLATTREE if OF 131 select OLD_SIGACTION 132 select OLD_SIGSUSPEND3 133 select PCI_DOMAINS_GENERIC if PCI 134 select PCI_SYSCALL if PCI 135 select PERF_USE_VMALLOC 136 select RTC_LIB 137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 138 select SYS_SUPPORTS_APM_EMULATION 139 select THREAD_INFO_IN_TASK 140 select TIMER_OF if OF 141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 144 # Above selects are sorted alphabetically; please add new ones 145 # according to that. Thanks. 146 help 147 The ARM series is a line of low-power-consumption RISC chip designs 148 licensed by ARM Ltd and targeted at embedded applications and 149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 150 manufactured, but legacy ARM-based PC hardware remains popular in 151 Europe. There is an ARM Linux project with a web page at 152 <http://www.arm.linux.org.uk/>. 153 154config ARM_HAS_GROUP_RELOCS 155 def_bool y 156 depends on !LD_IS_LLD || LLD_VERSION >= 140000 157 depends on !COMPILE_TEST 158 help 159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 160 relocations, which have been around for a long time, but were not 161 supported in LLD until version 14. The combined range is -/+ 256 MiB, 162 which is usually sufficient, but not for allyesconfig, so we disable 163 this feature when doing compile testing. 164 165config ARM_DMA_USE_IOMMU 166 bool 167 select NEED_SG_DMA_LENGTH 168 169if ARM_DMA_USE_IOMMU 170 171config ARM_DMA_IOMMU_ALIGNMENT 172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 173 range 4 9 174 default 8 175 help 176 DMA mapping framework by default aligns all buffers to the smallest 177 PAGE_SIZE order which is greater than or equal to the requested buffer 178 size. This works well for buffers up to a few hundreds kilobytes, but 179 for larger buffers it just a waste of address space. Drivers which has 180 relatively small addressing window (like 64Mib) might run out of 181 virtual space with just a few allocations. 182 183 With this parameter you can specify the maximum PAGE_SIZE order for 184 DMA IOMMU buffers. Larger buffers will be aligned only to this 185 specified order. The order is expressed as a power of two multiplied 186 by the PAGE_SIZE. 187 188endif 189 190config SYS_SUPPORTS_APM_EMULATION 191 bool 192 193config HAVE_TCM 194 bool 195 select GENERIC_ALLOCATOR 196 197config HAVE_PROC_CPU 198 bool 199 200config NO_IOPORT_MAP 201 bool 202 203config SBUS 204 bool 205 206config STACKTRACE_SUPPORT 207 bool 208 default y 209 210config LOCKDEP_SUPPORT 211 bool 212 default y 213 214config ARCH_HAS_ILOG2_U32 215 bool 216 217config ARCH_HAS_ILOG2_U64 218 bool 219 220config ARCH_HAS_BANDGAP 221 bool 222 223config FIX_EARLYCON_MEM 224 def_bool y if MMU 225 226config GENERIC_HWEIGHT 227 bool 228 default y 229 230config GENERIC_CALIBRATE_DELAY 231 bool 232 default y 233 234config ARCH_MAY_HAVE_PC_FDC 235 bool 236 237config ARCH_SUPPORTS_UPROBES 238 def_bool y 239 240config GENERIC_ISA_DMA 241 bool 242 243config FIQ 244 bool 245 246config ARCH_MTD_XIP 247 bool 248 249config ARM_PATCH_PHYS_VIRT 250 bool "Patch physical to virtual translations at runtime" if EMBEDDED 251 default y 252 depends on MMU 253 help 254 Patch phys-to-virt and virt-to-phys translation functions at 255 boot and module load time according to the position of the 256 kernel in system memory. 257 258 This can only be used with non-XIP MMU kernels where the base 259 of physical memory is at a 2 MiB boundary. 260 261 Only disable this option if you know that you do not require 262 this feature (eg, building a kernel for a single machine) and 263 you need to shrink the kernel to the minimal size. 264 265config NEED_MACH_IO_H 266 bool 267 help 268 Select this when mach/io.h is required to provide special 269 definitions for this platform. The need for mach/io.h should 270 be avoided when possible. 271 272config NEED_MACH_MEMORY_H 273 bool 274 help 275 Select this when mach/memory.h is required to provide special 276 definitions for this platform. The need for mach/memory.h should 277 be avoided when possible. 278 279config PHYS_OFFSET 280 hex "Physical address of main memory" if MMU 281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 282 default DRAM_BASE if !MMU 283 default 0x00000000 if ARCH_FOOTBRIDGE 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0xa0000000 if ARCH_PXA 286 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 287 default 0 288 help 289 Please provide the physical address corresponding to the 290 location of main memory in your system. 291 292config GENERIC_BUG 293 def_bool y 294 depends on BUG 295 296config PGTABLE_LEVELS 297 int 298 default 3 if ARM_LPAE 299 default 2 300 301menu "System Type" 302 303config MMU 304 bool "MMU-based Paged Memory Management Support" 305 default y 306 help 307 Select if you want MMU-based virtualised addressing space 308 support by paged memory management. If unsure, say 'Y'. 309 310config ARM_SINGLE_ARMV7M 311 def_bool !MMU 312 select ARM_NVIC 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 316config ARCH_MMAP_RND_BITS_MIN 317 default 8 318 319config ARCH_MMAP_RND_BITS_MAX 320 default 14 if PAGE_OFFSET=0x40000000 321 default 15 if PAGE_OFFSET=0x80000000 322 default 16 323 324config ARCH_MULTIPLATFORM 325 bool "Require kernel to be portable to multiple machines" if EXPERT 326 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 327 default y 328 help 329 In general, all Arm machines can be supported in a single 330 kernel image, covering either Armv4/v5 or Armv6/v7. 331 332 However, some configuration options require hardcoding machine 333 specific physical addresses or enable errata workarounds that may 334 break other machines. 335 336 Selecting N here allows using those options, including 337 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 338 339menu "Platform selection" 340 depends on MMU 341 342comment "CPU Core family selection" 343 344config ARCH_MULTI_V4 345 bool "ARMv4 based platforms (FA526, StrongARM)" 346 depends on !ARCH_MULTI_V6_V7 347 depends on !LD_IS_LLD 348 select ARCH_MULTI_V4_V5 349 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 350 351config ARCH_MULTI_V4T 352 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 353 depends on !ARCH_MULTI_V6_V7 354 depends on !LD_IS_LLD 355 select ARCH_MULTI_V4_V5 356 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 357 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 358 CPU_ARM925T || CPU_ARM940T) 359 360config ARCH_MULTI_V5 361 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 362 depends on !ARCH_MULTI_V6_V7 363 select ARCH_MULTI_V4_V5 364 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 365 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 366 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 367 368config ARCH_MULTI_V4_V5 369 bool 370 371config ARCH_MULTI_V6 372 bool "ARMv6 based platforms (ARM11)" 373 select ARCH_MULTI_V6_V7 374 select CPU_V6K 375 376config ARCH_MULTI_V7 377 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 378 default y 379 select ARCH_MULTI_V6_V7 380 select CPU_V7 381 select HAVE_SMP 382 383config ARCH_MULTI_V6_V7 384 bool 385 select MIGHT_HAVE_CACHE_L2X0 386 387config ARCH_MULTI_CPU_AUTO 388 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 389 select ARCH_MULTI_V5 390 391endmenu 392 393config ARCH_VIRT 394 bool "Dummy Virtual Machine" 395 depends on ARCH_MULTI_V7 396 select ARM_AMBA 397 select ARM_GIC 398 select ARM_GIC_V2M if PCI 399 select ARM_GIC_V3 400 select ARM_GIC_V3_ITS if PCI 401 select ARM_PSCI 402 select HAVE_ARM_ARCH_TIMER 403 404config ARCH_AIROHA 405 bool "Airoha SoC Support" 406 depends on ARCH_MULTI_V7 407 select ARM_AMBA 408 select ARM_GIC 409 select ARM_GIC_V3 410 select ARM_PSCI 411 select HAVE_ARM_ARCH_TIMER 412 help 413 Support for Airoha EN7523 SoCs 414 415# 416# This is sorted alphabetically by mach-* pathname. However, plat-* 417# Kconfigs may be included either alphabetically (according to the 418# plat- suffix) or along side the corresponding mach-* source. 419# 420source "arch/arm/mach-actions/Kconfig" 421 422source "arch/arm/mach-alpine/Kconfig" 423 424source "arch/arm/mach-artpec/Kconfig" 425 426source "arch/arm/mach-asm9260/Kconfig" 427 428source "arch/arm/mach-aspeed/Kconfig" 429 430source "arch/arm/mach-at91/Kconfig" 431 432source "arch/arm/mach-axxia/Kconfig" 433 434source "arch/arm/mach-bcm/Kconfig" 435 436source "arch/arm/mach-berlin/Kconfig" 437 438source "arch/arm/mach-clps711x/Kconfig" 439 440source "arch/arm/mach-davinci/Kconfig" 441 442source "arch/arm/mach-digicolor/Kconfig" 443 444source "arch/arm/mach-dove/Kconfig" 445 446source "arch/arm/mach-ep93xx/Kconfig" 447 448source "arch/arm/mach-exynos/Kconfig" 449 450source "arch/arm/mach-footbridge/Kconfig" 451 452source "arch/arm/mach-gemini/Kconfig" 453 454source "arch/arm/mach-highbank/Kconfig" 455 456source "arch/arm/mach-hisi/Kconfig" 457 458source "arch/arm/mach-hpe/Kconfig" 459 460source "arch/arm/mach-imx/Kconfig" 461 462source "arch/arm/mach-ixp4xx/Kconfig" 463 464source "arch/arm/mach-keystone/Kconfig" 465 466source "arch/arm/mach-lpc32xx/Kconfig" 467 468source "arch/arm/mach-mediatek/Kconfig" 469 470source "arch/arm/mach-meson/Kconfig" 471 472source "arch/arm/mach-milbeaut/Kconfig" 473 474source "arch/arm/mach-mmp/Kconfig" 475 476source "arch/arm/mach-moxart/Kconfig" 477 478source "arch/arm/mach-mstar/Kconfig" 479 480source "arch/arm/mach-mv78xx0/Kconfig" 481 482source "arch/arm/mach-mvebu/Kconfig" 483 484source "arch/arm/mach-mxs/Kconfig" 485 486source "arch/arm/mach-nomadik/Kconfig" 487 488source "arch/arm/mach-npcm/Kconfig" 489 490source "arch/arm/mach-nspire/Kconfig" 491 492source "arch/arm/mach-omap1/Kconfig" 493 494source "arch/arm/mach-omap2/Kconfig" 495 496source "arch/arm/mach-orion5x/Kconfig" 497 498source "arch/arm/mach-oxnas/Kconfig" 499 500source "arch/arm/mach-pxa/Kconfig" 501 502source "arch/arm/mach-qcom/Kconfig" 503 504source "arch/arm/mach-rda/Kconfig" 505 506source "arch/arm/mach-realtek/Kconfig" 507 508source "arch/arm/mach-rpc/Kconfig" 509 510source "arch/arm/mach-rockchip/Kconfig" 511 512source "arch/arm/mach-s3c/Kconfig" 513 514source "arch/arm/mach-s5pv210/Kconfig" 515 516source "arch/arm/mach-sa1100/Kconfig" 517 518source "arch/arm/mach-shmobile/Kconfig" 519 520source "arch/arm/mach-socfpga/Kconfig" 521 522source "arch/arm/mach-spear/Kconfig" 523 524source "arch/arm/mach-sti/Kconfig" 525 526source "arch/arm/mach-stm32/Kconfig" 527 528source "arch/arm/mach-sunplus/Kconfig" 529 530source "arch/arm/mach-sunxi/Kconfig" 531 532source "arch/arm/mach-tegra/Kconfig" 533 534source "arch/arm/mach-uniphier/Kconfig" 535 536source "arch/arm/mach-ux500/Kconfig" 537 538source "arch/arm/mach-versatile/Kconfig" 539 540source "arch/arm/mach-vt8500/Kconfig" 541 542source "arch/arm/mach-zynq/Kconfig" 543 544# ARMv7-M architecture 545config ARCH_LPC18XX 546 bool "NXP LPC18xx/LPC43xx" 547 depends on ARM_SINGLE_ARMV7M 548 select ARCH_HAS_RESET_CONTROLLER 549 select ARM_AMBA 550 select CLKSRC_LPC32XX 551 select PINCTRL 552 help 553 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 554 high performance microcontrollers. 555 556config ARCH_MPS2 557 bool "ARM MPS2 platform" 558 depends on ARM_SINGLE_ARMV7M 559 select ARM_AMBA 560 select CLKSRC_MPS2 561 help 562 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 563 with a range of available cores like Cortex-M3/M4/M7. 564 565 Please, note that depends which Application Note is used memory map 566 for the platform may vary, so adjustment of RAM base might be needed. 567 568# Definitions to make life easier 569config ARCH_ACORN 570 bool 571 572config PLAT_ORION 573 bool 574 select CLKSRC_MMIO 575 select GENERIC_IRQ_CHIP 576 select IRQ_DOMAIN 577 578config PLAT_ORION_LEGACY 579 bool 580 select PLAT_ORION 581 582config PLAT_VERSATILE 583 bool 584 585source "arch/arm/mm/Kconfig" 586 587config IWMMXT 588 bool "Enable iWMMXt support" 589 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 590 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 591 help 592 Enable support for iWMMXt context switching at run time if 593 running on a CPU that supports it. 594 595if !MMU 596source "arch/arm/Kconfig-nommu" 597endif 598 599config PJ4B_ERRATA_4742 600 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 601 depends on CPU_PJ4B && MACH_ARMADA_370 602 default y 603 help 604 When coming out of either a Wait for Interrupt (WFI) or a Wait for 605 Event (WFE) IDLE states, a specific timing sensitivity exists between 606 the retiring WFI/WFE instructions and the newly issued subsequent 607 instructions. This sensitivity can result in a CPU hang scenario. 608 Workaround: 609 The software must insert either a Data Synchronization Barrier (DSB) 610 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 611 instruction 612 613config ARM_ERRATA_326103 614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 615 depends on CPU_V6 616 help 617 Executing a SWP instruction to read-only memory does not set bit 11 618 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 619 treat the access as a read, preventing a COW from occurring and 620 causing the faulting task to livelock. 621 622config ARM_ERRATA_411920 623 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 624 depends on CPU_V6 || CPU_V6K 625 help 626 Invalidation of the Instruction Cache operation can 627 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 628 It does not affect the MPCore. This option enables the ARM Ltd. 629 recommended workaround. 630 631config ARM_ERRATA_430973 632 bool "ARM errata: Stale prediction on replaced interworking branch" 633 depends on CPU_V7 634 help 635 This option enables the workaround for the 430973 Cortex-A8 636 r1p* erratum. If a code sequence containing an ARM/Thumb 637 interworking branch is replaced with another code sequence at the 638 same virtual address, whether due to self-modifying code or virtual 639 to physical address re-mapping, Cortex-A8 does not recover from the 640 stale interworking branch prediction. This results in Cortex-A8 641 executing the new code sequence in the incorrect ARM or Thumb state. 642 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 643 and also flushes the branch target cache at every context switch. 644 Note that setting specific bits in the ACTLR register may not be 645 available in non-secure mode. 646 647config ARM_ERRATA_458693 648 bool "ARM errata: Processor deadlock when a false hazard is created" 649 depends on CPU_V7 650 depends on !ARCH_MULTIPLATFORM 651 help 652 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 653 erratum. For very specific sequences of memory operations, it is 654 possible for a hazard condition intended for a cache line to instead 655 be incorrectly associated with a different cache line. This false 656 hazard might then cause a processor deadlock. The workaround enables 657 the L1 caching of the NEON accesses and disables the PLD instruction 658 in the ACTLR register. Note that setting specific bits in the ACTLR 659 register may not be available in non-secure mode. 660 661config ARM_ERRATA_460075 662 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 663 depends on CPU_V7 664 depends on !ARCH_MULTIPLATFORM 665 help 666 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 667 erratum. Any asynchronous access to the L2 cache may encounter a 668 situation in which recent store transactions to the L2 cache are lost 669 and overwritten with stale memory contents from external memory. The 670 workaround disables the write-allocate mode for the L2 cache via the 671 ACTLR register. Note that setting specific bits in the ACTLR register 672 may not be available in non-secure mode. 673 674config ARM_ERRATA_742230 675 bool "ARM errata: DMB operation may be faulty" 676 depends on CPU_V7 && SMP 677 depends on !ARCH_MULTIPLATFORM 678 help 679 This option enables the workaround for the 742230 Cortex-A9 680 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 681 between two write operations may not ensure the correct visibility 682 ordering of the two writes. This workaround sets a specific bit in 683 the diagnostic register of the Cortex-A9 which causes the DMB 684 instruction to behave as a DSB, ensuring the correct behaviour of 685 the two writes. 686 687config ARM_ERRATA_742231 688 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 689 depends on CPU_V7 && SMP 690 depends on !ARCH_MULTIPLATFORM 691 help 692 This option enables the workaround for the 742231 Cortex-A9 693 (r2p0..r2p2) erratum. Under certain conditions, specific to the 694 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 695 accessing some data located in the same cache line, may get corrupted 696 data due to bad handling of the address hazard when the line gets 697 replaced from one of the CPUs at the same time as another CPU is 698 accessing it. This workaround sets specific bits in the diagnostic 699 register of the Cortex-A9 which reduces the linefill issuing 700 capabilities of the processor. 701 702config ARM_ERRATA_643719 703 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 704 depends on CPU_V7 && SMP 705 default y 706 help 707 This option enables the workaround for the 643719 Cortex-A9 (prior to 708 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 709 register returns zero when it should return one. The workaround 710 corrects this value, ensuring cache maintenance operations which use 711 it behave as intended and avoiding data corruption. 712 713config ARM_ERRATA_720789 714 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 715 depends on CPU_V7 716 help 717 This option enables the workaround for the 720789 Cortex-A9 (prior to 718 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 719 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 720 As a consequence of this erratum, some TLB entries which should be 721 invalidated are not, resulting in an incoherency in the system page 722 tables. The workaround changes the TLB flushing routines to invalidate 723 entries regardless of the ASID. 724 725config ARM_ERRATA_743622 726 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 727 depends on CPU_V7 728 depends on !ARCH_MULTIPLATFORM 729 help 730 This option enables the workaround for the 743622 Cortex-A9 731 (r2p*) erratum. Under very rare conditions, a faulty 732 optimisation in the Cortex-A9 Store Buffer may lead to data 733 corruption. This workaround sets a specific bit in the diagnostic 734 register of the Cortex-A9 which disables the Store Buffer 735 optimisation, preventing the defect from occurring. This has no 736 visible impact on the overall performance or power consumption of the 737 processor. 738 739config ARM_ERRATA_751472 740 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 741 depends on CPU_V7 742 depends on !ARCH_MULTIPLATFORM 743 help 744 This option enables the workaround for the 751472 Cortex-A9 (prior 745 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 746 completion of a following broadcasted operation if the second 747 operation is received by a CPU before the ICIALLUIS has completed, 748 potentially leading to corrupted entries in the cache or TLB. 749 750config ARM_ERRATA_754322 751 bool "ARM errata: possible faulty MMU translations following an ASID switch" 752 depends on CPU_V7 753 help 754 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 755 r3p*) erratum. A speculative memory access may cause a page table walk 756 which starts prior to an ASID switch but completes afterwards. This 757 can populate the micro-TLB with a stale entry which may be hit with 758 the new ASID. This workaround places two dsb instructions in the mm 759 switching code so that no page table walks can cross the ASID switch. 760 761config ARM_ERRATA_754327 762 bool "ARM errata: no automatic Store Buffer drain" 763 depends on CPU_V7 && SMP 764 help 765 This option enables the workaround for the 754327 Cortex-A9 (prior to 766 r2p0) erratum. The Store Buffer does not have any automatic draining 767 mechanism and therefore a livelock may occur if an external agent 768 continuously polls a memory location waiting to observe an update. 769 This workaround defines cpu_relax() as smp_mb(), preventing correctly 770 written polling loops from denying visibility of updates to memory. 771 772config ARM_ERRATA_364296 773 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 774 depends on CPU_V6 775 help 776 This options enables the workaround for the 364296 ARM1136 777 r0p2 erratum (possible cache data corruption with 778 hit-under-miss enabled). It sets the undocumented bit 31 in 779 the auxiliary control register and the FI bit in the control 780 register, thus disabling hit-under-miss without putting the 781 processor into full low interrupt latency mode. ARM11MPCore 782 is not affected. 783 784config ARM_ERRATA_764369 785 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 786 depends on CPU_V7 && SMP 787 help 788 This option enables the workaround for erratum 764369 789 affecting Cortex-A9 MPCore with two or more processors (all 790 current revisions). Under certain timing circumstances, a data 791 cache line maintenance operation by MVA targeting an Inner 792 Shareable memory region may fail to proceed up to either the 793 Point of Coherency or to the Point of Unification of the 794 system. This workaround adds a DSB instruction before the 795 relevant cache maintenance functions and sets a specific bit 796 in the diagnostic control register of the SCU. 797 798config ARM_ERRATA_764319 799 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 800 depends on CPU_V7 801 help 802 This option enables the workaround for the 764319 Cortex A-9 erratum. 803 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 804 unexpected Undefined Instruction exception when the DBGSWENABLE 805 external pin is set to 0, even when the CP14 accesses are performed 806 from a privileged mode. This work around catches the exception in a 807 way the kernel does not stop execution. 808 809config ARM_ERRATA_775420 810 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 811 depends on CPU_V7 812 help 813 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 814 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 815 operation aborts with MMU exception, it might cause the processor 816 to deadlock. This workaround puts DSB before executing ISB if 817 an abort may occur on cache maintenance. 818 819config ARM_ERRATA_798181 820 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 821 depends on CPU_V7 && SMP 822 help 823 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 824 adequately shooting down all use of the old entries. This 825 option enables the Linux kernel workaround for this erratum 826 which sends an IPI to the CPUs that are running the same ASID 827 as the one being invalidated. 828 829config ARM_ERRATA_773022 830 bool "ARM errata: incorrect instructions may be executed from loop buffer" 831 depends on CPU_V7 832 help 833 This option enables the workaround for the 773022 Cortex-A15 834 (up to r0p4) erratum. In certain rare sequences of code, the 835 loop buffer may deliver incorrect instructions. This 836 workaround disables the loop buffer to avoid the erratum. 837 838config ARM_ERRATA_818325_852422 839 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 840 depends on CPU_V7 841 help 842 This option enables the workaround for: 843 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 844 instruction might deadlock. Fixed in r0p1. 845 - Cortex-A12 852422: Execution of a sequence of instructions might 846 lead to either a data corruption or a CPU deadlock. Not fixed in 847 any Cortex-A12 cores yet. 848 This workaround for all both errata involves setting bit[12] of the 849 Feature Register. This bit disables an optimisation applied to a 850 sequence of 2 instructions that use opposing condition codes. 851 852config ARM_ERRATA_821420 853 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 854 depends on CPU_V7 855 help 856 This option enables the workaround for the 821420 Cortex-A12 857 (all revs) erratum. In very rare timing conditions, a sequence 858 of VMOV to Core registers instructions, for which the second 859 one is in the shadow of a branch or abort, can lead to a 860 deadlock when the VMOV instructions are issued out-of-order. 861 862config ARM_ERRATA_825619 863 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 864 depends on CPU_V7 865 help 866 This option enables the workaround for the 825619 Cortex-A12 867 (all revs) erratum. Within rare timing constraints, executing a 868 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 869 and Device/Strongly-Ordered loads and stores might cause deadlock 870 871config ARM_ERRATA_857271 872 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 873 depends on CPU_V7 874 help 875 This option enables the workaround for the 857271 Cortex-A12 876 (all revs) erratum. Under very rare timing conditions, the CPU might 877 hang. The workaround is expected to have a < 1% performance impact. 878 879config ARM_ERRATA_852421 880 bool "ARM errata: A17: DMB ST might fail to create order between stores" 881 depends on CPU_V7 882 help 883 This option enables the workaround for the 852421 Cortex-A17 884 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 885 execution of a DMB ST instruction might fail to properly order 886 stores from GroupA and stores from GroupB. 887 888config ARM_ERRATA_852423 889 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 890 depends on CPU_V7 891 help 892 This option enables the workaround for: 893 - Cortex-A17 852423: Execution of a sequence of instructions might 894 lead to either a data corruption or a CPU deadlock. Not fixed in 895 any Cortex-A17 cores yet. 896 This is identical to Cortex-A12 erratum 852422. It is a separate 897 config option from the A12 erratum due to the way errata are checked 898 for and handled. 899 900config ARM_ERRATA_857272 901 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 902 depends on CPU_V7 903 help 904 This option enables the workaround for the 857272 Cortex-A17 erratum. 905 This erratum is not known to be fixed in any A17 revision. 906 This is identical to Cortex-A12 erratum 857271. It is a separate 907 config option from the A12 erratum due to the way errata are checked 908 for and handled. 909 910endmenu 911 912source "arch/arm/common/Kconfig" 913 914menu "Bus support" 915 916config ISA 917 bool 918 help 919 Find out whether you have ISA slots on your motherboard. ISA is the 920 name of a bus system, i.e. the way the CPU talks to the other stuff 921 inside your box. Other bus systems are PCI, EISA, MicroChannel 922 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 923 newer boards don't support it. If you have ISA, say Y, otherwise N. 924 925# Select ISA DMA interface 926config ISA_DMA_API 927 bool 928 929config ARM_ERRATA_814220 930 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 931 depends on CPU_V7 932 help 933 The v7 ARM states that all cache and branch predictor maintenance 934 operations that do not specify an address execute, relative to 935 each other, in program order. 936 However, because of this erratum, an L2 set/way cache maintenance 937 operation can overtake an L1 set/way cache maintenance operation. 938 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 939 r0p4, r0p5. 940 941endmenu 942 943menu "Kernel Features" 944 945config HAVE_SMP 946 bool 947 help 948 This option should be selected by machines which have an SMP- 949 capable CPU. 950 951 The only effect of this option is to make the SMP-related 952 options available to the user for configuration. 953 954config SMP 955 bool "Symmetric Multi-Processing" 956 depends on CPU_V6K || CPU_V7 957 depends on HAVE_SMP 958 depends on MMU || ARM_MPU 959 select IRQ_WORK 960 help 961 This enables support for systems with more than one CPU. If you have 962 a system with only one CPU, say N. If you have a system with more 963 than one CPU, say Y. 964 965 If you say N here, the kernel will run on uni- and multiprocessor 966 machines, but will use only one CPU of a multiprocessor machine. If 967 you say Y here, the kernel will run on many, but not all, 968 uniprocessor machines. On a uniprocessor machine, the kernel 969 will run faster if you say N here. 970 971 See also <file:Documentation/x86/i386/IO-APIC.rst>, 972 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 973 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 974 975 If you don't know what to do here, say N. 976 977config SMP_ON_UP 978 bool "Allow booting SMP kernel on uniprocessor systems" 979 depends on SMP && MMU 980 default y 981 help 982 SMP kernels contain instructions which fail on non-SMP processors. 983 Enabling this option allows the kernel to modify itself to make 984 these instructions safe. Disabling it allows about 1K of space 985 savings. 986 987 If you don't know what to do here, say Y. 988 989 990config CURRENT_POINTER_IN_TPIDRURO 991 def_bool y 992 depends on CPU_32v6K && !CPU_V6 993 994config IRQSTACKS 995 def_bool y 996 select HAVE_IRQ_EXIT_ON_IRQ_STACK 997 select HAVE_SOFTIRQ_ON_OWN_STACK 998 999config ARM_CPU_TOPOLOGY 1000 bool "Support cpu topology definition" 1001 depends on SMP && CPU_V7 1002 default y 1003 help 1004 Support ARM cpu topology definition. The MPIDR register defines 1005 affinity between processors which is then used to describe the cpu 1006 topology of an ARM System. 1007 1008config SCHED_MC 1009 bool "Multi-core scheduler support" 1010 depends on ARM_CPU_TOPOLOGY 1011 help 1012 Multi-core scheduler support improves the CPU scheduler's decision 1013 making when dealing with multi-core CPU chips at a cost of slightly 1014 increased overhead in some places. If unsure say N here. 1015 1016config SCHED_SMT 1017 bool "SMT scheduler support" 1018 depends on ARM_CPU_TOPOLOGY 1019 help 1020 Improves the CPU scheduler's decision making when dealing with 1021 MultiThreading at a cost of slightly increased overhead in some 1022 places. If unsure say N here. 1023 1024config HAVE_ARM_SCU 1025 bool 1026 help 1027 This option enables support for the ARM snoop control unit 1028 1029config HAVE_ARM_ARCH_TIMER 1030 bool "Architected timer support" 1031 depends on CPU_V7 1032 select ARM_ARCH_TIMER 1033 help 1034 This option enables support for the ARM architected timer 1035 1036config HAVE_ARM_TWD 1037 bool 1038 help 1039 This options enables support for the ARM timer and watchdog unit 1040 1041config MCPM 1042 bool "Multi-Cluster Power Management" 1043 depends on CPU_V7 && SMP 1044 help 1045 This option provides the common power management infrastructure 1046 for (multi-)cluster based systems, such as big.LITTLE based 1047 systems. 1048 1049config MCPM_QUAD_CLUSTER 1050 bool 1051 depends on MCPM 1052 help 1053 To avoid wasting resources unnecessarily, MCPM only supports up 1054 to 2 clusters by default. 1055 Platforms with 3 or 4 clusters that use MCPM must select this 1056 option to allow the additional clusters to be managed. 1057 1058config BIG_LITTLE 1059 bool "big.LITTLE support (Experimental)" 1060 depends on CPU_V7 && SMP 1061 select MCPM 1062 help 1063 This option enables support selections for the big.LITTLE 1064 system architecture. 1065 1066config BL_SWITCHER 1067 bool "big.LITTLE switcher support" 1068 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1069 select CPU_PM 1070 help 1071 The big.LITTLE "switcher" provides the core functionality to 1072 transparently handle transition between a cluster of A15's 1073 and a cluster of A7's in a big.LITTLE system. 1074 1075config BL_SWITCHER_DUMMY_IF 1076 tristate "Simple big.LITTLE switcher user interface" 1077 depends on BL_SWITCHER && DEBUG_KERNEL 1078 help 1079 This is a simple and dummy char dev interface to control 1080 the big.LITTLE switcher core code. It is meant for 1081 debugging purposes only. 1082 1083choice 1084 prompt "Memory split" 1085 depends on MMU 1086 default VMSPLIT_3G 1087 help 1088 Select the desired split between kernel and user memory. 1089 1090 If you are not absolutely sure what you are doing, leave this 1091 option alone! 1092 1093 config VMSPLIT_3G 1094 bool "3G/1G user/kernel split" 1095 config VMSPLIT_3G_OPT 1096 depends on !ARM_LPAE 1097 bool "3G/1G user/kernel split (for full 1G low memory)" 1098 config VMSPLIT_2G 1099 bool "2G/2G user/kernel split" 1100 config VMSPLIT_1G 1101 bool "1G/3G user/kernel split" 1102endchoice 1103 1104config PAGE_OFFSET 1105 hex 1106 default PHYS_OFFSET if !MMU 1107 default 0x40000000 if VMSPLIT_1G 1108 default 0x80000000 if VMSPLIT_2G 1109 default 0xB0000000 if VMSPLIT_3G_OPT 1110 default 0xC0000000 1111 1112config KASAN_SHADOW_OFFSET 1113 hex 1114 depends on KASAN 1115 default 0x1f000000 if PAGE_OFFSET=0x40000000 1116 default 0x5f000000 if PAGE_OFFSET=0x80000000 1117 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1118 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1119 default 0xffffffff 1120 1121config NR_CPUS 1122 int "Maximum number of CPUs (2-32)" 1123 range 2 16 if DEBUG_KMAP_LOCAL 1124 range 2 32 if !DEBUG_KMAP_LOCAL 1125 depends on SMP 1126 default "4" 1127 help 1128 The maximum number of CPUs that the kernel can support. 1129 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1130 debugging is enabled, which uses half of the per-CPU fixmap 1131 slots as guard regions. 1132 1133config HOTPLUG_CPU 1134 bool "Support for hot-pluggable CPUs" 1135 depends on SMP 1136 select GENERIC_IRQ_MIGRATION 1137 help 1138 Say Y here to experiment with turning CPUs off and on. CPUs 1139 can be controlled through /sys/devices/system/cpu. 1140 1141config ARM_PSCI 1142 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1143 depends on HAVE_ARM_SMCCC 1144 select ARM_PSCI_FW 1145 help 1146 Say Y here if you want Linux to communicate with system firmware 1147 implementing the PSCI specification for CPU-centric power 1148 management operations described in ARM document number ARM DEN 1149 0022A ("Power State Coordination Interface System Software on 1150 ARM processors"). 1151 1152config HZ_FIXED 1153 int 1154 default 128 if SOC_AT91RM9200 1155 default 0 1156 1157choice 1158 depends on HZ_FIXED = 0 1159 prompt "Timer frequency" 1160 1161config HZ_100 1162 bool "100 Hz" 1163 1164config HZ_200 1165 bool "200 Hz" 1166 1167config HZ_250 1168 bool "250 Hz" 1169 1170config HZ_300 1171 bool "300 Hz" 1172 1173config HZ_500 1174 bool "500 Hz" 1175 1176config HZ_1000 1177 bool "1000 Hz" 1178 1179endchoice 1180 1181config HZ 1182 int 1183 default HZ_FIXED if HZ_FIXED != 0 1184 default 100 if HZ_100 1185 default 200 if HZ_200 1186 default 250 if HZ_250 1187 default 300 if HZ_300 1188 default 500 if HZ_500 1189 default 1000 1190 1191config SCHED_HRTICK 1192 def_bool HIGH_RES_TIMERS 1193 1194config THUMB2_KERNEL 1195 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1196 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1197 default y if CPU_THUMBONLY 1198 select ARM_UNWIND 1199 help 1200 By enabling this option, the kernel will be compiled in 1201 Thumb-2 mode. 1202 1203 If unsure, say N. 1204 1205config ARM_PATCH_IDIV 1206 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1207 depends on CPU_32v7 1208 default y 1209 help 1210 The ARM compiler inserts calls to __aeabi_idiv() and 1211 __aeabi_uidiv() when it needs to perform division on signed 1212 and unsigned integers. Some v7 CPUs have support for the sdiv 1213 and udiv instructions that can be used to implement those 1214 functions. 1215 1216 Enabling this option allows the kernel to modify itself to 1217 replace the first two instructions of these library functions 1218 with the sdiv or udiv plus "bx lr" instructions when the CPU 1219 it is running on supports them. Typically this will be faster 1220 and less power intensive than running the original library 1221 code to do integer division. 1222 1223config AEABI 1224 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1225 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1226 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1227 help 1228 This option allows for the kernel to be compiled using the latest 1229 ARM ABI (aka EABI). This is only useful if you are using a user 1230 space environment that is also compiled with EABI. 1231 1232 Since there are major incompatibilities between the legacy ABI and 1233 EABI, especially with regard to structure member alignment, this 1234 option also changes the kernel syscall calling convention to 1235 disambiguate both ABIs and allow for backward compatibility support 1236 (selected with CONFIG_OABI_COMPAT). 1237 1238 To use this you need GCC version 4.0.0 or later. 1239 1240config OABI_COMPAT 1241 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1242 depends on AEABI && !THUMB2_KERNEL 1243 help 1244 This option preserves the old syscall interface along with the 1245 new (ARM EABI) one. It also provides a compatibility layer to 1246 intercept syscalls that have structure arguments which layout 1247 in memory differs between the legacy ABI and the new ARM EABI 1248 (only for non "thumb" binaries). This option adds a tiny 1249 overhead to all syscalls and produces a slightly larger kernel. 1250 1251 The seccomp filter system will not be available when this is 1252 selected, since there is no way yet to sensibly distinguish 1253 between calling conventions during filtering. 1254 1255 If you know you'll be using only pure EABI user space then you 1256 can say N here. If this option is not selected and you attempt 1257 to execute a legacy ABI binary then the result will be 1258 UNPREDICTABLE (in fact it can be predicted that it won't work 1259 at all). If in doubt say N. 1260 1261config ARCH_SELECT_MEMORY_MODEL 1262 def_bool y 1263 1264config ARCH_FLATMEM_ENABLE 1265 def_bool !(ARCH_RPC || ARCH_SA1100) 1266 1267config ARCH_SPARSEMEM_ENABLE 1268 def_bool !ARCH_FOOTBRIDGE 1269 select SPARSEMEM_STATIC if SPARSEMEM 1270 1271config HIGHMEM 1272 bool "High Memory Support" 1273 depends on MMU 1274 select KMAP_LOCAL 1275 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1276 help 1277 The address space of ARM processors is only 4 Gigabytes large 1278 and it has to accommodate user address space, kernel address 1279 space as well as some memory mapped IO. That means that, if you 1280 have a large amount of physical memory and/or IO, not all of the 1281 memory can be "permanently mapped" by the kernel. The physical 1282 memory that is not permanently mapped is called "high memory". 1283 1284 Depending on the selected kernel/user memory split, minimum 1285 vmalloc space and actual amount of RAM, you may not need this 1286 option which should result in a slightly faster kernel. 1287 1288 If unsure, say n. 1289 1290config HIGHPTE 1291 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1292 depends on HIGHMEM 1293 default y 1294 help 1295 The VM uses one page of physical memory for each page table. 1296 For systems with a lot of processes, this can use a lot of 1297 precious low memory, eventually leading to low memory being 1298 consumed by page tables. Setting this option will allow 1299 user-space 2nd level page tables to reside in high memory. 1300 1301config CPU_SW_DOMAIN_PAN 1302 bool "Enable use of CPU domains to implement privileged no-access" 1303 depends on MMU && !ARM_LPAE 1304 default y 1305 help 1306 Increase kernel security by ensuring that normal kernel accesses 1307 are unable to access userspace addresses. This can help prevent 1308 use-after-free bugs becoming an exploitable privilege escalation 1309 by ensuring that magic values (such as LIST_POISON) will always 1310 fault when dereferenced. 1311 1312 CPUs with low-vector mappings use a best-efforts implementation. 1313 Their lower 1MB needs to remain accessible for the vectors, but 1314 the remainder of userspace will become appropriately inaccessible. 1315 1316config HW_PERF_EVENTS 1317 def_bool y 1318 depends on ARM_PMU 1319 1320config ARM_MODULE_PLTS 1321 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1322 depends on MODULES 1323 select KASAN_VMALLOC if KASAN 1324 default y 1325 help 1326 Allocate PLTs when loading modules so that jumps and calls whose 1327 targets are too far away for their relative offsets to be encoded 1328 in the instructions themselves can be bounced via veneers in the 1329 module's PLT. This allows modules to be allocated in the generic 1330 vmalloc area after the dedicated module memory area has been 1331 exhausted. The modules will use slightly more memory, but after 1332 rounding up to page size, the actual memory footprint is usually 1333 the same. 1334 1335 Disabling this is usually safe for small single-platform 1336 configurations. If unsure, say y. 1337 1338config ARCH_FORCE_MAX_ORDER 1339 int "Maximum zone order" 1340 default "12" if SOC_AM33XX 1341 default "9" if SA1111 1342 default "11" 1343 help 1344 The kernel memory allocator divides physically contiguous memory 1345 blocks into "zones", where each zone is a power of two number of 1346 pages. This option selects the largest power of two that the kernel 1347 keeps in the memory allocator. If you need to allocate very large 1348 blocks of physically contiguous memory, then you may need to 1349 increase this value. 1350 1351 This config option is actually maximum order plus one. For example, 1352 a value of 11 means that the largest free memory block is 2^10 pages. 1353 1354config ALIGNMENT_TRAP 1355 def_bool CPU_CP15_MMU 1356 select HAVE_PROC_CPU if PROC_FS 1357 help 1358 ARM processors cannot fetch/store information which is not 1359 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1360 address divisible by 4. On 32-bit ARM processors, these non-aligned 1361 fetch/store instructions will be emulated in software if you say 1362 here, which has a severe performance impact. This is necessary for 1363 correct operation of some network protocols. With an IP-only 1364 configuration it is safe to say N, otherwise say Y. 1365 1366config UACCESS_WITH_MEMCPY 1367 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1368 depends on MMU 1369 default y if CPU_FEROCEON 1370 help 1371 Implement faster copy_to_user and clear_user methods for CPU 1372 cores where a 8-word STM instruction give significantly higher 1373 memory write throughput than a sequence of individual 32bit stores. 1374 1375 A possible side effect is a slight increase in scheduling latency 1376 between threads sharing the same address space if they invoke 1377 such copy operations with large buffers. 1378 1379 However, if the CPU data cache is using a write-allocate mode, 1380 this option is unlikely to provide any performance gain. 1381 1382config PARAVIRT 1383 bool "Enable paravirtualization code" 1384 help 1385 This changes the kernel so it can modify itself when it is run 1386 under a hypervisor, potentially improving performance significantly 1387 over full virtualization. 1388 1389config PARAVIRT_TIME_ACCOUNTING 1390 bool "Paravirtual steal time accounting" 1391 select PARAVIRT 1392 help 1393 Select this option to enable fine granularity task steal time 1394 accounting. Time spent executing other tasks in parallel with 1395 the current vCPU is discounted from the vCPU power. To account for 1396 that, there can be a small performance impact. 1397 1398 If in doubt, say N here. 1399 1400config XEN_DOM0 1401 def_bool y 1402 depends on XEN 1403 1404config XEN 1405 bool "Xen guest support on ARM" 1406 depends on ARM && AEABI && OF 1407 depends on CPU_V7 && !CPU_V6 1408 depends on !GENERIC_ATOMIC64 1409 depends on MMU 1410 select ARCH_DMA_ADDR_T_64BIT 1411 select ARM_PSCI 1412 select SWIOTLB 1413 select SWIOTLB_XEN 1414 select PARAVIRT 1415 help 1416 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1417 1418config CC_HAVE_STACKPROTECTOR_TLS 1419 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1420 1421config STACKPROTECTOR_PER_TASK 1422 bool "Use a unique stack canary value for each task" 1423 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1424 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1425 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1426 default y 1427 help 1428 Due to the fact that GCC uses an ordinary symbol reference from 1429 which to load the value of the stack canary, this value can only 1430 change at reboot time on SMP systems, and all tasks running in the 1431 kernel's address space are forced to use the same canary value for 1432 the entire duration that the system is up. 1433 1434 Enable this option to switch to a different method that uses a 1435 different canary value for each task. 1436 1437endmenu 1438 1439menu "Boot options" 1440 1441config USE_OF 1442 bool "Flattened Device Tree support" 1443 select IRQ_DOMAIN 1444 select OF 1445 help 1446 Include support for flattened device tree machine descriptions. 1447 1448config ATAGS 1449 bool "Support for the traditional ATAGS boot data passing" 1450 default y 1451 help 1452 This is the traditional way of passing data to the kernel at boot 1453 time. If you are solely relying on the flattened device tree (or 1454 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1455 to remove ATAGS support from your kernel binary. 1456 1457config DEPRECATED_PARAM_STRUCT 1458 bool "Provide old way to pass kernel parameters" 1459 depends on ATAGS 1460 help 1461 This was deprecated in 2001 and announced to live on for 5 years. 1462 Some old boot loaders still use this way. 1463 1464# Compressed boot loader in ROM. Yes, we really want to ask about 1465# TEXT and BSS so we preserve their values in the config files. 1466config ZBOOT_ROM_TEXT 1467 hex "Compressed ROM boot loader base address" 1468 default 0x0 1469 help 1470 The physical address at which the ROM-able zImage is to be 1471 placed in the target. Platforms which normally make use of 1472 ROM-able zImage formats normally set this to a suitable 1473 value in their defconfig file. 1474 1475 If ZBOOT_ROM is not enabled, this has no effect. 1476 1477config ZBOOT_ROM_BSS 1478 hex "Compressed ROM boot loader BSS address" 1479 default 0x0 1480 help 1481 The base address of an area of read/write memory in the target 1482 for the ROM-able zImage which must be available while the 1483 decompressor is running. It must be large enough to hold the 1484 entire decompressed kernel plus an additional 128 KiB. 1485 Platforms which normally make use of ROM-able zImage formats 1486 normally set this to a suitable value in their defconfig file. 1487 1488 If ZBOOT_ROM is not enabled, this has no effect. 1489 1490config ZBOOT_ROM 1491 bool "Compressed boot loader in ROM/flash" 1492 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1493 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1494 help 1495 Say Y here if you intend to execute your compressed kernel image 1496 (zImage) directly from ROM or flash. If unsure, say N. 1497 1498config ARM_APPENDED_DTB 1499 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1500 depends on OF 1501 help 1502 With this option, the boot code will look for a device tree binary 1503 (DTB) appended to zImage 1504 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1505 1506 This is meant as a backward compatibility convenience for those 1507 systems with a bootloader that can't be upgraded to accommodate 1508 the documented boot protocol using a device tree. 1509 1510 Beware that there is very little in terms of protection against 1511 this option being confused by leftover garbage in memory that might 1512 look like a DTB header after a reboot if no actual DTB is appended 1513 to zImage. Do not leave this option active in a production kernel 1514 if you don't intend to always append a DTB. Proper passing of the 1515 location into r2 of a bootloader provided DTB is always preferable 1516 to this option. 1517 1518config ARM_ATAG_DTB_COMPAT 1519 bool "Supplement the appended DTB with traditional ATAG information" 1520 depends on ARM_APPENDED_DTB 1521 help 1522 Some old bootloaders can't be updated to a DTB capable one, yet 1523 they provide ATAGs with memory configuration, the ramdisk address, 1524 the kernel cmdline string, etc. Such information is dynamically 1525 provided by the bootloader and can't always be stored in a static 1526 DTB. To allow a device tree enabled kernel to be used with such 1527 bootloaders, this option allows zImage to extract the information 1528 from the ATAG list and store it at run time into the appended DTB. 1529 1530choice 1531 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1532 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1533 1534config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1535 bool "Use bootloader kernel arguments if available" 1536 help 1537 Uses the command-line options passed by the boot loader instead of 1538 the device tree bootargs property. If the boot loader doesn't provide 1539 any, the device tree bootargs property will be used. 1540 1541config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1542 bool "Extend with bootloader kernel arguments" 1543 help 1544 The command-line arguments provided by the boot loader will be 1545 appended to the the device tree bootargs property. 1546 1547endchoice 1548 1549config CMDLINE 1550 string "Default kernel command string" 1551 default "" 1552 help 1553 On some architectures (e.g. CATS), there is currently no way 1554 for the boot loader to pass arguments to the kernel. For these 1555 architectures, you should supply some command-line options at build 1556 time by entering them here. As a minimum, you should specify the 1557 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1558 1559choice 1560 prompt "Kernel command line type" if CMDLINE != "" 1561 default CMDLINE_FROM_BOOTLOADER 1562 1563config CMDLINE_FROM_BOOTLOADER 1564 bool "Use bootloader kernel arguments if available" 1565 help 1566 Uses the command-line options passed by the boot loader. If 1567 the boot loader doesn't provide any, the default kernel command 1568 string provided in CMDLINE will be used. 1569 1570config CMDLINE_EXTEND 1571 bool "Extend bootloader kernel arguments" 1572 help 1573 The command-line arguments provided by the boot loader will be 1574 appended to the default kernel command string. 1575 1576config CMDLINE_FORCE 1577 bool "Always use the default kernel command string" 1578 help 1579 Always use the default kernel command string, even if the boot 1580 loader passes other arguments to the kernel. 1581 This is useful if you cannot or don't want to change the 1582 command-line options your boot loader passes to the kernel. 1583endchoice 1584 1585config XIP_KERNEL 1586 bool "Kernel Execute-In-Place from ROM" 1587 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1588 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1589 help 1590 Execute-In-Place allows the kernel to run from non-volatile storage 1591 directly addressable by the CPU, such as NOR flash. This saves RAM 1592 space since the text section of the kernel is not loaded from flash 1593 to RAM. Read-write sections, such as the data section and stack, 1594 are still copied to RAM. The XIP kernel is not compressed since 1595 it has to run directly from flash, so it will take more space to 1596 store it. The flash address used to link the kernel object files, 1597 and for storing it, is configuration dependent. Therefore, if you 1598 say Y here, you must know the proper physical address where to 1599 store the kernel image depending on your own flash memory usage. 1600 1601 Also note that the make target becomes "make xipImage" rather than 1602 "make zImage" or "make Image". The final kernel binary to put in 1603 ROM memory will be arch/arm/boot/xipImage. 1604 1605 If unsure, say N. 1606 1607config XIP_PHYS_ADDR 1608 hex "XIP Kernel Physical Location" 1609 depends on XIP_KERNEL 1610 default "0x00080000" 1611 help 1612 This is the physical address in your flash memory the kernel will 1613 be linked for and stored to. This address is dependent on your 1614 own flash usage. 1615 1616config XIP_DEFLATED_DATA 1617 bool "Store kernel .data section compressed in ROM" 1618 depends on XIP_KERNEL 1619 select ZLIB_INFLATE 1620 help 1621 Before the kernel is actually executed, its .data section has to be 1622 copied to RAM from ROM. This option allows for storing that data 1623 in compressed form and decompressed to RAM rather than merely being 1624 copied, saving some precious ROM space. A possible drawback is a 1625 slightly longer boot delay. 1626 1627config KEXEC 1628 bool "Kexec system call (EXPERIMENTAL)" 1629 depends on (!SMP || PM_SLEEP_SMP) 1630 depends on MMU 1631 select KEXEC_CORE 1632 help 1633 kexec is a system call that implements the ability to shutdown your 1634 current kernel, and to start another kernel. It is like a reboot 1635 but it is independent of the system firmware. And like a reboot 1636 you can start any kernel with it, not just Linux. 1637 1638 It is an ongoing process to be certain the hardware in a machine 1639 is properly shutdown, so do not be surprised if this code does not 1640 initially work for you. 1641 1642config ATAGS_PROC 1643 bool "Export atags in procfs" 1644 depends on ATAGS && KEXEC 1645 default y 1646 help 1647 Should the atags used to boot the kernel be exported in an "atags" 1648 file in procfs. Useful with kexec. 1649 1650config CRASH_DUMP 1651 bool "Build kdump crash kernel (EXPERIMENTAL)" 1652 help 1653 Generate crash dump after being started by kexec. This should 1654 be normally only set in special crash dump kernels which are 1655 loaded in the main kernel with kexec-tools into a specially 1656 reserved region and then later executed after a crash by 1657 kdump/kexec. The crash dump kernel must be compiled to a 1658 memory address not used by the main kernel 1659 1660 For more details see Documentation/admin-guide/kdump/kdump.rst 1661 1662config AUTO_ZRELADDR 1663 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1664 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1665 help 1666 ZRELADDR is the physical address where the decompressed kernel 1667 image will be placed. If AUTO_ZRELADDR is selected, the address 1668 will be determined at run-time, either by masking the current IP 1669 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1670 This assumes the zImage being placed in the first 128MB from 1671 start of memory. 1672 1673config EFI_STUB 1674 bool 1675 1676config EFI 1677 bool "UEFI runtime support" 1678 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1679 select UCS2_STRING 1680 select EFI_PARAMS_FROM_FDT 1681 select EFI_STUB 1682 select EFI_GENERIC_STUB 1683 select EFI_RUNTIME_WRAPPERS 1684 help 1685 This option provides support for runtime services provided 1686 by UEFI firmware (such as non-volatile variables, realtime 1687 clock, and platform reset). A UEFI stub is also provided to 1688 allow the kernel to be booted as an EFI application. This 1689 is only useful for kernels that may run on systems that have 1690 UEFI firmware. 1691 1692config DMI 1693 bool "Enable support for SMBIOS (DMI) tables" 1694 depends on EFI 1695 default y 1696 help 1697 This enables SMBIOS/DMI feature for systems. 1698 1699 This option is only useful on systems that have UEFI firmware. 1700 However, even with this option, the resultant kernel should 1701 continue to boot on existing non-UEFI platforms. 1702 1703 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1704 i.e., the the practice of identifying the platform via DMI to 1705 decide whether certain workarounds for buggy hardware and/or 1706 firmware need to be enabled. This would require the DMI subsystem 1707 to be enabled much earlier than we do on ARM, which is non-trivial. 1708 1709endmenu 1710 1711menu "CPU Power Management" 1712 1713source "drivers/cpufreq/Kconfig" 1714 1715source "drivers/cpuidle/Kconfig" 1716 1717endmenu 1718 1719menu "Floating point emulation" 1720 1721comment "At least one emulation must be selected" 1722 1723config FPE_NWFPE 1724 bool "NWFPE math emulation" 1725 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1726 help 1727 Say Y to include the NWFPE floating point emulator in the kernel. 1728 This is necessary to run most binaries. Linux does not currently 1729 support floating point hardware so you need to say Y here even if 1730 your machine has an FPA or floating point co-processor podule. 1731 1732 You may say N here if you are going to load the Acorn FPEmulator 1733 early in the bootup. 1734 1735config FPE_NWFPE_XP 1736 bool "Support extended precision" 1737 depends on FPE_NWFPE 1738 help 1739 Say Y to include 80-bit support in the kernel floating-point 1740 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1741 Note that gcc does not generate 80-bit operations by default, 1742 so in most cases this option only enlarges the size of the 1743 floating point emulator without any good reason. 1744 1745 You almost surely want to say N here. 1746 1747config FPE_FASTFPE 1748 bool "FastFPE math emulation (EXPERIMENTAL)" 1749 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1750 help 1751 Say Y here to include the FAST floating point emulator in the kernel. 1752 This is an experimental much faster emulator which now also has full 1753 precision for the mantissa. It does not support any exceptions. 1754 It is very simple, and approximately 3-6 times faster than NWFPE. 1755 1756 It should be sufficient for most programs. It may be not suitable 1757 for scientific calculations, but you have to check this for yourself. 1758 If you do not feel you need a faster FP emulation you should better 1759 choose NWFPE. 1760 1761config VFP 1762 bool "VFP-format floating point maths" 1763 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1764 help 1765 Say Y to include VFP support code in the kernel. This is needed 1766 if your hardware includes a VFP unit. 1767 1768 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1769 release notes and additional status information. 1770 1771 Say N if your target does not have VFP hardware. 1772 1773config VFPv3 1774 bool 1775 depends on VFP 1776 default y if CPU_V7 1777 1778config NEON 1779 bool "Advanced SIMD (NEON) Extension support" 1780 depends on VFPv3 && CPU_V7 1781 help 1782 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1783 Extension. 1784 1785config KERNEL_MODE_NEON 1786 bool "Support for NEON in kernel mode" 1787 depends on NEON && AEABI 1788 help 1789 Say Y to include support for NEON in kernel mode. 1790 1791endmenu 1792 1793menu "Power management options" 1794 1795source "kernel/power/Kconfig" 1796 1797config ARCH_SUSPEND_POSSIBLE 1798 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1799 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1800 def_bool y 1801 1802config ARM_CPU_SUSPEND 1803 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1804 depends on ARCH_SUSPEND_POSSIBLE 1805 1806config ARCH_HIBERNATION_POSSIBLE 1807 bool 1808 depends on MMU 1809 default y if ARCH_SUSPEND_POSSIBLE 1810 1811endmenu 1812 1813source "arch/arm/Kconfig.assembler" 1814