1config ARM 2 bool 3 default y 4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 6 select ARCH_HAVE_CUSTOM_GPIO_H 7 select ARCH_WANT_IPC_PARSE_VERSION 8 select BUILDTIME_EXTABLE_SORT if MMU 9 select CPU_PM if (SUSPEND || CPU_IDLE) 10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU 11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 13 select GENERIC_IRQ_PROBE 14 select GENERIC_IRQ_SHOW 15 select GENERIC_PCI_IOMAP 16 select GENERIC_SMP_IDLE_THREAD 17 select GENERIC_STRNCPY_FROM_USER 18 select GENERIC_STRNLEN_USER 19 select HARDIRQS_SW_RESEND 20 select HAVE_AOUT 21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 22 select HAVE_ARCH_KGDB 23 select HAVE_ARCH_SECCOMP_FILTER 24 select HAVE_ARCH_TRACEHOOK 25 select HAVE_BPF_JIT 26 select HAVE_C_RECORDMCOUNT 27 select HAVE_DEBUG_KMEMLEAK 28 select HAVE_DMA_API_DEBUG 29 select HAVE_DMA_ATTRS 30 select HAVE_DMA_CONTIGUOUS if MMU 31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 35 select HAVE_GENERIC_DMA_COHERENT 36 select HAVE_GENERIC_HARDIRQS 37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 38 select HAVE_IDE if PCI || ISA || PCMCIA 39 select HAVE_IRQ_WORK 40 select HAVE_KERNEL_GZIP 41 select HAVE_KERNEL_LZMA 42 select HAVE_KERNEL_LZO 43 select HAVE_KERNEL_XZ 44 select HAVE_KPROBES if !XIP_KERNEL 45 select HAVE_KRETPROBES if (HAVE_KPROBES) 46 select HAVE_MEMBLOCK 47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 48 select HAVE_PERF_EVENTS 49 select HAVE_REGS_AND_STACK_ACCESS_API 50 select HAVE_SYSCALL_TRACEPOINTS 51 select HAVE_UID16 52 select KTIME_SCALAR 53 select PERF_USE_VMALLOC 54 select RTC_LIB 55 select SYS_SUPPORTS_APM_EMULATION 56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND 57 select MODULES_USE_ELF_REL 58 select CLONE_BACKWARDS 59 help 60 The ARM series is a line of low-power-consumption RISC chip designs 61 licensed by ARM Ltd and targeted at embedded applications and 62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 63 manufactured, but legacy ARM-based PC hardware remains popular in 64 Europe. There is an ARM Linux project with a web page at 65 <http://www.arm.linux.org.uk/>. 66 67config ARM_HAS_SG_CHAIN 68 bool 69 70config NEED_SG_DMA_LENGTH 71 bool 72 73config ARM_DMA_USE_IOMMU 74 bool 75 select ARM_HAS_SG_CHAIN 76 select NEED_SG_DMA_LENGTH 77 78config HAVE_PWM 79 bool 80 81config MIGHT_HAVE_PCI 82 bool 83 84config SYS_SUPPORTS_APM_EMULATION 85 bool 86 87config GENERIC_GPIO 88 bool 89 90config HAVE_TCM 91 bool 92 select GENERIC_ALLOCATOR 93 94config HAVE_PROC_CPU 95 bool 96 97config NO_IOPORT 98 bool 99 100config EISA 101 bool 102 ---help--- 103 The Extended Industry Standard Architecture (EISA) bus was 104 developed as an open alternative to the IBM MicroChannel bus. 105 106 The EISA bus provided some of the features of the IBM MicroChannel 107 bus while maintaining backward compatibility with cards made for 108 the older ISA bus. The EISA bus saw limited use between 1988 and 109 1995 when it was made obsolete by the PCI bus. 110 111 Say Y here if you are building a kernel for an EISA-based machine. 112 113 Otherwise, say N. 114 115config SBUS 116 bool 117 118config STACKTRACE_SUPPORT 119 bool 120 default y 121 122config HAVE_LATENCYTOP_SUPPORT 123 bool 124 depends on !SMP 125 default y 126 127config LOCKDEP_SUPPORT 128 bool 129 default y 130 131config TRACE_IRQFLAGS_SUPPORT 132 bool 133 default y 134 135config RWSEM_GENERIC_SPINLOCK 136 bool 137 default y 138 139config RWSEM_XCHGADD_ALGORITHM 140 bool 141 142config ARCH_HAS_ILOG2_U32 143 bool 144 145config ARCH_HAS_ILOG2_U64 146 bool 147 148config ARCH_HAS_CPUFREQ 149 bool 150 help 151 Internal node to signify that the ARCH has CPUFREQ support 152 and that the relevant menu configurations are displayed for 153 it. 154 155config GENERIC_HWEIGHT 156 bool 157 default y 158 159config GENERIC_CALIBRATE_DELAY 160 bool 161 default y 162 163config ARCH_MAY_HAVE_PC_FDC 164 bool 165 166config ZONE_DMA 167 bool 168 169config NEED_DMA_MAP_STATE 170 def_bool y 171 172config ARCH_HAS_DMA_SET_COHERENT_MASK 173 bool 174 175config GENERIC_ISA_DMA 176 bool 177 178config FIQ 179 bool 180 181config NEED_RET_TO_USER 182 bool 183 184config ARCH_MTD_XIP 185 bool 186 187config VECTORS_BASE 188 hex 189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 190 default DRAM_BASE if REMAP_VECTORS_TO_RAM 191 default 0x00000000 192 help 193 The base address of exception vectors. 194 195config ARM_PATCH_PHYS_VIRT 196 bool "Patch physical to virtual translations at runtime" if EMBEDDED 197 default y 198 depends on !XIP_KERNEL && MMU 199 depends on !ARCH_REALVIEW || !SPARSEMEM 200 help 201 Patch phys-to-virt and virt-to-phys translation functions at 202 boot and module load time according to the position of the 203 kernel in system memory. 204 205 This can only be used with non-XIP MMU kernels where the base 206 of physical memory is at a 16MB boundary. 207 208 Only disable this option if you know that you do not require 209 this feature (eg, building a kernel for a single machine) and 210 you need to shrink the kernel to the minimal size. 211 212config NEED_MACH_GPIO_H 213 bool 214 help 215 Select this when mach/gpio.h is required to provide special 216 definitions for this platform. The need for mach/gpio.h should 217 be avoided when possible. 218 219config NEED_MACH_IO_H 220 bool 221 help 222 Select this when mach/io.h is required to provide special 223 definitions for this platform. The need for mach/io.h should 224 be avoided when possible. 225 226config NEED_MACH_MEMORY_H 227 bool 228 help 229 Select this when mach/memory.h is required to provide special 230 definitions for this platform. The need for mach/memory.h should 231 be avoided when possible. 232 233config PHYS_OFFSET 234 hex "Physical address of main memory" if MMU 235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 236 default DRAM_BASE if !MMU 237 help 238 Please provide the physical address corresponding to the 239 location of main memory in your system. 240 241config GENERIC_BUG 242 def_bool y 243 depends on BUG 244 245source "init/Kconfig" 246 247source "kernel/Kconfig.freezer" 248 249menu "System Type" 250 251config MMU 252 bool "MMU-based Paged Memory Management Support" 253 default y 254 help 255 Select if you want MMU-based virtualised addressing space 256 support by paged memory management. If unsure, say 'Y'. 257 258# 259# The "ARM system type" choice list is ordered alphabetically by option 260# text. Please add new entries in the option alphabetic order. 261# 262choice 263 prompt "ARM system type" 264 default ARCH_MULTIPLATFORM 265 266config ARCH_MULTIPLATFORM 267 bool "Allow multiple platforms to be selected" 268 depends on MMU 269 select ARM_PATCH_PHYS_VIRT 270 select AUTO_ZRELADDR 271 select COMMON_CLK 272 select MULTI_IRQ_HANDLER 273 select SPARSE_IRQ 274 select USE_OF 275 276config ARCH_INTEGRATOR 277 bool "ARM Ltd. Integrator family" 278 select ARCH_HAS_CPUFREQ 279 select ARM_AMBA 280 select COMMON_CLK 281 select COMMON_CLK_VERSATILE 282 select GENERIC_CLOCKEVENTS 283 select HAVE_TCM 284 select ICST 285 select MULTI_IRQ_HANDLER 286 select NEED_MACH_MEMORY_H 287 select PLAT_VERSATILE 288 select SPARSE_IRQ 289 select VERSATILE_FPGA_IRQ 290 help 291 Support for ARM's Integrator platform. 292 293config ARCH_REALVIEW 294 bool "ARM Ltd. RealView family" 295 select ARCH_WANT_OPTIONAL_GPIOLIB 296 select ARM_AMBA 297 select ARM_TIMER_SP804 298 select COMMON_CLK 299 select COMMON_CLK_VERSATILE 300 select GENERIC_CLOCKEVENTS 301 select GPIO_PL061 if GPIOLIB 302 select ICST 303 select NEED_MACH_MEMORY_H 304 select PLAT_VERSATILE 305 select PLAT_VERSATILE_CLCD 306 help 307 This enables support for ARM Ltd RealView boards. 308 309config ARCH_VERSATILE 310 bool "ARM Ltd. Versatile family" 311 select ARCH_WANT_OPTIONAL_GPIOLIB 312 select ARM_AMBA 313 select ARM_TIMER_SP804 314 select ARM_VIC 315 select CLKDEV_LOOKUP 316 select GENERIC_CLOCKEVENTS 317 select HAVE_MACH_CLKDEV 318 select ICST 319 select PLAT_VERSATILE 320 select PLAT_VERSATILE_CLCD 321 select PLAT_VERSATILE_CLOCK 322 select VERSATILE_FPGA_IRQ 323 help 324 This enables support for ARM Ltd Versatile board. 325 326config ARCH_AT91 327 bool "Atmel AT91" 328 select ARCH_REQUIRE_GPIOLIB 329 select CLKDEV_LOOKUP 330 select HAVE_CLK 331 select IRQ_DOMAIN 332 select NEED_MACH_GPIO_H 333 select NEED_MACH_IO_H if PCCARD 334 select PINCTRL 335 select PINCTRL_AT91 if USE_OF 336 help 337 This enables support for systems based on Atmel 338 AT91RM9200 and AT91SAM9* processors. 339 340config ARCH_BCM2835 341 bool "Broadcom BCM2835 family" 342 select ARCH_REQUIRE_GPIOLIB 343 select ARM_AMBA 344 select ARM_ERRATA_411920 345 select ARM_TIMER_SP804 346 select CLKDEV_LOOKUP 347 select COMMON_CLK 348 select CPU_V6 349 select GENERIC_CLOCKEVENTS 350 select GENERIC_GPIO 351 select MULTI_IRQ_HANDLER 352 select PINCTRL 353 select PINCTRL_BCM2835 354 select SPARSE_IRQ 355 select USE_OF 356 help 357 This enables support for the Broadcom BCM2835 SoC. This SoC is 358 use in the Raspberry Pi, and Roku 2 devices. 359 360config ARCH_CNS3XXX 361 bool "Cavium Networks CNS3XXX family" 362 select ARM_GIC 363 select CPU_V6K 364 select GENERIC_CLOCKEVENTS 365 select MIGHT_HAVE_CACHE_L2X0 366 select MIGHT_HAVE_PCI 367 select PCI_DOMAINS if PCI 368 help 369 Support for Cavium Networks CNS3XXX platform. 370 371config ARCH_CLPS711X 372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 373 select ARCH_REQUIRE_GPIOLIB 374 select AUTO_ZRELADDR 375 select CLKDEV_LOOKUP 376 select COMMON_CLK 377 select CPU_ARM720T 378 select GENERIC_CLOCKEVENTS 379 select MULTI_IRQ_HANDLER 380 select NEED_MACH_MEMORY_H 381 select SPARSE_IRQ 382 help 383 Support for Cirrus Logic 711x/721x/731x based boards. 384 385config ARCH_GEMINI 386 bool "Cortina Systems Gemini" 387 select ARCH_REQUIRE_GPIOLIB 388 select ARCH_USES_GETTIMEOFFSET 389 select CPU_FA526 390 help 391 Support for the Cortina Systems Gemini family SoCs 392 393config ARCH_SIRF 394 bool "CSR SiRF" 395 select ARCH_REQUIRE_GPIOLIB 396 select COMMON_CLK 397 select GENERIC_CLOCKEVENTS 398 select GENERIC_IRQ_CHIP 399 select MIGHT_HAVE_CACHE_L2X0 400 select NO_IOPORT 401 select PINCTRL 402 select PINCTRL_SIRF 403 select USE_OF 404 help 405 Support for CSR SiRFprimaII/Marco/Polo platforms 406 407config ARCH_EBSA110 408 bool "EBSA-110" 409 select ARCH_USES_GETTIMEOFFSET 410 select CPU_SA110 411 select ISA 412 select NEED_MACH_IO_H 413 select NEED_MACH_MEMORY_H 414 select NO_IOPORT 415 help 416 This is an evaluation board for the StrongARM processor available 417 from Digital. It has limited hardware on-board, including an 418 Ethernet interface, two PCMCIA sockets, two serial ports and a 419 parallel port. 420 421config ARCH_EP93XX 422 bool "EP93xx-based" 423 select ARCH_HAS_HOLES_MEMORYMODEL 424 select ARCH_REQUIRE_GPIOLIB 425 select ARCH_USES_GETTIMEOFFSET 426 select ARM_AMBA 427 select ARM_VIC 428 select CLKDEV_LOOKUP 429 select CPU_ARM920T 430 select NEED_MACH_MEMORY_H 431 help 432 This enables support for the Cirrus EP93xx series of CPUs. 433 434config ARCH_FOOTBRIDGE 435 bool "FootBridge" 436 select CPU_SA110 437 select FOOTBRIDGE 438 select GENERIC_CLOCKEVENTS 439 select HAVE_IDE 440 select NEED_MACH_IO_H if !MMU 441 select NEED_MACH_MEMORY_H 442 help 443 Support for systems based on the DC21285 companion chip 444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 445 446config ARCH_MXS 447 bool "Freescale MXS-based" 448 select ARCH_REQUIRE_GPIOLIB 449 select CLKDEV_LOOKUP 450 select CLKSRC_MMIO 451 select COMMON_CLK 452 select GENERIC_CLOCKEVENTS 453 select HAVE_CLK_PREPARE 454 select MULTI_IRQ_HANDLER 455 select PINCTRL 456 select SPARSE_IRQ 457 select USE_OF 458 help 459 Support for Freescale MXS-based family of processors 460 461config ARCH_NETX 462 bool "Hilscher NetX based" 463 select ARM_VIC 464 select CLKSRC_MMIO 465 select CPU_ARM926T 466 select GENERIC_CLOCKEVENTS 467 help 468 This enables support for systems based on the Hilscher NetX Soc 469 470config ARCH_H720X 471 bool "Hynix HMS720x-based" 472 select ARCH_USES_GETTIMEOFFSET 473 select CPU_ARM720T 474 select ISA_DMA_API 475 help 476 This enables support for systems based on the Hynix HMS720x 477 478config ARCH_IOP13XX 479 bool "IOP13xx-based" 480 depends on MMU 481 select ARCH_SUPPORTS_MSI 482 select CPU_XSC3 483 select NEED_MACH_MEMORY_H 484 select NEED_RET_TO_USER 485 select PCI 486 select PLAT_IOP 487 select VMSPLIT_1G 488 help 489 Support for Intel's IOP13XX (XScale) family of processors. 490 491config ARCH_IOP32X 492 bool "IOP32x-based" 493 depends on MMU 494 select ARCH_REQUIRE_GPIOLIB 495 select CPU_XSCALE 496 select NEED_MACH_GPIO_H 497 select NEED_RET_TO_USER 498 select PCI 499 select PLAT_IOP 500 help 501 Support for Intel's 80219 and IOP32X (XScale) family of 502 processors. 503 504config ARCH_IOP33X 505 bool "IOP33x-based" 506 depends on MMU 507 select ARCH_REQUIRE_GPIOLIB 508 select CPU_XSCALE 509 select NEED_MACH_GPIO_H 510 select NEED_RET_TO_USER 511 select PCI 512 select PLAT_IOP 513 help 514 Support for Intel's IOP33X (XScale) family of processors. 515 516config ARCH_IXP4XX 517 bool "IXP4xx-based" 518 depends on MMU 519 select ARCH_HAS_DMA_SET_COHERENT_MASK 520 select ARCH_REQUIRE_GPIOLIB 521 select CLKSRC_MMIO 522 select CPU_XSCALE 523 select DMABOUNCE if PCI 524 select GENERIC_CLOCKEVENTS 525 select MIGHT_HAVE_PCI 526 select NEED_MACH_IO_H 527 help 528 Support for Intel's IXP4XX (XScale) family of processors. 529 530config ARCH_DOVE 531 bool "Marvell Dove" 532 select ARCH_REQUIRE_GPIOLIB 533 select COMMON_CLK_DOVE 534 select CPU_V7 535 select GENERIC_CLOCKEVENTS 536 select MIGHT_HAVE_PCI 537 select PINCTRL 538 select PINCTRL_DOVE 539 select PLAT_ORION_LEGACY 540 select USB_ARCH_HAS_EHCI 541 help 542 Support for the Marvell Dove SoC 88AP510 543 544config ARCH_KIRKWOOD 545 bool "Marvell Kirkwood" 546 select ARCH_REQUIRE_GPIOLIB 547 select CPU_FEROCEON 548 select GENERIC_CLOCKEVENTS 549 select PCI 550 select PCI_QUIRKS 551 select PINCTRL 552 select PINCTRL_KIRKWOOD 553 select PLAT_ORION_LEGACY 554 help 555 Support for the following Marvell Kirkwood series SoCs: 556 88F6180, 88F6192 and 88F6281. 557 558config ARCH_MV78XX0 559 bool "Marvell MV78xx0" 560 select ARCH_REQUIRE_GPIOLIB 561 select CPU_FEROCEON 562 select GENERIC_CLOCKEVENTS 563 select PCI 564 select PLAT_ORION_LEGACY 565 help 566 Support for the following Marvell MV78xx0 series SoCs: 567 MV781x0, MV782x0. 568 569config ARCH_ORION5X 570 bool "Marvell Orion" 571 depends on MMU 572 select ARCH_REQUIRE_GPIOLIB 573 select CPU_FEROCEON 574 select GENERIC_CLOCKEVENTS 575 select PCI 576 select PLAT_ORION_LEGACY 577 help 578 Support for the following Marvell Orion 5x series SoCs: 579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 580 Orion-2 (5281), Orion-1-90 (6183). 581 582config ARCH_MMP 583 bool "Marvell PXA168/910/MMP2" 584 depends on MMU 585 select ARCH_REQUIRE_GPIOLIB 586 select CLKDEV_LOOKUP 587 select GENERIC_ALLOCATOR 588 select GENERIC_CLOCKEVENTS 589 select GPIO_PXA 590 select IRQ_DOMAIN 591 select NEED_MACH_GPIO_H 592 select PINCTRL 593 select PLAT_PXA 594 select SPARSE_IRQ 595 help 596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 597 598config ARCH_KS8695 599 bool "Micrel/Kendin KS8695" 600 select ARCH_REQUIRE_GPIOLIB 601 select CLKSRC_MMIO 602 select CPU_ARM922T 603 select GENERIC_CLOCKEVENTS 604 select NEED_MACH_MEMORY_H 605 help 606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 607 System-on-Chip devices. 608 609config ARCH_W90X900 610 bool "Nuvoton W90X900 CPU" 611 select ARCH_REQUIRE_GPIOLIB 612 select CLKDEV_LOOKUP 613 select CLKSRC_MMIO 614 select CPU_ARM926T 615 select GENERIC_CLOCKEVENTS 616 help 617 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 618 At present, the w90x900 has been renamed nuc900, regarding 619 the ARM series product line, you can login the following 620 link address to know more. 621 622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 624 625config ARCH_LPC32XX 626 bool "NXP LPC32XX" 627 select ARCH_REQUIRE_GPIOLIB 628 select ARM_AMBA 629 select CLKDEV_LOOKUP 630 select CLKSRC_MMIO 631 select CPU_ARM926T 632 select GENERIC_CLOCKEVENTS 633 select HAVE_IDE 634 select HAVE_PWM 635 select USB_ARCH_HAS_OHCI 636 select USE_OF 637 help 638 Support for the NXP LPC32XX family of processors 639 640config ARCH_TEGRA 641 bool "NVIDIA Tegra" 642 select ARCH_HAS_CPUFREQ 643 select CLKDEV_LOOKUP 644 select CLKSRC_MMIO 645 select COMMON_CLK 646 select GENERIC_CLOCKEVENTS 647 select GENERIC_GPIO 648 select HAVE_CLK 649 select HAVE_SMP 650 select MIGHT_HAVE_CACHE_L2X0 651 select SPARSE_IRQ 652 select USE_OF 653 help 654 This enables support for NVIDIA Tegra based systems (Tegra APX, 655 Tegra 6xx and Tegra 2 series). 656 657config ARCH_PXA 658 bool "PXA2xx/PXA3xx-based" 659 depends on MMU 660 select ARCH_HAS_CPUFREQ 661 select ARCH_MTD_XIP 662 select ARCH_REQUIRE_GPIOLIB 663 select ARM_CPU_SUSPEND if PM 664 select AUTO_ZRELADDR 665 select CLKDEV_LOOKUP 666 select CLKSRC_MMIO 667 select GENERIC_CLOCKEVENTS 668 select GPIO_PXA 669 select HAVE_IDE 670 select MULTI_IRQ_HANDLER 671 select NEED_MACH_GPIO_H 672 select PLAT_PXA 673 select SPARSE_IRQ 674 help 675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 676 677config ARCH_MSM 678 bool "Qualcomm MSM" 679 select ARCH_REQUIRE_GPIOLIB 680 select CLKDEV_LOOKUP 681 select GENERIC_CLOCKEVENTS 682 select HAVE_CLK 683 help 684 Support for Qualcomm MSM/QSD based systems. This runs on the 685 apps processor of the MSM/QSD and depends on a shared memory 686 interface to the modem processor which runs the baseband 687 stack and controls some vital subsystems 688 (clock and power control, etc). 689 690config ARCH_SHMOBILE 691 bool "Renesas SH-Mobile / R-Mobile" 692 select CLKDEV_LOOKUP 693 select GENERIC_CLOCKEVENTS 694 select HAVE_CLK 695 select HAVE_MACH_CLKDEV 696 select HAVE_SMP 697 select MIGHT_HAVE_CACHE_L2X0 698 select MULTI_IRQ_HANDLER 699 select NEED_MACH_MEMORY_H 700 select NO_IOPORT 701 select PM_GENERIC_DOMAINS if PM 702 select SPARSE_IRQ 703 help 704 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 705 706config ARCH_RPC 707 bool "RiscPC" 708 select ARCH_ACORN 709 select ARCH_MAY_HAVE_PC_FDC 710 select ARCH_SPARSEMEM_ENABLE 711 select ARCH_USES_GETTIMEOFFSET 712 select FIQ 713 select HAVE_IDE 714 select HAVE_PATA_PLATFORM 715 select ISA_DMA_API 716 select NEED_MACH_IO_H 717 select NEED_MACH_MEMORY_H 718 select NO_IOPORT 719 help 720 On the Acorn Risc-PC, Linux can support the internal IDE disk and 721 CD-ROM interface, serial and parallel port, and the floppy drive. 722 723config ARCH_SA1100 724 bool "SA1100-based" 725 select ARCH_HAS_CPUFREQ 726 select ARCH_MTD_XIP 727 select ARCH_REQUIRE_GPIOLIB 728 select ARCH_SPARSEMEM_ENABLE 729 select CLKDEV_LOOKUP 730 select CLKSRC_MMIO 731 select CPU_FREQ 732 select CPU_SA1100 733 select GENERIC_CLOCKEVENTS 734 select HAVE_IDE 735 select ISA 736 select NEED_MACH_GPIO_H 737 select NEED_MACH_MEMORY_H 738 select SPARSE_IRQ 739 help 740 Support for StrongARM 11x0 based boards. 741 742config ARCH_S3C24XX 743 bool "Samsung S3C24XX SoCs" 744 select ARCH_HAS_CPUFREQ 745 select ARCH_USES_GETTIMEOFFSET 746 select CLKDEV_LOOKUP 747 select GENERIC_GPIO 748 select HAVE_CLK 749 select HAVE_S3C2410_I2C if I2C 750 select HAVE_S3C2410_WATCHDOG if WATCHDOG 751 select HAVE_S3C_RTC if RTC_CLASS 752 select NEED_MACH_GPIO_H 753 select NEED_MACH_IO_H 754 help 755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 758 Samsung SMDK2410 development board (and derivatives). 759 760config ARCH_S3C64XX 761 bool "Samsung S3C64XX" 762 select ARCH_HAS_CPUFREQ 763 select ARCH_REQUIRE_GPIOLIB 764 select ARCH_USES_GETTIMEOFFSET 765 select ARM_VIC 766 select CLKDEV_LOOKUP 767 select CPU_V6 768 select HAVE_CLK 769 select HAVE_S3C2410_I2C if I2C 770 select HAVE_S3C2410_WATCHDOG if WATCHDOG 771 select HAVE_TCM 772 select NEED_MACH_GPIO_H 773 select NO_IOPORT 774 select PLAT_SAMSUNG 775 select S3C_DEV_NAND 776 select S3C_GPIO_TRACK 777 select SAMSUNG_CLKSRC 778 select SAMSUNG_GPIOLIB_4BIT 779 select SAMSUNG_IRQ_VIC_TIMER 780 select USB_ARCH_HAS_OHCI 781 help 782 Samsung S3C64XX series based systems 783 784config ARCH_S5P64X0 785 bool "Samsung S5P6440 S5P6450" 786 select CLKDEV_LOOKUP 787 select CLKSRC_MMIO 788 select CPU_V6 789 select GENERIC_CLOCKEVENTS 790 select GENERIC_GPIO 791 select HAVE_CLK 792 select HAVE_S3C2410_I2C if I2C 793 select HAVE_S3C2410_WATCHDOG if WATCHDOG 794 select HAVE_S3C_RTC if RTC_CLASS 795 select NEED_MACH_GPIO_H 796 help 797 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 798 SMDK6450. 799 800config ARCH_S5PC100 801 bool "Samsung S5PC100" 802 select ARCH_USES_GETTIMEOFFSET 803 select CLKDEV_LOOKUP 804 select CPU_V7 805 select GENERIC_GPIO 806 select HAVE_CLK 807 select HAVE_S3C2410_I2C if I2C 808 select HAVE_S3C2410_WATCHDOG if WATCHDOG 809 select HAVE_S3C_RTC if RTC_CLASS 810 select NEED_MACH_GPIO_H 811 help 812 Samsung S5PC100 series based systems 813 814config ARCH_S5PV210 815 bool "Samsung S5PV210/S5PC110" 816 select ARCH_HAS_CPUFREQ 817 select ARCH_HAS_HOLES_MEMORYMODEL 818 select ARCH_SPARSEMEM_ENABLE 819 select CLKDEV_LOOKUP 820 select CLKSRC_MMIO 821 select CPU_V7 822 select GENERIC_CLOCKEVENTS 823 select GENERIC_GPIO 824 select HAVE_CLK 825 select HAVE_S3C2410_I2C if I2C 826 select HAVE_S3C2410_WATCHDOG if WATCHDOG 827 select HAVE_S3C_RTC if RTC_CLASS 828 select NEED_MACH_GPIO_H 829 select NEED_MACH_MEMORY_H 830 help 831 Samsung S5PV210/S5PC110 series based systems 832 833config ARCH_EXYNOS 834 bool "Samsung EXYNOS" 835 select ARCH_HAS_CPUFREQ 836 select ARCH_HAS_HOLES_MEMORYMODEL 837 select ARCH_SPARSEMEM_ENABLE 838 select CLKDEV_LOOKUP 839 select CPU_V7 840 select GENERIC_CLOCKEVENTS 841 select GENERIC_GPIO 842 select HAVE_CLK 843 select HAVE_S3C2410_I2C if I2C 844 select HAVE_S3C2410_WATCHDOG if WATCHDOG 845 select HAVE_S3C_RTC if RTC_CLASS 846 select NEED_MACH_GPIO_H 847 select NEED_MACH_MEMORY_H 848 help 849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 850 851config ARCH_SHARK 852 bool "Shark" 853 select ARCH_USES_GETTIMEOFFSET 854 select CPU_SA110 855 select ISA 856 select ISA_DMA 857 select NEED_MACH_MEMORY_H 858 select PCI 859 select ZONE_DMA 860 help 861 Support for the StrongARM based Digital DNARD machine, also known 862 as "Shark" (<http://www.shark-linux.de/shark.html>). 863 864config ARCH_U300 865 bool "ST-Ericsson U300 Series" 866 depends on MMU 867 select ARCH_REQUIRE_GPIOLIB 868 select ARM_AMBA 869 select ARM_PATCH_PHYS_VIRT 870 select ARM_VIC 871 select CLKDEV_LOOKUP 872 select CLKSRC_MMIO 873 select COMMON_CLK 874 select CPU_ARM926T 875 select GENERIC_CLOCKEVENTS 876 select GENERIC_GPIO 877 select HAVE_TCM 878 select SPARSE_IRQ 879 help 880 Support for ST-Ericsson U300 series mobile platforms. 881 882config ARCH_U8500 883 bool "ST-Ericsson U8500 Series" 884 depends on MMU 885 select ARCH_HAS_CPUFREQ 886 select ARCH_REQUIRE_GPIOLIB 887 select ARM_AMBA 888 select CLKDEV_LOOKUP 889 select CPU_V7 890 select GENERIC_CLOCKEVENTS 891 select HAVE_SMP 892 select MIGHT_HAVE_CACHE_L2X0 893 select SPARSE_IRQ 894 help 895 Support for ST-Ericsson's Ux500 architecture 896 897config ARCH_NOMADIK 898 bool "STMicroelectronics Nomadik" 899 select ARCH_REQUIRE_GPIOLIB 900 select ARM_AMBA 901 select ARM_VIC 902 select COMMON_CLK 903 select CPU_ARM926T 904 select GENERIC_CLOCKEVENTS 905 select MIGHT_HAVE_CACHE_L2X0 906 select PINCTRL 907 select PINCTRL_STN8815 908 select SPARSE_IRQ 909 help 910 Support for the Nomadik platform by ST-Ericsson 911 912config PLAT_SPEAR 913 bool "ST SPEAr" 914 select ARCH_HAS_CPUFREQ 915 select ARCH_REQUIRE_GPIOLIB 916 select ARM_AMBA 917 select CLKDEV_LOOKUP 918 select CLKSRC_MMIO 919 select COMMON_CLK 920 select GENERIC_CLOCKEVENTS 921 select HAVE_CLK 922 help 923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 924 925config ARCH_DAVINCI 926 bool "TI DaVinci" 927 select ARCH_HAS_HOLES_MEMORYMODEL 928 select ARCH_REQUIRE_GPIOLIB 929 select CLKDEV_LOOKUP 930 select GENERIC_ALLOCATOR 931 select GENERIC_CLOCKEVENTS 932 select GENERIC_IRQ_CHIP 933 select HAVE_IDE 934 select NEED_MACH_GPIO_H 935 select USE_OF 936 select ZONE_DMA 937 help 938 Support for TI's DaVinci platform. 939 940config ARCH_OMAP 941 bool "TI OMAP" 942 depends on MMU 943 select ARCH_HAS_CPUFREQ 944 select ARCH_HAS_HOLES_MEMORYMODEL 945 select ARCH_REQUIRE_GPIOLIB 946 select CLKSRC_MMIO 947 select GENERIC_CLOCKEVENTS 948 select HAVE_CLK 949 help 950 Support for TI's OMAP platform (OMAP1/2/3/4). 951 952config ARCH_VT8500_SINGLE 953 bool "VIA/WonderMedia 85xx" 954 select ARCH_HAS_CPUFREQ 955 select ARCH_REQUIRE_GPIOLIB 956 select CLKDEV_LOOKUP 957 select COMMON_CLK 958 select CPU_ARM926T 959 select GENERIC_CLOCKEVENTS 960 select GENERIC_GPIO 961 select HAVE_CLK 962 select MULTI_IRQ_HANDLER 963 select SPARSE_IRQ 964 select USE_OF 965 help 966 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 967 968endchoice 969 970menu "Multiple platform selection" 971 depends on ARCH_MULTIPLATFORM 972 973comment "CPU Core family selection" 974 975config ARCH_MULTI_V4 976 bool "ARMv4 based platforms (FA526, StrongARM)" 977 depends on !ARCH_MULTI_V6_V7 978 select ARCH_MULTI_V4_V5 979 980config ARCH_MULTI_V4T 981 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 982 depends on !ARCH_MULTI_V6_V7 983 select ARCH_MULTI_V4_V5 984 985config ARCH_MULTI_V5 986 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 987 depends on !ARCH_MULTI_V6_V7 988 select ARCH_MULTI_V4_V5 989 990config ARCH_MULTI_V4_V5 991 bool 992 993config ARCH_MULTI_V6 994 bool "ARMv6 based platforms (ARM11, Scorpion, ...)" 995 select ARCH_MULTI_V6_V7 996 select CPU_V6 997 998config ARCH_MULTI_V7 999 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" 1000 default y 1001 select ARCH_MULTI_V6_V7 1002 select ARCH_VEXPRESS 1003 select CPU_V7 1004 1005config ARCH_MULTI_V6_V7 1006 bool 1007 1008config ARCH_MULTI_CPU_AUTO 1009 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 1010 select ARCH_MULTI_V5 1011 1012endmenu 1013 1014# 1015# This is sorted alphabetically by mach-* pathname. However, plat-* 1016# Kconfigs may be included either alphabetically (according to the 1017# plat- suffix) or along side the corresponding mach-* source. 1018# 1019source "arch/arm/mach-mvebu/Kconfig" 1020 1021source "arch/arm/mach-at91/Kconfig" 1022 1023source "arch/arm/mach-bcm/Kconfig" 1024 1025source "arch/arm/mach-clps711x/Kconfig" 1026 1027source "arch/arm/mach-cns3xxx/Kconfig" 1028 1029source "arch/arm/mach-davinci/Kconfig" 1030 1031source "arch/arm/mach-dove/Kconfig" 1032 1033source "arch/arm/mach-ep93xx/Kconfig" 1034 1035source "arch/arm/mach-footbridge/Kconfig" 1036 1037source "arch/arm/mach-gemini/Kconfig" 1038 1039source "arch/arm/mach-h720x/Kconfig" 1040 1041source "arch/arm/mach-highbank/Kconfig" 1042 1043source "arch/arm/mach-integrator/Kconfig" 1044 1045source "arch/arm/mach-iop32x/Kconfig" 1046 1047source "arch/arm/mach-iop33x/Kconfig" 1048 1049source "arch/arm/mach-iop13xx/Kconfig" 1050 1051source "arch/arm/mach-ixp4xx/Kconfig" 1052 1053source "arch/arm/mach-kirkwood/Kconfig" 1054 1055source "arch/arm/mach-ks8695/Kconfig" 1056 1057source "arch/arm/mach-msm/Kconfig" 1058 1059source "arch/arm/mach-mv78xx0/Kconfig" 1060 1061source "arch/arm/mach-imx/Kconfig" 1062 1063source "arch/arm/mach-mxs/Kconfig" 1064 1065source "arch/arm/mach-netx/Kconfig" 1066 1067source "arch/arm/mach-nomadik/Kconfig" 1068 1069source "arch/arm/plat-omap/Kconfig" 1070 1071source "arch/arm/mach-omap1/Kconfig" 1072 1073source "arch/arm/mach-omap2/Kconfig" 1074 1075source "arch/arm/mach-orion5x/Kconfig" 1076 1077source "arch/arm/mach-picoxcell/Kconfig" 1078 1079source "arch/arm/mach-pxa/Kconfig" 1080source "arch/arm/plat-pxa/Kconfig" 1081 1082source "arch/arm/mach-mmp/Kconfig" 1083 1084source "arch/arm/mach-realview/Kconfig" 1085 1086source "arch/arm/mach-sa1100/Kconfig" 1087 1088source "arch/arm/plat-samsung/Kconfig" 1089source "arch/arm/plat-s3c24xx/Kconfig" 1090 1091source "arch/arm/mach-socfpga/Kconfig" 1092 1093source "arch/arm/plat-spear/Kconfig" 1094 1095source "arch/arm/mach-s3c24xx/Kconfig" 1096if ARCH_S3C24XX 1097source "arch/arm/mach-s3c2412/Kconfig" 1098source "arch/arm/mach-s3c2440/Kconfig" 1099endif 1100 1101if ARCH_S3C64XX 1102source "arch/arm/mach-s3c64xx/Kconfig" 1103endif 1104 1105source "arch/arm/mach-s5p64x0/Kconfig" 1106 1107source "arch/arm/mach-s5pc100/Kconfig" 1108 1109source "arch/arm/mach-s5pv210/Kconfig" 1110 1111source "arch/arm/mach-exynos/Kconfig" 1112 1113source "arch/arm/mach-shmobile/Kconfig" 1114 1115source "arch/arm/mach-sunxi/Kconfig" 1116 1117source "arch/arm/mach-prima2/Kconfig" 1118 1119source "arch/arm/mach-tegra/Kconfig" 1120 1121source "arch/arm/mach-u300/Kconfig" 1122 1123source "arch/arm/mach-ux500/Kconfig" 1124 1125source "arch/arm/mach-versatile/Kconfig" 1126 1127source "arch/arm/mach-vexpress/Kconfig" 1128source "arch/arm/plat-versatile/Kconfig" 1129 1130source "arch/arm/mach-vt8500/Kconfig" 1131 1132source "arch/arm/mach-w90x900/Kconfig" 1133 1134source "arch/arm/mach-zynq/Kconfig" 1135 1136# Definitions to make life easier 1137config ARCH_ACORN 1138 bool 1139 1140config PLAT_IOP 1141 bool 1142 select GENERIC_CLOCKEVENTS 1143 1144config PLAT_ORION 1145 bool 1146 select CLKSRC_MMIO 1147 select COMMON_CLK 1148 select GENERIC_IRQ_CHIP 1149 select IRQ_DOMAIN 1150 1151config PLAT_ORION_LEGACY 1152 bool 1153 select PLAT_ORION 1154 1155config PLAT_PXA 1156 bool 1157 1158config PLAT_VERSATILE 1159 bool 1160 1161config ARM_TIMER_SP804 1162 bool 1163 select CLKSRC_MMIO 1164 select HAVE_SCHED_CLOCK 1165 1166source arch/arm/mm/Kconfig 1167 1168config ARM_NR_BANKS 1169 int 1170 default 16 if ARCH_EP93XX 1171 default 8 1172 1173config IWMMXT 1174 bool "Enable iWMMXt support" 1175 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1176 default y if PXA27x || PXA3xx || ARCH_MMP 1177 help 1178 Enable support for iWMMXt context switching at run time if 1179 running on a CPU that supports it. 1180 1181config XSCALE_PMU 1182 bool 1183 depends on CPU_XSCALE 1184 default y 1185 1186config MULTI_IRQ_HANDLER 1187 bool 1188 help 1189 Allow each machine to specify it's own IRQ handler at run time. 1190 1191if !MMU 1192source "arch/arm/Kconfig-nommu" 1193endif 1194 1195config ARM_ERRATA_326103 1196 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1197 depends on CPU_V6 1198 help 1199 Executing a SWP instruction to read-only memory does not set bit 11 1200 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1201 treat the access as a read, preventing a COW from occurring and 1202 causing the faulting task to livelock. 1203 1204config ARM_ERRATA_411920 1205 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1206 depends on CPU_V6 || CPU_V6K 1207 help 1208 Invalidation of the Instruction Cache operation can 1209 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1210 It does not affect the MPCore. This option enables the ARM Ltd. 1211 recommended workaround. 1212 1213config ARM_ERRATA_430973 1214 bool "ARM errata: Stale prediction on replaced interworking branch" 1215 depends on CPU_V7 1216 help 1217 This option enables the workaround for the 430973 Cortex-A8 1218 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1219 interworking branch is replaced with another code sequence at the 1220 same virtual address, whether due to self-modifying code or virtual 1221 to physical address re-mapping, Cortex-A8 does not recover from the 1222 stale interworking branch prediction. This results in Cortex-A8 1223 executing the new code sequence in the incorrect ARM or Thumb state. 1224 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1225 and also flushes the branch target cache at every context switch. 1226 Note that setting specific bits in the ACTLR register may not be 1227 available in non-secure mode. 1228 1229config ARM_ERRATA_458693 1230 bool "ARM errata: Processor deadlock when a false hazard is created" 1231 depends on CPU_V7 1232 depends on !ARCH_MULTIPLATFORM 1233 help 1234 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1235 erratum. For very specific sequences of memory operations, it is 1236 possible for a hazard condition intended for a cache line to instead 1237 be incorrectly associated with a different cache line. This false 1238 hazard might then cause a processor deadlock. The workaround enables 1239 the L1 caching of the NEON accesses and disables the PLD instruction 1240 in the ACTLR register. Note that setting specific bits in the ACTLR 1241 register may not be available in non-secure mode. 1242 1243config ARM_ERRATA_460075 1244 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1245 depends on CPU_V7 1246 depends on !ARCH_MULTIPLATFORM 1247 help 1248 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1249 erratum. Any asynchronous access to the L2 cache may encounter a 1250 situation in which recent store transactions to the L2 cache are lost 1251 and overwritten with stale memory contents from external memory. The 1252 workaround disables the write-allocate mode for the L2 cache via the 1253 ACTLR register. Note that setting specific bits in the ACTLR register 1254 may not be available in non-secure mode. 1255 1256config ARM_ERRATA_742230 1257 bool "ARM errata: DMB operation may be faulty" 1258 depends on CPU_V7 && SMP 1259 depends on !ARCH_MULTIPLATFORM 1260 help 1261 This option enables the workaround for the 742230 Cortex-A9 1262 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1263 between two write operations may not ensure the correct visibility 1264 ordering of the two writes. This workaround sets a specific bit in 1265 the diagnostic register of the Cortex-A9 which causes the DMB 1266 instruction to behave as a DSB, ensuring the correct behaviour of 1267 the two writes. 1268 1269config ARM_ERRATA_742231 1270 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1271 depends on CPU_V7 && SMP 1272 depends on !ARCH_MULTIPLATFORM 1273 help 1274 This option enables the workaround for the 742231 Cortex-A9 1275 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1276 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1277 accessing some data located in the same cache line, may get corrupted 1278 data due to bad handling of the address hazard when the line gets 1279 replaced from one of the CPUs at the same time as another CPU is 1280 accessing it. This workaround sets specific bits in the diagnostic 1281 register of the Cortex-A9 which reduces the linefill issuing 1282 capabilities of the processor. 1283 1284config PL310_ERRATA_588369 1285 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1286 depends on CACHE_L2X0 1287 help 1288 The PL310 L2 cache controller implements three types of Clean & 1289 Invalidate maintenance operations: by Physical Address 1290 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1291 They are architecturally defined to behave as the execution of a 1292 clean operation followed immediately by an invalidate operation, 1293 both performing to the same memory location. This functionality 1294 is not correctly implemented in PL310 as clean lines are not 1295 invalidated as a result of these operations. 1296 1297config ARM_ERRATA_720789 1298 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1299 depends on CPU_V7 1300 help 1301 This option enables the workaround for the 720789 Cortex-A9 (prior to 1302 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1303 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1304 As a consequence of this erratum, some TLB entries which should be 1305 invalidated are not, resulting in an incoherency in the system page 1306 tables. The workaround changes the TLB flushing routines to invalidate 1307 entries regardless of the ASID. 1308 1309config PL310_ERRATA_727915 1310 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1311 depends on CACHE_L2X0 1312 help 1313 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1314 operation (offset 0x7FC). This operation runs in background so that 1315 PL310 can handle normal accesses while it is in progress. Under very 1316 rare circumstances, due to this erratum, write data can be lost when 1317 PL310 treats a cacheable write transaction during a Clean & 1318 Invalidate by Way operation. 1319 1320config ARM_ERRATA_743622 1321 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1322 depends on CPU_V7 1323 depends on !ARCH_MULTIPLATFORM 1324 help 1325 This option enables the workaround for the 743622 Cortex-A9 1326 (r2p*) erratum. Under very rare conditions, a faulty 1327 optimisation in the Cortex-A9 Store Buffer may lead to data 1328 corruption. This workaround sets a specific bit in the diagnostic 1329 register of the Cortex-A9 which disables the Store Buffer 1330 optimisation, preventing the defect from occurring. This has no 1331 visible impact on the overall performance or power consumption of the 1332 processor. 1333 1334config ARM_ERRATA_751472 1335 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1336 depends on CPU_V7 1337 depends on !ARCH_MULTIPLATFORM 1338 help 1339 This option enables the workaround for the 751472 Cortex-A9 (prior 1340 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1341 completion of a following broadcasted operation if the second 1342 operation is received by a CPU before the ICIALLUIS has completed, 1343 potentially leading to corrupted entries in the cache or TLB. 1344 1345config PL310_ERRATA_753970 1346 bool "PL310 errata: cache sync operation may be faulty" 1347 depends on CACHE_PL310 1348 help 1349 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1350 1351 Under some condition the effect of cache sync operation on 1352 the store buffer still remains when the operation completes. 1353 This means that the store buffer is always asked to drain and 1354 this prevents it from merging any further writes. The workaround 1355 is to replace the normal offset of cache sync operation (0x730) 1356 by another offset targeting an unmapped PL310 register 0x740. 1357 This has the same effect as the cache sync operation: store buffer 1358 drain and waiting for all buffers empty. 1359 1360config ARM_ERRATA_754322 1361 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1362 depends on CPU_V7 1363 help 1364 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1365 r3p*) erratum. A speculative memory access may cause a page table walk 1366 which starts prior to an ASID switch but completes afterwards. This 1367 can populate the micro-TLB with a stale entry which may be hit with 1368 the new ASID. This workaround places two dsb instructions in the mm 1369 switching code so that no page table walks can cross the ASID switch. 1370 1371config ARM_ERRATA_754327 1372 bool "ARM errata: no automatic Store Buffer drain" 1373 depends on CPU_V7 && SMP 1374 help 1375 This option enables the workaround for the 754327 Cortex-A9 (prior to 1376 r2p0) erratum. The Store Buffer does not have any automatic draining 1377 mechanism and therefore a livelock may occur if an external agent 1378 continuously polls a memory location waiting to observe an update. 1379 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1380 written polling loops from denying visibility of updates to memory. 1381 1382config ARM_ERRATA_364296 1383 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1384 depends on CPU_V6 && !SMP 1385 help 1386 This options enables the workaround for the 364296 ARM1136 1387 r0p2 erratum (possible cache data corruption with 1388 hit-under-miss enabled). It sets the undocumented bit 31 in 1389 the auxiliary control register and the FI bit in the control 1390 register, thus disabling hit-under-miss without putting the 1391 processor into full low interrupt latency mode. ARM11MPCore 1392 is not affected. 1393 1394config ARM_ERRATA_764369 1395 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1396 depends on CPU_V7 && SMP 1397 help 1398 This option enables the workaround for erratum 764369 1399 affecting Cortex-A9 MPCore with two or more processors (all 1400 current revisions). Under certain timing circumstances, a data 1401 cache line maintenance operation by MVA targeting an Inner 1402 Shareable memory region may fail to proceed up to either the 1403 Point of Coherency or to the Point of Unification of the 1404 system. This workaround adds a DSB instruction before the 1405 relevant cache maintenance functions and sets a specific bit 1406 in the diagnostic control register of the SCU. 1407 1408config PL310_ERRATA_769419 1409 bool "PL310 errata: no automatic Store Buffer drain" 1410 depends on CACHE_L2X0 1411 help 1412 On revisions of the PL310 prior to r3p2, the Store Buffer does 1413 not automatically drain. This can cause normal, non-cacheable 1414 writes to be retained when the memory system is idle, leading 1415 to suboptimal I/O performance for drivers using coherent DMA. 1416 This option adds a write barrier to the cpu_idle loop so that, 1417 on systems with an outer cache, the store buffer is drained 1418 explicitly. 1419 1420config ARM_ERRATA_775420 1421 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1422 depends on CPU_V7 1423 help 1424 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1425 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1426 operation aborts with MMU exception, it might cause the processor 1427 to deadlock. This workaround puts DSB before executing ISB if 1428 an abort may occur on cache maintenance. 1429 1430endmenu 1431 1432source "arch/arm/common/Kconfig" 1433 1434menu "Bus support" 1435 1436config ARM_AMBA 1437 bool 1438 1439config ISA 1440 bool 1441 help 1442 Find out whether you have ISA slots on your motherboard. ISA is the 1443 name of a bus system, i.e. the way the CPU talks to the other stuff 1444 inside your box. Other bus systems are PCI, EISA, MicroChannel 1445 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1446 newer boards don't support it. If you have ISA, say Y, otherwise N. 1447 1448# Select ISA DMA controller support 1449config ISA_DMA 1450 bool 1451 select ISA_DMA_API 1452 1453# Select ISA DMA interface 1454config ISA_DMA_API 1455 bool 1456 1457config PCI 1458 bool "PCI support" if MIGHT_HAVE_PCI 1459 help 1460 Find out whether you have a PCI motherboard. PCI is the name of a 1461 bus system, i.e. the way the CPU talks to the other stuff inside 1462 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1463 VESA. If you have PCI, say Y, otherwise N. 1464 1465config PCI_DOMAINS 1466 bool 1467 depends on PCI 1468 1469config PCI_NANOENGINE 1470 bool "BSE nanoEngine PCI support" 1471 depends on SA1100_NANOENGINE 1472 help 1473 Enable PCI on the BSE nanoEngine board. 1474 1475config PCI_SYSCALL 1476 def_bool PCI 1477 1478# Select the host bridge type 1479config PCI_HOST_VIA82C505 1480 bool 1481 depends on PCI && ARCH_SHARK 1482 default y 1483 1484config PCI_HOST_ITE8152 1485 bool 1486 depends on PCI && MACH_ARMCORE 1487 default y 1488 select DMABOUNCE 1489 1490source "drivers/pci/Kconfig" 1491 1492source "drivers/pcmcia/Kconfig" 1493 1494endmenu 1495 1496menu "Kernel Features" 1497 1498config HAVE_SMP 1499 bool 1500 help 1501 This option should be selected by machines which have an SMP- 1502 capable CPU. 1503 1504 The only effect of this option is to make the SMP-related 1505 options available to the user for configuration. 1506 1507config SMP 1508 bool "Symmetric Multi-Processing" 1509 depends on CPU_V6K || CPU_V7 1510 depends on GENERIC_CLOCKEVENTS 1511 depends on HAVE_SMP 1512 depends on MMU 1513 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1514 select USE_GENERIC_SMP_HELPERS 1515 help 1516 This enables support for systems with more than one CPU. If you have 1517 a system with only one CPU, like most personal computers, say N. If 1518 you have a system with more than one CPU, say Y. 1519 1520 If you say N here, the kernel will run on single and multiprocessor 1521 machines, but will use only one CPU of a multiprocessor machine. If 1522 you say Y here, the kernel will run on many, but not all, single 1523 processor machines. On a single processor machine, the kernel will 1524 run faster if you say N here. 1525 1526 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1527 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1528 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1529 1530 If you don't know what to do here, say N. 1531 1532config SMP_ON_UP 1533 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1534 depends on EXPERIMENTAL 1535 depends on SMP && !XIP_KERNEL 1536 default y 1537 help 1538 SMP kernels contain instructions which fail on non-SMP processors. 1539 Enabling this option allows the kernel to modify itself to make 1540 these instructions safe. Disabling it allows about 1K of space 1541 savings. 1542 1543 If you don't know what to do here, say Y. 1544 1545config ARM_CPU_TOPOLOGY 1546 bool "Support cpu topology definition" 1547 depends on SMP && CPU_V7 1548 default y 1549 help 1550 Support ARM cpu topology definition. The MPIDR register defines 1551 affinity between processors which is then used to describe the cpu 1552 topology of an ARM System. 1553 1554config SCHED_MC 1555 bool "Multi-core scheduler support" 1556 depends on ARM_CPU_TOPOLOGY 1557 help 1558 Multi-core scheduler support improves the CPU scheduler's decision 1559 making when dealing with multi-core CPU chips at a cost of slightly 1560 increased overhead in some places. If unsure say N here. 1561 1562config SCHED_SMT 1563 bool "SMT scheduler support" 1564 depends on ARM_CPU_TOPOLOGY 1565 help 1566 Improves the CPU scheduler's decision making when dealing with 1567 MultiThreading at a cost of slightly increased overhead in some 1568 places. If unsure say N here. 1569 1570config HAVE_ARM_SCU 1571 bool 1572 help 1573 This option enables support for the ARM system coherency unit 1574 1575config HAVE_ARM_ARCH_TIMER 1576 bool "Architected timer support" 1577 depends on CPU_V7 1578 select ARM_ARCH_TIMER 1579 help 1580 This option enables support for the ARM architected timer 1581 1582config HAVE_ARM_TWD 1583 bool 1584 depends on SMP 1585 help 1586 This options enables support for the ARM timer and watchdog unit 1587 1588choice 1589 prompt "Memory split" 1590 default VMSPLIT_3G 1591 help 1592 Select the desired split between kernel and user memory. 1593 1594 If you are not absolutely sure what you are doing, leave this 1595 option alone! 1596 1597 config VMSPLIT_3G 1598 bool "3G/1G user/kernel split" 1599 config VMSPLIT_2G 1600 bool "2G/2G user/kernel split" 1601 config VMSPLIT_1G 1602 bool "1G/3G user/kernel split" 1603endchoice 1604 1605config PAGE_OFFSET 1606 hex 1607 default 0x40000000 if VMSPLIT_1G 1608 default 0x80000000 if VMSPLIT_2G 1609 default 0xC0000000 1610 1611config NR_CPUS 1612 int "Maximum number of CPUs (2-32)" 1613 range 2 32 1614 depends on SMP 1615 default "4" 1616 1617config HOTPLUG_CPU 1618 bool "Support for hot-pluggable CPUs" 1619 depends on SMP && HOTPLUG 1620 help 1621 Say Y here to experiment with turning CPUs off and on. CPUs 1622 can be controlled through /sys/devices/system/cpu. 1623 1624config LOCAL_TIMERS 1625 bool "Use local timer interrupts" 1626 depends on SMP 1627 default y 1628 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1629 help 1630 Enable support for local timers on SMP platforms, rather then the 1631 legacy IPI broadcast method. Local timers allows the system 1632 accounting to be spread across the timer interval, preventing a 1633 "thundering herd" at every timer tick. 1634 1635config ARCH_NR_GPIO 1636 int 1637 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1638 default 355 if ARCH_U8500 1639 default 264 if MACH_H4700 1640 default 512 if SOC_OMAP5 1641 default 288 if ARCH_VT8500 1642 default 0 1643 help 1644 Maximum number of GPIOs in the system. 1645 1646 If unsure, leave the default value. 1647 1648source kernel/Kconfig.preempt 1649 1650config HZ 1651 int 1652 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1653 ARCH_S5PV210 || ARCH_EXYNOS4 1654 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1655 default AT91_TIMER_HZ if ARCH_AT91 1656 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1657 default 100 1658 1659config THUMB2_KERNEL 1660 bool "Compile the kernel in Thumb-2 mode" 1661 depends on CPU_V7 && !CPU_V6 && !CPU_V6K 1662 select AEABI 1663 select ARM_ASM_UNIFIED 1664 select ARM_UNWIND 1665 help 1666 By enabling this option, the kernel will be compiled in 1667 Thumb-2 mode. A compiler/assembler that understand the unified 1668 ARM-Thumb syntax is needed. 1669 1670 If unsure, say N. 1671 1672config THUMB2_AVOID_R_ARM_THM_JUMP11 1673 bool "Work around buggy Thumb-2 short branch relocations in gas" 1674 depends on THUMB2_KERNEL && MODULES 1675 default y 1676 help 1677 Various binutils versions can resolve Thumb-2 branches to 1678 locally-defined, preemptible global symbols as short-range "b.n" 1679 branch instructions. 1680 1681 This is a problem, because there's no guarantee the final 1682 destination of the symbol, or any candidate locations for a 1683 trampoline, are within range of the branch. For this reason, the 1684 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1685 relocation in modules at all, and it makes little sense to add 1686 support. 1687 1688 The symptom is that the kernel fails with an "unsupported 1689 relocation" error when loading some modules. 1690 1691 Until fixed tools are available, passing 1692 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1693 code which hits this problem, at the cost of a bit of extra runtime 1694 stack usage in some cases. 1695 1696 The problem is described in more detail at: 1697 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1698 1699 Only Thumb-2 kernels are affected. 1700 1701 Unless you are sure your tools don't have this problem, say Y. 1702 1703config ARM_ASM_UNIFIED 1704 bool 1705 1706config AEABI 1707 bool "Use the ARM EABI to compile the kernel" 1708 help 1709 This option allows for the kernel to be compiled using the latest 1710 ARM ABI (aka EABI). This is only useful if you are using a user 1711 space environment that is also compiled with EABI. 1712 1713 Since there are major incompatibilities between the legacy ABI and 1714 EABI, especially with regard to structure member alignment, this 1715 option also changes the kernel syscall calling convention to 1716 disambiguate both ABIs and allow for backward compatibility support 1717 (selected with CONFIG_OABI_COMPAT). 1718 1719 To use this you need GCC version 4.0.0 or later. 1720 1721config OABI_COMPAT 1722 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1723 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1724 default y 1725 help 1726 This option preserves the old syscall interface along with the 1727 new (ARM EABI) one. It also provides a compatibility layer to 1728 intercept syscalls that have structure arguments which layout 1729 in memory differs between the legacy ABI and the new ARM EABI 1730 (only for non "thumb" binaries). This option adds a tiny 1731 overhead to all syscalls and produces a slightly larger kernel. 1732 If you know you'll be using only pure EABI user space then you 1733 can say N here. If this option is not selected and you attempt 1734 to execute a legacy ABI binary then the result will be 1735 UNPREDICTABLE (in fact it can be predicted that it won't work 1736 at all). If in doubt say Y. 1737 1738config ARCH_HAS_HOLES_MEMORYMODEL 1739 bool 1740 1741config ARCH_SPARSEMEM_ENABLE 1742 bool 1743 1744config ARCH_SPARSEMEM_DEFAULT 1745 def_bool ARCH_SPARSEMEM_ENABLE 1746 1747config ARCH_SELECT_MEMORY_MODEL 1748 def_bool ARCH_SPARSEMEM_ENABLE 1749 1750config HAVE_ARCH_PFN_VALID 1751 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1752 1753config HIGHMEM 1754 bool "High Memory Support" 1755 depends on MMU 1756 help 1757 The address space of ARM processors is only 4 Gigabytes large 1758 and it has to accommodate user address space, kernel address 1759 space as well as some memory mapped IO. That means that, if you 1760 have a large amount of physical memory and/or IO, not all of the 1761 memory can be "permanently mapped" by the kernel. The physical 1762 memory that is not permanently mapped is called "high memory". 1763 1764 Depending on the selected kernel/user memory split, minimum 1765 vmalloc space and actual amount of RAM, you may not need this 1766 option which should result in a slightly faster kernel. 1767 1768 If unsure, say n. 1769 1770config HIGHPTE 1771 bool "Allocate 2nd-level pagetables from highmem" 1772 depends on HIGHMEM 1773 1774config HW_PERF_EVENTS 1775 bool "Enable hardware performance counter support for perf events" 1776 depends on PERF_EVENTS 1777 default y 1778 help 1779 Enable hardware performance counter support for perf events. If 1780 disabled, perf events will use software events only. 1781 1782source "mm/Kconfig" 1783 1784config FORCE_MAX_ZONEORDER 1785 int "Maximum zone order" if ARCH_SHMOBILE 1786 range 11 64 if ARCH_SHMOBILE 1787 default "12" if SOC_AM33XX 1788 default "9" if SA1111 1789 default "11" 1790 help 1791 The kernel memory allocator divides physically contiguous memory 1792 blocks into "zones", where each zone is a power of two number of 1793 pages. This option selects the largest power of two that the kernel 1794 keeps in the memory allocator. If you need to allocate very large 1795 blocks of physically contiguous memory, then you may need to 1796 increase this value. 1797 1798 This config option is actually maximum order plus one. For example, 1799 a value of 11 means that the largest free memory block is 2^10 pages. 1800 1801config ALIGNMENT_TRAP 1802 bool 1803 depends on CPU_CP15_MMU 1804 default y if !ARCH_EBSA110 1805 select HAVE_PROC_CPU if PROC_FS 1806 help 1807 ARM processors cannot fetch/store information which is not 1808 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1809 address divisible by 4. On 32-bit ARM processors, these non-aligned 1810 fetch/store instructions will be emulated in software if you say 1811 here, which has a severe performance impact. This is necessary for 1812 correct operation of some network protocols. With an IP-only 1813 configuration it is safe to say N, otherwise say Y. 1814 1815config UACCESS_WITH_MEMCPY 1816 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1817 depends on MMU 1818 default y if CPU_FEROCEON 1819 help 1820 Implement faster copy_to_user and clear_user methods for CPU 1821 cores where a 8-word STM instruction give significantly higher 1822 memory write throughput than a sequence of individual 32bit stores. 1823 1824 A possible side effect is a slight increase in scheduling latency 1825 between threads sharing the same address space if they invoke 1826 such copy operations with large buffers. 1827 1828 However, if the CPU data cache is using a write-allocate mode, 1829 this option is unlikely to provide any performance gain. 1830 1831config SECCOMP 1832 bool 1833 prompt "Enable seccomp to safely compute untrusted bytecode" 1834 ---help--- 1835 This kernel feature is useful for number crunching applications 1836 that may need to compute untrusted bytecode during their 1837 execution. By using pipes or other transports made available to 1838 the process as file descriptors supporting the read/write 1839 syscalls, it's possible to isolate those applications in 1840 their own address space using seccomp. Once seccomp is 1841 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1842 and the task is only allowed to execute a few safe syscalls 1843 defined by each seccomp mode. 1844 1845config CC_STACKPROTECTOR 1846 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1847 depends on EXPERIMENTAL 1848 help 1849 This option turns on the -fstack-protector GCC feature. This 1850 feature puts, at the beginning of functions, a canary value on 1851 the stack just before the return address, and validates 1852 the value just before actually returning. Stack based buffer 1853 overflows (that need to overwrite this return address) now also 1854 overwrite the canary, which gets detected and the attack is then 1855 neutralized via a kernel panic. 1856 This feature requires gcc version 4.2 or above. 1857 1858config XEN_DOM0 1859 def_bool y 1860 depends on XEN 1861 1862config XEN 1863 bool "Xen guest support on ARM (EXPERIMENTAL)" 1864 depends on EXPERIMENTAL && ARM && OF 1865 depends on CPU_V7 && !CPU_V6 1866 help 1867 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1868 1869endmenu 1870 1871menu "Boot options" 1872 1873config USE_OF 1874 bool "Flattened Device Tree support" 1875 select IRQ_DOMAIN 1876 select OF 1877 select OF_EARLY_FLATTREE 1878 help 1879 Include support for flattened device tree machine descriptions. 1880 1881config ATAGS 1882 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1883 default y 1884 help 1885 This is the traditional way of passing data to the kernel at boot 1886 time. If you are solely relying on the flattened device tree (or 1887 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1888 to remove ATAGS support from your kernel binary. If unsure, 1889 leave this to y. 1890 1891config DEPRECATED_PARAM_STRUCT 1892 bool "Provide old way to pass kernel parameters" 1893 depends on ATAGS 1894 help 1895 This was deprecated in 2001 and announced to live on for 5 years. 1896 Some old boot loaders still use this way. 1897 1898# Compressed boot loader in ROM. Yes, we really want to ask about 1899# TEXT and BSS so we preserve their values in the config files. 1900config ZBOOT_ROM_TEXT 1901 hex "Compressed ROM boot loader base address" 1902 default "0" 1903 help 1904 The physical address at which the ROM-able zImage is to be 1905 placed in the target. Platforms which normally make use of 1906 ROM-able zImage formats normally set this to a suitable 1907 value in their defconfig file. 1908 1909 If ZBOOT_ROM is not enabled, this has no effect. 1910 1911config ZBOOT_ROM_BSS 1912 hex "Compressed ROM boot loader BSS address" 1913 default "0" 1914 help 1915 The base address of an area of read/write memory in the target 1916 for the ROM-able zImage which must be available while the 1917 decompressor is running. It must be large enough to hold the 1918 entire decompressed kernel plus an additional 128 KiB. 1919 Platforms which normally make use of ROM-able zImage formats 1920 normally set this to a suitable value in their defconfig file. 1921 1922 If ZBOOT_ROM is not enabled, this has no effect. 1923 1924config ZBOOT_ROM 1925 bool "Compressed boot loader in ROM/flash" 1926 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1927 help 1928 Say Y here if you intend to execute your compressed kernel image 1929 (zImage) directly from ROM or flash. If unsure, say N. 1930 1931choice 1932 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1933 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1934 default ZBOOT_ROM_NONE 1935 help 1936 Include experimental SD/MMC loading code in the ROM-able zImage. 1937 With this enabled it is possible to write the ROM-able zImage 1938 kernel image to an MMC or SD card and boot the kernel straight 1939 from the reset vector. At reset the processor Mask ROM will load 1940 the first part of the ROM-able zImage which in turn loads the 1941 rest the kernel image to RAM. 1942 1943config ZBOOT_ROM_NONE 1944 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1945 help 1946 Do not load image from SD or MMC 1947 1948config ZBOOT_ROM_MMCIF 1949 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1950 help 1951 Load image from MMCIF hardware block. 1952 1953config ZBOOT_ROM_SH_MOBILE_SDHI 1954 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1955 help 1956 Load image from SDHI hardware block 1957 1958endchoice 1959 1960config ARM_APPENDED_DTB 1961 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1962 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1963 help 1964 With this option, the boot code will look for a device tree binary 1965 (DTB) appended to zImage 1966 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1967 1968 This is meant as a backward compatibility convenience for those 1969 systems with a bootloader that can't be upgraded to accommodate 1970 the documented boot protocol using a device tree. 1971 1972 Beware that there is very little in terms of protection against 1973 this option being confused by leftover garbage in memory that might 1974 look like a DTB header after a reboot if no actual DTB is appended 1975 to zImage. Do not leave this option active in a production kernel 1976 if you don't intend to always append a DTB. Proper passing of the 1977 location into r2 of a bootloader provided DTB is always preferable 1978 to this option. 1979 1980config ARM_ATAG_DTB_COMPAT 1981 bool "Supplement the appended DTB with traditional ATAG information" 1982 depends on ARM_APPENDED_DTB 1983 help 1984 Some old bootloaders can't be updated to a DTB capable one, yet 1985 they provide ATAGs with memory configuration, the ramdisk address, 1986 the kernel cmdline string, etc. Such information is dynamically 1987 provided by the bootloader and can't always be stored in a static 1988 DTB. To allow a device tree enabled kernel to be used with such 1989 bootloaders, this option allows zImage to extract the information 1990 from the ATAG list and store it at run time into the appended DTB. 1991 1992choice 1993 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1994 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1995 1996config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1997 bool "Use bootloader kernel arguments if available" 1998 help 1999 Uses the command-line options passed by the boot loader instead of 2000 the device tree bootargs property. If the boot loader doesn't provide 2001 any, the device tree bootargs property will be used. 2002 2003config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 2004 bool "Extend with bootloader kernel arguments" 2005 help 2006 The command-line arguments provided by the boot loader will be 2007 appended to the the device tree bootargs property. 2008 2009endchoice 2010 2011config CMDLINE 2012 string "Default kernel command string" 2013 default "" 2014 help 2015 On some architectures (EBSA110 and CATS), there is currently no way 2016 for the boot loader to pass arguments to the kernel. For these 2017 architectures, you should supply some command-line options at build 2018 time by entering them here. As a minimum, you should specify the 2019 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2020 2021choice 2022 prompt "Kernel command line type" if CMDLINE != "" 2023 default CMDLINE_FROM_BOOTLOADER 2024 depends on ATAGS 2025 2026config CMDLINE_FROM_BOOTLOADER 2027 bool "Use bootloader kernel arguments if available" 2028 help 2029 Uses the command-line options passed by the boot loader. If 2030 the boot loader doesn't provide any, the default kernel command 2031 string provided in CMDLINE will be used. 2032 2033config CMDLINE_EXTEND 2034 bool "Extend bootloader kernel arguments" 2035 help 2036 The command-line arguments provided by the boot loader will be 2037 appended to the default kernel command string. 2038 2039config CMDLINE_FORCE 2040 bool "Always use the default kernel command string" 2041 help 2042 Always use the default kernel command string, even if the boot 2043 loader passes other arguments to the kernel. 2044 This is useful if you cannot or don't want to change the 2045 command-line options your boot loader passes to the kernel. 2046endchoice 2047 2048config XIP_KERNEL 2049 bool "Kernel Execute-In-Place from ROM" 2050 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM 2051 help 2052 Execute-In-Place allows the kernel to run from non-volatile storage 2053 directly addressable by the CPU, such as NOR flash. This saves RAM 2054 space since the text section of the kernel is not loaded from flash 2055 to RAM. Read-write sections, such as the data section and stack, 2056 are still copied to RAM. The XIP kernel is not compressed since 2057 it has to run directly from flash, so it will take more space to 2058 store it. The flash address used to link the kernel object files, 2059 and for storing it, is configuration dependent. Therefore, if you 2060 say Y here, you must know the proper physical address where to 2061 store the kernel image depending on your own flash memory usage. 2062 2063 Also note that the make target becomes "make xipImage" rather than 2064 "make zImage" or "make Image". The final kernel binary to put in 2065 ROM memory will be arch/arm/boot/xipImage. 2066 2067 If unsure, say N. 2068 2069config XIP_PHYS_ADDR 2070 hex "XIP Kernel Physical Location" 2071 depends on XIP_KERNEL 2072 default "0x00080000" 2073 help 2074 This is the physical address in your flash memory the kernel will 2075 be linked for and stored to. This address is dependent on your 2076 own flash usage. 2077 2078config KEXEC 2079 bool "Kexec system call (EXPERIMENTAL)" 2080 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2081 help 2082 kexec is a system call that implements the ability to shutdown your 2083 current kernel, and to start another kernel. It is like a reboot 2084 but it is independent of the system firmware. And like a reboot 2085 you can start any kernel with it, not just Linux. 2086 2087 It is an ongoing process to be certain the hardware in a machine 2088 is properly shutdown, so do not be surprised if this code does not 2089 initially work for you. It may help to enable device hotplugging 2090 support. 2091 2092config ATAGS_PROC 2093 bool "Export atags in procfs" 2094 depends on ATAGS && KEXEC 2095 default y 2096 help 2097 Should the atags used to boot the kernel be exported in an "atags" 2098 file in procfs. Useful with kexec. 2099 2100config CRASH_DUMP 2101 bool "Build kdump crash kernel (EXPERIMENTAL)" 2102 depends on EXPERIMENTAL 2103 help 2104 Generate crash dump after being started by kexec. This should 2105 be normally only set in special crash dump kernels which are 2106 loaded in the main kernel with kexec-tools into a specially 2107 reserved region and then later executed after a crash by 2108 kdump/kexec. The crash dump kernel must be compiled to a 2109 memory address not used by the main kernel 2110 2111 For more details see Documentation/kdump/kdump.txt 2112 2113config AUTO_ZRELADDR 2114 bool "Auto calculation of the decompressed kernel image address" 2115 depends on !ZBOOT_ROM && !ARCH_U300 2116 help 2117 ZRELADDR is the physical address where the decompressed kernel 2118 image will be placed. If AUTO_ZRELADDR is selected, the address 2119 will be determined at run-time by masking the current IP with 2120 0xf8000000. This assumes the zImage being placed in the first 128MB 2121 from start of memory. 2122 2123endmenu 2124 2125menu "CPU Power Management" 2126 2127if ARCH_HAS_CPUFREQ 2128 2129source "drivers/cpufreq/Kconfig" 2130 2131config CPU_FREQ_IMX 2132 tristate "CPUfreq driver for i.MX CPUs" 2133 depends on ARCH_MXC && CPU_FREQ 2134 select CPU_FREQ_TABLE 2135 help 2136 This enables the CPUfreq driver for i.MX CPUs. 2137 2138config CPU_FREQ_SA1100 2139 bool 2140 2141config CPU_FREQ_SA1110 2142 bool 2143 2144config CPU_FREQ_INTEGRATOR 2145 tristate "CPUfreq driver for ARM Integrator CPUs" 2146 depends on ARCH_INTEGRATOR && CPU_FREQ 2147 default y 2148 help 2149 This enables the CPUfreq driver for ARM Integrator CPUs. 2150 2151 For details, take a look at <file:Documentation/cpu-freq>. 2152 2153 If in doubt, say Y. 2154 2155config CPU_FREQ_PXA 2156 bool 2157 depends on CPU_FREQ && ARCH_PXA && PXA25x 2158 default y 2159 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2160 select CPU_FREQ_TABLE 2161 2162config CPU_FREQ_S3C 2163 bool 2164 help 2165 Internal configuration node for common cpufreq on Samsung SoC 2166 2167config CPU_FREQ_S3C24XX 2168 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2169 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL 2170 select CPU_FREQ_S3C 2171 help 2172 This enables the CPUfreq driver for the Samsung S3C24XX family 2173 of CPUs. 2174 2175 For details, take a look at <file:Documentation/cpu-freq>. 2176 2177 If in doubt, say N. 2178 2179config CPU_FREQ_S3C24XX_PLL 2180 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2181 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2182 help 2183 Compile in support for changing the PLL frequency from the 2184 S3C24XX series CPUfreq driver. The PLL takes time to settle 2185 after a frequency change, so by default it is not enabled. 2186 2187 This also means that the PLL tables for the selected CPU(s) will 2188 be built which may increase the size of the kernel image. 2189 2190config CPU_FREQ_S3C24XX_DEBUG 2191 bool "Debug CPUfreq Samsung driver core" 2192 depends on CPU_FREQ_S3C24XX 2193 help 2194 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2195 2196config CPU_FREQ_S3C24XX_IODEBUG 2197 bool "Debug CPUfreq Samsung driver IO timing" 2198 depends on CPU_FREQ_S3C24XX 2199 help 2200 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2201 2202config CPU_FREQ_S3C24XX_DEBUGFS 2203 bool "Export debugfs for CPUFreq" 2204 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2205 help 2206 Export status information via debugfs. 2207 2208endif 2209 2210source "drivers/cpuidle/Kconfig" 2211 2212endmenu 2213 2214menu "Floating point emulation" 2215 2216comment "At least one emulation must be selected" 2217 2218config FPE_NWFPE 2219 bool "NWFPE math emulation" 2220 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2221 ---help--- 2222 Say Y to include the NWFPE floating point emulator in the kernel. 2223 This is necessary to run most binaries. Linux does not currently 2224 support floating point hardware so you need to say Y here even if 2225 your machine has an FPA or floating point co-processor podule. 2226 2227 You may say N here if you are going to load the Acorn FPEmulator 2228 early in the bootup. 2229 2230config FPE_NWFPE_XP 2231 bool "Support extended precision" 2232 depends on FPE_NWFPE 2233 help 2234 Say Y to include 80-bit support in the kernel floating-point 2235 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2236 Note that gcc does not generate 80-bit operations by default, 2237 so in most cases this option only enlarges the size of the 2238 floating point emulator without any good reason. 2239 2240 You almost surely want to say N here. 2241 2242config FPE_FASTFPE 2243 bool "FastFPE math emulation (EXPERIMENTAL)" 2244 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2245 ---help--- 2246 Say Y here to include the FAST floating point emulator in the kernel. 2247 This is an experimental much faster emulator which now also has full 2248 precision for the mantissa. It does not support any exceptions. 2249 It is very simple, and approximately 3-6 times faster than NWFPE. 2250 2251 It should be sufficient for most programs. It may be not suitable 2252 for scientific calculations, but you have to check this for yourself. 2253 If you do not feel you need a faster FP emulation you should better 2254 choose NWFPE. 2255 2256config VFP 2257 bool "VFP-format floating point maths" 2258 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2259 help 2260 Say Y to include VFP support code in the kernel. This is needed 2261 if your hardware includes a VFP unit. 2262 2263 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2264 release notes and additional status information. 2265 2266 Say N if your target does not have VFP hardware. 2267 2268config VFPv3 2269 bool 2270 depends on VFP 2271 default y if CPU_V7 2272 2273config NEON 2274 bool "Advanced SIMD (NEON) Extension support" 2275 depends on VFPv3 && CPU_V7 2276 help 2277 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2278 Extension. 2279 2280endmenu 2281 2282menu "Userspace binary formats" 2283 2284source "fs/Kconfig.binfmt" 2285 2286config ARTHUR 2287 tristate "RISC OS personality" 2288 depends on !AEABI 2289 help 2290 Say Y here to include the kernel code necessary if you want to run 2291 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2292 experimental; if this sounds frightening, say N and sleep in peace. 2293 You can also say M here to compile this support as a module (which 2294 will be called arthur). 2295 2296endmenu 2297 2298menu "Power management options" 2299 2300source "kernel/power/Kconfig" 2301 2302config ARCH_SUSPEND_POSSIBLE 2303 depends on !ARCH_S5PC100 2304 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2305 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2306 def_bool y 2307 2308config ARM_CPU_SUSPEND 2309 def_bool PM_SLEEP 2310 2311endmenu 2312 2313source "net/Kconfig" 2314 2315source "drivers/Kconfig" 2316 2317source "fs/Kconfig" 2318 2319source "arch/arm/Kconfig.debug" 2320 2321source "security/Kconfig" 2322 2323source "crypto/Kconfig" 2324 2325source "lib/Kconfig" 2326