1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 15 select ARCH_HAS_PHYS_TO_DMA 16 select ARCH_HAS_SET_MEMORY 17 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 18 select ARCH_HAS_STRICT_MODULE_RWX if MMU 19 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 20 select ARCH_HAVE_CUSTOM_GPIO_H 21 select ARCH_HAS_GCOV_PROFILE_ALL 22 select ARCH_MIGHT_HAVE_PC_PARPORT 23 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 24 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 25 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 26 select ARCH_SUPPORTS_ATOMIC_RMW 27 select ARCH_USE_BUILTIN_BSWAP 28 select ARCH_USE_CMPXCHG_LOCKREF 29 select ARCH_WANT_IPC_PARSE_VERSION 30 select BUILDTIME_EXTABLE_SORT if MMU 31 select CLONE_BACKWARDS 32 select CPU_PM if SUSPEND || CPU_IDLE 33 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 34 select DMA_REMAP if MMU 35 select EDAC_SUPPORT 36 select EDAC_ATOMIC_SCRUB 37 select GENERIC_ALLOCATOR 38 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 39 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 40 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 41 select GENERIC_CPU_AUTOPROBE 42 select GENERIC_EARLY_IOREMAP 43 select GENERIC_IDLE_POLL_SETUP 44 select GENERIC_IRQ_PROBE 45 select GENERIC_IRQ_SHOW 46 select GENERIC_IRQ_SHOW_LEVEL 47 select GENERIC_PCI_IOMAP 48 select GENERIC_SCHED_CLOCK 49 select GENERIC_SMP_IDLE_THREAD 50 select GENERIC_STRNCPY_FROM_USER 51 select GENERIC_STRNLEN_USER 52 select HANDLE_DOMAIN_IRQ 53 select HARDIRQS_SW_RESEND 54 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 55 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 56 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 57 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 58 select HAVE_ARCH_MMAP_RND_BITS if MMU 59 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 60 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 61 select HAVE_ARCH_TRACEHOOK 62 select HAVE_ARM_SMCCC if CPU_V7 63 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 64 select HAVE_CONTEXT_TRACKING 65 select HAVE_C_RECORDMCOUNT 66 select HAVE_DEBUG_KMEMLEAK 67 select HAVE_DMA_CONTIGUOUS if MMU 68 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 70 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 71 select HAVE_EXIT_THREAD 72 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 73 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL 74 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 75 select HAVE_GCC_PLUGINS 76 select HAVE_GENERIC_DMA_COHERENT 77 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 78 select HAVE_IDE if PCI || ISA || PCMCIA 79 select HAVE_IRQ_TIME_ACCOUNTING 80 select HAVE_KERNEL_GZIP 81 select HAVE_KERNEL_LZ4 82 select HAVE_KERNEL_LZMA 83 select HAVE_KERNEL_LZO 84 select HAVE_KERNEL_XZ 85 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 86 select HAVE_KRETPROBES if HAVE_KPROBES 87 select HAVE_MOD_ARCH_SPECIFIC 88 select HAVE_NMI 89 select HAVE_OPROFILE if HAVE_PERF_EVENTS 90 select HAVE_OPTPROBES if !THUMB2_KERNEL 91 select HAVE_PERF_EVENTS 92 select HAVE_PERF_REGS 93 select HAVE_PERF_USER_STACK_DUMP 94 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 95 select HAVE_REGS_AND_STACK_ACCESS_API 96 select HAVE_RSEQ 97 select HAVE_STACKPROTECTOR 98 select HAVE_SYSCALL_TRACEPOINTS 99 select HAVE_UID16 100 select HAVE_VIRT_CPU_ACCOUNTING_GEN 101 select IRQ_FORCED_THREADING 102 select MODULES_USE_ELF_REL 103 select NEED_DMA_MAP_STATE 104 select OF_EARLY_FLATTREE if OF 105 select OF_RESERVED_MEM if OF 106 select OLD_SIGACTION 107 select OLD_SIGSUSPEND3 108 select PCI_SYSCALL if PCI 109 select PERF_USE_VMALLOC 110 select REFCOUNT_FULL 111 select RTC_LIB 112 select SYS_SUPPORTS_APM_EMULATION 113 # Above selects are sorted alphabetically; please add new ones 114 # according to that. Thanks. 115 help 116 The ARM series is a line of low-power-consumption RISC chip designs 117 licensed by ARM Ltd and targeted at embedded applications and 118 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 119 manufactured, but legacy ARM-based PC hardware remains popular in 120 Europe. There is an ARM Linux project with a web page at 121 <http://www.arm.linux.org.uk/>. 122 123config ARM_HAS_SG_CHAIN 124 bool 125 126config ARM_DMA_USE_IOMMU 127 bool 128 select ARM_HAS_SG_CHAIN 129 select NEED_SG_DMA_LENGTH 130 131if ARM_DMA_USE_IOMMU 132 133config ARM_DMA_IOMMU_ALIGNMENT 134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 135 range 4 9 136 default 8 137 help 138 DMA mapping framework by default aligns all buffers to the smallest 139 PAGE_SIZE order which is greater than or equal to the requested buffer 140 size. This works well for buffers up to a few hundreds kilobytes, but 141 for larger buffers it just a waste of address space. Drivers which has 142 relatively small addressing window (like 64Mib) might run out of 143 virtual space with just a few allocations. 144 145 With this parameter you can specify the maximum PAGE_SIZE order for 146 DMA IOMMU buffers. Larger buffers will be aligned only to this 147 specified order. The order is expressed as a power of two multiplied 148 by the PAGE_SIZE. 149 150endif 151 152config SYS_SUPPORTS_APM_EMULATION 153 bool 154 155config HAVE_TCM 156 bool 157 select GENERIC_ALLOCATOR 158 159config HAVE_PROC_CPU 160 bool 161 162config NO_IOPORT_MAP 163 bool 164 165config SBUS 166 bool 167 168config STACKTRACE_SUPPORT 169 bool 170 default y 171 172config LOCKDEP_SUPPORT 173 bool 174 default y 175 176config TRACE_IRQFLAGS_SUPPORT 177 bool 178 default !CPU_V7M 179 180config RWSEM_XCHGADD_ALGORITHM 181 bool 182 default y 183 184config ARCH_HAS_ILOG2_U32 185 bool 186 187config ARCH_HAS_ILOG2_U64 188 bool 189 190config ARCH_HAS_BANDGAP 191 bool 192 193config FIX_EARLYCON_MEM 194 def_bool y if MMU 195 196config GENERIC_HWEIGHT 197 bool 198 default y 199 200config GENERIC_CALIBRATE_DELAY 201 bool 202 default y 203 204config ARCH_MAY_HAVE_PC_FDC 205 bool 206 207config ZONE_DMA 208 bool 209 210config ARCH_SUPPORTS_UPROBES 211 def_bool y 212 213config ARCH_HAS_DMA_SET_COHERENT_MASK 214 bool 215 216config GENERIC_ISA_DMA 217 bool 218 219config FIQ 220 bool 221 222config NEED_RET_TO_USER 223 bool 224 225config ARCH_MTD_XIP 226 bool 227 228config ARM_PATCH_PHYS_VIRT 229 bool "Patch physical to virtual translations at runtime" if EMBEDDED 230 default y 231 depends on !XIP_KERNEL && MMU 232 help 233 Patch phys-to-virt and virt-to-phys translation functions at 234 boot and module load time according to the position of the 235 kernel in system memory. 236 237 This can only be used with non-XIP MMU kernels where the base 238 of physical memory is at a 16MB boundary. 239 240 Only disable this option if you know that you do not require 241 this feature (eg, building a kernel for a single machine) and 242 you need to shrink the kernel to the minimal size. 243 244config NEED_MACH_IO_H 245 bool 246 help 247 Select this when mach/io.h is required to provide special 248 definitions for this platform. The need for mach/io.h should 249 be avoided when possible. 250 251config NEED_MACH_MEMORY_H 252 bool 253 help 254 Select this when mach/memory.h is required to provide special 255 definitions for this platform. The need for mach/memory.h should 256 be avoided when possible. 257 258config PHYS_OFFSET 259 hex "Physical address of main memory" if MMU 260 depends on !ARM_PATCH_PHYS_VIRT 261 default DRAM_BASE if !MMU 262 default 0x00000000 if ARCH_EBSA110 || \ 263 ARCH_FOOTBRIDGE || \ 264 ARCH_INTEGRATOR || \ 265 ARCH_IOP13XX || \ 266 ARCH_KS8695 || \ 267 ARCH_REALVIEW 268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 269 default 0x20000000 if ARCH_S5PV210 270 default 0xc0000000 if ARCH_SA1100 271 help 272 Please provide the physical address corresponding to the 273 location of main memory in your system. 274 275config GENERIC_BUG 276 def_bool y 277 depends on BUG 278 279config PGTABLE_LEVELS 280 int 281 default 3 if ARM_LPAE 282 default 2 283 284menu "System Type" 285 286config MMU 287 bool "MMU-based Paged Memory Management Support" 288 default y 289 help 290 Select if you want MMU-based virtualised addressing space 291 support by paged memory management. If unsure, say 'Y'. 292 293config ARCH_MMAP_RND_BITS_MIN 294 default 8 295 296config ARCH_MMAP_RND_BITS_MAX 297 default 14 if PAGE_OFFSET=0x40000000 298 default 15 if PAGE_OFFSET=0x80000000 299 default 16 300 301# 302# The "ARM system type" choice list is ordered alphabetically by option 303# text. Please add new entries in the option alphabetic order. 304# 305choice 306 prompt "ARM system type" 307 default ARM_SINGLE_ARMV7M if !MMU 308 default ARCH_MULTIPLATFORM if MMU 309 310config ARCH_MULTIPLATFORM 311 bool "Allow multiple platforms to be selected" 312 depends on MMU 313 select ARM_HAS_SG_CHAIN 314 select ARM_PATCH_PHYS_VIRT 315 select AUTO_ZRELADDR 316 select TIMER_OF 317 select COMMON_CLK 318 select GENERIC_CLOCKEVENTS 319 select GENERIC_IRQ_MULTI_HANDLER 320 select HAVE_PCI 321 select PCI_DOMAINS_GENERIC if PCI 322 select SPARSE_IRQ 323 select USE_OF 324 325config ARM_SINGLE_ARMV7M 326 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 327 depends on !MMU 328 select ARM_NVIC 329 select AUTO_ZRELADDR 330 select TIMER_OF 331 select COMMON_CLK 332 select CPU_V7M 333 select GENERIC_CLOCKEVENTS 334 select NO_IOPORT_MAP 335 select SPARSE_IRQ 336 select USE_OF 337 338config ARCH_EBSA110 339 bool "EBSA-110" 340 select ARCH_USES_GETTIMEOFFSET 341 select CPU_SA110 342 select ISA 343 select NEED_MACH_IO_H 344 select NEED_MACH_MEMORY_H 345 select NO_IOPORT_MAP 346 help 347 This is an evaluation board for the StrongARM processor available 348 from Digital. It has limited hardware on-board, including an 349 Ethernet interface, two PCMCIA sockets, two serial ports and a 350 parallel port. 351 352config ARCH_EP93XX 353 bool "EP93xx-based" 354 select ARCH_SPARSEMEM_ENABLE 355 select ARM_AMBA 356 imply ARM_PATCH_PHYS_VIRT 357 select ARM_VIC 358 select AUTO_ZRELADDR 359 select CLKDEV_LOOKUP 360 select CLKSRC_MMIO 361 select CPU_ARM920T 362 select GENERIC_CLOCKEVENTS 363 select GPIOLIB 364 help 365 This enables support for the Cirrus EP93xx series of CPUs. 366 367config ARCH_FOOTBRIDGE 368 bool "FootBridge" 369 select CPU_SA110 370 select FOOTBRIDGE 371 select GENERIC_CLOCKEVENTS 372 select HAVE_IDE 373 select NEED_MACH_IO_H if !MMU 374 select NEED_MACH_MEMORY_H 375 help 376 Support for systems based on the DC21285 companion chip 377 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 378 379config ARCH_NETX 380 bool "Hilscher NetX based" 381 select ARM_VIC 382 select CLKSRC_MMIO 383 select CPU_ARM926T 384 select GENERIC_CLOCKEVENTS 385 help 386 This enables support for systems based on the Hilscher NetX Soc 387 388config ARCH_IOP13XX 389 bool "IOP13xx-based" 390 depends on MMU 391 select CPU_XSC3 392 select NEED_MACH_MEMORY_H 393 select NEED_RET_TO_USER 394 select FORCE_PCI 395 select PLAT_IOP 396 select VMSPLIT_1G 397 select SPARSE_IRQ 398 help 399 Support for Intel's IOP13XX (XScale) family of processors. 400 401config ARCH_IOP32X 402 bool "IOP32x-based" 403 depends on MMU 404 select CPU_XSCALE 405 select GPIO_IOP 406 select GPIOLIB 407 select NEED_RET_TO_USER 408 select FORCE_PCI 409 select PLAT_IOP 410 help 411 Support for Intel's 80219 and IOP32X (XScale) family of 412 processors. 413 414config ARCH_IOP33X 415 bool "IOP33x-based" 416 depends on MMU 417 select CPU_XSCALE 418 select GPIO_IOP 419 select GPIOLIB 420 select NEED_RET_TO_USER 421 select FORCE_PCI 422 select PLAT_IOP 423 help 424 Support for Intel's IOP33X (XScale) family of processors. 425 426config ARCH_IXP4XX 427 bool "IXP4xx-based" 428 depends on MMU 429 select ARCH_HAS_DMA_SET_COHERENT_MASK 430 select ARCH_SUPPORTS_BIG_ENDIAN 431 select CLKSRC_MMIO 432 select CPU_XSCALE 433 select DMABOUNCE if PCI 434 select GENERIC_CLOCKEVENTS 435 select GPIOLIB 436 select HAVE_PCI 437 select NEED_MACH_IO_H 438 select USB_EHCI_BIG_ENDIAN_DESC 439 select USB_EHCI_BIG_ENDIAN_MMIO 440 help 441 Support for Intel's IXP4XX (XScale) family of processors. 442 443config ARCH_DOVE 444 bool "Marvell Dove" 445 select CPU_PJ4 446 select GENERIC_CLOCKEVENTS 447 select GENERIC_IRQ_MULTI_HANDLER 448 select GPIOLIB 449 select HAVE_PCI 450 select MVEBU_MBUS 451 select PINCTRL 452 select PINCTRL_DOVE 453 select PLAT_ORION_LEGACY 454 select SPARSE_IRQ 455 select PM_GENERIC_DOMAINS if PM 456 help 457 Support for the Marvell Dove SoC 88AP510 458 459config ARCH_KS8695 460 bool "Micrel/Kendin KS8695" 461 select CLKSRC_MMIO 462 select CPU_ARM922T 463 select GENERIC_CLOCKEVENTS 464 select GPIOLIB 465 select NEED_MACH_MEMORY_H 466 help 467 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 468 System-on-Chip devices. 469 470config ARCH_W90X900 471 bool "Nuvoton W90X900 CPU" 472 select CLKDEV_LOOKUP 473 select CLKSRC_MMIO 474 select CPU_ARM926T 475 select GENERIC_CLOCKEVENTS 476 select GPIOLIB 477 help 478 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 479 At present, the w90x900 has been renamed nuc900, regarding 480 the ARM series product line, you can login the following 481 link address to know more. 482 483 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 484 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 485 486config ARCH_LPC32XX 487 bool "NXP LPC32XX" 488 select ARM_AMBA 489 select CLKDEV_LOOKUP 490 select CLKSRC_LPC32XX 491 select COMMON_CLK 492 select CPU_ARM926T 493 select GENERIC_CLOCKEVENTS 494 select GENERIC_IRQ_MULTI_HANDLER 495 select GPIOLIB 496 select SPARSE_IRQ 497 select USE_OF 498 help 499 Support for the NXP LPC32XX family of processors 500 501config ARCH_PXA 502 bool "PXA2xx/PXA3xx-based" 503 depends on MMU 504 select ARCH_MTD_XIP 505 select ARM_CPU_SUSPEND if PM 506 select AUTO_ZRELADDR 507 select COMMON_CLK 508 select CLKDEV_LOOKUP 509 select CLKSRC_PXA 510 select CLKSRC_MMIO 511 select TIMER_OF 512 select CPU_XSCALE if !CPU_XSC3 513 select GENERIC_CLOCKEVENTS 514 select GENERIC_IRQ_MULTI_HANDLER 515 select GPIO_PXA 516 select GPIOLIB 517 select HAVE_IDE 518 select IRQ_DOMAIN 519 select PLAT_PXA 520 select SPARSE_IRQ 521 help 522 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 523 524config ARCH_RPC 525 bool "RiscPC" 526 depends on MMU 527 select ARCH_ACORN 528 select ARCH_MAY_HAVE_PC_FDC 529 select ARCH_SPARSEMEM_ENABLE 530 select ARCH_USES_GETTIMEOFFSET 531 select CPU_SA110 532 select FIQ 533 select HAVE_IDE 534 select HAVE_PATA_PLATFORM 535 select ISA_DMA_API 536 select NEED_MACH_IO_H 537 select NEED_MACH_MEMORY_H 538 select NO_IOPORT_MAP 539 help 540 On the Acorn Risc-PC, Linux can support the internal IDE disk and 541 CD-ROM interface, serial and parallel port, and the floppy drive. 542 543config ARCH_SA1100 544 bool "SA1100-based" 545 select ARCH_MTD_XIP 546 select ARCH_SPARSEMEM_ENABLE 547 select CLKDEV_LOOKUP 548 select CLKSRC_MMIO 549 select CLKSRC_PXA 550 select TIMER_OF if OF 551 select CPU_FREQ 552 select CPU_SA1100 553 select GENERIC_CLOCKEVENTS 554 select GENERIC_IRQ_MULTI_HANDLER 555 select GPIOLIB 556 select HAVE_IDE 557 select IRQ_DOMAIN 558 select ISA 559 select NEED_MACH_MEMORY_H 560 select SPARSE_IRQ 561 help 562 Support for StrongARM 11x0 based boards. 563 564config ARCH_S3C24XX 565 bool "Samsung S3C24XX SoCs" 566 select ATAGS 567 select CLKDEV_LOOKUP 568 select CLKSRC_SAMSUNG_PWM 569 select GENERIC_CLOCKEVENTS 570 select GPIO_SAMSUNG 571 select GPIOLIB 572 select GENERIC_IRQ_MULTI_HANDLER 573 select HAVE_S3C2410_I2C if I2C 574 select HAVE_S3C2410_WATCHDOG if WATCHDOG 575 select HAVE_S3C_RTC if RTC_CLASS 576 select NEED_MACH_IO_H 577 select SAMSUNG_ATAGS 578 select USE_OF 579 help 580 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 581 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 582 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 583 Samsung SMDK2410 development board (and derivatives). 584 585config ARCH_DAVINCI 586 bool "TI DaVinci" 587 select ARCH_HAS_HOLES_MEMORYMODEL 588 select COMMON_CLK 589 select CPU_ARM926T 590 select GENERIC_ALLOCATOR 591 select GENERIC_CLOCKEVENTS 592 select GENERIC_IRQ_CHIP 593 select GPIOLIB 594 select HAVE_IDE 595 select PM_GENERIC_DOMAINS if PM 596 select PM_GENERIC_DOMAINS_OF if PM && OF 597 select RESET_CONTROLLER 598 select USE_OF 599 select ZONE_DMA 600 help 601 Support for TI's DaVinci platform. 602 603config ARCH_OMAP1 604 bool "TI OMAP1" 605 depends on MMU 606 select ARCH_HAS_HOLES_MEMORYMODEL 607 select ARCH_OMAP 608 select CLKDEV_LOOKUP 609 select CLKSRC_MMIO 610 select GENERIC_CLOCKEVENTS 611 select GENERIC_IRQ_CHIP 612 select GENERIC_IRQ_MULTI_HANDLER 613 select GPIOLIB 614 select HAVE_IDE 615 select IRQ_DOMAIN 616 select NEED_MACH_IO_H if PCCARD 617 select NEED_MACH_MEMORY_H 618 select SPARSE_IRQ 619 help 620 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 621 622endchoice 623 624menu "Multiple platform selection" 625 depends on ARCH_MULTIPLATFORM 626 627comment "CPU Core family selection" 628 629config ARCH_MULTI_V4 630 bool "ARMv4 based platforms (FA526)" 631 depends on !ARCH_MULTI_V6_V7 632 select ARCH_MULTI_V4_V5 633 select CPU_FA526 634 635config ARCH_MULTI_V4T 636 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 637 depends on !ARCH_MULTI_V6_V7 638 select ARCH_MULTI_V4_V5 639 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 640 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 641 CPU_ARM925T || CPU_ARM940T) 642 643config ARCH_MULTI_V5 644 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 645 depends on !ARCH_MULTI_V6_V7 646 select ARCH_MULTI_V4_V5 647 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 648 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 649 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 650 651config ARCH_MULTI_V4_V5 652 bool 653 654config ARCH_MULTI_V6 655 bool "ARMv6 based platforms (ARM11)" 656 select ARCH_MULTI_V6_V7 657 select CPU_V6K 658 659config ARCH_MULTI_V7 660 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 661 default y 662 select ARCH_MULTI_V6_V7 663 select CPU_V7 664 select HAVE_SMP 665 666config ARCH_MULTI_V6_V7 667 bool 668 select MIGHT_HAVE_CACHE_L2X0 669 670config ARCH_MULTI_CPU_AUTO 671 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 672 select ARCH_MULTI_V5 673 674endmenu 675 676config ARCH_VIRT 677 bool "Dummy Virtual Machine" 678 depends on ARCH_MULTI_V7 679 select ARM_AMBA 680 select ARM_GIC 681 select ARM_GIC_V2M if PCI 682 select ARM_GIC_V3 683 select ARM_GIC_V3_ITS if PCI 684 select ARM_PSCI 685 select HAVE_ARM_ARCH_TIMER 686 select ARCH_SUPPORTS_BIG_ENDIAN 687 688# 689# This is sorted alphabetically by mach-* pathname. However, plat-* 690# Kconfigs may be included either alphabetically (according to the 691# plat- suffix) or along side the corresponding mach-* source. 692# 693source "arch/arm/mach-actions/Kconfig" 694 695source "arch/arm/mach-alpine/Kconfig" 696 697source "arch/arm/mach-artpec/Kconfig" 698 699source "arch/arm/mach-asm9260/Kconfig" 700 701source "arch/arm/mach-aspeed/Kconfig" 702 703source "arch/arm/mach-at91/Kconfig" 704 705source "arch/arm/mach-axxia/Kconfig" 706 707source "arch/arm/mach-bcm/Kconfig" 708 709source "arch/arm/mach-berlin/Kconfig" 710 711source "arch/arm/mach-clps711x/Kconfig" 712 713source "arch/arm/mach-cns3xxx/Kconfig" 714 715source "arch/arm/mach-davinci/Kconfig" 716 717source "arch/arm/mach-digicolor/Kconfig" 718 719source "arch/arm/mach-dove/Kconfig" 720 721source "arch/arm/mach-ep93xx/Kconfig" 722 723source "arch/arm/mach-exynos/Kconfig" 724source "arch/arm/plat-samsung/Kconfig" 725 726source "arch/arm/mach-footbridge/Kconfig" 727 728source "arch/arm/mach-gemini/Kconfig" 729 730source "arch/arm/mach-highbank/Kconfig" 731 732source "arch/arm/mach-hisi/Kconfig" 733 734source "arch/arm/mach-imx/Kconfig" 735 736source "arch/arm/mach-integrator/Kconfig" 737 738source "arch/arm/mach-iop13xx/Kconfig" 739 740source "arch/arm/mach-iop32x/Kconfig" 741 742source "arch/arm/mach-iop33x/Kconfig" 743 744source "arch/arm/mach-ixp4xx/Kconfig" 745 746source "arch/arm/mach-keystone/Kconfig" 747 748source "arch/arm/mach-ks8695/Kconfig" 749 750source "arch/arm/mach-mediatek/Kconfig" 751 752source "arch/arm/mach-meson/Kconfig" 753 754source "arch/arm/mach-mmp/Kconfig" 755 756source "arch/arm/mach-moxart/Kconfig" 757 758source "arch/arm/mach-mv78xx0/Kconfig" 759 760source "arch/arm/mach-mvebu/Kconfig" 761 762source "arch/arm/mach-mxs/Kconfig" 763 764source "arch/arm/mach-netx/Kconfig" 765 766source "arch/arm/mach-nomadik/Kconfig" 767 768source "arch/arm/mach-npcm/Kconfig" 769 770source "arch/arm/mach-nspire/Kconfig" 771 772source "arch/arm/plat-omap/Kconfig" 773 774source "arch/arm/mach-omap1/Kconfig" 775 776source "arch/arm/mach-omap2/Kconfig" 777 778source "arch/arm/mach-orion5x/Kconfig" 779 780source "arch/arm/mach-oxnas/Kconfig" 781 782source "arch/arm/mach-picoxcell/Kconfig" 783 784source "arch/arm/mach-prima2/Kconfig" 785 786source "arch/arm/mach-pxa/Kconfig" 787source "arch/arm/plat-pxa/Kconfig" 788 789source "arch/arm/mach-qcom/Kconfig" 790 791source "arch/arm/mach-rda/Kconfig" 792 793source "arch/arm/mach-realview/Kconfig" 794 795source "arch/arm/mach-rockchip/Kconfig" 796 797source "arch/arm/mach-s3c24xx/Kconfig" 798 799source "arch/arm/mach-s3c64xx/Kconfig" 800 801source "arch/arm/mach-s5pv210/Kconfig" 802 803source "arch/arm/mach-sa1100/Kconfig" 804 805source "arch/arm/mach-shmobile/Kconfig" 806 807source "arch/arm/mach-socfpga/Kconfig" 808 809source "arch/arm/mach-spear/Kconfig" 810 811source "arch/arm/mach-sti/Kconfig" 812 813source "arch/arm/mach-stm32/Kconfig" 814 815source "arch/arm/mach-sunxi/Kconfig" 816 817source "arch/arm/mach-tango/Kconfig" 818 819source "arch/arm/mach-tegra/Kconfig" 820 821source "arch/arm/mach-u300/Kconfig" 822 823source "arch/arm/mach-uniphier/Kconfig" 824 825source "arch/arm/mach-ux500/Kconfig" 826 827source "arch/arm/mach-versatile/Kconfig" 828 829source "arch/arm/mach-vexpress/Kconfig" 830source "arch/arm/plat-versatile/Kconfig" 831 832source "arch/arm/mach-vt8500/Kconfig" 833 834source "arch/arm/mach-w90x900/Kconfig" 835 836source "arch/arm/mach-zx/Kconfig" 837 838source "arch/arm/mach-zynq/Kconfig" 839 840# ARMv7-M architecture 841config ARCH_EFM32 842 bool "Energy Micro efm32" 843 depends on ARM_SINGLE_ARMV7M 844 select GPIOLIB 845 help 846 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 847 processors. 848 849config ARCH_LPC18XX 850 bool "NXP LPC18xx/LPC43xx" 851 depends on ARM_SINGLE_ARMV7M 852 select ARCH_HAS_RESET_CONTROLLER 853 select ARM_AMBA 854 select CLKSRC_LPC32XX 855 select PINCTRL 856 help 857 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 858 high performance microcontrollers. 859 860config ARCH_MPS2 861 bool "ARM MPS2 platform" 862 depends on ARM_SINGLE_ARMV7M 863 select ARM_AMBA 864 select CLKSRC_MPS2 865 help 866 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 867 with a range of available cores like Cortex-M3/M4/M7. 868 869 Please, note that depends which Application Note is used memory map 870 for the platform may vary, so adjustment of RAM base might be needed. 871 872# Definitions to make life easier 873config ARCH_ACORN 874 bool 875 876config PLAT_IOP 877 bool 878 select GENERIC_CLOCKEVENTS 879 880config PLAT_ORION 881 bool 882 select CLKSRC_MMIO 883 select COMMON_CLK 884 select GENERIC_IRQ_CHIP 885 select IRQ_DOMAIN 886 887config PLAT_ORION_LEGACY 888 bool 889 select PLAT_ORION 890 891config PLAT_PXA 892 bool 893 894config PLAT_VERSATILE 895 bool 896 897source "arch/arm/firmware/Kconfig" 898 899source "arch/arm/mm/Kconfig" 900 901config IWMMXT 902 bool "Enable iWMMXt support" 903 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 904 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 905 help 906 Enable support for iWMMXt context switching at run time if 907 running on a CPU that supports it. 908 909if !MMU 910source "arch/arm/Kconfig-nommu" 911endif 912 913config PJ4B_ERRATA_4742 914 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 915 depends on CPU_PJ4B && MACH_ARMADA_370 916 default y 917 help 918 When coming out of either a Wait for Interrupt (WFI) or a Wait for 919 Event (WFE) IDLE states, a specific timing sensitivity exists between 920 the retiring WFI/WFE instructions and the newly issued subsequent 921 instructions. This sensitivity can result in a CPU hang scenario. 922 Workaround: 923 The software must insert either a Data Synchronization Barrier (DSB) 924 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 925 instruction 926 927config ARM_ERRATA_326103 928 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 929 depends on CPU_V6 930 help 931 Executing a SWP instruction to read-only memory does not set bit 11 932 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 933 treat the access as a read, preventing a COW from occurring and 934 causing the faulting task to livelock. 935 936config ARM_ERRATA_411920 937 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 938 depends on CPU_V6 || CPU_V6K 939 help 940 Invalidation of the Instruction Cache operation can 941 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 942 It does not affect the MPCore. This option enables the ARM Ltd. 943 recommended workaround. 944 945config ARM_ERRATA_430973 946 bool "ARM errata: Stale prediction on replaced interworking branch" 947 depends on CPU_V7 948 help 949 This option enables the workaround for the 430973 Cortex-A8 950 r1p* erratum. If a code sequence containing an ARM/Thumb 951 interworking branch is replaced with another code sequence at the 952 same virtual address, whether due to self-modifying code or virtual 953 to physical address re-mapping, Cortex-A8 does not recover from the 954 stale interworking branch prediction. This results in Cortex-A8 955 executing the new code sequence in the incorrect ARM or Thumb state. 956 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 957 and also flushes the branch target cache at every context switch. 958 Note that setting specific bits in the ACTLR register may not be 959 available in non-secure mode. 960 961config ARM_ERRATA_458693 962 bool "ARM errata: Processor deadlock when a false hazard is created" 963 depends on CPU_V7 964 depends on !ARCH_MULTIPLATFORM 965 help 966 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 967 erratum. For very specific sequences of memory operations, it is 968 possible for a hazard condition intended for a cache line to instead 969 be incorrectly associated with a different cache line. This false 970 hazard might then cause a processor deadlock. The workaround enables 971 the L1 caching of the NEON accesses and disables the PLD instruction 972 in the ACTLR register. Note that setting specific bits in the ACTLR 973 register may not be available in non-secure mode. 974 975config ARM_ERRATA_460075 976 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 977 depends on CPU_V7 978 depends on !ARCH_MULTIPLATFORM 979 help 980 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 981 erratum. Any asynchronous access to the L2 cache may encounter a 982 situation in which recent store transactions to the L2 cache are lost 983 and overwritten with stale memory contents from external memory. The 984 workaround disables the write-allocate mode for the L2 cache via the 985 ACTLR register. Note that setting specific bits in the ACTLR register 986 may not be available in non-secure mode. 987 988config ARM_ERRATA_742230 989 bool "ARM errata: DMB operation may be faulty" 990 depends on CPU_V7 && SMP 991 depends on !ARCH_MULTIPLATFORM 992 help 993 This option enables the workaround for the 742230 Cortex-A9 994 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 995 between two write operations may not ensure the correct visibility 996 ordering of the two writes. This workaround sets a specific bit in 997 the diagnostic register of the Cortex-A9 which causes the DMB 998 instruction to behave as a DSB, ensuring the correct behaviour of 999 the two writes. 1000 1001config ARM_ERRATA_742231 1002 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1003 depends on CPU_V7 && SMP 1004 depends on !ARCH_MULTIPLATFORM 1005 help 1006 This option enables the workaround for the 742231 Cortex-A9 1007 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1008 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1009 accessing some data located in the same cache line, may get corrupted 1010 data due to bad handling of the address hazard when the line gets 1011 replaced from one of the CPUs at the same time as another CPU is 1012 accessing it. This workaround sets specific bits in the diagnostic 1013 register of the Cortex-A9 which reduces the linefill issuing 1014 capabilities of the processor. 1015 1016config ARM_ERRATA_643719 1017 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1018 depends on CPU_V7 && SMP 1019 default y 1020 help 1021 This option enables the workaround for the 643719 Cortex-A9 (prior to 1022 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1023 register returns zero when it should return one. The workaround 1024 corrects this value, ensuring cache maintenance operations which use 1025 it behave as intended and avoiding data corruption. 1026 1027config ARM_ERRATA_720789 1028 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1029 depends on CPU_V7 1030 help 1031 This option enables the workaround for the 720789 Cortex-A9 (prior to 1032 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1033 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1034 As a consequence of this erratum, some TLB entries which should be 1035 invalidated are not, resulting in an incoherency in the system page 1036 tables. The workaround changes the TLB flushing routines to invalidate 1037 entries regardless of the ASID. 1038 1039config ARM_ERRATA_743622 1040 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1041 depends on CPU_V7 1042 depends on !ARCH_MULTIPLATFORM 1043 help 1044 This option enables the workaround for the 743622 Cortex-A9 1045 (r2p*) erratum. Under very rare conditions, a faulty 1046 optimisation in the Cortex-A9 Store Buffer may lead to data 1047 corruption. This workaround sets a specific bit in the diagnostic 1048 register of the Cortex-A9 which disables the Store Buffer 1049 optimisation, preventing the defect from occurring. This has no 1050 visible impact on the overall performance or power consumption of the 1051 processor. 1052 1053config ARM_ERRATA_751472 1054 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1055 depends on CPU_V7 1056 depends on !ARCH_MULTIPLATFORM 1057 help 1058 This option enables the workaround for the 751472 Cortex-A9 (prior 1059 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1060 completion of a following broadcasted operation if the second 1061 operation is received by a CPU before the ICIALLUIS has completed, 1062 potentially leading to corrupted entries in the cache or TLB. 1063 1064config ARM_ERRATA_754322 1065 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1066 depends on CPU_V7 1067 help 1068 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1069 r3p*) erratum. A speculative memory access may cause a page table walk 1070 which starts prior to an ASID switch but completes afterwards. This 1071 can populate the micro-TLB with a stale entry which may be hit with 1072 the new ASID. This workaround places two dsb instructions in the mm 1073 switching code so that no page table walks can cross the ASID switch. 1074 1075config ARM_ERRATA_754327 1076 bool "ARM errata: no automatic Store Buffer drain" 1077 depends on CPU_V7 && SMP 1078 help 1079 This option enables the workaround for the 754327 Cortex-A9 (prior to 1080 r2p0) erratum. The Store Buffer does not have any automatic draining 1081 mechanism and therefore a livelock may occur if an external agent 1082 continuously polls a memory location waiting to observe an update. 1083 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1084 written polling loops from denying visibility of updates to memory. 1085 1086config ARM_ERRATA_364296 1087 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1088 depends on CPU_V6 1089 help 1090 This options enables the workaround for the 364296 ARM1136 1091 r0p2 erratum (possible cache data corruption with 1092 hit-under-miss enabled). It sets the undocumented bit 31 in 1093 the auxiliary control register and the FI bit in the control 1094 register, thus disabling hit-under-miss without putting the 1095 processor into full low interrupt latency mode. ARM11MPCore 1096 is not affected. 1097 1098config ARM_ERRATA_764369 1099 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1100 depends on CPU_V7 && SMP 1101 help 1102 This option enables the workaround for erratum 764369 1103 affecting Cortex-A9 MPCore with two or more processors (all 1104 current revisions). Under certain timing circumstances, a data 1105 cache line maintenance operation by MVA targeting an Inner 1106 Shareable memory region may fail to proceed up to either the 1107 Point of Coherency or to the Point of Unification of the 1108 system. This workaround adds a DSB instruction before the 1109 relevant cache maintenance functions and sets a specific bit 1110 in the diagnostic control register of the SCU. 1111 1112config ARM_ERRATA_775420 1113 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1114 depends on CPU_V7 1115 help 1116 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1117 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1118 operation aborts with MMU exception, it might cause the processor 1119 to deadlock. This workaround puts DSB before executing ISB if 1120 an abort may occur on cache maintenance. 1121 1122config ARM_ERRATA_798181 1123 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1124 depends on CPU_V7 && SMP 1125 help 1126 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1127 adequately shooting down all use of the old entries. This 1128 option enables the Linux kernel workaround for this erratum 1129 which sends an IPI to the CPUs that are running the same ASID 1130 as the one being invalidated. 1131 1132config ARM_ERRATA_773022 1133 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1134 depends on CPU_V7 1135 help 1136 This option enables the workaround for the 773022 Cortex-A15 1137 (up to r0p4) erratum. In certain rare sequences of code, the 1138 loop buffer may deliver incorrect instructions. This 1139 workaround disables the loop buffer to avoid the erratum. 1140 1141config ARM_ERRATA_818325_852422 1142 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1143 depends on CPU_V7 1144 help 1145 This option enables the workaround for: 1146 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1147 instruction might deadlock. Fixed in r0p1. 1148 - Cortex-A12 852422: Execution of a sequence of instructions might 1149 lead to either a data corruption or a CPU deadlock. Not fixed in 1150 any Cortex-A12 cores yet. 1151 This workaround for all both errata involves setting bit[12] of the 1152 Feature Register. This bit disables an optimisation applied to a 1153 sequence of 2 instructions that use opposing condition codes. 1154 1155config ARM_ERRATA_821420 1156 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1157 depends on CPU_V7 1158 help 1159 This option enables the workaround for the 821420 Cortex-A12 1160 (all revs) erratum. In very rare timing conditions, a sequence 1161 of VMOV to Core registers instructions, for which the second 1162 one is in the shadow of a branch or abort, can lead to a 1163 deadlock when the VMOV instructions are issued out-of-order. 1164 1165config ARM_ERRATA_825619 1166 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1167 depends on CPU_V7 1168 help 1169 This option enables the workaround for the 825619 Cortex-A12 1170 (all revs) erratum. Within rare timing constraints, executing a 1171 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1172 and Device/Strongly-Ordered loads and stores might cause deadlock 1173 1174config ARM_ERRATA_852421 1175 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1176 depends on CPU_V7 1177 help 1178 This option enables the workaround for the 852421 Cortex-A17 1179 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1180 execution of a DMB ST instruction might fail to properly order 1181 stores from GroupA and stores from GroupB. 1182 1183config ARM_ERRATA_852423 1184 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1185 depends on CPU_V7 1186 help 1187 This option enables the workaround for: 1188 - Cortex-A17 852423: Execution of a sequence of instructions might 1189 lead to either a data corruption or a CPU deadlock. Not fixed in 1190 any Cortex-A17 cores yet. 1191 This is identical to Cortex-A12 erratum 852422. It is a separate 1192 config option from the A12 erratum due to the way errata are checked 1193 for and handled. 1194 1195endmenu 1196 1197source "arch/arm/common/Kconfig" 1198 1199menu "Bus support" 1200 1201config ISA 1202 bool 1203 help 1204 Find out whether you have ISA slots on your motherboard. ISA is the 1205 name of a bus system, i.e. the way the CPU talks to the other stuff 1206 inside your box. Other bus systems are PCI, EISA, MicroChannel 1207 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1208 newer boards don't support it. If you have ISA, say Y, otherwise N. 1209 1210# Select ISA DMA controller support 1211config ISA_DMA 1212 bool 1213 select ISA_DMA_API 1214 1215# Select ISA DMA interface 1216config ISA_DMA_API 1217 bool 1218 1219config PCI_NANOENGINE 1220 bool "BSE nanoEngine PCI support" 1221 depends on SA1100_NANOENGINE 1222 help 1223 Enable PCI on the BSE nanoEngine board. 1224 1225config PCI_HOST_ITE8152 1226 bool 1227 depends on PCI && MACH_ARMCORE 1228 default y 1229 select DMABOUNCE 1230 1231endmenu 1232 1233menu "Kernel Features" 1234 1235config HAVE_SMP 1236 bool 1237 help 1238 This option should be selected by machines which have an SMP- 1239 capable CPU. 1240 1241 The only effect of this option is to make the SMP-related 1242 options available to the user for configuration. 1243 1244config SMP 1245 bool "Symmetric Multi-Processing" 1246 depends on CPU_V6K || CPU_V7 1247 depends on GENERIC_CLOCKEVENTS 1248 depends on HAVE_SMP 1249 depends on MMU || ARM_MPU 1250 select IRQ_WORK 1251 help 1252 This enables support for systems with more than one CPU. If you have 1253 a system with only one CPU, say N. If you have a system with more 1254 than one CPU, say Y. 1255 1256 If you say N here, the kernel will run on uni- and multiprocessor 1257 machines, but will use only one CPU of a multiprocessor machine. If 1258 you say Y here, the kernel will run on many, but not all, 1259 uniprocessor machines. On a uniprocessor machine, the kernel 1260 will run faster if you say N here. 1261 1262 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1263 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1264 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1265 1266 If you don't know what to do here, say N. 1267 1268config SMP_ON_UP 1269 bool "Allow booting SMP kernel on uniprocessor systems" 1270 depends on SMP && !XIP_KERNEL && MMU 1271 default y 1272 help 1273 SMP kernels contain instructions which fail on non-SMP processors. 1274 Enabling this option allows the kernel to modify itself to make 1275 these instructions safe. Disabling it allows about 1K of space 1276 savings. 1277 1278 If you don't know what to do here, say Y. 1279 1280config ARM_CPU_TOPOLOGY 1281 bool "Support cpu topology definition" 1282 depends on SMP && CPU_V7 1283 default y 1284 help 1285 Support ARM cpu topology definition. The MPIDR register defines 1286 affinity between processors which is then used to describe the cpu 1287 topology of an ARM System. 1288 1289config SCHED_MC 1290 bool "Multi-core scheduler support" 1291 depends on ARM_CPU_TOPOLOGY 1292 help 1293 Multi-core scheduler support improves the CPU scheduler's decision 1294 making when dealing with multi-core CPU chips at a cost of slightly 1295 increased overhead in some places. If unsure say N here. 1296 1297config SCHED_SMT 1298 bool "SMT scheduler support" 1299 depends on ARM_CPU_TOPOLOGY 1300 help 1301 Improves the CPU scheduler's decision making when dealing with 1302 MultiThreading at a cost of slightly increased overhead in some 1303 places. If unsure say N here. 1304 1305config HAVE_ARM_SCU 1306 bool 1307 help 1308 This option enables support for the ARM system coherency unit 1309 1310config HAVE_ARM_ARCH_TIMER 1311 bool "Architected timer support" 1312 depends on CPU_V7 1313 select ARM_ARCH_TIMER 1314 select GENERIC_CLOCKEVENTS 1315 help 1316 This option enables support for the ARM architected timer 1317 1318config HAVE_ARM_TWD 1319 bool 1320 select TIMER_OF if OF 1321 help 1322 This options enables support for the ARM timer and watchdog unit 1323 1324config MCPM 1325 bool "Multi-Cluster Power Management" 1326 depends on CPU_V7 && SMP 1327 help 1328 This option provides the common power management infrastructure 1329 for (multi-)cluster based systems, such as big.LITTLE based 1330 systems. 1331 1332config MCPM_QUAD_CLUSTER 1333 bool 1334 depends on MCPM 1335 help 1336 To avoid wasting resources unnecessarily, MCPM only supports up 1337 to 2 clusters by default. 1338 Platforms with 3 or 4 clusters that use MCPM must select this 1339 option to allow the additional clusters to be managed. 1340 1341config BIG_LITTLE 1342 bool "big.LITTLE support (Experimental)" 1343 depends on CPU_V7 && SMP 1344 select MCPM 1345 help 1346 This option enables support selections for the big.LITTLE 1347 system architecture. 1348 1349config BL_SWITCHER 1350 bool "big.LITTLE switcher support" 1351 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1352 select CPU_PM 1353 help 1354 The big.LITTLE "switcher" provides the core functionality to 1355 transparently handle transition between a cluster of A15's 1356 and a cluster of A7's in a big.LITTLE system. 1357 1358config BL_SWITCHER_DUMMY_IF 1359 tristate "Simple big.LITTLE switcher user interface" 1360 depends on BL_SWITCHER && DEBUG_KERNEL 1361 help 1362 This is a simple and dummy char dev interface to control 1363 the big.LITTLE switcher core code. It is meant for 1364 debugging purposes only. 1365 1366choice 1367 prompt "Memory split" 1368 depends on MMU 1369 default VMSPLIT_3G 1370 help 1371 Select the desired split between kernel and user memory. 1372 1373 If you are not absolutely sure what you are doing, leave this 1374 option alone! 1375 1376 config VMSPLIT_3G 1377 bool "3G/1G user/kernel split" 1378 config VMSPLIT_3G_OPT 1379 depends on !ARM_LPAE 1380 bool "3G/1G user/kernel split (for full 1G low memory)" 1381 config VMSPLIT_2G 1382 bool "2G/2G user/kernel split" 1383 config VMSPLIT_1G 1384 bool "1G/3G user/kernel split" 1385endchoice 1386 1387config PAGE_OFFSET 1388 hex 1389 default PHYS_OFFSET if !MMU 1390 default 0x40000000 if VMSPLIT_1G 1391 default 0x80000000 if VMSPLIT_2G 1392 default 0xB0000000 if VMSPLIT_3G_OPT 1393 default 0xC0000000 1394 1395config NR_CPUS 1396 int "Maximum number of CPUs (2-32)" 1397 range 2 32 1398 depends on SMP 1399 default "4" 1400 1401config HOTPLUG_CPU 1402 bool "Support for hot-pluggable CPUs" 1403 depends on SMP 1404 help 1405 Say Y here to experiment with turning CPUs off and on. CPUs 1406 can be controlled through /sys/devices/system/cpu. 1407 1408config ARM_PSCI 1409 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1410 depends on HAVE_ARM_SMCCC 1411 select ARM_PSCI_FW 1412 help 1413 Say Y here if you want Linux to communicate with system firmware 1414 implementing the PSCI specification for CPU-centric power 1415 management operations described in ARM document number ARM DEN 1416 0022A ("Power State Coordination Interface System Software on 1417 ARM processors"). 1418 1419# The GPIO number here must be sorted by descending number. In case of 1420# a multiplatform kernel, we just want the highest value required by the 1421# selected platforms. 1422config ARCH_NR_GPIO 1423 int 1424 default 2048 if ARCH_SOCFPGA 1425 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1426 ARCH_ZYNQ 1427 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1428 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1429 default 416 if ARCH_SUNXI 1430 default 392 if ARCH_U8500 1431 default 352 if ARCH_VT8500 1432 default 288 if ARCH_ROCKCHIP 1433 default 264 if MACH_H4700 1434 default 0 1435 help 1436 Maximum number of GPIOs in the system. 1437 1438 If unsure, leave the default value. 1439 1440config HZ_FIXED 1441 int 1442 default 200 if ARCH_EBSA110 1443 default 128 if SOC_AT91RM9200 1444 default 0 1445 1446choice 1447 depends on HZ_FIXED = 0 1448 prompt "Timer frequency" 1449 1450config HZ_100 1451 bool "100 Hz" 1452 1453config HZ_200 1454 bool "200 Hz" 1455 1456config HZ_250 1457 bool "250 Hz" 1458 1459config HZ_300 1460 bool "300 Hz" 1461 1462config HZ_500 1463 bool "500 Hz" 1464 1465config HZ_1000 1466 bool "1000 Hz" 1467 1468endchoice 1469 1470config HZ 1471 int 1472 default HZ_FIXED if HZ_FIXED != 0 1473 default 100 if HZ_100 1474 default 200 if HZ_200 1475 default 250 if HZ_250 1476 default 300 if HZ_300 1477 default 500 if HZ_500 1478 default 1000 1479 1480config SCHED_HRTICK 1481 def_bool HIGH_RES_TIMERS 1482 1483config THUMB2_KERNEL 1484 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1485 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1486 default y if CPU_THUMBONLY 1487 select ARM_UNWIND 1488 help 1489 By enabling this option, the kernel will be compiled in 1490 Thumb-2 mode. 1491 1492 If unsure, say N. 1493 1494config THUMB2_AVOID_R_ARM_THM_JUMP11 1495 bool "Work around buggy Thumb-2 short branch relocations in gas" 1496 depends on THUMB2_KERNEL && MODULES 1497 default y 1498 help 1499 Various binutils versions can resolve Thumb-2 branches to 1500 locally-defined, preemptible global symbols as short-range "b.n" 1501 branch instructions. 1502 1503 This is a problem, because there's no guarantee the final 1504 destination of the symbol, or any candidate locations for a 1505 trampoline, are within range of the branch. For this reason, the 1506 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1507 relocation in modules at all, and it makes little sense to add 1508 support. 1509 1510 The symptom is that the kernel fails with an "unsupported 1511 relocation" error when loading some modules. 1512 1513 Until fixed tools are available, passing 1514 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1515 code which hits this problem, at the cost of a bit of extra runtime 1516 stack usage in some cases. 1517 1518 The problem is described in more detail at: 1519 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1520 1521 Only Thumb-2 kernels are affected. 1522 1523 Unless you are sure your tools don't have this problem, say Y. 1524 1525config ARM_PATCH_IDIV 1526 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1527 depends on CPU_32v7 && !XIP_KERNEL 1528 default y 1529 help 1530 The ARM compiler inserts calls to __aeabi_idiv() and 1531 __aeabi_uidiv() when it needs to perform division on signed 1532 and unsigned integers. Some v7 CPUs have support for the sdiv 1533 and udiv instructions that can be used to implement those 1534 functions. 1535 1536 Enabling this option allows the kernel to modify itself to 1537 replace the first two instructions of these library functions 1538 with the sdiv or udiv plus "bx lr" instructions when the CPU 1539 it is running on supports them. Typically this will be faster 1540 and less power intensive than running the original library 1541 code to do integer division. 1542 1543config AEABI 1544 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1545 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1546 help 1547 This option allows for the kernel to be compiled using the latest 1548 ARM ABI (aka EABI). This is only useful if you are using a user 1549 space environment that is also compiled with EABI. 1550 1551 Since there are major incompatibilities between the legacy ABI and 1552 EABI, especially with regard to structure member alignment, this 1553 option also changes the kernel syscall calling convention to 1554 disambiguate both ABIs and allow for backward compatibility support 1555 (selected with CONFIG_OABI_COMPAT). 1556 1557 To use this you need GCC version 4.0.0 or later. 1558 1559config OABI_COMPAT 1560 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1561 depends on AEABI && !THUMB2_KERNEL 1562 help 1563 This option preserves the old syscall interface along with the 1564 new (ARM EABI) one. It also provides a compatibility layer to 1565 intercept syscalls that have structure arguments which layout 1566 in memory differs between the legacy ABI and the new ARM EABI 1567 (only for non "thumb" binaries). This option adds a tiny 1568 overhead to all syscalls and produces a slightly larger kernel. 1569 1570 The seccomp filter system will not be available when this is 1571 selected, since there is no way yet to sensibly distinguish 1572 between calling conventions during filtering. 1573 1574 If you know you'll be using only pure EABI user space then you 1575 can say N here. If this option is not selected and you attempt 1576 to execute a legacy ABI binary then the result will be 1577 UNPREDICTABLE (in fact it can be predicted that it won't work 1578 at all). If in doubt say N. 1579 1580config ARCH_HAS_HOLES_MEMORYMODEL 1581 bool 1582 1583config ARCH_SPARSEMEM_ENABLE 1584 bool 1585 1586config ARCH_SPARSEMEM_DEFAULT 1587 def_bool ARCH_SPARSEMEM_ENABLE 1588 1589config ARCH_SELECT_MEMORY_MODEL 1590 def_bool ARCH_SPARSEMEM_ENABLE 1591 1592config HAVE_ARCH_PFN_VALID 1593 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1594 1595config HAVE_GENERIC_GUP 1596 def_bool y 1597 depends on ARM_LPAE 1598 1599config HIGHMEM 1600 bool "High Memory Support" 1601 depends on MMU 1602 help 1603 The address space of ARM processors is only 4 Gigabytes large 1604 and it has to accommodate user address space, kernel address 1605 space as well as some memory mapped IO. That means that, if you 1606 have a large amount of physical memory and/or IO, not all of the 1607 memory can be "permanently mapped" by the kernel. The physical 1608 memory that is not permanently mapped is called "high memory". 1609 1610 Depending on the selected kernel/user memory split, minimum 1611 vmalloc space and actual amount of RAM, you may not need this 1612 option which should result in a slightly faster kernel. 1613 1614 If unsure, say n. 1615 1616config HIGHPTE 1617 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1618 depends on HIGHMEM 1619 default y 1620 help 1621 The VM uses one page of physical memory for each page table. 1622 For systems with a lot of processes, this can use a lot of 1623 precious low memory, eventually leading to low memory being 1624 consumed by page tables. Setting this option will allow 1625 user-space 2nd level page tables to reside in high memory. 1626 1627config CPU_SW_DOMAIN_PAN 1628 bool "Enable use of CPU domains to implement privileged no-access" 1629 depends on MMU && !ARM_LPAE 1630 default y 1631 help 1632 Increase kernel security by ensuring that normal kernel accesses 1633 are unable to access userspace addresses. This can help prevent 1634 use-after-free bugs becoming an exploitable privilege escalation 1635 by ensuring that magic values (such as LIST_POISON) will always 1636 fault when dereferenced. 1637 1638 CPUs with low-vector mappings use a best-efforts implementation. 1639 Their lower 1MB needs to remain accessible for the vectors, but 1640 the remainder of userspace will become appropriately inaccessible. 1641 1642config HW_PERF_EVENTS 1643 def_bool y 1644 depends on ARM_PMU 1645 1646config SYS_SUPPORTS_HUGETLBFS 1647 def_bool y 1648 depends on ARM_LPAE 1649 1650config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1651 def_bool y 1652 depends on ARM_LPAE 1653 1654config ARCH_WANT_GENERAL_HUGETLB 1655 def_bool y 1656 1657config ARM_MODULE_PLTS 1658 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1659 depends on MODULES 1660 default y 1661 help 1662 Allocate PLTs when loading modules so that jumps and calls whose 1663 targets are too far away for their relative offsets to be encoded 1664 in the instructions themselves can be bounced via veneers in the 1665 module's PLT. This allows modules to be allocated in the generic 1666 vmalloc area after the dedicated module memory area has been 1667 exhausted. The modules will use slightly more memory, but after 1668 rounding up to page size, the actual memory footprint is usually 1669 the same. 1670 1671 Disabling this is usually safe for small single-platform 1672 configurations. If unsure, say y. 1673 1674config FORCE_MAX_ZONEORDER 1675 int "Maximum zone order" 1676 default "12" if SOC_AM33XX 1677 default "9" if SA1111 || ARCH_EFM32 1678 default "11" 1679 help 1680 The kernel memory allocator divides physically contiguous memory 1681 blocks into "zones", where each zone is a power of two number of 1682 pages. This option selects the largest power of two that the kernel 1683 keeps in the memory allocator. If you need to allocate very large 1684 blocks of physically contiguous memory, then you may need to 1685 increase this value. 1686 1687 This config option is actually maximum order plus one. For example, 1688 a value of 11 means that the largest free memory block is 2^10 pages. 1689 1690config ALIGNMENT_TRAP 1691 bool 1692 depends on CPU_CP15_MMU 1693 default y if !ARCH_EBSA110 1694 select HAVE_PROC_CPU if PROC_FS 1695 help 1696 ARM processors cannot fetch/store information which is not 1697 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1698 address divisible by 4. On 32-bit ARM processors, these non-aligned 1699 fetch/store instructions will be emulated in software if you say 1700 here, which has a severe performance impact. This is necessary for 1701 correct operation of some network protocols. With an IP-only 1702 configuration it is safe to say N, otherwise say Y. 1703 1704config UACCESS_WITH_MEMCPY 1705 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1706 depends on MMU 1707 default y if CPU_FEROCEON 1708 help 1709 Implement faster copy_to_user and clear_user methods for CPU 1710 cores where a 8-word STM instruction give significantly higher 1711 memory write throughput than a sequence of individual 32bit stores. 1712 1713 A possible side effect is a slight increase in scheduling latency 1714 between threads sharing the same address space if they invoke 1715 such copy operations with large buffers. 1716 1717 However, if the CPU data cache is using a write-allocate mode, 1718 this option is unlikely to provide any performance gain. 1719 1720config SECCOMP 1721 bool 1722 prompt "Enable seccomp to safely compute untrusted bytecode" 1723 ---help--- 1724 This kernel feature is useful for number crunching applications 1725 that may need to compute untrusted bytecode during their 1726 execution. By using pipes or other transports made available to 1727 the process as file descriptors supporting the read/write 1728 syscalls, it's possible to isolate those applications in 1729 their own address space using seccomp. Once seccomp is 1730 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1731 and the task is only allowed to execute a few safe syscalls 1732 defined by each seccomp mode. 1733 1734config PARAVIRT 1735 bool "Enable paravirtualization code" 1736 help 1737 This changes the kernel so it can modify itself when it is run 1738 under a hypervisor, potentially improving performance significantly 1739 over full virtualization. 1740 1741config PARAVIRT_TIME_ACCOUNTING 1742 bool "Paravirtual steal time accounting" 1743 select PARAVIRT 1744 help 1745 Select this option to enable fine granularity task steal time 1746 accounting. Time spent executing other tasks in parallel with 1747 the current vCPU is discounted from the vCPU power. To account for 1748 that, there can be a small performance impact. 1749 1750 If in doubt, say N here. 1751 1752config XEN_DOM0 1753 def_bool y 1754 depends on XEN 1755 1756config XEN 1757 bool "Xen guest support on ARM" 1758 depends on ARM && AEABI && OF 1759 depends on CPU_V7 && !CPU_V6 1760 depends on !GENERIC_ATOMIC64 1761 depends on MMU 1762 select ARCH_DMA_ADDR_T_64BIT 1763 select ARM_PSCI 1764 select SWIOTLB 1765 select SWIOTLB_XEN 1766 select PARAVIRT 1767 help 1768 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1769 1770config STACKPROTECTOR_PER_TASK 1771 bool "Use a unique stack canary value for each task" 1772 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1773 select GCC_PLUGIN_ARM_SSP_PER_TASK 1774 default y 1775 help 1776 Due to the fact that GCC uses an ordinary symbol reference from 1777 which to load the value of the stack canary, this value can only 1778 change at reboot time on SMP systems, and all tasks running in the 1779 kernel's address space are forced to use the same canary value for 1780 the entire duration that the system is up. 1781 1782 Enable this option to switch to a different method that uses a 1783 different canary value for each task. 1784 1785endmenu 1786 1787menu "Boot options" 1788 1789config USE_OF 1790 bool "Flattened Device Tree support" 1791 select IRQ_DOMAIN 1792 select OF 1793 help 1794 Include support for flattened device tree machine descriptions. 1795 1796config ATAGS 1797 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1798 default y 1799 help 1800 This is the traditional way of passing data to the kernel at boot 1801 time. If you are solely relying on the flattened device tree (or 1802 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1803 to remove ATAGS support from your kernel binary. If unsure, 1804 leave this to y. 1805 1806config DEPRECATED_PARAM_STRUCT 1807 bool "Provide old way to pass kernel parameters" 1808 depends on ATAGS 1809 help 1810 This was deprecated in 2001 and announced to live on for 5 years. 1811 Some old boot loaders still use this way. 1812 1813# Compressed boot loader in ROM. Yes, we really want to ask about 1814# TEXT and BSS so we preserve their values in the config files. 1815config ZBOOT_ROM_TEXT 1816 hex "Compressed ROM boot loader base address" 1817 default "0" 1818 help 1819 The physical address at which the ROM-able zImage is to be 1820 placed in the target. Platforms which normally make use of 1821 ROM-able zImage formats normally set this to a suitable 1822 value in their defconfig file. 1823 1824 If ZBOOT_ROM is not enabled, this has no effect. 1825 1826config ZBOOT_ROM_BSS 1827 hex "Compressed ROM boot loader BSS address" 1828 default "0" 1829 help 1830 The base address of an area of read/write memory in the target 1831 for the ROM-able zImage which must be available while the 1832 decompressor is running. It must be large enough to hold the 1833 entire decompressed kernel plus an additional 128 KiB. 1834 Platforms which normally make use of ROM-able zImage formats 1835 normally set this to a suitable value in their defconfig file. 1836 1837 If ZBOOT_ROM is not enabled, this has no effect. 1838 1839config ZBOOT_ROM 1840 bool "Compressed boot loader in ROM/flash" 1841 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1842 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1843 help 1844 Say Y here if you intend to execute your compressed kernel image 1845 (zImage) directly from ROM or flash. If unsure, say N. 1846 1847config ARM_APPENDED_DTB 1848 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1849 depends on OF 1850 help 1851 With this option, the boot code will look for a device tree binary 1852 (DTB) appended to zImage 1853 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1854 1855 This is meant as a backward compatibility convenience for those 1856 systems with a bootloader that can't be upgraded to accommodate 1857 the documented boot protocol using a device tree. 1858 1859 Beware that there is very little in terms of protection against 1860 this option being confused by leftover garbage in memory that might 1861 look like a DTB header after a reboot if no actual DTB is appended 1862 to zImage. Do not leave this option active in a production kernel 1863 if you don't intend to always append a DTB. Proper passing of the 1864 location into r2 of a bootloader provided DTB is always preferable 1865 to this option. 1866 1867config ARM_ATAG_DTB_COMPAT 1868 bool "Supplement the appended DTB with traditional ATAG information" 1869 depends on ARM_APPENDED_DTB 1870 help 1871 Some old bootloaders can't be updated to a DTB capable one, yet 1872 they provide ATAGs with memory configuration, the ramdisk address, 1873 the kernel cmdline string, etc. Such information is dynamically 1874 provided by the bootloader and can't always be stored in a static 1875 DTB. To allow a device tree enabled kernel to be used with such 1876 bootloaders, this option allows zImage to extract the information 1877 from the ATAG list and store it at run time into the appended DTB. 1878 1879choice 1880 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1881 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1882 1883config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1884 bool "Use bootloader kernel arguments if available" 1885 help 1886 Uses the command-line options passed by the boot loader instead of 1887 the device tree bootargs property. If the boot loader doesn't provide 1888 any, the device tree bootargs property will be used. 1889 1890config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1891 bool "Extend with bootloader kernel arguments" 1892 help 1893 The command-line arguments provided by the boot loader will be 1894 appended to the the device tree bootargs property. 1895 1896endchoice 1897 1898config CMDLINE 1899 string "Default kernel command string" 1900 default "" 1901 help 1902 On some architectures (EBSA110 and CATS), there is currently no way 1903 for the boot loader to pass arguments to the kernel. For these 1904 architectures, you should supply some command-line options at build 1905 time by entering them here. As a minimum, you should specify the 1906 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1907 1908choice 1909 prompt "Kernel command line type" if CMDLINE != "" 1910 default CMDLINE_FROM_BOOTLOADER 1911 depends on ATAGS 1912 1913config CMDLINE_FROM_BOOTLOADER 1914 bool "Use bootloader kernel arguments if available" 1915 help 1916 Uses the command-line options passed by the boot loader. If 1917 the boot loader doesn't provide any, the default kernel command 1918 string provided in CMDLINE will be used. 1919 1920config CMDLINE_EXTEND 1921 bool "Extend bootloader kernel arguments" 1922 help 1923 The command-line arguments provided by the boot loader will be 1924 appended to the default kernel command string. 1925 1926config CMDLINE_FORCE 1927 bool "Always use the default kernel command string" 1928 help 1929 Always use the default kernel command string, even if the boot 1930 loader passes other arguments to the kernel. 1931 This is useful if you cannot or don't want to change the 1932 command-line options your boot loader passes to the kernel. 1933endchoice 1934 1935config XIP_KERNEL 1936 bool "Kernel Execute-In-Place from ROM" 1937 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1938 help 1939 Execute-In-Place allows the kernel to run from non-volatile storage 1940 directly addressable by the CPU, such as NOR flash. This saves RAM 1941 space since the text section of the kernel is not loaded from flash 1942 to RAM. Read-write sections, such as the data section and stack, 1943 are still copied to RAM. The XIP kernel is not compressed since 1944 it has to run directly from flash, so it will take more space to 1945 store it. The flash address used to link the kernel object files, 1946 and for storing it, is configuration dependent. Therefore, if you 1947 say Y here, you must know the proper physical address where to 1948 store the kernel image depending on your own flash memory usage. 1949 1950 Also note that the make target becomes "make xipImage" rather than 1951 "make zImage" or "make Image". The final kernel binary to put in 1952 ROM memory will be arch/arm/boot/xipImage. 1953 1954 If unsure, say N. 1955 1956config XIP_PHYS_ADDR 1957 hex "XIP Kernel Physical Location" 1958 depends on XIP_KERNEL 1959 default "0x00080000" 1960 help 1961 This is the physical address in your flash memory the kernel will 1962 be linked for and stored to. This address is dependent on your 1963 own flash usage. 1964 1965config XIP_DEFLATED_DATA 1966 bool "Store kernel .data section compressed in ROM" 1967 depends on XIP_KERNEL 1968 select ZLIB_INFLATE 1969 help 1970 Before the kernel is actually executed, its .data section has to be 1971 copied to RAM from ROM. This option allows for storing that data 1972 in compressed form and decompressed to RAM rather than merely being 1973 copied, saving some precious ROM space. A possible drawback is a 1974 slightly longer boot delay. 1975 1976config KEXEC 1977 bool "Kexec system call (EXPERIMENTAL)" 1978 depends on (!SMP || PM_SLEEP_SMP) 1979 depends on !CPU_V7M 1980 select KEXEC_CORE 1981 help 1982 kexec is a system call that implements the ability to shutdown your 1983 current kernel, and to start another kernel. It is like a reboot 1984 but it is independent of the system firmware. And like a reboot 1985 you can start any kernel with it, not just Linux. 1986 1987 It is an ongoing process to be certain the hardware in a machine 1988 is properly shutdown, so do not be surprised if this code does not 1989 initially work for you. 1990 1991config ATAGS_PROC 1992 bool "Export atags in procfs" 1993 depends on ATAGS && KEXEC 1994 default y 1995 help 1996 Should the atags used to boot the kernel be exported in an "atags" 1997 file in procfs. Useful with kexec. 1998 1999config CRASH_DUMP 2000 bool "Build kdump crash kernel (EXPERIMENTAL)" 2001 help 2002 Generate crash dump after being started by kexec. This should 2003 be normally only set in special crash dump kernels which are 2004 loaded in the main kernel with kexec-tools into a specially 2005 reserved region and then later executed after a crash by 2006 kdump/kexec. The crash dump kernel must be compiled to a 2007 memory address not used by the main kernel 2008 2009 For more details see Documentation/kdump/kdump.txt 2010 2011config AUTO_ZRELADDR 2012 bool "Auto calculation of the decompressed kernel image address" 2013 help 2014 ZRELADDR is the physical address where the decompressed kernel 2015 image will be placed. If AUTO_ZRELADDR is selected, the address 2016 will be determined at run-time by masking the current IP with 2017 0xf8000000. This assumes the zImage being placed in the first 128MB 2018 from start of memory. 2019 2020config EFI_STUB 2021 bool 2022 2023config EFI 2024 bool "UEFI runtime support" 2025 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2026 select UCS2_STRING 2027 select EFI_PARAMS_FROM_FDT 2028 select EFI_STUB 2029 select EFI_ARMSTUB 2030 select EFI_RUNTIME_WRAPPERS 2031 ---help--- 2032 This option provides support for runtime services provided 2033 by UEFI firmware (such as non-volatile variables, realtime 2034 clock, and platform reset). A UEFI stub is also provided to 2035 allow the kernel to be booted as an EFI application. This 2036 is only useful for kernels that may run on systems that have 2037 UEFI firmware. 2038 2039config DMI 2040 bool "Enable support for SMBIOS (DMI) tables" 2041 depends on EFI 2042 default y 2043 help 2044 This enables SMBIOS/DMI feature for systems. 2045 2046 This option is only useful on systems that have UEFI firmware. 2047 However, even with this option, the resultant kernel should 2048 continue to boot on existing non-UEFI platforms. 2049 2050 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2051 i.e., the the practice of identifying the platform via DMI to 2052 decide whether certain workarounds for buggy hardware and/or 2053 firmware need to be enabled. This would require the DMI subsystem 2054 to be enabled much earlier than we do on ARM, which is non-trivial. 2055 2056endmenu 2057 2058menu "CPU Power Management" 2059 2060source "drivers/cpufreq/Kconfig" 2061 2062source "drivers/cpuidle/Kconfig" 2063 2064endmenu 2065 2066menu "Floating point emulation" 2067 2068comment "At least one emulation must be selected" 2069 2070config FPE_NWFPE 2071 bool "NWFPE math emulation" 2072 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2073 ---help--- 2074 Say Y to include the NWFPE floating point emulator in the kernel. 2075 This is necessary to run most binaries. Linux does not currently 2076 support floating point hardware so you need to say Y here even if 2077 your machine has an FPA or floating point co-processor podule. 2078 2079 You may say N here if you are going to load the Acorn FPEmulator 2080 early in the bootup. 2081 2082config FPE_NWFPE_XP 2083 bool "Support extended precision" 2084 depends on FPE_NWFPE 2085 help 2086 Say Y to include 80-bit support in the kernel floating-point 2087 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2088 Note that gcc does not generate 80-bit operations by default, 2089 so in most cases this option only enlarges the size of the 2090 floating point emulator without any good reason. 2091 2092 You almost surely want to say N here. 2093 2094config FPE_FASTFPE 2095 bool "FastFPE math emulation (EXPERIMENTAL)" 2096 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2097 ---help--- 2098 Say Y here to include the FAST floating point emulator in the kernel. 2099 This is an experimental much faster emulator which now also has full 2100 precision for the mantissa. It does not support any exceptions. 2101 It is very simple, and approximately 3-6 times faster than NWFPE. 2102 2103 It should be sufficient for most programs. It may be not suitable 2104 for scientific calculations, but you have to check this for yourself. 2105 If you do not feel you need a faster FP emulation you should better 2106 choose NWFPE. 2107 2108config VFP 2109 bool "VFP-format floating point maths" 2110 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2111 help 2112 Say Y to include VFP support code in the kernel. This is needed 2113 if your hardware includes a VFP unit. 2114 2115 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2116 release notes and additional status information. 2117 2118 Say N if your target does not have VFP hardware. 2119 2120config VFPv3 2121 bool 2122 depends on VFP 2123 default y if CPU_V7 2124 2125config NEON 2126 bool "Advanced SIMD (NEON) Extension support" 2127 depends on VFPv3 && CPU_V7 2128 help 2129 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2130 Extension. 2131 2132config KERNEL_MODE_NEON 2133 bool "Support for NEON in kernel mode" 2134 depends on NEON && AEABI 2135 help 2136 Say Y to include support for NEON in kernel mode. 2137 2138endmenu 2139 2140menu "Power management options" 2141 2142source "kernel/power/Kconfig" 2143 2144config ARCH_SUSPEND_POSSIBLE 2145 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2146 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2147 def_bool y 2148 2149config ARM_CPU_SUSPEND 2150 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2151 depends on ARCH_SUSPEND_POSSIBLE 2152 2153config ARCH_HIBERNATION_POSSIBLE 2154 bool 2155 depends on MMU 2156 default y if ARCH_SUSPEND_POSSIBLE 2157 2158endmenu 2159 2160source "drivers/firmware/Kconfig" 2161 2162if CRYPTO 2163source "arch/arm/crypto/Kconfig" 2164endif 2165 2166source "arch/arm/kvm/Kconfig" 2167