1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CC_CAN_LINK 10 select ARCH_HAS_CPU_CACHE_ALIASING 11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_HAS_DEBUG_VIRTUAL if MMU 14 select ARCH_HAS_DMA_ALLOC if MMU 15 select ARCH_HAS_DMA_OPS 16 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 17 select ARCH_HAS_ELF_RANDOMIZE 18 select ARCH_HAS_FORTIFY_SOURCE 19 select ARCH_HAS_KEEPINITRD 20 select ARCH_HAS_KCOV 21 select ARCH_HAS_MEMBARRIER_SYNC_CORE 22 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 23 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 24 select ARCH_HAS_SETUP_DMA_OPS 25 select ARCH_HAS_SET_MEMORY 26 select ARCH_STACKWALK 27 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 28 select ARCH_HAS_STRICT_MODULE_RWX if MMU 29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 30 select ARCH_HAS_SYNC_DMA_FOR_CPU 31 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 33 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_KEEP_MEMBLOCK 36 select ARCH_HAS_UBSAN 37 select ARCH_MIGHT_HAVE_PC_PARPORT 38 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 39 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 40 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 41 select ARCH_SUPPORTS_ATOMIC_RMW 42 select ARCH_SUPPORTS_CFI 43 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 44 select ARCH_SUPPORTS_PER_VMA_LOCK 45 select ARCH_SUPPORTS_RT 46 select ARCH_USE_BUILTIN_BSWAP 47 select ARCH_USE_CMPXCHG_LOCKREF 48 select ARCH_USE_MEMTEST 49 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 50 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 51 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 52 select ARCH_WANT_GENERAL_HUGETLB 53 select ARCH_WANT_IPC_PARSE_VERSION 54 select ARCH_WANT_LD_ORPHAN_WARN 55 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 56 select BUILDTIME_TABLE_SORT if MMU 57 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 58 select CLONE_BACKWARDS 59 select CPU_PM if SUSPEND || CPU_IDLE 60 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 61 select DMA_DECLARE_COHERENT 62 select DMA_GLOBAL_POOL if !MMU 63 select DMA_NONCOHERENT_MMAP if MMU 64 select EDAC_SUPPORT 65 select EDAC_ATOMIC_SCRUB 66 select GENERIC_ALLOCATOR 67 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 68 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 69 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 70 select GENERIC_IRQ_IPI if SMP 71 select GENERIC_CPU_AUTOPROBE 72 select GENERIC_CPU_DEVICES 73 select GENERIC_EARLY_IOREMAP 74 select GENERIC_IDLE_POLL_SETUP 75 select GENERIC_IRQ_MULTI_HANDLER 76 select GENERIC_IRQ_PROBE 77 select GENERIC_IRQ_SHOW 78 select GENERIC_IRQ_SHOW_LEVEL 79 select GENERIC_LIB_DEVMEM_IS_ALLOWED 80 select GENERIC_PCI_IOMAP 81 select GENERIC_SCHED_CLOCK 82 select GENERIC_SMP_IDLE_THREAD 83 select HARDIRQS_SW_RESEND 84 select HAS_IOPORT 85 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 86 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 && BITREVERSE 87 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP) 88 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 89 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 90 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 91 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 92 select HAVE_ARCH_KSTACK_ERASE 93 select HAVE_ARCH_MMAP_RND_BITS if MMU 94 select HAVE_ARCH_PFN_VALID 95 select HAVE_ARCH_SECCOMP 96 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 97 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 98 select HAVE_ARCH_TRACEHOOK 99 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 100 select HAVE_ARM_SMCCC if CPU_V7 101 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 102 select HAVE_CONTEXT_TRACKING_USER 103 select HAVE_C_RECORDMCOUNT 104 select HAVE_BUILDTIME_MCOUNT_SORT 105 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 106 select HAVE_DMA_CONTIGUOUS if MMU 107 select HAVE_EXTRA_IPI_TRACEPOINTS 108 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 109 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 110 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 111 select HAVE_EXIT_THREAD 112 select HAVE_GUP_FAST if ARM_LPAE 113 select HAVE_FUNCTION_ERROR_INJECTION 114 select HAVE_FUNCTION_GRAPH_TRACER 115 select HAVE_FUNCTION_GRAPH_FREGS 116 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 117 select HAVE_GCC_PLUGINS 118 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 119 select HAVE_IRQ_TIME_ACCOUNTING 120 select HAVE_KERNEL_GZIP 121 select HAVE_KERNEL_LZ4 122 select HAVE_KERNEL_LZMA 123 select HAVE_KERNEL_LZO 124 select HAVE_KERNEL_XZ 125 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 126 select HAVE_KRETPROBES if HAVE_KPROBES 127 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 128 select HAVE_MOD_ARCH_SPECIFIC 129 select HAVE_NMI 130 select HAVE_OPTPROBES if !THUMB2_KERNEL 131 select HAVE_PAGE_SIZE_4KB 132 select HAVE_PCI if MMU 133 select HAVE_PERF_EVENTS 134 select HAVE_PERF_REGS 135 select HAVE_PERF_USER_STACK_DUMP 136 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 137 select HAVE_REGS_AND_STACK_ACCESS_API 138 select HAVE_RSEQ 139 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN 140 select HAVE_STACKPROTECTOR 141 select HAVE_SYSCALL_TRACEPOINTS 142 select HAVE_UID16 143 select HAVE_VIRT_CPU_ACCOUNTING_GEN 144 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 145 select IRQ_FORCED_THREADING 146 select LOCK_MM_AND_FIND_VMA 147 select MODULES_USE_ELF_REL 148 select NEED_DMA_MAP_STATE 149 select OF_EARLY_FLATTREE if OF 150 select OLD_SIGACTION 151 select OLD_SIGSUSPEND3 152 select PCI_DOMAINS_GENERIC if PCI 153 select PCI_SYSCALL if PCI 154 select PERF_USE_VMALLOC 155 select RTC_LIB 156 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 157 select SYS_SUPPORTS_APM_EMULATION 158 select THREAD_INFO_IN_TASK 159 select TIMER_OF if OF 160 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 161 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 162 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 163 # Above selects are sorted alphabetically; please add new ones 164 # according to that. Thanks. 165 help 166 The ARM series is a line of low-power-consumption RISC chip designs 167 licensed by ARM Ltd and targeted at embedded applications and 168 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 169 manufactured, but legacy ARM-based PC hardware remains popular in 170 Europe. There is an ARM Linux project with a web page at 171 <http://www.arm.linux.org.uk/>. 172 173config ARM_HAS_GROUP_RELOCS 174 def_bool !COMPILE_TEST 175 help 176 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 177 relocations. The combined range is -/+ 256 MiB, which is usually 178 sufficient, but not for allyesconfig, so we disable this feature 179 when doing compile testing. 180 181config ARM_DMA_USE_IOMMU 182 bool 183 select NEED_SG_DMA_LENGTH 184 185if ARM_DMA_USE_IOMMU 186 187config ARM_DMA_IOMMU_ALIGNMENT 188 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 189 range 4 9 190 default 8 191 help 192 DMA mapping framework by default aligns all buffers to the smallest 193 PAGE_SIZE order which is greater than or equal to the requested buffer 194 size. This works well for buffers up to a few hundreds kilobytes, but 195 for larger buffers it just a waste of address space. Drivers which has 196 relatively small addressing window (like 64Mib) might run out of 197 virtual space with just a few allocations. 198 199 With this parameter you can specify the maximum PAGE_SIZE order for 200 DMA IOMMU buffers. Larger buffers will be aligned only to this 201 specified order. The order is expressed as a power of two multiplied 202 by the PAGE_SIZE. 203 204endif 205 206config SYS_SUPPORTS_APM_EMULATION 207 bool 208 209config HAVE_TCM 210 bool 211 select GENERIC_ALLOCATOR 212 213config HAVE_PROC_CPU 214 bool 215 216config NO_IOPORT_MAP 217 bool 218 219config SBUS 220 bool 221 222config STACKTRACE_SUPPORT 223 bool 224 default y 225 226config LOCKDEP_SUPPORT 227 bool 228 default y 229 230config ARCH_HAS_ILOG2_U32 231 bool 232 233config ARCH_HAS_ILOG2_U64 234 bool 235 236config ARCH_HAS_BANDGAP 237 bool 238 239config FIX_EARLYCON_MEM 240 def_bool y if MMU 241 242config GENERIC_HWEIGHT 243 bool 244 default y 245 246config GENERIC_CALIBRATE_DELAY 247 bool 248 default y 249 250config ARCH_MAY_HAVE_PC_FDC 251 bool 252 253config ARCH_SUPPORTS_UPROBES 254 def_bool y 255 256config GENERIC_ISA_DMA 257 bool 258 259config FIQ 260 bool 261 262config ARCH_MTD_XIP 263 bool 264 265config ARM_PATCH_PHYS_VIRT 266 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 267 default y 268 depends on MMU 269 help 270 Patch phys-to-virt and virt-to-phys translation functions at 271 boot and module load time according to the position of the 272 kernel in system memory. 273 274 This can only be used with non-XIP MMU kernels where the base 275 of physical memory is at a 2 MiB boundary. 276 277 Only disable this option if you know that you do not require 278 this feature (eg, building a kernel for a single machine) and 279 you need to shrink the kernel to the minimal size. 280 281config NEED_MACH_IO_H 282 bool 283 help 284 Select this when mach/io.h is required to provide special 285 definitions for this platform. The need for mach/io.h should 286 be avoided when possible. 287 288config NEED_MACH_MEMORY_H 289 bool 290 help 291 Select this when mach/memory.h is required to provide special 292 definitions for this platform. The need for mach/memory.h should 293 be avoided when possible. 294 295config PHYS_OFFSET 296 hex "Physical address of main memory" if MMU 297 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 298 default DRAM_BASE if !MMU 299 default 0x00000000 if ARCH_FOOTBRIDGE 300 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 301 default 0xa0000000 if ARCH_PXA 302 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 303 default 0 304 help 305 Please provide the physical address corresponding to the 306 location of main memory in your system. 307 308config GENERIC_BUG 309 def_bool y 310 depends on BUG 311 312config PGTABLE_LEVELS 313 int 314 default 3 if ARM_LPAE 315 default 2 316 317menu "System Type" 318 319config MMU 320 bool "MMU-based Paged Memory Management Support" 321 default y 322 help 323 Select if you want MMU-based virtualised addressing space 324 support by paged memory management. If unsure, say 'Y'. 325 326config ARM_SINGLE_ARMV7M 327 def_bool !MMU 328 select ARM_NVIC 329 select CPU_V7M 330 select NO_IOPORT_MAP 331 332config ARCH_MMAP_RND_BITS_MIN 333 default 8 334 335config ARCH_MMAP_RND_BITS_MAX 336 default 14 if PAGE_OFFSET=0x40000000 337 default 15 if PAGE_OFFSET=0x80000000 338 default 16 339 340config ARCH_MULTIPLATFORM 341 bool "Require kernel to be portable to multiple machines" if EXPERT 342 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 343 default y 344 help 345 In general, all Arm machines can be supported in a single 346 kernel image, covering either Armv4/v5 or Armv6/v7. 347 348 However, some configuration options require hardcoding machine 349 specific physical addresses or enable errata workarounds that may 350 break other machines. 351 352 Selecting N here allows using those options, including 353 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 354 355source "arch/arm/Kconfig.platforms" 356 357# 358# This is sorted alphabetically by mach-* pathname. However, plat-* 359# Kconfigs may be included either alphabetically (according to the 360# plat- suffix) or along side the corresponding mach-* source. 361# 362source "arch/arm/mach-actions/Kconfig" 363 364source "arch/arm/mach-alpine/Kconfig" 365 366source "arch/arm/mach-artpec/Kconfig" 367 368source "arch/arm/mach-aspeed/Kconfig" 369 370source "arch/arm/mach-at91/Kconfig" 371 372source "arch/arm/mach-axxia/Kconfig" 373 374source "arch/arm/mach-bcm/Kconfig" 375 376source "arch/arm/mach-berlin/Kconfig" 377 378source "arch/arm/mach-clps711x/Kconfig" 379 380source "arch/arm/mach-davinci/Kconfig" 381 382source "arch/arm/mach-digicolor/Kconfig" 383 384source "arch/arm/mach-dove/Kconfig" 385 386source "arch/arm/mach-ep93xx/Kconfig" 387 388source "arch/arm/mach-exynos/Kconfig" 389 390source "arch/arm/mach-footbridge/Kconfig" 391 392source "arch/arm/mach-gemini/Kconfig" 393 394source "arch/arm/mach-highbank/Kconfig" 395 396source "arch/arm/mach-hisi/Kconfig" 397 398source "arch/arm/mach-imx/Kconfig" 399 400source "arch/arm/mach-ixp4xx/Kconfig" 401 402source "arch/arm/mach-keystone/Kconfig" 403 404source "arch/arm/mach-lpc32xx/Kconfig" 405 406source "arch/arm/mach-mediatek/Kconfig" 407 408source "arch/arm/mach-meson/Kconfig" 409 410source "arch/arm/mach-milbeaut/Kconfig" 411 412source "arch/arm/mach-mmp/Kconfig" 413 414source "arch/arm/mach-mstar/Kconfig" 415 416source "arch/arm/mach-mv78xx0/Kconfig" 417 418source "arch/arm/mach-mvebu/Kconfig" 419 420source "arch/arm/mach-mxs/Kconfig" 421 422source "arch/arm/mach-nomadik/Kconfig" 423 424source "arch/arm/mach-npcm/Kconfig" 425 426source "arch/arm/mach-omap1/Kconfig" 427 428source "arch/arm/mach-omap2/Kconfig" 429 430source "arch/arm/mach-orion5x/Kconfig" 431 432source "arch/arm/mach-pxa/Kconfig" 433 434source "arch/arm/mach-qcom/Kconfig" 435 436source "arch/arm/mach-realtek/Kconfig" 437 438source "arch/arm/mach-rpc/Kconfig" 439 440source "arch/arm/mach-rockchip/Kconfig" 441 442source "arch/arm/mach-s3c/Kconfig" 443 444source "arch/arm/mach-s5pv210/Kconfig" 445 446source "arch/arm/mach-sa1100/Kconfig" 447 448source "arch/arm/mach-shmobile/Kconfig" 449 450source "arch/arm/mach-socfpga/Kconfig" 451 452source "arch/arm/mach-spear/Kconfig" 453 454source "arch/arm/mach-sti/Kconfig" 455 456source "arch/arm/mach-stm32/Kconfig" 457 458source "arch/arm/mach-sunxi/Kconfig" 459 460source "arch/arm/mach-tegra/Kconfig" 461 462source "arch/arm/mach-ux500/Kconfig" 463 464source "arch/arm/mach-versatile/Kconfig" 465 466source "arch/arm/mach-vt8500/Kconfig" 467 468source "arch/arm/mach-zte/Kconfig" 469 470source "arch/arm/mach-zynq/Kconfig" 471 472# ARMv7-M architecture 473config ARCH_LPC18XX 474 bool "NXP LPC18xx/LPC43xx (DEPRECATED)" 475 depends on ARM_SINGLE_ARMV7M 476 select ARCH_HAS_RESET_CONTROLLER 477 select ARM_AMBA 478 select CLKSRC_LPC32XX 479 select PINCTRL 480 help 481 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 482 high performance microcontrollers. 483 484 This platform is scheduled for removal in early 2027 485 486config ARCH_MPS2 487 bool "ARM MPS2 platform (DEPRECATED)" 488 depends on ARM_SINGLE_ARMV7M 489 select ARM_AMBA 490 select CLKSRC_MPS2 491 help 492 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 493 with a range of available cores like Cortex-M3/M4/M7. 494 495 Please, note that depends which Application Note is used memory map 496 for the platform may vary, so adjustment of RAM base might be needed. 497 498 This platform is scheduled for removal in early 2027 499 500# Definitions to make life easier 501config ARCH_ACORN 502 bool 503 504config PLAT_ORION 505 bool 506 select CLKSRC_MMIO 507 select GENERIC_IRQ_CHIP 508 select IRQ_DOMAIN 509 510config PLAT_ORION_LEGACY 511 bool 512 select PLAT_ORION 513 514config PLAT_VERSATILE 515 bool 516 517source "arch/arm/mm/Kconfig" 518 519config IWMMXT 520 bool "Enable iWMMXt support (DEPRECATED)" 521 depends on PXA27x || PXA3xx || ARCH_MMP 522 help 523 Enable support for iWMMXt context switching at run time if 524 running on a CPU that supports it. 525 526 Machines that actually support this feature are very rare, 527 and support is deprecated in new gcc-14. While there were a 528 few applications that used this in the past, none are known 529 to still do so. 530 531 If you use this, please send a patch to remove the 532 deprecation, otherwise this will be removed in early 533 2027. 534 535if !MMU 536source "arch/arm/Kconfig-nommu" 537endif 538 539config PJ4B_ERRATA_4742 540 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 541 depends on CPU_PJ4B && MACH_ARMADA_370 542 default y 543 help 544 When coming out of either a Wait for Interrupt (WFI) or a Wait for 545 Event (WFE) IDLE states, a specific timing sensitivity exists between 546 the retiring WFI/WFE instructions and the newly issued subsequent 547 instructions. This sensitivity can result in a CPU hang scenario. 548 Workaround: 549 The software must insert either a Data Synchronization Barrier (DSB) 550 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 551 instruction 552 553config ARM_ERRATA_326103 554 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 555 depends on CPU_V6 556 help 557 Executing a SWP instruction to read-only memory does not set bit 11 558 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 559 treat the access as a read, preventing a COW from occurring and 560 causing the faulting task to livelock. 561 562config ARM_ERRATA_411920 563 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 564 depends on CPU_V6 || CPU_V6K 565 help 566 Invalidation of the Instruction Cache operation can 567 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 568 It does not affect the MPCore. This option enables the ARM Ltd. 569 recommended workaround. 570 571config ARM_ERRATA_430973 572 bool "ARM errata: Stale prediction on replaced interworking branch" 573 depends on CPU_V7 574 help 575 This option enables the workaround for the 430973 Cortex-A8 576 r1p* erratum. If a code sequence containing an ARM/Thumb 577 interworking branch is replaced with another code sequence at the 578 same virtual address, whether due to self-modifying code or virtual 579 to physical address re-mapping, Cortex-A8 does not recover from the 580 stale interworking branch prediction. This results in Cortex-A8 581 executing the new code sequence in the incorrect ARM or Thumb state. 582 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 583 and also flushes the branch target cache at every context switch. 584 Note that setting specific bits in the ACTLR register may not be 585 available in non-secure mode. 586 587config ARM_ERRATA_458693 588 bool "ARM errata: Processor deadlock when a false hazard is created" 589 depends on CPU_V7 590 depends on !ARCH_MULTIPLATFORM 591 help 592 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 593 erratum. For very specific sequences of memory operations, it is 594 possible for a hazard condition intended for a cache line to instead 595 be incorrectly associated with a different cache line. This false 596 hazard might then cause a processor deadlock. The workaround enables 597 the L1 caching of the NEON accesses and disables the PLD instruction 598 in the ACTLR register. Note that setting specific bits in the ACTLR 599 register may not be available in non-secure mode and thus is not 600 available on a multiplatform kernel. This should be applied by the 601 bootloader instead. 602 603config ARM_ERRATA_460075 604 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 605 depends on CPU_V7 606 depends on !ARCH_MULTIPLATFORM 607 help 608 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 609 erratum. Any asynchronous access to the L2 cache may encounter a 610 situation in which recent store transactions to the L2 cache are lost 611 and overwritten with stale memory contents from external memory. The 612 workaround disables the write-allocate mode for the L2 cache via the 613 ACTLR register. Note that setting specific bits in the ACTLR register 614 may not be available in non-secure mode and thus is not available on 615 a multiplatform kernel. This should be applied by the bootloader 616 instead. 617 618config ARM_ERRATA_742230 619 bool "ARM errata: DMB operation may be faulty" 620 depends on CPU_V7 && SMP 621 depends on !ARCH_MULTIPLATFORM 622 help 623 This option enables the workaround for the 742230 Cortex-A9 624 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 625 between two write operations may not ensure the correct visibility 626 ordering of the two writes. This workaround sets a specific bit in 627 the diagnostic register of the Cortex-A9 which causes the DMB 628 instruction to behave as a DSB, ensuring the correct behaviour of 629 the two writes. Note that setting specific bits in the diagnostics 630 register may not be available in non-secure mode and thus is not 631 available on a multiplatform kernel. This should be applied by the 632 bootloader instead. 633 634config ARM_ERRATA_742231 635 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 636 depends on CPU_V7 && SMP 637 depends on !ARCH_MULTIPLATFORM 638 help 639 This option enables the workaround for the 742231 Cortex-A9 640 (r2p0..r2p2) erratum. Under certain conditions, specific to the 641 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 642 accessing some data located in the same cache line, may get corrupted 643 data due to bad handling of the address hazard when the line gets 644 replaced from one of the CPUs at the same time as another CPU is 645 accessing it. This workaround sets specific bits in the diagnostic 646 register of the Cortex-A9 which reduces the linefill issuing 647 capabilities of the processor. Note that setting specific bits in the 648 diagnostics register may not be available in non-secure mode and thus 649 is not available on a multiplatform kernel. This should be applied by 650 the bootloader instead. 651 652config ARM_ERRATA_643719 653 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 654 depends on CPU_V7 && SMP 655 default y 656 help 657 This option enables the workaround for the 643719 Cortex-A9 (prior to 658 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 659 register returns zero when it should return one. The workaround 660 corrects this value, ensuring cache maintenance operations which use 661 it behave as intended and avoiding data corruption. 662 663config ARM_ERRATA_720789 664 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 665 depends on CPU_V7 666 help 667 This option enables the workaround for the 720789 Cortex-A9 (prior to 668 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 669 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 670 As a consequence of this erratum, some TLB entries which should be 671 invalidated are not, resulting in an incoherency in the system page 672 tables. The workaround changes the TLB flushing routines to invalidate 673 entries regardless of the ASID. 674 675config ARM_ERRATA_743622 676 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 677 depends on CPU_V7 678 depends on !ARCH_MULTIPLATFORM 679 help 680 This option enables the workaround for the 743622 Cortex-A9 681 (r2p*) erratum. Under very rare conditions, a faulty 682 optimisation in the Cortex-A9 Store Buffer may lead to data 683 corruption. This workaround sets a specific bit in the diagnostic 684 register of the Cortex-A9 which disables the Store Buffer 685 optimisation, preventing the defect from occurring. This has no 686 visible impact on the overall performance or power consumption of the 687 processor. Note that setting specific bits in the diagnostics register 688 may not be available in non-secure mode and thus is not available on a 689 multiplatform kernel. This should be applied by the bootloader instead. 690 691config ARM_ERRATA_751472 692 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 693 depends on CPU_V7 694 depends on !ARCH_MULTIPLATFORM 695 help 696 This option enables the workaround for the 751472 Cortex-A9 (prior 697 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 698 completion of a following broadcasted operation if the second 699 operation is received by a CPU before the ICIALLUIS has completed, 700 potentially leading to corrupted entries in the cache or TLB. 701 Note that setting specific bits in the diagnostics register may 702 not be available in non-secure mode and thus is not available on 703 a multiplatform kernel. This should be applied by the bootloader 704 instead. 705 706config ARM_ERRATA_754322 707 bool "ARM errata: possible faulty MMU translations following an ASID switch" 708 depends on CPU_V7 709 help 710 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 711 r3p*) erratum. A speculative memory access may cause a page table walk 712 which starts prior to an ASID switch but completes afterwards. This 713 can populate the micro-TLB with a stale entry which may be hit with 714 the new ASID. This workaround places two dsb instructions in the mm 715 switching code so that no page table walks can cross the ASID switch. 716 717config ARM_ERRATA_754327 718 bool "ARM errata: no automatic Store Buffer drain" 719 depends on CPU_V7 && SMP 720 help 721 This option enables the workaround for the 754327 Cortex-A9 (prior to 722 r2p0) erratum. The Store Buffer does not have any automatic draining 723 mechanism and therefore a livelock may occur if an external agent 724 continuously polls a memory location waiting to observe an update. 725 This workaround defines cpu_relax() as smp_mb(), preventing correctly 726 written polling loops from denying visibility of updates to memory. 727 728config ARM_ERRATA_364296 729 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 730 depends on CPU_V6 731 help 732 This options enables the workaround for the 364296 ARM1136 733 r0p2 erratum (possible cache data corruption with 734 hit-under-miss enabled). It sets the undocumented bit 31 in 735 the auxiliary control register and the FI bit in the control 736 register, thus disabling hit-under-miss without putting the 737 processor into full low interrupt latency mode. ARM11MPCore 738 is not affected. 739 740config ARM_ERRATA_764369 741 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 742 depends on CPU_V7 && SMP 743 help 744 This option enables the workaround for erratum 764369 745 affecting Cortex-A9 MPCore with two or more processors (all 746 current revisions). Under certain timing circumstances, a data 747 cache line maintenance operation by MVA targeting an Inner 748 Shareable memory region may fail to proceed up to either the 749 Point of Coherency or to the Point of Unification of the 750 system. This workaround adds a DSB instruction before the 751 relevant cache maintenance functions and sets a specific bit 752 in the diagnostic control register of the SCU. 753 754config ARM_ERRATA_764319 755 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 756 depends on CPU_V7 757 help 758 This option enables the workaround for the 764319 Cortex-A9 erratum. 759 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 760 unexpected Undefined Instruction exception when the DBGSWENABLE 761 external pin is set to 0, even when the CP14 accesses are performed 762 from a privileged mode. This work around catches the exception in a 763 way the kernel does not stop execution. 764 765config ARM_ERRATA_775420 766 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 767 depends on CPU_V7 768 help 769 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 770 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 771 operation aborts with MMU exception, it might cause the processor 772 to deadlock. This workaround puts DSB before executing ISB if 773 an abort may occur on cache maintenance. 774 775config ARM_ERRATA_798181 776 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 777 depends on CPU_V7 && SMP 778 help 779 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 780 adequately shooting down all use of the old entries. This 781 option enables the Linux kernel workaround for this erratum 782 which sends an IPI to the CPUs that are running the same ASID 783 as the one being invalidated. 784 785config ARM_ERRATA_773022 786 bool "ARM errata: incorrect instructions may be executed from loop buffer" 787 depends on CPU_V7 788 help 789 This option enables the workaround for the 773022 Cortex-A15 790 (up to r0p4) erratum. In certain rare sequences of code, the 791 loop buffer may deliver incorrect instructions. This 792 workaround disables the loop buffer to avoid the erratum. 793 794config ARM_ERRATA_818325_852422 795 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 796 depends on CPU_V7 797 help 798 This option enables the workaround for: 799 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 800 instruction might deadlock. Fixed in r0p1. 801 - Cortex-A12 852422: Execution of a sequence of instructions might 802 lead to either a data corruption or a CPU deadlock. Not fixed in 803 any Cortex-A12 cores yet. 804 This workaround for all both errata involves setting bit[12] of the 805 Feature Register. This bit disables an optimisation applied to a 806 sequence of 2 instructions that use opposing condition codes. 807 808config ARM_ERRATA_821420 809 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 821420 Cortex-A12 813 (all revs) erratum. In very rare timing conditions, a sequence 814 of VMOV to Core registers instructions, for which the second 815 one is in the shadow of a branch or abort, can lead to a 816 deadlock when the VMOV instructions are issued out-of-order. 817 818config ARM_ERRATA_825619 819 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 820 depends on CPU_V7 821 help 822 This option enables the workaround for the 825619 Cortex-A12 823 (all revs) erratum. Within rare timing constraints, executing a 824 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 825 and Device/Strongly-Ordered loads and stores might cause deadlock 826 827config ARM_ERRATA_857271 828 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 829 depends on CPU_V7 830 help 831 This option enables the workaround for the 857271 Cortex-A12 832 (all revs) erratum. Under very rare timing conditions, the CPU might 833 hang. The workaround is expected to have a < 1% performance impact. 834 835config ARM_ERRATA_852421 836 bool "ARM errata: A17: DMB ST might fail to create order between stores" 837 depends on CPU_V7 838 help 839 This option enables the workaround for the 852421 Cortex-A17 840 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 841 execution of a DMB ST instruction might fail to properly order 842 stores from GroupA and stores from GroupB. 843 844config ARM_ERRATA_852423 845 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 846 depends on CPU_V7 847 help 848 This option enables the workaround for: 849 - Cortex-A17 852423: Execution of a sequence of instructions might 850 lead to either a data corruption or a CPU deadlock. Not fixed in 851 any Cortex-A17 cores yet. 852 This is identical to Cortex-A12 erratum 852422. It is a separate 853 config option from the A12 erratum due to the way errata are checked 854 for and handled. 855 856config ARM_ERRATA_857272 857 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 858 depends on CPU_V7 859 help 860 This option enables the workaround for the 857272 Cortex-A17 erratum. 861 This erratum is not known to be fixed in any A17 revision. 862 This is identical to Cortex-A12 erratum 857271. It is a separate 863 config option from the A12 erratum due to the way errata are checked 864 for and handled. 865 866endmenu 867 868source "arch/arm/common/Kconfig" 869 870menu "Bus support" 871 872config ISA 873 bool 874 help 875 Find out whether you have ISA slots on your motherboard. ISA is the 876 name of a bus system, i.e. the way the CPU talks to the other stuff 877 inside your box. Other bus systems are PCI, EISA, MicroChannel 878 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 879 newer boards don't support it. If you have ISA, say Y, otherwise N. 880 881# Select ISA DMA interface 882config ISA_DMA_API 883 bool 884 885config ARM_ERRATA_814220 886 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 887 depends on CPU_V7 888 help 889 The v7 ARM states that all cache and branch predictor maintenance 890 operations that do not specify an address execute, relative to 891 each other, in program order. 892 However, because of this erratum, an L2 set/way cache maintenance 893 operation can overtake an L1 set/way cache maintenance operation. 894 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 895 r0p4, r0p5. 896 897endmenu 898 899menu "Kernel Features" 900 901config HAVE_SMP 902 bool 903 help 904 This option should be selected by machines which have an SMP- 905 capable CPU. 906 907 The only effect of this option is to make the SMP-related 908 options available to the user for configuration. 909 910config SMP 911 bool "Symmetric Multi-Processing" 912 depends on CPU_V6K || CPU_V7 913 depends on HAVE_SMP 914 depends on MMU || ARM_MPU 915 select IRQ_WORK 916 help 917 This enables support for systems with more than one CPU. If you have 918 a system with only one CPU, say N. If you have a system with more 919 than one CPU, say Y. 920 921 If you say N here, the kernel will run on uni- and multiprocessor 922 machines, but will use only one CPU of a multiprocessor machine. If 923 you say Y here, the kernel will run on many, but not all, 924 uniprocessor machines. On a uniprocessor machine, the kernel 925 will run faster if you say N here. 926 927 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 928 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 929 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 930 931 If you don't know what to do here, say N. 932 933config SMP_ON_UP 934 bool "Allow booting SMP kernel on uniprocessor systems" 935 depends on SMP && MMU 936 default y 937 help 938 SMP kernels contain instructions which fail on non-SMP processors. 939 Enabling this option allows the kernel to modify itself to make 940 these instructions safe. Disabling it allows about 1K of space 941 savings. 942 943 If you don't know what to do here, say Y. 944 945 946config CURRENT_POINTER_IN_TPIDRURO 947 def_bool y 948 depends on CPU_32v6K && !CPU_V6 949 950config IRQSTACKS 951 def_bool y 952 select HAVE_IRQ_EXIT_ON_IRQ_STACK 953 select HAVE_SOFTIRQ_ON_OWN_STACK 954 955config ARM_CPU_TOPOLOGY 956 bool "Support cpu topology definition" 957 depends on SMP && CPU_V7 958 select ARCH_SUPPORTS_SCHED_MC 959 select ARCH_SUPPORTS_SCHED_SMT 960 default y 961 help 962 Support ARM cpu topology definition. The MPIDR register defines 963 affinity between processors which is then used to describe the cpu 964 topology of an ARM System. 965 966config HAVE_ARM_SCU 967 bool 968 help 969 This option enables support for the ARM snoop control unit 970 971config HAVE_ARM_ARCH_TIMER 972 bool "Architected timer support" 973 depends on CPU_V7 974 select ARM_ARCH_TIMER 975 help 976 This option enables support for the ARM architected timer 977 978config HAVE_ARM_TWD 979 bool 980 help 981 This options enables support for the ARM timer and watchdog unit 982 983config MCPM 984 bool "Multi-Cluster Power Management" 985 depends on CPU_V7 && SMP 986 help 987 This option provides the common power management infrastructure 988 for (multi-)cluster based systems, such as big.LITTLE based 989 systems. 990 991config MCPM_QUAD_CLUSTER 992 bool 993 depends on MCPM 994 help 995 To avoid wasting resources unnecessarily, MCPM only supports up 996 to 2 clusters by default. 997 Platforms with 3 or 4 clusters that use MCPM must select this 998 option to allow the additional clusters to be managed. 999 1000config BIG_LITTLE 1001 bool "big.LITTLE support (Experimental)" 1002 depends on CPU_V7 && SMP 1003 select MCPM 1004 help 1005 This option enables support selections for the big.LITTLE 1006 system architecture. 1007 1008config BL_SWITCHER 1009 bool "big.LITTLE switcher support" 1010 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1011 select CPU_PM 1012 help 1013 The big.LITTLE "switcher" provides the core functionality to 1014 transparently handle transition between a cluster of A15's 1015 and a cluster of A7's in a big.LITTLE system. 1016 1017config BL_SWITCHER_DUMMY_IF 1018 tristate "Simple big.LITTLE switcher user interface" 1019 depends on BL_SWITCHER && DEBUG_KERNEL 1020 help 1021 This is a simple and dummy char dev interface to control 1022 the big.LITTLE switcher core code. It is meant for 1023 debugging purposes only. 1024 1025choice 1026 prompt "Memory split" 1027 depends on MMU 1028 default VMSPLIT_3G 1029 help 1030 Select the desired split between kernel and user memory. 1031 1032 If you are not absolutely sure what you are doing, leave this 1033 option alone! 1034 1035 config VMSPLIT_3G 1036 bool "3G/1G user/kernel split" 1037 config VMSPLIT_3G_OPT 1038 depends on !ARM_LPAE 1039 bool "3G/1G user/kernel split (for full 1G low memory)" 1040 config VMSPLIT_2G 1041 bool "2G/2G user/kernel split" 1042 config VMSPLIT_1G 1043 bool "1G/3G user/kernel split" 1044endchoice 1045 1046config PAGE_OFFSET 1047 hex 1048 default PHYS_OFFSET if !MMU 1049 default 0x40000000 if VMSPLIT_1G 1050 default 0x80000000 if VMSPLIT_2G 1051 default 0xB0000000 if VMSPLIT_3G_OPT 1052 default 0xC0000000 1053 1054config KASAN_SHADOW_OFFSET 1055 hex 1056 depends on KASAN 1057 default 0x1f000000 if PAGE_OFFSET=0x40000000 1058 default 0x5f000000 if PAGE_OFFSET=0x80000000 1059 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1060 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1061 default 0xffffffff 1062 1063config NR_CPUS 1064 int "Maximum number of CPUs (2-32)" 1065 range 2 16 if DEBUG_KMAP_LOCAL 1066 range 2 32 if !DEBUG_KMAP_LOCAL 1067 depends on SMP 1068 default "4" 1069 help 1070 The maximum number of CPUs that the kernel can support. 1071 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1072 debugging is enabled, which uses half of the per-CPU fixmap 1073 slots as guard regions. 1074 1075config HOTPLUG_CPU 1076 bool "Support for hot-pluggable CPUs" 1077 depends on SMP 1078 select GENERIC_IRQ_MIGRATION 1079 help 1080 Say Y here to experiment with turning CPUs off and on. CPUs 1081 can be controlled through /sys/devices/system/cpu. 1082 1083config ARM_PSCI 1084 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1085 depends on HAVE_ARM_SMCCC 1086 select ARM_PSCI_FW 1087 help 1088 Say Y here if you want Linux to communicate with system firmware 1089 implementing the PSCI specification for CPU-centric power 1090 management operations described in ARM document number ARM DEN 1091 0022A ("Power State Coordination Interface System Software on 1092 ARM processors"). 1093 1094config HZ_FIXED 1095 int 1096 default 128 if SOC_AT91RM9200 1097 default 0 1098 1099choice 1100 depends on HZ_FIXED = 0 1101 prompt "Timer frequency" 1102 1103config HZ_100 1104 bool "100 Hz" 1105 1106config HZ_200 1107 bool "200 Hz" 1108 1109config HZ_250 1110 bool "250 Hz" 1111 1112config HZ_300 1113 bool "300 Hz" 1114 1115config HZ_500 1116 bool "500 Hz" 1117 1118config HZ_1000 1119 bool "1000 Hz" 1120 1121endchoice 1122 1123config HZ 1124 int 1125 default HZ_FIXED if HZ_FIXED != 0 1126 default 100 if HZ_100 1127 default 200 if HZ_200 1128 default 250 if HZ_250 1129 default 300 if HZ_300 1130 default 500 if HZ_500 1131 default 1000 1132 1133config SCHED_HRTICK 1134 def_bool HIGH_RES_TIMERS 1135 1136config THUMB2_KERNEL 1137 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1138 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1139 default y if CPU_THUMBONLY 1140 select ARM_UNWIND 1141 help 1142 By enabling this option, the kernel will be compiled in 1143 Thumb-2 mode. 1144 1145 If unsure, say N. 1146 1147config ARM_PATCH_IDIV 1148 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1149 depends on CPU_32v7 1150 default y 1151 help 1152 The ARM compiler inserts calls to __aeabi_idiv() and 1153 __aeabi_uidiv() when it needs to perform division on signed 1154 and unsigned integers. Some v7 CPUs have support for the sdiv 1155 and udiv instructions that can be used to implement those 1156 functions. 1157 1158 Enabling this option allows the kernel to modify itself to 1159 replace the first two instructions of these library functions 1160 with the sdiv or udiv plus "bx lr" instructions when the CPU 1161 it is running on supports them. Typically this will be faster 1162 and less power intensive than running the original library 1163 code to do integer division. 1164 1165config AEABI 1166 bool "Use the ARM EABI to compile the kernel" if CPU_SA110 || CPU_SA1100 1167 default y 1168 help 1169 The Arm EABI is the default ABI on all modern Linux 1170 distributions, replacing the obsolete and "OABI" that was 1171 commonly used on ARMv4 distributions before ca. 2013. 1172 1173 Everyone should enable this, as support for OABI user space 1174 was dropped in gcc-4.8 and most distributions after ca. 2013. 1175 1176 Support for OABI mode will be removed from the kernel 1177 once Intel StrongARM CPUs are phased out. 1178 1179config OABI_COMPAT 1180 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1181 depends on AEABI && !THUMB2_KERNEL 1182 depends on CPU_SA110 || CPU_SA1100 1183 help 1184 This option preserves the old syscall interface along with the 1185 new (ARM EABI) one. It also provides a compatibility layer to 1186 intercept syscalls that have structure arguments which layout 1187 in memory differs between the legacy ABI and the new ARM EABI 1188 (only for non "thumb" binaries). This option adds a tiny 1189 overhead to all syscalls and produces a slightly larger kernel. 1190 1191 The seccomp filter system will not be available when this is 1192 selected, since there is no way yet to sensibly distinguish 1193 between calling conventions during filtering. 1194 1195 Support for OABI_COMPAT will be removed from the kernel 1196 once Intel StrongARM CPUs are phased out. 1197 1198config ARCH_SELECT_MEMORY_MODEL 1199 def_bool y 1200 1201config ARCH_FLATMEM_ENABLE 1202 def_bool !(ARCH_RPC || ARCH_SA1100) 1203 1204config ARCH_SPARSEMEM_ENABLE 1205 def_bool !ARCH_FOOTBRIDGE 1206 select SPARSEMEM_STATIC if SPARSEMEM 1207 1208config HIGHMEM 1209 bool "High Memory Support" 1210 depends on MMU 1211 select KMAP_LOCAL 1212 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1213 help 1214 The address space of ARM processors is only 4 Gigabytes large 1215 and it has to accommodate user address space, kernel address 1216 space as well as some memory mapped IO. That means that, if you 1217 have a large amount of physical memory and/or IO, not all of the 1218 memory can be "permanently mapped" by the kernel. The physical 1219 memory that is not permanently mapped is called "high memory". 1220 1221 Depending on the selected kernel/user memory split, minimum 1222 vmalloc space and actual amount of RAM, you may not need this 1223 option which should result in a slightly faster kernel. 1224 1225 If unsure, say n. 1226 1227config HIGHPTE 1228 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1229 depends on HIGHMEM && !PREEMPT_RT 1230 default y 1231 help 1232 The VM uses one page of physical memory for each page table. 1233 For systems with a lot of processes, this can use a lot of 1234 precious low memory, eventually leading to low memory being 1235 consumed by page tables. Setting this option will allow 1236 user-space 2nd level page tables to reside in high memory. 1237 1238config ARM_PAN 1239 bool "Enable privileged no-access" 1240 depends on MMU 1241 default y 1242 help 1243 Increase kernel security by ensuring that normal kernel accesses 1244 are unable to access userspace addresses. This can help prevent 1245 use-after-free bugs becoming an exploitable privilege escalation 1246 by ensuring that magic values (such as LIST_POISON) will always 1247 fault when dereferenced. 1248 1249 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1250 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1251 1252config CPU_SW_DOMAIN_PAN 1253 def_bool y 1254 depends on ARM_PAN && !ARM_LPAE 1255 help 1256 Enable use of CPU domains to implement privileged no-access. 1257 1258 CPUs with low-vector mappings use a best-efforts implementation. 1259 Their lower 1MB needs to remain accessible for the vectors, but 1260 the remainder of userspace will become appropriately inaccessible. 1261 1262config CPU_TTBR0_PAN 1263 def_bool y 1264 depends on ARM_PAN && ARM_LPAE 1265 help 1266 Enable privileged no-access by disabling TTBR0 page table walks when 1267 running in kernel mode. 1268 1269config HW_PERF_EVENTS 1270 def_bool y 1271 depends on ARM_PMU 1272 1273config ARM_MODULE_PLTS 1274 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1275 depends on MODULES 1276 select KASAN_VMALLOC if KASAN 1277 default y 1278 help 1279 Allocate PLTs when loading modules so that jumps and calls whose 1280 targets are too far away for their relative offsets to be encoded 1281 in the instructions themselves can be bounced via veneers in the 1282 module's PLT. This allows modules to be allocated in the generic 1283 vmalloc area after the dedicated module memory area has been 1284 exhausted. The modules will use slightly more memory, but after 1285 rounding up to page size, the actual memory footprint is usually 1286 the same. 1287 1288 Disabling this is usually safe for small single-platform 1289 configurations. If unsure, say y. 1290 1291config ARCH_FORCE_MAX_ORDER 1292 int "Order of maximal physically contiguous allocations" 1293 default "11" if SOC_AM33XX 1294 default "8" if SA1111 1295 default "10" 1296 help 1297 The kernel page allocator limits the size of maximal physically 1298 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1299 defines the maximal power of two of number of pages that can be 1300 allocated as a single contiguous block. This option allows 1301 overriding the default setting when ability to allocate very 1302 large blocks of physically contiguous memory is required. 1303 1304 Don't change if unsure. 1305 1306config ALIGNMENT_TRAP 1307 def_bool CPU_CP15_MMU 1308 select HAVE_PROC_CPU if PROC_FS 1309 help 1310 ARM processors cannot fetch/store information which is not 1311 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1312 address divisible by 4. On 32-bit ARM processors, these non-aligned 1313 fetch/store instructions will be emulated in software if you say 1314 here, which has a severe performance impact. This is necessary for 1315 correct operation of some network protocols. With an IP-only 1316 configuration it is safe to say N, otherwise say Y. 1317 1318config UACCESS_WITH_MEMCPY 1319 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1320 depends on MMU 1321 default y if CPU_FEROCEON 1322 help 1323 Implement faster copy_to_user and clear_user methods for CPU 1324 cores where a 8-word STM instruction give significantly higher 1325 memory write throughput than a sequence of individual 32bit stores. 1326 1327 A possible side effect is a slight increase in scheduling latency 1328 between threads sharing the same address space if they invoke 1329 such copy operations with large buffers. 1330 1331 However, if the CPU data cache is using a write-allocate mode, 1332 this option is unlikely to provide any performance gain. 1333 1334config PARAVIRT 1335 bool "Enable paravirtualization code" 1336 select HAVE_PV_STEAL_CLOCK_GEN 1337 help 1338 This changes the kernel so it can modify itself when it is run 1339 under a hypervisor, potentially improving performance significantly 1340 over full virtualization. 1341 1342config PARAVIRT_TIME_ACCOUNTING 1343 bool "Paravirtual steal time accounting" 1344 select PARAVIRT 1345 help 1346 Select this option to enable fine granularity task steal time 1347 accounting. Time spent executing other tasks in parallel with 1348 the current vCPU is discounted from the vCPU power. To account for 1349 that, there can be a small performance impact. 1350 1351 If in doubt, say N here. 1352 1353config XEN_DOM0 1354 def_bool y 1355 depends on XEN 1356 1357config XEN 1358 bool "Xen guest support on ARM" 1359 depends on ARM && AEABI && OF 1360 depends on CPU_V7 && !CPU_V6 1361 depends on !GENERIC_ATOMIC64 1362 depends on MMU 1363 select ARCH_DMA_ADDR_T_64BIT 1364 select ARM_PSCI 1365 select SWIOTLB 1366 select SWIOTLB_XEN 1367 select PARAVIRT 1368 help 1369 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1370 1371config CC_HAVE_STACKPROTECTOR_TLS 1372 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1373 1374config STACKPROTECTOR_PER_TASK 1375 bool "Use a unique stack canary value for each task" 1376 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1377 depends on CC_HAVE_STACKPROTECTOR_TLS 1378 default y 1379 help 1380 Due to the fact that GCC uses an ordinary symbol reference from 1381 which to load the value of the stack canary, this value can only 1382 change at reboot time on SMP systems, and all tasks running in the 1383 kernel's address space are forced to use the same canary value for 1384 the entire duration that the system is up. 1385 1386 Enable this option to switch to a different method that uses a 1387 different canary value for each task. 1388 1389endmenu 1390 1391menu "Boot options" 1392 1393config USE_OF 1394 bool "Flattened Device Tree support" 1395 select IRQ_DOMAIN 1396 select OF 1397 help 1398 Include support for flattened device tree machine descriptions. 1399 1400config ARCH_WANT_FLAT_DTB_INSTALL 1401 def_bool y 1402 1403config ATAGS 1404 bool "Support for the traditional ATAGS boot data passing" 1405 depends on EXPERT 1406 help 1407 This is the traditional way of passing data to the kernel at 1408 boot but is now only used by a few of the oldest ARMv4 and 1409 ARMv5 machines. Users that still rely on ATAGS should plan 1410 on migrating to devicetree based booting. 1411 1412 Support for ATAGS will be removed when the last machine using 1413 it is either converted to DT or removed. 1414 1415config DEPRECATED_PARAM_STRUCT 1416 bool "Provide old way to pass kernel parameters (DEPRECATED)" 1417 depends on ATAGS 1418 help 1419 This was deprecated in 2001 and announced to live on for 5 years. 1420 It is now scheduled for removal in early 2027. 1421 1422# Compressed boot loader in ROM. Yes, we really want to ask about 1423# TEXT and BSS so we preserve their values in the config files. 1424config ZBOOT_ROM_TEXT 1425 hex "Compressed ROM boot loader base address" 1426 default 0x0 1427 help 1428 The physical address at which the ROM-able zImage is to be 1429 placed in the target. Platforms which normally make use of 1430 ROM-able zImage formats normally set this to a suitable 1431 value in their defconfig file. 1432 1433 If ZBOOT_ROM is not enabled, this has no effect. 1434 1435config ZBOOT_ROM_BSS 1436 hex "Compressed ROM boot loader BSS address" 1437 default 0x0 1438 help 1439 The base address of an area of read/write memory in the target 1440 for the ROM-able zImage which must be available while the 1441 decompressor is running. It must be large enough to hold the 1442 entire decompressed kernel plus an additional 128 KiB. 1443 Platforms which normally make use of ROM-able zImage formats 1444 normally set this to a suitable value in their defconfig file. 1445 1446 If ZBOOT_ROM is not enabled, this has no effect. 1447 1448config ZBOOT_ROM 1449 bool "Compressed boot loader in ROM/flash" 1450 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1451 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1452 help 1453 Say Y here if you intend to execute your compressed kernel image 1454 (zImage) directly from ROM or flash. If unsure, say N. 1455 1456config ARM_APPENDED_DTB 1457 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1458 depends on OF 1459 help 1460 With this option, the boot code will look for a device tree binary 1461 (DTB) appended to zImage 1462 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1463 1464 This is meant as a backward compatibility convenience for those 1465 systems with a bootloader that can't be upgraded to accommodate 1466 the documented boot protocol using a device tree. 1467 1468 Beware that there is very little in terms of protection against 1469 this option being confused by leftover garbage in memory that might 1470 look like a DTB header after a reboot if no actual DTB is appended 1471 to zImage. Do not leave this option active in a production kernel 1472 if you don't intend to always append a DTB. Proper passing of the 1473 location into r2 of a bootloader provided DTB is always preferable 1474 to this option. 1475 1476config ARM_ATAG_DTB_COMPAT 1477 bool "Supplement the appended DTB with traditional ATAG information" 1478 depends on ARM_APPENDED_DTB 1479 help 1480 Some old bootloaders can't be updated to a DTB capable one, yet 1481 they provide ATAGs with memory configuration, the ramdisk address, 1482 the kernel cmdline string, etc. Such information is dynamically 1483 provided by the bootloader and can't always be stored in a static 1484 DTB. To allow a device tree enabled kernel to be used with such 1485 bootloaders, this option allows zImage to extract the information 1486 from the ATAG list and store it at run time into the appended DTB. 1487 1488choice 1489 prompt "Kernel command line type" 1490 depends on ARM_ATAG_DTB_COMPAT 1491 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1492 1493config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1494 bool "Use bootloader kernel arguments if available" 1495 help 1496 Uses the command-line options passed by the boot loader instead of 1497 the device tree bootargs property. If the boot loader doesn't provide 1498 any, the device tree bootargs property will be used. 1499 1500config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1501 bool "Extend with bootloader kernel arguments" 1502 help 1503 The command-line arguments provided by the boot loader will be 1504 appended to the the device tree bootargs property. 1505 1506endchoice 1507 1508config CMDLINE 1509 string "Default kernel command string" 1510 default "" 1511 help 1512 On some architectures (e.g. CATS), there is currently no way 1513 for the boot loader to pass arguments to the kernel. For these 1514 architectures, you should supply some command-line options at build 1515 time by entering them here. As a minimum, you should specify the 1516 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1517 1518choice 1519 prompt "Kernel command line type" 1520 depends on CMDLINE != "" 1521 default CMDLINE_FROM_BOOTLOADER 1522 1523config CMDLINE_FROM_BOOTLOADER 1524 bool "Use bootloader kernel arguments if available" 1525 help 1526 Uses the command-line options passed by the boot loader. If 1527 the boot loader doesn't provide any, the default kernel command 1528 string provided in CMDLINE will be used. 1529 1530config CMDLINE_EXTEND 1531 bool "Extend bootloader kernel arguments" 1532 help 1533 The command-line arguments provided by the boot loader will be 1534 appended to the default kernel command string. 1535 1536config CMDLINE_FORCE 1537 bool "Always use the default kernel command string" 1538 help 1539 Always use the default kernel command string, even if the boot 1540 loader passes other arguments to the kernel. 1541 This is useful if you cannot or don't want to change the 1542 command-line options your boot loader passes to the kernel. 1543endchoice 1544 1545config XIP_KERNEL 1546 bool "Kernel Execute-In-Place from ROM" 1547 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1548 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1549 help 1550 Execute-In-Place allows the kernel to run from non-volatile storage 1551 directly addressable by the CPU, such as NOR flash. This saves RAM 1552 space since the text section of the kernel is not loaded from flash 1553 to RAM. Read-write sections, such as the data section and stack, 1554 are still copied to RAM. The XIP kernel is not compressed since 1555 it has to run directly from flash, so it will take more space to 1556 store it. The flash address used to link the kernel object files, 1557 and for storing it, is configuration dependent. Therefore, if you 1558 say Y here, you must know the proper physical address where to 1559 store the kernel image depending on your own flash memory usage. 1560 1561 Also note that the make target becomes "make xipImage" rather than 1562 "make zImage" or "make Image". The final kernel binary to put in 1563 ROM memory will be arch/arm/boot/xipImage. 1564 1565 If unsure, say N. 1566 1567config XIP_PHYS_ADDR 1568 hex "XIP Kernel Physical Location" 1569 depends on XIP_KERNEL 1570 default "0x00080000" 1571 help 1572 This is the physical address in your flash memory the kernel will 1573 be linked for and stored to. This address is dependent on your 1574 own flash usage. 1575 1576config XIP_DEFLATED_DATA 1577 bool "Store kernel .data section compressed in ROM" 1578 depends on XIP_KERNEL 1579 select ZLIB_INFLATE 1580 help 1581 Before the kernel is actually executed, its .data section has to be 1582 copied to RAM from ROM. This option allows for storing that data 1583 in compressed form and decompressed to RAM rather than merely being 1584 copied, saving some precious ROM space. A possible drawback is a 1585 slightly longer boot delay. 1586 1587config ARCH_SUPPORTS_KEXEC 1588 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1589 1590config ATAGS_PROC 1591 bool "Export atags in procfs" 1592 depends on ATAGS && KEXEC 1593 default y 1594 help 1595 Should the atags used to boot the kernel be exported in an "atags" 1596 file in procfs. Useful with kexec. 1597 1598config ARCH_SUPPORTS_CRASH_DUMP 1599 def_bool y 1600 1601config ARCH_DEFAULT_CRASH_DUMP 1602 def_bool y 1603 1604config AUTO_ZRELADDR 1605 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1606 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1607 help 1608 ZRELADDR is the physical address where the decompressed kernel 1609 image will be placed. If AUTO_ZRELADDR is selected, the address 1610 will be determined at run-time, either by masking the current IP 1611 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1612 This assumes the zImage being placed in the first 128MB from 1613 start of memory. 1614 1615config EFI_STUB 1616 bool 1617 1618config EFI 1619 bool "UEFI runtime support" 1620 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1621 select UCS2_STRING 1622 select EFI_PARAMS_FROM_FDT 1623 select EFI_STUB 1624 select EFI_GENERIC_STUB 1625 select EFI_RUNTIME_WRAPPERS 1626 help 1627 This option provides support for runtime services provided 1628 by UEFI firmware (such as non-volatile variables, realtime 1629 clock, and platform reset). A UEFI stub is also provided to 1630 allow the kernel to be booted as an EFI application. This 1631 is only useful for kernels that may run on systems that have 1632 UEFI firmware. 1633 1634config DMI 1635 bool "Enable support for SMBIOS (DMI) tables" 1636 depends on EFI 1637 default y 1638 help 1639 This enables SMBIOS/DMI feature for systems. 1640 1641 This option is only useful on systems that have UEFI firmware. 1642 However, even with this option, the resultant kernel should 1643 continue to boot on existing non-UEFI platforms. 1644 1645 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1646 i.e., the the practice of identifying the platform via DMI to 1647 decide whether certain workarounds for buggy hardware and/or 1648 firmware need to be enabled. This would require the DMI subsystem 1649 to be enabled much earlier than we do on ARM, which is non-trivial. 1650 1651endmenu 1652 1653menu "CPU Power Management" 1654 1655source "drivers/cpufreq/Kconfig" 1656 1657source "drivers/cpuidle/Kconfig" 1658 1659endmenu 1660 1661menu "Floating point emulation" 1662 1663comment "At least one emulation must be selected" 1664 1665config FPE_NWFPE 1666 bool "NWFPE math emulation (DEPRECATED)" 1667 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1668 help 1669 Say Y to include the NWFPE floating point emulator in the kernel. 1670 1671 This is only used on OABI userspace binaries, either using a 1672 pure OABI (!CONFIG_AEABI) kernel, or the OABI emulation. 1673 1674 Support for NWFPE will be removed in the future when OABI 1675 support is removed. 1676 1677config FPE_NWFPE_XP 1678 bool "Support extended precision" 1679 depends on FPE_NWFPE 1680 help 1681 Say Y to include 80-bit support in the kernel floating-point 1682 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1683 Note that gcc does not generate 80-bit operations by default, 1684 so in most cases this option only enlarges the size of the 1685 floating point emulator without any good reason. 1686 1687 You almost surely want to say N here. 1688 1689config FPE_FASTFPE 1690 bool "FastFPE math emulation (EXPERIMENTAL)" 1691 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1692 help 1693 Say Y here to include the FAST floating point emulator in the kernel. 1694 This is an experimental much faster emulator which now also has full 1695 precision for the mantissa. It does not support any exceptions. 1696 It is very simple, and approximately 3-6 times faster than NWFPE. 1697 1698 It should be sufficient for most programs. It may be not suitable 1699 for scientific calculations, but you have to check this for yourself. 1700 If you do not feel you need a faster FP emulation you should better 1701 choose NWFPE. 1702 1703config VFP 1704 bool "VFP-format floating point maths" 1705 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1706 help 1707 Say Y to include VFP support code in the kernel. This is needed 1708 if your hardware includes a VFP unit. 1709 1710 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1711 release notes and additional status information. 1712 1713 Say N if your target does not have VFP hardware. 1714 1715config VFPv3 1716 bool 1717 depends on VFP 1718 default y if CPU_V7 1719 1720config NEON 1721 bool "Advanced SIMD (NEON) Extension support" 1722 depends on VFPv3 && CPU_V7 1723 help 1724 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1725 Extension. 1726 1727config KERNEL_MODE_NEON 1728 bool "Support for NEON in kernel mode" 1729 depends on NEON && AEABI 1730 help 1731 Say Y to include support for NEON in kernel mode. 1732 1733endmenu 1734 1735config ARCH_CC_CAN_LINK 1736 bool 1737 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN 1738 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8 1739 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32 1740 1741config ARCH_USERFLAGS 1742 string 1743 default "-mlittle-endian" if CPU_LITTLE_ENDIAN 1744 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8 1745 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32 1746 1747menu "Power management options" 1748 1749source "kernel/power/Kconfig" 1750 1751config ARCH_SUSPEND_POSSIBLE 1752 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1753 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1754 def_bool y 1755 1756config ARM_CPU_SUSPEND 1757 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1758 depends on ARCH_SUSPEND_POSSIBLE 1759 1760config ARCH_HIBERNATION_POSSIBLE 1761 bool 1762 depends on MMU 1763 default y if ARCH_SUSPEND_POSSIBLE 1764 1765endmenu 1766