1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKSRC_MMIO 358 select CPU_ARM920T 359 select GPIOLIB 360 select COMMON_CLK 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select NEED_MACH_MEMORY_H 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_IOP32X 374 bool "IOP32x-based" 375 select CPU_XSCALE 376 select GPIO_IOP 377 select GPIOLIB 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 select ARCH_SUPPORTS_BIG_ENDIAN 387 select ARM_PATCH_PHYS_VIRT 388 select CPU_XSCALE 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 select SPARSE_IRQ 395 select USB_EHCI_BIG_ENDIAN_DESC 396 select USB_EHCI_BIG_ENDIAN_MMIO 397 help 398 Support for Intel's IXP4XX (XScale) family of processors. 399 400config ARCH_DOVE 401 bool "Marvell Dove" 402 select CPU_PJ4 403 select GPIOLIB 404 select HAVE_PCI 405 select MVEBU_MBUS 406 select PINCTRL 407 select PINCTRL_DOVE 408 select PLAT_ORION_LEGACY 409 select SPARSE_IRQ 410 select PM_GENERIC_DOMAINS if PM 411 help 412 Support for the Marvell Dove SoC 88AP510 413 414config ARCH_PXA 415 bool "PXA2xx/PXA3xx-based" 416 select ARCH_MTD_XIP 417 select ARM_CPU_SUSPEND if PM 418 select AUTO_ZRELADDR 419 select COMMON_CLK 420 select CLKSRC_PXA 421 select CLKSRC_MMIO 422 select TIMER_OF 423 select CPU_XSCALE if !CPU_XSC3 424 select GPIO_PXA 425 select GPIOLIB 426 select IRQ_DOMAIN 427 select PLAT_PXA 428 select SPARSE_IRQ 429 help 430 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 431 432config ARCH_RPC 433 bool "RiscPC" 434 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 435 select ARCH_ACORN 436 select ARCH_MAY_HAVE_PC_FDC 437 select ARCH_SPARSEMEM_ENABLE 438 select ARM_HAS_SG_CHAIN 439 select CPU_SA110 440 select FIQ 441 select HAVE_PATA_PLATFORM 442 select ISA_DMA_API 443 select LEGACY_TIMER_TICK 444 select NEED_MACH_IO_H 445 select NEED_MACH_MEMORY_H 446 select NO_IOPORT_MAP 447 help 448 On the Acorn Risc-PC, Linux can support the internal IDE disk and 449 CD-ROM interface, serial and parallel port, and the floppy drive. 450 451config ARCH_SA1100 452 bool "SA1100-based" 453 select ARCH_MTD_XIP 454 select ARCH_SPARSEMEM_ENABLE 455 select CLKSRC_MMIO 456 select CLKSRC_PXA 457 select TIMER_OF if OF 458 select COMMON_CLK 459 select CPU_FREQ 460 select CPU_SA1100 461 select GPIOLIB 462 select IRQ_DOMAIN 463 select ISA 464 select NEED_MACH_MEMORY_H 465 select SPARSE_IRQ 466 help 467 Support for StrongARM 11x0 based boards. 468 469config ARCH_S3C24XX 470 bool "Samsung S3C24XX SoCs" 471 select ATAGS 472 select CLKSRC_SAMSUNG_PWM 473 select GPIO_SAMSUNG 474 select GPIOLIB 475 select NEED_MACH_IO_H 476 select S3C2410_WATCHDOG 477 select SAMSUNG_ATAGS 478 select USE_OF 479 select WATCHDOG 480 help 481 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 482 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 483 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 484 Samsung SMDK2410 development board (and derivatives). 485 486config ARCH_OMAP1 487 bool "TI OMAP1" 488 select ARCH_OMAP 489 select CLKSRC_MMIO 490 select GENERIC_IRQ_CHIP 491 select GPIOLIB 492 select HAVE_LEGACY_CLK 493 select IRQ_DOMAIN 494 select NEED_MACH_IO_H if PCCARD 495 select NEED_MACH_MEMORY_H 496 select SPARSE_IRQ 497 help 498 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 499 500endchoice 501 502menu "Multiple platform selection" 503 depends on ARCH_MULTIPLATFORM 504 505comment "CPU Core family selection" 506 507config ARCH_MULTI_V4 508 bool "ARMv4 based platforms (FA526)" 509 depends on !ARCH_MULTI_V6_V7 510 select ARCH_MULTI_V4_V5 511 select CPU_FA526 512 513config ARCH_MULTI_V4T 514 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 515 depends on !ARCH_MULTI_V6_V7 516 select ARCH_MULTI_V4_V5 517 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 518 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 519 CPU_ARM925T || CPU_ARM940T) 520 521config ARCH_MULTI_V5 522 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 523 depends on !ARCH_MULTI_V6_V7 524 select ARCH_MULTI_V4_V5 525 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 526 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 527 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 528 529config ARCH_MULTI_V4_V5 530 bool 531 532config ARCH_MULTI_V6 533 bool "ARMv6 based platforms (ARM11)" 534 select ARCH_MULTI_V6_V7 535 select CPU_V6K 536 537config ARCH_MULTI_V7 538 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 539 default y 540 select ARCH_MULTI_V6_V7 541 select CPU_V7 542 select HAVE_SMP 543 544config ARCH_MULTI_V6_V7 545 bool 546 select MIGHT_HAVE_CACHE_L2X0 547 548config ARCH_MULTI_CPU_AUTO 549 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 550 select ARCH_MULTI_V5 551 552endmenu 553 554config ARCH_VIRT 555 bool "Dummy Virtual Machine" 556 depends on ARCH_MULTI_V7 557 select ARM_AMBA 558 select ARM_GIC 559 select ARM_GIC_V2M if PCI 560 select ARM_GIC_V3 561 select ARM_GIC_V3_ITS if PCI 562 select ARM_PSCI 563 select HAVE_ARM_ARCH_TIMER 564 select ARCH_SUPPORTS_BIG_ENDIAN 565 566config ARCH_AIROHA 567 bool "Airoha SoC Support" 568 depends on ARCH_MULTI_V7 569 select ARM_AMBA 570 select ARM_GIC 571 select ARM_GIC_V3 572 select ARM_PSCI 573 select HAVE_ARM_ARCH_TIMER 574 select COMMON_CLK 575 help 576 Support for Airoha EN7523 SoCs 577 578# 579# This is sorted alphabetically by mach-* pathname. However, plat-* 580# Kconfigs may be included either alphabetically (according to the 581# plat- suffix) or along side the corresponding mach-* source. 582# 583source "arch/arm/mach-actions/Kconfig" 584 585source "arch/arm/mach-alpine/Kconfig" 586 587source "arch/arm/mach-artpec/Kconfig" 588 589source "arch/arm/mach-asm9260/Kconfig" 590 591source "arch/arm/mach-aspeed/Kconfig" 592 593source "arch/arm/mach-at91/Kconfig" 594 595source "arch/arm/mach-axxia/Kconfig" 596 597source "arch/arm/mach-bcm/Kconfig" 598 599source "arch/arm/mach-berlin/Kconfig" 600 601source "arch/arm/mach-clps711x/Kconfig" 602 603source "arch/arm/mach-cns3xxx/Kconfig" 604 605source "arch/arm/mach-davinci/Kconfig" 606 607source "arch/arm/mach-digicolor/Kconfig" 608 609source "arch/arm/mach-dove/Kconfig" 610 611source "arch/arm/mach-ep93xx/Kconfig" 612 613source "arch/arm/mach-exynos/Kconfig" 614 615source "arch/arm/mach-footbridge/Kconfig" 616 617source "arch/arm/mach-gemini/Kconfig" 618 619source "arch/arm/mach-highbank/Kconfig" 620 621source "arch/arm/mach-hisi/Kconfig" 622 623source "arch/arm/mach-imx/Kconfig" 624 625source "arch/arm/mach-integrator/Kconfig" 626 627source "arch/arm/mach-iop32x/Kconfig" 628 629source "arch/arm/mach-ixp4xx/Kconfig" 630 631source "arch/arm/mach-keystone/Kconfig" 632 633source "arch/arm/mach-lpc32xx/Kconfig" 634 635source "arch/arm/mach-mediatek/Kconfig" 636 637source "arch/arm/mach-meson/Kconfig" 638 639source "arch/arm/mach-milbeaut/Kconfig" 640 641source "arch/arm/mach-mmp/Kconfig" 642 643source "arch/arm/mach-moxart/Kconfig" 644 645source "arch/arm/mach-mstar/Kconfig" 646 647source "arch/arm/mach-mv78xx0/Kconfig" 648 649source "arch/arm/mach-mvebu/Kconfig" 650 651source "arch/arm/mach-mxs/Kconfig" 652 653source "arch/arm/mach-nomadik/Kconfig" 654 655source "arch/arm/mach-npcm/Kconfig" 656 657source "arch/arm/mach-nspire/Kconfig" 658 659source "arch/arm/plat-omap/Kconfig" 660 661source "arch/arm/mach-omap1/Kconfig" 662 663source "arch/arm/mach-omap2/Kconfig" 664 665source "arch/arm/mach-orion5x/Kconfig" 666 667source "arch/arm/mach-oxnas/Kconfig" 668 669source "arch/arm/mach-pxa/Kconfig" 670source "arch/arm/plat-pxa/Kconfig" 671 672source "arch/arm/mach-qcom/Kconfig" 673 674source "arch/arm/mach-rda/Kconfig" 675 676source "arch/arm/mach-realtek/Kconfig" 677 678source "arch/arm/mach-realview/Kconfig" 679 680source "arch/arm/mach-rockchip/Kconfig" 681 682source "arch/arm/mach-s3c/Kconfig" 683 684source "arch/arm/mach-s5pv210/Kconfig" 685 686source "arch/arm/mach-sa1100/Kconfig" 687 688source "arch/arm/mach-shmobile/Kconfig" 689 690source "arch/arm/mach-socfpga/Kconfig" 691 692source "arch/arm/mach-spear/Kconfig" 693 694source "arch/arm/mach-sti/Kconfig" 695 696source "arch/arm/mach-stm32/Kconfig" 697 698source "arch/arm/mach-sunxi/Kconfig" 699 700source "arch/arm/mach-tegra/Kconfig" 701 702source "arch/arm/mach-uniphier/Kconfig" 703 704source "arch/arm/mach-ux500/Kconfig" 705 706source "arch/arm/mach-versatile/Kconfig" 707 708source "arch/arm/mach-vexpress/Kconfig" 709 710source "arch/arm/mach-vt8500/Kconfig" 711 712source "arch/arm/mach-zynq/Kconfig" 713 714# ARMv7-M architecture 715config ARCH_LPC18XX 716 bool "NXP LPC18xx/LPC43xx" 717 depends on ARM_SINGLE_ARMV7M 718 select ARCH_HAS_RESET_CONTROLLER 719 select ARM_AMBA 720 select CLKSRC_LPC32XX 721 select PINCTRL 722 help 723 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 724 high performance microcontrollers. 725 726config ARCH_MPS2 727 bool "ARM MPS2 platform" 728 depends on ARM_SINGLE_ARMV7M 729 select ARM_AMBA 730 select CLKSRC_MPS2 731 help 732 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 733 with a range of available cores like Cortex-M3/M4/M7. 734 735 Please, note that depends which Application Note is used memory map 736 for the platform may vary, so adjustment of RAM base might be needed. 737 738# Definitions to make life easier 739config ARCH_ACORN 740 bool 741 742config PLAT_IOP 743 bool 744 745config PLAT_ORION 746 bool 747 select CLKSRC_MMIO 748 select COMMON_CLK 749 select GENERIC_IRQ_CHIP 750 select IRQ_DOMAIN 751 752config PLAT_ORION_LEGACY 753 bool 754 select PLAT_ORION 755 756config PLAT_PXA 757 bool 758 759config PLAT_VERSATILE 760 bool 761 762source "arch/arm/mm/Kconfig" 763 764config IWMMXT 765 bool "Enable iWMMXt support" 766 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 767 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 768 help 769 Enable support for iWMMXt context switching at run time if 770 running on a CPU that supports it. 771 772if !MMU 773source "arch/arm/Kconfig-nommu" 774endif 775 776config PJ4B_ERRATA_4742 777 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 778 depends on CPU_PJ4B && MACH_ARMADA_370 779 default y 780 help 781 When coming out of either a Wait for Interrupt (WFI) or a Wait for 782 Event (WFE) IDLE states, a specific timing sensitivity exists between 783 the retiring WFI/WFE instructions and the newly issued subsequent 784 instructions. This sensitivity can result in a CPU hang scenario. 785 Workaround: 786 The software must insert either a Data Synchronization Barrier (DSB) 787 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 788 instruction 789 790config ARM_ERRATA_326103 791 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 792 depends on CPU_V6 793 help 794 Executing a SWP instruction to read-only memory does not set bit 11 795 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 796 treat the access as a read, preventing a COW from occurring and 797 causing the faulting task to livelock. 798 799config ARM_ERRATA_411920 800 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 801 depends on CPU_V6 || CPU_V6K 802 help 803 Invalidation of the Instruction Cache operation can 804 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 805 It does not affect the MPCore. This option enables the ARM Ltd. 806 recommended workaround. 807 808config ARM_ERRATA_430973 809 bool "ARM errata: Stale prediction on replaced interworking branch" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 430973 Cortex-A8 813 r1p* erratum. If a code sequence containing an ARM/Thumb 814 interworking branch is replaced with another code sequence at the 815 same virtual address, whether due to self-modifying code or virtual 816 to physical address re-mapping, Cortex-A8 does not recover from the 817 stale interworking branch prediction. This results in Cortex-A8 818 executing the new code sequence in the incorrect ARM or Thumb state. 819 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 820 and also flushes the branch target cache at every context switch. 821 Note that setting specific bits in the ACTLR register may not be 822 available in non-secure mode. 823 824config ARM_ERRATA_458693 825 bool "ARM errata: Processor deadlock when a false hazard is created" 826 depends on CPU_V7 827 depends on !ARCH_MULTIPLATFORM 828 help 829 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 830 erratum. For very specific sequences of memory operations, it is 831 possible for a hazard condition intended for a cache line to instead 832 be incorrectly associated with a different cache line. This false 833 hazard might then cause a processor deadlock. The workaround enables 834 the L1 caching of the NEON accesses and disables the PLD instruction 835 in the ACTLR register. Note that setting specific bits in the ACTLR 836 register may not be available in non-secure mode. 837 838config ARM_ERRATA_460075 839 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 840 depends on CPU_V7 841 depends on !ARCH_MULTIPLATFORM 842 help 843 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 844 erratum. Any asynchronous access to the L2 cache may encounter a 845 situation in which recent store transactions to the L2 cache are lost 846 and overwritten with stale memory contents from external memory. The 847 workaround disables the write-allocate mode for the L2 cache via the 848 ACTLR register. Note that setting specific bits in the ACTLR register 849 may not be available in non-secure mode. 850 851config ARM_ERRATA_742230 852 bool "ARM errata: DMB operation may be faulty" 853 depends on CPU_V7 && SMP 854 depends on !ARCH_MULTIPLATFORM 855 help 856 This option enables the workaround for the 742230 Cortex-A9 857 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 858 between two write operations may not ensure the correct visibility 859 ordering of the two writes. This workaround sets a specific bit in 860 the diagnostic register of the Cortex-A9 which causes the DMB 861 instruction to behave as a DSB, ensuring the correct behaviour of 862 the two writes. 863 864config ARM_ERRATA_742231 865 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 866 depends on CPU_V7 && SMP 867 depends on !ARCH_MULTIPLATFORM 868 help 869 This option enables the workaround for the 742231 Cortex-A9 870 (r2p0..r2p2) erratum. Under certain conditions, specific to the 871 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 872 accessing some data located in the same cache line, may get corrupted 873 data due to bad handling of the address hazard when the line gets 874 replaced from one of the CPUs at the same time as another CPU is 875 accessing it. This workaround sets specific bits in the diagnostic 876 register of the Cortex-A9 which reduces the linefill issuing 877 capabilities of the processor. 878 879config ARM_ERRATA_643719 880 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 881 depends on CPU_V7 && SMP 882 default y 883 help 884 This option enables the workaround for the 643719 Cortex-A9 (prior to 885 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 886 register returns zero when it should return one. The workaround 887 corrects this value, ensuring cache maintenance operations which use 888 it behave as intended and avoiding data corruption. 889 890config ARM_ERRATA_720789 891 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 892 depends on CPU_V7 893 help 894 This option enables the workaround for the 720789 Cortex-A9 (prior to 895 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 896 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 897 As a consequence of this erratum, some TLB entries which should be 898 invalidated are not, resulting in an incoherency in the system page 899 tables. The workaround changes the TLB flushing routines to invalidate 900 entries regardless of the ASID. 901 902config ARM_ERRATA_743622 903 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 904 depends on CPU_V7 905 depends on !ARCH_MULTIPLATFORM 906 help 907 This option enables the workaround for the 743622 Cortex-A9 908 (r2p*) erratum. Under very rare conditions, a faulty 909 optimisation in the Cortex-A9 Store Buffer may lead to data 910 corruption. This workaround sets a specific bit in the diagnostic 911 register of the Cortex-A9 which disables the Store Buffer 912 optimisation, preventing the defect from occurring. This has no 913 visible impact on the overall performance or power consumption of the 914 processor. 915 916config ARM_ERRATA_751472 917 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 918 depends on CPU_V7 919 depends on !ARCH_MULTIPLATFORM 920 help 921 This option enables the workaround for the 751472 Cortex-A9 (prior 922 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 923 completion of a following broadcasted operation if the second 924 operation is received by a CPU before the ICIALLUIS has completed, 925 potentially leading to corrupted entries in the cache or TLB. 926 927config ARM_ERRATA_754322 928 bool "ARM errata: possible faulty MMU translations following an ASID switch" 929 depends on CPU_V7 930 help 931 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 932 r3p*) erratum. A speculative memory access may cause a page table walk 933 which starts prior to an ASID switch but completes afterwards. This 934 can populate the micro-TLB with a stale entry which may be hit with 935 the new ASID. This workaround places two dsb instructions in the mm 936 switching code so that no page table walks can cross the ASID switch. 937 938config ARM_ERRATA_754327 939 bool "ARM errata: no automatic Store Buffer drain" 940 depends on CPU_V7 && SMP 941 help 942 This option enables the workaround for the 754327 Cortex-A9 (prior to 943 r2p0) erratum. The Store Buffer does not have any automatic draining 944 mechanism and therefore a livelock may occur if an external agent 945 continuously polls a memory location waiting to observe an update. 946 This workaround defines cpu_relax() as smp_mb(), preventing correctly 947 written polling loops from denying visibility of updates to memory. 948 949config ARM_ERRATA_364296 950 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 951 depends on CPU_V6 952 help 953 This options enables the workaround for the 364296 ARM1136 954 r0p2 erratum (possible cache data corruption with 955 hit-under-miss enabled). It sets the undocumented bit 31 in 956 the auxiliary control register and the FI bit in the control 957 register, thus disabling hit-under-miss without putting the 958 processor into full low interrupt latency mode. ARM11MPCore 959 is not affected. 960 961config ARM_ERRATA_764369 962 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 963 depends on CPU_V7 && SMP 964 help 965 This option enables the workaround for erratum 764369 966 affecting Cortex-A9 MPCore with two or more processors (all 967 current revisions). Under certain timing circumstances, a data 968 cache line maintenance operation by MVA targeting an Inner 969 Shareable memory region may fail to proceed up to either the 970 Point of Coherency or to the Point of Unification of the 971 system. This workaround adds a DSB instruction before the 972 relevant cache maintenance functions and sets a specific bit 973 in the diagnostic control register of the SCU. 974 975config ARM_ERRATA_764319 976 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 764319 Cortex A-9 erratum. 980 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 981 unexpected Undefined Instruction exception when the DBGSWENABLE 982 external pin is set to 0, even when the CP14 accesses are performed 983 from a privileged mode. This work around catches the exception in a 984 way the kernel does not stop execution. 985 986config ARM_ERRATA_775420 987 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 988 depends on CPU_V7 989 help 990 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 991 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 992 operation aborts with MMU exception, it might cause the processor 993 to deadlock. This workaround puts DSB before executing ISB if 994 an abort may occur on cache maintenance. 995 996config ARM_ERRATA_798181 997 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 998 depends on CPU_V7 && SMP 999 help 1000 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1001 adequately shooting down all use of the old entries. This 1002 option enables the Linux kernel workaround for this erratum 1003 which sends an IPI to the CPUs that are running the same ASID 1004 as the one being invalidated. 1005 1006config ARM_ERRATA_773022 1007 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1008 depends on CPU_V7 1009 help 1010 This option enables the workaround for the 773022 Cortex-A15 1011 (up to r0p4) erratum. In certain rare sequences of code, the 1012 loop buffer may deliver incorrect instructions. This 1013 workaround disables the loop buffer to avoid the erratum. 1014 1015config ARM_ERRATA_818325_852422 1016 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1017 depends on CPU_V7 1018 help 1019 This option enables the workaround for: 1020 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1021 instruction might deadlock. Fixed in r0p1. 1022 - Cortex-A12 852422: Execution of a sequence of instructions might 1023 lead to either a data corruption or a CPU deadlock. Not fixed in 1024 any Cortex-A12 cores yet. 1025 This workaround for all both errata involves setting bit[12] of the 1026 Feature Register. This bit disables an optimisation applied to a 1027 sequence of 2 instructions that use opposing condition codes. 1028 1029config ARM_ERRATA_821420 1030 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1031 depends on CPU_V7 1032 help 1033 This option enables the workaround for the 821420 Cortex-A12 1034 (all revs) erratum. In very rare timing conditions, a sequence 1035 of VMOV to Core registers instructions, for which the second 1036 one is in the shadow of a branch or abort, can lead to a 1037 deadlock when the VMOV instructions are issued out-of-order. 1038 1039config ARM_ERRATA_825619 1040 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1041 depends on CPU_V7 1042 help 1043 This option enables the workaround for the 825619 Cortex-A12 1044 (all revs) erratum. Within rare timing constraints, executing a 1045 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1046 and Device/Strongly-Ordered loads and stores might cause deadlock 1047 1048config ARM_ERRATA_857271 1049 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1050 depends on CPU_V7 1051 help 1052 This option enables the workaround for the 857271 Cortex-A12 1053 (all revs) erratum. Under very rare timing conditions, the CPU might 1054 hang. The workaround is expected to have a < 1% performance impact. 1055 1056config ARM_ERRATA_852421 1057 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1058 depends on CPU_V7 1059 help 1060 This option enables the workaround for the 852421 Cortex-A17 1061 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1062 execution of a DMB ST instruction might fail to properly order 1063 stores from GroupA and stores from GroupB. 1064 1065config ARM_ERRATA_852423 1066 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1067 depends on CPU_V7 1068 help 1069 This option enables the workaround for: 1070 - Cortex-A17 852423: Execution of a sequence of instructions might 1071 lead to either a data corruption or a CPU deadlock. Not fixed in 1072 any Cortex-A17 cores yet. 1073 This is identical to Cortex-A12 erratum 852422. It is a separate 1074 config option from the A12 erratum due to the way errata are checked 1075 for and handled. 1076 1077config ARM_ERRATA_857272 1078 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1079 depends on CPU_V7 1080 help 1081 This option enables the workaround for the 857272 Cortex-A17 erratum. 1082 This erratum is not known to be fixed in any A17 revision. 1083 This is identical to Cortex-A12 erratum 857271. It is a separate 1084 config option from the A12 erratum due to the way errata are checked 1085 for and handled. 1086 1087endmenu 1088 1089source "arch/arm/common/Kconfig" 1090 1091menu "Bus support" 1092 1093config ISA 1094 bool 1095 help 1096 Find out whether you have ISA slots on your motherboard. ISA is the 1097 name of a bus system, i.e. the way the CPU talks to the other stuff 1098 inside your box. Other bus systems are PCI, EISA, MicroChannel 1099 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1100 newer boards don't support it. If you have ISA, say Y, otherwise N. 1101 1102# Select ISA DMA controller support 1103config ISA_DMA 1104 bool 1105 select ISA_DMA_API 1106 1107# Select ISA DMA interface 1108config ISA_DMA_API 1109 bool 1110 1111config PCI_NANOENGINE 1112 bool "BSE nanoEngine PCI support" 1113 depends on SA1100_NANOENGINE 1114 help 1115 Enable PCI on the BSE nanoEngine board. 1116 1117config ARM_ERRATA_814220 1118 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1119 depends on CPU_V7 1120 help 1121 The v7 ARM states that all cache and branch predictor maintenance 1122 operations that do not specify an address execute, relative to 1123 each other, in program order. 1124 However, because of this erratum, an L2 set/way cache maintenance 1125 operation can overtake an L1 set/way cache maintenance operation. 1126 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1127 r0p4, r0p5. 1128 1129endmenu 1130 1131menu "Kernel Features" 1132 1133config HAVE_SMP 1134 bool 1135 help 1136 This option should be selected by machines which have an SMP- 1137 capable CPU. 1138 1139 The only effect of this option is to make the SMP-related 1140 options available to the user for configuration. 1141 1142config SMP 1143 bool "Symmetric Multi-Processing" 1144 depends on CPU_V6K || CPU_V7 1145 depends on HAVE_SMP 1146 depends on MMU || ARM_MPU 1147 select IRQ_WORK 1148 help 1149 This enables support for systems with more than one CPU. If you have 1150 a system with only one CPU, say N. If you have a system with more 1151 than one CPU, say Y. 1152 1153 If you say N here, the kernel will run on uni- and multiprocessor 1154 machines, but will use only one CPU of a multiprocessor machine. If 1155 you say Y here, the kernel will run on many, but not all, 1156 uniprocessor machines. On a uniprocessor machine, the kernel 1157 will run faster if you say N here. 1158 1159 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1160 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1161 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1162 1163 If you don't know what to do here, say N. 1164 1165config SMP_ON_UP 1166 bool "Allow booting SMP kernel on uniprocessor systems" 1167 depends on SMP && !XIP_KERNEL && MMU 1168 default y 1169 help 1170 SMP kernels contain instructions which fail on non-SMP processors. 1171 Enabling this option allows the kernel to modify itself to make 1172 these instructions safe. Disabling it allows about 1K of space 1173 savings. 1174 1175 If you don't know what to do here, say Y. 1176 1177 1178config CURRENT_POINTER_IN_TPIDRURO 1179 def_bool y 1180 depends on CPU_32v6K && !CPU_V6 1181 1182config IRQSTACKS 1183 def_bool y 1184 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1185 select HAVE_SOFTIRQ_ON_OWN_STACK 1186 1187config ARM_CPU_TOPOLOGY 1188 bool "Support cpu topology definition" 1189 depends on SMP && CPU_V7 1190 default y 1191 help 1192 Support ARM cpu topology definition. The MPIDR register defines 1193 affinity between processors which is then used to describe the cpu 1194 topology of an ARM System. 1195 1196config SCHED_MC 1197 bool "Multi-core scheduler support" 1198 depends on ARM_CPU_TOPOLOGY 1199 help 1200 Multi-core scheduler support improves the CPU scheduler's decision 1201 making when dealing with multi-core CPU chips at a cost of slightly 1202 increased overhead in some places. If unsure say N here. 1203 1204config SCHED_SMT 1205 bool "SMT scheduler support" 1206 depends on ARM_CPU_TOPOLOGY 1207 help 1208 Improves the CPU scheduler's decision making when dealing with 1209 MultiThreading at a cost of slightly increased overhead in some 1210 places. If unsure say N here. 1211 1212config HAVE_ARM_SCU 1213 bool 1214 help 1215 This option enables support for the ARM snoop control unit 1216 1217config HAVE_ARM_ARCH_TIMER 1218 bool "Architected timer support" 1219 depends on CPU_V7 1220 select ARM_ARCH_TIMER 1221 help 1222 This option enables support for the ARM architected timer 1223 1224config HAVE_ARM_TWD 1225 bool 1226 help 1227 This options enables support for the ARM timer and watchdog unit 1228 1229config MCPM 1230 bool "Multi-Cluster Power Management" 1231 depends on CPU_V7 && SMP 1232 help 1233 This option provides the common power management infrastructure 1234 for (multi-)cluster based systems, such as big.LITTLE based 1235 systems. 1236 1237config MCPM_QUAD_CLUSTER 1238 bool 1239 depends on MCPM 1240 help 1241 To avoid wasting resources unnecessarily, MCPM only supports up 1242 to 2 clusters by default. 1243 Platforms with 3 or 4 clusters that use MCPM must select this 1244 option to allow the additional clusters to be managed. 1245 1246config BIG_LITTLE 1247 bool "big.LITTLE support (Experimental)" 1248 depends on CPU_V7 && SMP 1249 select MCPM 1250 help 1251 This option enables support selections for the big.LITTLE 1252 system architecture. 1253 1254config BL_SWITCHER 1255 bool "big.LITTLE switcher support" 1256 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1257 select CPU_PM 1258 help 1259 The big.LITTLE "switcher" provides the core functionality to 1260 transparently handle transition between a cluster of A15's 1261 and a cluster of A7's in a big.LITTLE system. 1262 1263config BL_SWITCHER_DUMMY_IF 1264 tristate "Simple big.LITTLE switcher user interface" 1265 depends on BL_SWITCHER && DEBUG_KERNEL 1266 help 1267 This is a simple and dummy char dev interface to control 1268 the big.LITTLE switcher core code. It is meant for 1269 debugging purposes only. 1270 1271choice 1272 prompt "Memory split" 1273 depends on MMU 1274 default VMSPLIT_3G 1275 help 1276 Select the desired split between kernel and user memory. 1277 1278 If you are not absolutely sure what you are doing, leave this 1279 option alone! 1280 1281 config VMSPLIT_3G 1282 bool "3G/1G user/kernel split" 1283 config VMSPLIT_3G_OPT 1284 depends on !ARM_LPAE 1285 bool "3G/1G user/kernel split (for full 1G low memory)" 1286 config VMSPLIT_2G 1287 bool "2G/2G user/kernel split" 1288 config VMSPLIT_1G 1289 bool "1G/3G user/kernel split" 1290endchoice 1291 1292config PAGE_OFFSET 1293 hex 1294 default PHYS_OFFSET if !MMU 1295 default 0x40000000 if VMSPLIT_1G 1296 default 0x80000000 if VMSPLIT_2G 1297 default 0xB0000000 if VMSPLIT_3G_OPT 1298 default 0xC0000000 1299 1300config KASAN_SHADOW_OFFSET 1301 hex 1302 depends on KASAN 1303 default 0x1f000000 if PAGE_OFFSET=0x40000000 1304 default 0x5f000000 if PAGE_OFFSET=0x80000000 1305 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1306 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1307 default 0xffffffff 1308 1309config NR_CPUS 1310 int "Maximum number of CPUs (2-32)" 1311 range 2 16 if DEBUG_KMAP_LOCAL 1312 range 2 32 if !DEBUG_KMAP_LOCAL 1313 depends on SMP 1314 default "4" 1315 help 1316 The maximum number of CPUs that the kernel can support. 1317 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1318 debugging is enabled, which uses half of the per-CPU fixmap 1319 slots as guard regions. 1320 1321config HOTPLUG_CPU 1322 bool "Support for hot-pluggable CPUs" 1323 depends on SMP 1324 select GENERIC_IRQ_MIGRATION 1325 help 1326 Say Y here to experiment with turning CPUs off and on. CPUs 1327 can be controlled through /sys/devices/system/cpu. 1328 1329config ARM_PSCI 1330 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1331 depends on HAVE_ARM_SMCCC 1332 select ARM_PSCI_FW 1333 help 1334 Say Y here if you want Linux to communicate with system firmware 1335 implementing the PSCI specification for CPU-centric power 1336 management operations described in ARM document number ARM DEN 1337 0022A ("Power State Coordination Interface System Software on 1338 ARM processors"). 1339 1340# The GPIO number here must be sorted by descending number. In case of 1341# a multiplatform kernel, we just want the highest value required by the 1342# selected platforms. 1343config ARCH_NR_GPIO 1344 int 1345 default 2048 if ARCH_INTEL_SOCFPGA 1346 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1347 ARCH_ZYNQ || ARCH_ASPEED 1348 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1349 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1350 default 416 if ARCH_SUNXI 1351 default 392 if ARCH_U8500 1352 default 352 if ARCH_VT8500 1353 default 288 if ARCH_ROCKCHIP 1354 default 264 if MACH_H4700 1355 default 0 1356 help 1357 Maximum number of GPIOs in the system. 1358 1359 If unsure, leave the default value. 1360 1361config HZ_FIXED 1362 int 1363 default 128 if SOC_AT91RM9200 1364 default 0 1365 1366choice 1367 depends on HZ_FIXED = 0 1368 prompt "Timer frequency" 1369 1370config HZ_100 1371 bool "100 Hz" 1372 1373config HZ_200 1374 bool "200 Hz" 1375 1376config HZ_250 1377 bool "250 Hz" 1378 1379config HZ_300 1380 bool "300 Hz" 1381 1382config HZ_500 1383 bool "500 Hz" 1384 1385config HZ_1000 1386 bool "1000 Hz" 1387 1388endchoice 1389 1390config HZ 1391 int 1392 default HZ_FIXED if HZ_FIXED != 0 1393 default 100 if HZ_100 1394 default 200 if HZ_200 1395 default 250 if HZ_250 1396 default 300 if HZ_300 1397 default 500 if HZ_500 1398 default 1000 1399 1400config SCHED_HRTICK 1401 def_bool HIGH_RES_TIMERS 1402 1403config THUMB2_KERNEL 1404 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1405 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1406 default y if CPU_THUMBONLY 1407 select ARM_UNWIND 1408 help 1409 By enabling this option, the kernel will be compiled in 1410 Thumb-2 mode. 1411 1412 If unsure, say N. 1413 1414config ARM_PATCH_IDIV 1415 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1416 depends on CPU_32v7 && !XIP_KERNEL 1417 default y 1418 help 1419 The ARM compiler inserts calls to __aeabi_idiv() and 1420 __aeabi_uidiv() when it needs to perform division on signed 1421 and unsigned integers. Some v7 CPUs have support for the sdiv 1422 and udiv instructions that can be used to implement those 1423 functions. 1424 1425 Enabling this option allows the kernel to modify itself to 1426 replace the first two instructions of these library functions 1427 with the sdiv or udiv plus "bx lr" instructions when the CPU 1428 it is running on supports them. Typically this will be faster 1429 and less power intensive than running the original library 1430 code to do integer division. 1431 1432config AEABI 1433 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1434 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1435 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1436 help 1437 This option allows for the kernel to be compiled using the latest 1438 ARM ABI (aka EABI). This is only useful if you are using a user 1439 space environment that is also compiled with EABI. 1440 1441 Since there are major incompatibilities between the legacy ABI and 1442 EABI, especially with regard to structure member alignment, this 1443 option also changes the kernel syscall calling convention to 1444 disambiguate both ABIs and allow for backward compatibility support 1445 (selected with CONFIG_OABI_COMPAT). 1446 1447 To use this you need GCC version 4.0.0 or later. 1448 1449config OABI_COMPAT 1450 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1451 depends on AEABI && !THUMB2_KERNEL 1452 help 1453 This option preserves the old syscall interface along with the 1454 new (ARM EABI) one. It also provides a compatibility layer to 1455 intercept syscalls that have structure arguments which layout 1456 in memory differs between the legacy ABI and the new ARM EABI 1457 (only for non "thumb" binaries). This option adds a tiny 1458 overhead to all syscalls and produces a slightly larger kernel. 1459 1460 The seccomp filter system will not be available when this is 1461 selected, since there is no way yet to sensibly distinguish 1462 between calling conventions during filtering. 1463 1464 If you know you'll be using only pure EABI user space then you 1465 can say N here. If this option is not selected and you attempt 1466 to execute a legacy ABI binary then the result will be 1467 UNPREDICTABLE (in fact it can be predicted that it won't work 1468 at all). If in doubt say N. 1469 1470config ARCH_SELECT_MEMORY_MODEL 1471 bool 1472 1473config ARCH_FLATMEM_ENABLE 1474 bool 1475 1476config ARCH_SPARSEMEM_ENABLE 1477 bool 1478 select SPARSEMEM_STATIC if SPARSEMEM 1479 1480config HIGHMEM 1481 bool "High Memory Support" 1482 depends on MMU 1483 select KMAP_LOCAL 1484 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1485 help 1486 The address space of ARM processors is only 4 Gigabytes large 1487 and it has to accommodate user address space, kernel address 1488 space as well as some memory mapped IO. That means that, if you 1489 have a large amount of physical memory and/or IO, not all of the 1490 memory can be "permanently mapped" by the kernel. The physical 1491 memory that is not permanently mapped is called "high memory". 1492 1493 Depending on the selected kernel/user memory split, minimum 1494 vmalloc space and actual amount of RAM, you may not need this 1495 option which should result in a slightly faster kernel. 1496 1497 If unsure, say n. 1498 1499config HIGHPTE 1500 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1501 depends on HIGHMEM 1502 default y 1503 help 1504 The VM uses one page of physical memory for each page table. 1505 For systems with a lot of processes, this can use a lot of 1506 precious low memory, eventually leading to low memory being 1507 consumed by page tables. Setting this option will allow 1508 user-space 2nd level page tables to reside in high memory. 1509 1510config CPU_SW_DOMAIN_PAN 1511 bool "Enable use of CPU domains to implement privileged no-access" 1512 depends on MMU && !ARM_LPAE 1513 default y 1514 help 1515 Increase kernel security by ensuring that normal kernel accesses 1516 are unable to access userspace addresses. This can help prevent 1517 use-after-free bugs becoming an exploitable privilege escalation 1518 by ensuring that magic values (such as LIST_POISON) will always 1519 fault when dereferenced. 1520 1521 CPUs with low-vector mappings use a best-efforts implementation. 1522 Their lower 1MB needs to remain accessible for the vectors, but 1523 the remainder of userspace will become appropriately inaccessible. 1524 1525config HW_PERF_EVENTS 1526 def_bool y 1527 depends on ARM_PMU 1528 1529config ARM_MODULE_PLTS 1530 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1531 depends on MODULES 1532 default y 1533 help 1534 Allocate PLTs when loading modules so that jumps and calls whose 1535 targets are too far away for their relative offsets to be encoded 1536 in the instructions themselves can be bounced via veneers in the 1537 module's PLT. This allows modules to be allocated in the generic 1538 vmalloc area after the dedicated module memory area has been 1539 exhausted. The modules will use slightly more memory, but after 1540 rounding up to page size, the actual memory footprint is usually 1541 the same. 1542 1543 Disabling this is usually safe for small single-platform 1544 configurations. If unsure, say y. 1545 1546config FORCE_MAX_ZONEORDER 1547 int "Maximum zone order" 1548 default "12" if SOC_AM33XX 1549 default "9" if SA1111 1550 default "11" 1551 help 1552 The kernel memory allocator divides physically contiguous memory 1553 blocks into "zones", where each zone is a power of two number of 1554 pages. This option selects the largest power of two that the kernel 1555 keeps in the memory allocator. If you need to allocate very large 1556 blocks of physically contiguous memory, then you may need to 1557 increase this value. 1558 1559 This config option is actually maximum order plus one. For example, 1560 a value of 11 means that the largest free memory block is 2^10 pages. 1561 1562config ALIGNMENT_TRAP 1563 def_bool CPU_CP15_MMU 1564 select HAVE_PROC_CPU if PROC_FS 1565 help 1566 ARM processors cannot fetch/store information which is not 1567 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1568 address divisible by 4. On 32-bit ARM processors, these non-aligned 1569 fetch/store instructions will be emulated in software if you say 1570 here, which has a severe performance impact. This is necessary for 1571 correct operation of some network protocols. With an IP-only 1572 configuration it is safe to say N, otherwise say Y. 1573 1574config UACCESS_WITH_MEMCPY 1575 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1576 depends on MMU 1577 default y if CPU_FEROCEON 1578 help 1579 Implement faster copy_to_user and clear_user methods for CPU 1580 cores where a 8-word STM instruction give significantly higher 1581 memory write throughput than a sequence of individual 32bit stores. 1582 1583 A possible side effect is a slight increase in scheduling latency 1584 between threads sharing the same address space if they invoke 1585 such copy operations with large buffers. 1586 1587 However, if the CPU data cache is using a write-allocate mode, 1588 this option is unlikely to provide any performance gain. 1589 1590config PARAVIRT 1591 bool "Enable paravirtualization code" 1592 help 1593 This changes the kernel so it can modify itself when it is run 1594 under a hypervisor, potentially improving performance significantly 1595 over full virtualization. 1596 1597config PARAVIRT_TIME_ACCOUNTING 1598 bool "Paravirtual steal time accounting" 1599 select PARAVIRT 1600 help 1601 Select this option to enable fine granularity task steal time 1602 accounting. Time spent executing other tasks in parallel with 1603 the current vCPU is discounted from the vCPU power. To account for 1604 that, there can be a small performance impact. 1605 1606 If in doubt, say N here. 1607 1608config XEN_DOM0 1609 def_bool y 1610 depends on XEN 1611 1612config XEN 1613 bool "Xen guest support on ARM" 1614 depends on ARM && AEABI && OF 1615 depends on CPU_V7 && !CPU_V6 1616 depends on !GENERIC_ATOMIC64 1617 depends on MMU 1618 select ARCH_DMA_ADDR_T_64BIT 1619 select ARM_PSCI 1620 select SWIOTLB 1621 select SWIOTLB_XEN 1622 select PARAVIRT 1623 help 1624 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1625 1626config CC_HAVE_STACKPROTECTOR_TLS 1627 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1628 1629config STACKPROTECTOR_PER_TASK 1630 bool "Use a unique stack canary value for each task" 1631 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1632 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1633 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1634 default y 1635 help 1636 Due to the fact that GCC uses an ordinary symbol reference from 1637 which to load the value of the stack canary, this value can only 1638 change at reboot time on SMP systems, and all tasks running in the 1639 kernel's address space are forced to use the same canary value for 1640 the entire duration that the system is up. 1641 1642 Enable this option to switch to a different method that uses a 1643 different canary value for each task. 1644 1645endmenu 1646 1647menu "Boot options" 1648 1649config USE_OF 1650 bool "Flattened Device Tree support" 1651 select IRQ_DOMAIN 1652 select OF 1653 help 1654 Include support for flattened device tree machine descriptions. 1655 1656config ATAGS 1657 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1658 default y 1659 help 1660 This is the traditional way of passing data to the kernel at boot 1661 time. If you are solely relying on the flattened device tree (or 1662 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1663 to remove ATAGS support from your kernel binary. If unsure, 1664 leave this to y. 1665 1666config DEPRECATED_PARAM_STRUCT 1667 bool "Provide old way to pass kernel parameters" 1668 depends on ATAGS 1669 help 1670 This was deprecated in 2001 and announced to live on for 5 years. 1671 Some old boot loaders still use this way. 1672 1673# Compressed boot loader in ROM. Yes, we really want to ask about 1674# TEXT and BSS so we preserve their values in the config files. 1675config ZBOOT_ROM_TEXT 1676 hex "Compressed ROM boot loader base address" 1677 default 0x0 1678 help 1679 The physical address at which the ROM-able zImage is to be 1680 placed in the target. Platforms which normally make use of 1681 ROM-able zImage formats normally set this to a suitable 1682 value in their defconfig file. 1683 1684 If ZBOOT_ROM is not enabled, this has no effect. 1685 1686config ZBOOT_ROM_BSS 1687 hex "Compressed ROM boot loader BSS address" 1688 default 0x0 1689 help 1690 The base address of an area of read/write memory in the target 1691 for the ROM-able zImage which must be available while the 1692 decompressor is running. It must be large enough to hold the 1693 entire decompressed kernel plus an additional 128 KiB. 1694 Platforms which normally make use of ROM-able zImage formats 1695 normally set this to a suitable value in their defconfig file. 1696 1697 If ZBOOT_ROM is not enabled, this has no effect. 1698 1699config ZBOOT_ROM 1700 bool "Compressed boot loader in ROM/flash" 1701 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1702 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1703 help 1704 Say Y here if you intend to execute your compressed kernel image 1705 (zImage) directly from ROM or flash. If unsure, say N. 1706 1707config ARM_APPENDED_DTB 1708 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1709 depends on OF 1710 help 1711 With this option, the boot code will look for a device tree binary 1712 (DTB) appended to zImage 1713 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1714 1715 This is meant as a backward compatibility convenience for those 1716 systems with a bootloader that can't be upgraded to accommodate 1717 the documented boot protocol using a device tree. 1718 1719 Beware that there is very little in terms of protection against 1720 this option being confused by leftover garbage in memory that might 1721 look like a DTB header after a reboot if no actual DTB is appended 1722 to zImage. Do not leave this option active in a production kernel 1723 if you don't intend to always append a DTB. Proper passing of the 1724 location into r2 of a bootloader provided DTB is always preferable 1725 to this option. 1726 1727config ARM_ATAG_DTB_COMPAT 1728 bool "Supplement the appended DTB with traditional ATAG information" 1729 depends on ARM_APPENDED_DTB 1730 help 1731 Some old bootloaders can't be updated to a DTB capable one, yet 1732 they provide ATAGs with memory configuration, the ramdisk address, 1733 the kernel cmdline string, etc. Such information is dynamically 1734 provided by the bootloader and can't always be stored in a static 1735 DTB. To allow a device tree enabled kernel to be used with such 1736 bootloaders, this option allows zImage to extract the information 1737 from the ATAG list and store it at run time into the appended DTB. 1738 1739choice 1740 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1741 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1742 1743config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1744 bool "Use bootloader kernel arguments if available" 1745 help 1746 Uses the command-line options passed by the boot loader instead of 1747 the device tree bootargs property. If the boot loader doesn't provide 1748 any, the device tree bootargs property will be used. 1749 1750config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1751 bool "Extend with bootloader kernel arguments" 1752 help 1753 The command-line arguments provided by the boot loader will be 1754 appended to the the device tree bootargs property. 1755 1756endchoice 1757 1758config CMDLINE 1759 string "Default kernel command string" 1760 default "" 1761 help 1762 On some architectures (e.g. CATS), there is currently no way 1763 for the boot loader to pass arguments to the kernel. For these 1764 architectures, you should supply some command-line options at build 1765 time by entering them here. As a minimum, you should specify the 1766 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1767 1768choice 1769 prompt "Kernel command line type" if CMDLINE != "" 1770 default CMDLINE_FROM_BOOTLOADER 1771 depends on ATAGS 1772 1773config CMDLINE_FROM_BOOTLOADER 1774 bool "Use bootloader kernel arguments if available" 1775 help 1776 Uses the command-line options passed by the boot loader. If 1777 the boot loader doesn't provide any, the default kernel command 1778 string provided in CMDLINE will be used. 1779 1780config CMDLINE_EXTEND 1781 bool "Extend bootloader kernel arguments" 1782 help 1783 The command-line arguments provided by the boot loader will be 1784 appended to the default kernel command string. 1785 1786config CMDLINE_FORCE 1787 bool "Always use the default kernel command string" 1788 help 1789 Always use the default kernel command string, even if the boot 1790 loader passes other arguments to the kernel. 1791 This is useful if you cannot or don't want to change the 1792 command-line options your boot loader passes to the kernel. 1793endchoice 1794 1795config XIP_KERNEL 1796 bool "Kernel Execute-In-Place from ROM" 1797 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1798 help 1799 Execute-In-Place allows the kernel to run from non-volatile storage 1800 directly addressable by the CPU, such as NOR flash. This saves RAM 1801 space since the text section of the kernel is not loaded from flash 1802 to RAM. Read-write sections, such as the data section and stack, 1803 are still copied to RAM. The XIP kernel is not compressed since 1804 it has to run directly from flash, so it will take more space to 1805 store it. The flash address used to link the kernel object files, 1806 and for storing it, is configuration dependent. Therefore, if you 1807 say Y here, you must know the proper physical address where to 1808 store the kernel image depending on your own flash memory usage. 1809 1810 Also note that the make target becomes "make xipImage" rather than 1811 "make zImage" or "make Image". The final kernel binary to put in 1812 ROM memory will be arch/arm/boot/xipImage. 1813 1814 If unsure, say N. 1815 1816config XIP_PHYS_ADDR 1817 hex "XIP Kernel Physical Location" 1818 depends on XIP_KERNEL 1819 default "0x00080000" 1820 help 1821 This is the physical address in your flash memory the kernel will 1822 be linked for and stored to. This address is dependent on your 1823 own flash usage. 1824 1825config XIP_DEFLATED_DATA 1826 bool "Store kernel .data section compressed in ROM" 1827 depends on XIP_KERNEL 1828 select ZLIB_INFLATE 1829 help 1830 Before the kernel is actually executed, its .data section has to be 1831 copied to RAM from ROM. This option allows for storing that data 1832 in compressed form and decompressed to RAM rather than merely being 1833 copied, saving some precious ROM space. A possible drawback is a 1834 slightly longer boot delay. 1835 1836config KEXEC 1837 bool "Kexec system call (EXPERIMENTAL)" 1838 depends on (!SMP || PM_SLEEP_SMP) 1839 depends on MMU 1840 select KEXEC_CORE 1841 help 1842 kexec is a system call that implements the ability to shutdown your 1843 current kernel, and to start another kernel. It is like a reboot 1844 but it is independent of the system firmware. And like a reboot 1845 you can start any kernel with it, not just Linux. 1846 1847 It is an ongoing process to be certain the hardware in a machine 1848 is properly shutdown, so do not be surprised if this code does not 1849 initially work for you. 1850 1851config ATAGS_PROC 1852 bool "Export atags in procfs" 1853 depends on ATAGS && KEXEC 1854 default y 1855 help 1856 Should the atags used to boot the kernel be exported in an "atags" 1857 file in procfs. Useful with kexec. 1858 1859config CRASH_DUMP 1860 bool "Build kdump crash kernel (EXPERIMENTAL)" 1861 help 1862 Generate crash dump after being started by kexec. This should 1863 be normally only set in special crash dump kernels which are 1864 loaded in the main kernel with kexec-tools into a specially 1865 reserved region and then later executed after a crash by 1866 kdump/kexec. The crash dump kernel must be compiled to a 1867 memory address not used by the main kernel 1868 1869 For more details see Documentation/admin-guide/kdump/kdump.rst 1870 1871config AUTO_ZRELADDR 1872 bool "Auto calculation of the decompressed kernel image address" 1873 help 1874 ZRELADDR is the physical address where the decompressed kernel 1875 image will be placed. If AUTO_ZRELADDR is selected, the address 1876 will be determined at run-time, either by masking the current IP 1877 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1878 This assumes the zImage being placed in the first 128MB from 1879 start of memory. 1880 1881config EFI_STUB 1882 bool 1883 1884config EFI 1885 bool "UEFI runtime support" 1886 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1887 select UCS2_STRING 1888 select EFI_PARAMS_FROM_FDT 1889 select EFI_STUB 1890 select EFI_GENERIC_STUB 1891 select EFI_RUNTIME_WRAPPERS 1892 help 1893 This option provides support for runtime services provided 1894 by UEFI firmware (such as non-volatile variables, realtime 1895 clock, and platform reset). A UEFI stub is also provided to 1896 allow the kernel to be booted as an EFI application. This 1897 is only useful for kernels that may run on systems that have 1898 UEFI firmware. 1899 1900config DMI 1901 bool "Enable support for SMBIOS (DMI) tables" 1902 depends on EFI 1903 default y 1904 help 1905 This enables SMBIOS/DMI feature for systems. 1906 1907 This option is only useful on systems that have UEFI firmware. 1908 However, even with this option, the resultant kernel should 1909 continue to boot on existing non-UEFI platforms. 1910 1911 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1912 i.e., the the practice of identifying the platform via DMI to 1913 decide whether certain workarounds for buggy hardware and/or 1914 firmware need to be enabled. This would require the DMI subsystem 1915 to be enabled much earlier than we do on ARM, which is non-trivial. 1916 1917endmenu 1918 1919menu "CPU Power Management" 1920 1921source "drivers/cpufreq/Kconfig" 1922 1923source "drivers/cpuidle/Kconfig" 1924 1925endmenu 1926 1927menu "Floating point emulation" 1928 1929comment "At least one emulation must be selected" 1930 1931config FPE_NWFPE 1932 bool "NWFPE math emulation" 1933 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1934 help 1935 Say Y to include the NWFPE floating point emulator in the kernel. 1936 This is necessary to run most binaries. Linux does not currently 1937 support floating point hardware so you need to say Y here even if 1938 your machine has an FPA or floating point co-processor podule. 1939 1940 You may say N here if you are going to load the Acorn FPEmulator 1941 early in the bootup. 1942 1943config FPE_NWFPE_XP 1944 bool "Support extended precision" 1945 depends on FPE_NWFPE 1946 help 1947 Say Y to include 80-bit support in the kernel floating-point 1948 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1949 Note that gcc does not generate 80-bit operations by default, 1950 so in most cases this option only enlarges the size of the 1951 floating point emulator without any good reason. 1952 1953 You almost surely want to say N here. 1954 1955config FPE_FASTFPE 1956 bool "FastFPE math emulation (EXPERIMENTAL)" 1957 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1958 help 1959 Say Y here to include the FAST floating point emulator in the kernel. 1960 This is an experimental much faster emulator which now also has full 1961 precision for the mantissa. It does not support any exceptions. 1962 It is very simple, and approximately 3-6 times faster than NWFPE. 1963 1964 It should be sufficient for most programs. It may be not suitable 1965 for scientific calculations, but you have to check this for yourself. 1966 If you do not feel you need a faster FP emulation you should better 1967 choose NWFPE. 1968 1969config VFP 1970 bool "VFP-format floating point maths" 1971 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1972 help 1973 Say Y to include VFP support code in the kernel. This is needed 1974 if your hardware includes a VFP unit. 1975 1976 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1977 release notes and additional status information. 1978 1979 Say N if your target does not have VFP hardware. 1980 1981config VFPv3 1982 bool 1983 depends on VFP 1984 default y if CPU_V7 1985 1986config NEON 1987 bool "Advanced SIMD (NEON) Extension support" 1988 depends on VFPv3 && CPU_V7 1989 help 1990 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1991 Extension. 1992 1993config KERNEL_MODE_NEON 1994 bool "Support for NEON in kernel mode" 1995 depends on NEON && AEABI 1996 help 1997 Say Y to include support for NEON in kernel mode. 1998 1999endmenu 2000 2001menu "Power management options" 2002 2003source "kernel/power/Kconfig" 2004 2005config ARCH_SUSPEND_POSSIBLE 2006 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2007 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2008 def_bool y 2009 2010config ARM_CPU_SUSPEND 2011 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2012 depends on ARCH_SUSPEND_POSSIBLE 2013 2014config ARCH_HIBERNATION_POSSIBLE 2015 bool 2016 depends on MMU 2017 default y if ARCH_SUSPEND_POSSIBLE 2018 2019endmenu 2020 2021if CRYPTO 2022source "arch/arm/crypto/Kconfig" 2023endif 2024 2025source "arch/arm/Kconfig.assembler" 2026