1config ARM 2 bool 3 default y 4 select ARCH_HAVE_CUSTOM_GPIO_H 5 select HAVE_AOUT 6 select HAVE_DMA_API_DEBUG 7 select HAVE_IDE if PCI || ISA || PCMCIA 8 select HAVE_MEMBLOCK 9 select RTC_LIB 10 select SYS_SUPPORTS_APM_EMULATION 11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 12 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 13 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 14 select HAVE_ARCH_KGDB 15 select HAVE_KPROBES if !XIP_KERNEL 16 select HAVE_KRETPROBES if (HAVE_KPROBES) 17 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 18 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 19 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 20 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 21 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 22 select HAVE_GENERIC_DMA_COHERENT 23 select HAVE_KERNEL_GZIP 24 select HAVE_KERNEL_LZO 25 select HAVE_KERNEL_LZMA 26 select HAVE_KERNEL_XZ 27 select HAVE_IRQ_WORK 28 select HAVE_PERF_EVENTS 29 select PERF_USE_VMALLOC 30 select HAVE_REGS_AND_STACK_ACCESS_API 31 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 32 select HAVE_C_RECORDMCOUNT 33 select HAVE_GENERIC_HARDIRQS 34 select GENERIC_IRQ_SHOW 35 select CPU_PM if (SUSPEND || CPU_IDLE) 36 select GENERIC_PCI_IOMAP 37 select HAVE_BPF_JIT if NET 38 help 39 The ARM series is a line of low-power-consumption RISC chip designs 40 licensed by ARM Ltd and targeted at embedded applications and 41 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 42 manufactured, but legacy ARM-based PC hardware remains popular in 43 Europe. There is an ARM Linux project with a web page at 44 <http://www.arm.linux.org.uk/>. 45 46config ARM_HAS_SG_CHAIN 47 bool 48 49config HAVE_PWM 50 bool 51 52config MIGHT_HAVE_PCI 53 bool 54 55config SYS_SUPPORTS_APM_EMULATION 56 bool 57 58config GENERIC_GPIO 59 bool 60 61config ARCH_USES_GETTIMEOFFSET 62 bool 63 default n 64 65config GENERIC_CLOCKEVENTS 66 bool 67 68config GENERIC_CLOCKEVENTS_BROADCAST 69 bool 70 depends on GENERIC_CLOCKEVENTS 71 default y if SMP 72 73config KTIME_SCALAR 74 bool 75 default y 76 77config HAVE_TCM 78 bool 79 select GENERIC_ALLOCATOR 80 81config HAVE_PROC_CPU 82 bool 83 84config NO_IOPORT 85 bool 86 87config EISA 88 bool 89 ---help--- 90 The Extended Industry Standard Architecture (EISA) bus was 91 developed as an open alternative to the IBM MicroChannel bus. 92 93 The EISA bus provided some of the features of the IBM MicroChannel 94 bus while maintaining backward compatibility with cards made for 95 the older ISA bus. The EISA bus saw limited use between 1988 and 96 1995 when it was made obsolete by the PCI bus. 97 98 Say Y here if you are building a kernel for an EISA-based machine. 99 100 Otherwise, say N. 101 102config SBUS 103 bool 104 105config MCA 106 bool 107 help 108 MicroChannel Architecture is found in some IBM PS/2 machines and 109 laptops. It is a bus system similar to PCI or ISA. See 110 <file:Documentation/mca.txt> (and especially the web page given 111 there) before attempting to build an MCA bus kernel. 112 113config STACKTRACE_SUPPORT 114 bool 115 default y 116 117config HAVE_LATENCYTOP_SUPPORT 118 bool 119 depends on !SMP 120 default y 121 122config LOCKDEP_SUPPORT 123 bool 124 default y 125 126config TRACE_IRQFLAGS_SUPPORT 127 bool 128 default y 129 130config HARDIRQS_SW_RESEND 131 bool 132 default y 133 134config GENERIC_IRQ_PROBE 135 bool 136 default y 137 138config GENERIC_LOCKBREAK 139 bool 140 default y 141 depends on SMP && PREEMPT 142 143config RWSEM_GENERIC_SPINLOCK 144 bool 145 default y 146 147config RWSEM_XCHGADD_ALGORITHM 148 bool 149 150config ARCH_HAS_ILOG2_U32 151 bool 152 153config ARCH_HAS_ILOG2_U64 154 bool 155 156config ARCH_HAS_CPUFREQ 157 bool 158 help 159 Internal node to signify that the ARCH has CPUFREQ support 160 and that the relevant menu configurations are displayed for 161 it. 162 163config ARCH_HAS_CPU_IDLE_WAIT 164 def_bool y 165 166config GENERIC_HWEIGHT 167 bool 168 default y 169 170config GENERIC_CALIBRATE_DELAY 171 bool 172 default y 173 174config ARCH_MAY_HAVE_PC_FDC 175 bool 176 177config ZONE_DMA 178 bool 179 180config NEED_DMA_MAP_STATE 181 def_bool y 182 183config ARCH_HAS_DMA_SET_COHERENT_MASK 184 bool 185 186config GENERIC_ISA_DMA 187 bool 188 189config FIQ 190 bool 191 192config NEED_RET_TO_USER 193 bool 194 195config ARCH_MTD_XIP 196 bool 197 198config VECTORS_BASE 199 hex 200 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 201 default DRAM_BASE if REMAP_VECTORS_TO_RAM 202 default 0x00000000 203 help 204 The base address of exception vectors. 205 206config ARM_PATCH_PHYS_VIRT 207 bool "Patch physical to virtual translations at runtime" if EMBEDDED 208 default y 209 depends on !XIP_KERNEL && MMU 210 depends on !ARCH_REALVIEW || !SPARSEMEM 211 help 212 Patch phys-to-virt and virt-to-phys translation functions at 213 boot and module load time according to the position of the 214 kernel in system memory. 215 216 This can only be used with non-XIP MMU kernels where the base 217 of physical memory is at a 16MB boundary. 218 219 Only disable this option if you know that you do not require 220 this feature (eg, building a kernel for a single machine) and 221 you need to shrink the kernel to the minimal size. 222 223config NEED_MACH_IO_H 224 bool 225 help 226 Select this when mach/io.h is required to provide special 227 definitions for this platform. The need for mach/io.h should 228 be avoided when possible. 229 230config NEED_MACH_MEMORY_H 231 bool 232 help 233 Select this when mach/memory.h is required to provide special 234 definitions for this platform. The need for mach/memory.h should 235 be avoided when possible. 236 237config PHYS_OFFSET 238 hex "Physical address of main memory" if MMU 239 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 240 default DRAM_BASE if !MMU 241 help 242 Please provide the physical address corresponding to the 243 location of main memory in your system. 244 245config GENERIC_BUG 246 def_bool y 247 depends on BUG 248 249source "init/Kconfig" 250 251source "kernel/Kconfig.freezer" 252 253menu "System Type" 254 255config MMU 256 bool "MMU-based Paged Memory Management Support" 257 default y 258 help 259 Select if you want MMU-based virtualised addressing space 260 support by paged memory management. If unsure, say 'Y'. 261 262# 263# The "ARM system type" choice list is ordered alphabetically by option 264# text. Please add new entries in the option alphabetic order. 265# 266choice 267 prompt "ARM system type" 268 default ARCH_VERSATILE 269 270config ARCH_INTEGRATOR 271 bool "ARM Ltd. Integrator family" 272 select ARM_AMBA 273 select ARCH_HAS_CPUFREQ 274 select CLKDEV_LOOKUP 275 select HAVE_MACH_CLKDEV 276 select HAVE_TCM 277 select ICST 278 select GENERIC_CLOCKEVENTS 279 select PLAT_VERSATILE 280 select PLAT_VERSATILE_FPGA_IRQ 281 select NEED_MACH_IO_H 282 select NEED_MACH_MEMORY_H 283 select SPARSE_IRQ 284 help 285 Support for ARM's Integrator platform. 286 287config ARCH_REALVIEW 288 bool "ARM Ltd. RealView family" 289 select ARM_AMBA 290 select CLKDEV_LOOKUP 291 select HAVE_MACH_CLKDEV 292 select ICST 293 select GENERIC_CLOCKEVENTS 294 select ARCH_WANT_OPTIONAL_GPIOLIB 295 select PLAT_VERSATILE 296 select PLAT_VERSATILE_CLCD 297 select ARM_TIMER_SP804 298 select GPIO_PL061 if GPIOLIB 299 select NEED_MACH_MEMORY_H 300 help 301 This enables support for ARM Ltd RealView boards. 302 303config ARCH_VERSATILE 304 bool "ARM Ltd. Versatile family" 305 select ARM_AMBA 306 select ARM_VIC 307 select CLKDEV_LOOKUP 308 select HAVE_MACH_CLKDEV 309 select ICST 310 select GENERIC_CLOCKEVENTS 311 select ARCH_WANT_OPTIONAL_GPIOLIB 312 select PLAT_VERSATILE 313 select PLAT_VERSATILE_CLCD 314 select PLAT_VERSATILE_FPGA_IRQ 315 select ARM_TIMER_SP804 316 help 317 This enables support for ARM Ltd Versatile board. 318 319config ARCH_VEXPRESS 320 bool "ARM Ltd. Versatile Express family" 321 select ARCH_WANT_OPTIONAL_GPIOLIB 322 select ARM_AMBA 323 select ARM_TIMER_SP804 324 select CLKDEV_LOOKUP 325 select HAVE_MACH_CLKDEV 326 select GENERIC_CLOCKEVENTS 327 select HAVE_CLK 328 select HAVE_PATA_PLATFORM 329 select ICST 330 select NO_IOPORT 331 select PLAT_VERSATILE 332 select PLAT_VERSATILE_CLCD 333 help 334 This enables support for the ARM Ltd Versatile Express boards. 335 336config ARCH_AT91 337 bool "Atmel AT91" 338 select ARCH_REQUIRE_GPIOLIB 339 select HAVE_CLK 340 select CLKDEV_LOOKUP 341 select IRQ_DOMAIN 342 select NEED_MACH_IO_H if PCCARD 343 help 344 This enables support for systems based on the Atmel AT91RM9200, 345 AT91SAM9 processors. 346 347config ARCH_BCMRING 348 bool "Broadcom BCMRING" 349 depends on MMU 350 select CPU_V6 351 select ARM_AMBA 352 select ARM_TIMER_SP804 353 select CLKDEV_LOOKUP 354 select GENERIC_CLOCKEVENTS 355 select ARCH_WANT_OPTIONAL_GPIOLIB 356 help 357 Support for Broadcom's BCMRing platform. 358 359config ARCH_HIGHBANK 360 bool "Calxeda Highbank-based" 361 select ARCH_WANT_OPTIONAL_GPIOLIB 362 select ARM_AMBA 363 select ARM_GIC 364 select ARM_TIMER_SP804 365 select CACHE_L2X0 366 select CLKDEV_LOOKUP 367 select CPU_V7 368 select GENERIC_CLOCKEVENTS 369 select HAVE_ARM_SCU 370 select HAVE_SMP 371 select SPARSE_IRQ 372 select USE_OF 373 help 374 Support for the Calxeda Highbank SoC based boards. 375 376config ARCH_CLPS711X 377 bool "Cirrus Logic CLPS711x/EP721x-based" 378 select CPU_ARM720T 379 select ARCH_USES_GETTIMEOFFSET 380 select NEED_MACH_MEMORY_H 381 help 382 Support for Cirrus Logic 711x/721x based boards. 383 384config ARCH_CNS3XXX 385 bool "Cavium Networks CNS3XXX family" 386 select CPU_V6K 387 select GENERIC_CLOCKEVENTS 388 select ARM_GIC 389 select MIGHT_HAVE_CACHE_L2X0 390 select MIGHT_HAVE_PCI 391 select PCI_DOMAINS if PCI 392 help 393 Support for Cavium Networks CNS3XXX platform. 394 395config ARCH_GEMINI 396 bool "Cortina Systems Gemini" 397 select CPU_FA526 398 select ARCH_REQUIRE_GPIOLIB 399 select ARCH_USES_GETTIMEOFFSET 400 help 401 Support for the Cortina Systems Gemini family SoCs 402 403config ARCH_PRIMA2 404 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 405 select CPU_V7 406 select NO_IOPORT 407 select GENERIC_CLOCKEVENTS 408 select CLKDEV_LOOKUP 409 select GENERIC_IRQ_CHIP 410 select MIGHT_HAVE_CACHE_L2X0 411 select USE_OF 412 select ZONE_DMA 413 help 414 Support for CSR SiRFSoC ARM Cortex A9 Platform 415 416config ARCH_EBSA110 417 bool "EBSA-110" 418 select CPU_SA110 419 select ISA 420 select NO_IOPORT 421 select ARCH_USES_GETTIMEOFFSET 422 select NEED_MACH_IO_H 423 select NEED_MACH_MEMORY_H 424 help 425 This is an evaluation board for the StrongARM processor available 426 from Digital. It has limited hardware on-board, including an 427 Ethernet interface, two PCMCIA sockets, two serial ports and a 428 parallel port. 429 430config ARCH_EP93XX 431 bool "EP93xx-based" 432 select CPU_ARM920T 433 select ARM_AMBA 434 select ARM_VIC 435 select CLKDEV_LOOKUP 436 select ARCH_REQUIRE_GPIOLIB 437 select ARCH_HAS_HOLES_MEMORYMODEL 438 select ARCH_USES_GETTIMEOFFSET 439 select NEED_MACH_MEMORY_H 440 help 441 This enables support for the Cirrus EP93xx series of CPUs. 442 443config ARCH_FOOTBRIDGE 444 bool "FootBridge" 445 select CPU_SA110 446 select FOOTBRIDGE 447 select GENERIC_CLOCKEVENTS 448 select HAVE_IDE 449 select NEED_MACH_IO_H 450 select NEED_MACH_MEMORY_H 451 help 452 Support for systems based on the DC21285 companion chip 453 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 454 455config ARCH_MXC 456 bool "Freescale MXC/iMX-based" 457 select GENERIC_CLOCKEVENTS 458 select ARCH_REQUIRE_GPIOLIB 459 select CLKDEV_LOOKUP 460 select CLKSRC_MMIO 461 select GENERIC_IRQ_CHIP 462 select MULTI_IRQ_HANDLER 463 help 464 Support for Freescale MXC/iMX-based family of processors 465 466config ARCH_MXS 467 bool "Freescale MXS-based" 468 select GENERIC_CLOCKEVENTS 469 select ARCH_REQUIRE_GPIOLIB 470 select CLKDEV_LOOKUP 471 select CLKSRC_MMIO 472 select HAVE_CLK_PREPARE 473 help 474 Support for Freescale MXS-based family of processors 475 476config ARCH_NETX 477 bool "Hilscher NetX based" 478 select CLKSRC_MMIO 479 select CPU_ARM926T 480 select ARM_VIC 481 select GENERIC_CLOCKEVENTS 482 help 483 This enables support for systems based on the Hilscher NetX Soc 484 485config ARCH_H720X 486 bool "Hynix HMS720x-based" 487 select CPU_ARM720T 488 select ISA_DMA_API 489 select ARCH_USES_GETTIMEOFFSET 490 help 491 This enables support for systems based on the Hynix HMS720x 492 493config ARCH_IOP13XX 494 bool "IOP13xx-based" 495 depends on MMU 496 select CPU_XSC3 497 select PLAT_IOP 498 select PCI 499 select ARCH_SUPPORTS_MSI 500 select VMSPLIT_1G 501 select NEED_MACH_IO_H 502 select NEED_MACH_MEMORY_H 503 select NEED_RET_TO_USER 504 help 505 Support for Intel's IOP13XX (XScale) family of processors. 506 507config ARCH_IOP32X 508 bool "IOP32x-based" 509 depends on MMU 510 select CPU_XSCALE 511 select NEED_MACH_IO_H 512 select NEED_RET_TO_USER 513 select PLAT_IOP 514 select PCI 515 select ARCH_REQUIRE_GPIOLIB 516 help 517 Support for Intel's 80219 and IOP32X (XScale) family of 518 processors. 519 520config ARCH_IOP33X 521 bool "IOP33x-based" 522 depends on MMU 523 select CPU_XSCALE 524 select NEED_MACH_IO_H 525 select NEED_RET_TO_USER 526 select PLAT_IOP 527 select PCI 528 select ARCH_REQUIRE_GPIOLIB 529 help 530 Support for Intel's IOP33X (XScale) family of processors. 531 532config ARCH_IXP23XX 533 bool "IXP23XX-based" 534 depends on MMU 535 select CPU_XSC3 536 select PCI 537 select ARCH_USES_GETTIMEOFFSET 538 select NEED_MACH_IO_H 539 select NEED_MACH_MEMORY_H 540 help 541 Support for Intel's IXP23xx (XScale) family of processors. 542 543config ARCH_IXP2000 544 bool "IXP2400/2800-based" 545 depends on MMU 546 select CPU_XSCALE 547 select PCI 548 select ARCH_USES_GETTIMEOFFSET 549 select NEED_MACH_IO_H 550 select NEED_MACH_MEMORY_H 551 help 552 Support for Intel's IXP2400/2800 (XScale) family of processors. 553 554config ARCH_IXP4XX 555 bool "IXP4xx-based" 556 depends on MMU 557 select ARCH_HAS_DMA_SET_COHERENT_MASK 558 select CLKSRC_MMIO 559 select CPU_XSCALE 560 select GENERIC_GPIO 561 select GENERIC_CLOCKEVENTS 562 select MIGHT_HAVE_PCI 563 select NEED_MACH_IO_H 564 select DMABOUNCE if PCI 565 help 566 Support for Intel's IXP4XX (XScale) family of processors. 567 568config ARCH_DOVE 569 bool "Marvell Dove" 570 select CPU_V7 571 select PCI 572 select ARCH_REQUIRE_GPIOLIB 573 select GENERIC_CLOCKEVENTS 574 select NEED_MACH_IO_H 575 select PLAT_ORION 576 help 577 Support for the Marvell Dove SoC 88AP510 578 579config ARCH_KIRKWOOD 580 bool "Marvell Kirkwood" 581 select CPU_FEROCEON 582 select PCI 583 select ARCH_REQUIRE_GPIOLIB 584 select GENERIC_CLOCKEVENTS 585 select NEED_MACH_IO_H 586 select PLAT_ORION 587 help 588 Support for the following Marvell Kirkwood series SoCs: 589 88F6180, 88F6192 and 88F6281. 590 591config ARCH_LPC32XX 592 bool "NXP LPC32XX" 593 select CLKSRC_MMIO 594 select CPU_ARM926T 595 select ARCH_REQUIRE_GPIOLIB 596 select HAVE_IDE 597 select ARM_AMBA 598 select USB_ARCH_HAS_OHCI 599 select CLKDEV_LOOKUP 600 select GENERIC_CLOCKEVENTS 601 help 602 Support for the NXP LPC32XX family of processors 603 604config ARCH_MV78XX0 605 bool "Marvell MV78xx0" 606 select CPU_FEROCEON 607 select PCI 608 select ARCH_REQUIRE_GPIOLIB 609 select GENERIC_CLOCKEVENTS 610 select NEED_MACH_IO_H 611 select PLAT_ORION 612 help 613 Support for the following Marvell MV78xx0 series SoCs: 614 MV781x0, MV782x0. 615 616config ARCH_ORION5X 617 bool "Marvell Orion" 618 depends on MMU 619 select CPU_FEROCEON 620 select PCI 621 select ARCH_REQUIRE_GPIOLIB 622 select GENERIC_CLOCKEVENTS 623 select PLAT_ORION 624 help 625 Support for the following Marvell Orion 5x series SoCs: 626 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 627 Orion-2 (5281), Orion-1-90 (6183). 628 629config ARCH_MMP 630 bool "Marvell PXA168/910/MMP2" 631 depends on MMU 632 select ARCH_REQUIRE_GPIOLIB 633 select CLKDEV_LOOKUP 634 select GENERIC_CLOCKEVENTS 635 select GPIO_PXA 636 select TICK_ONESHOT 637 select PLAT_PXA 638 select SPARSE_IRQ 639 select GENERIC_ALLOCATOR 640 help 641 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 642 643config ARCH_KS8695 644 bool "Micrel/Kendin KS8695" 645 select CPU_ARM922T 646 select ARCH_REQUIRE_GPIOLIB 647 select ARCH_USES_GETTIMEOFFSET 648 select NEED_MACH_MEMORY_H 649 help 650 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 651 System-on-Chip devices. 652 653config ARCH_W90X900 654 bool "Nuvoton W90X900 CPU" 655 select CPU_ARM926T 656 select ARCH_REQUIRE_GPIOLIB 657 select CLKDEV_LOOKUP 658 select CLKSRC_MMIO 659 select GENERIC_CLOCKEVENTS 660 help 661 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 662 At present, the w90x900 has been renamed nuc900, regarding 663 the ARM series product line, you can login the following 664 link address to know more. 665 666 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 667 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 668 669config ARCH_TEGRA 670 bool "NVIDIA Tegra" 671 select CLKDEV_LOOKUP 672 select CLKSRC_MMIO 673 select GENERIC_CLOCKEVENTS 674 select GENERIC_GPIO 675 select HAVE_CLK 676 select HAVE_SMP 677 select MIGHT_HAVE_CACHE_L2X0 678 select NEED_MACH_IO_H if PCI 679 select ARCH_HAS_CPUFREQ 680 help 681 This enables support for NVIDIA Tegra based systems (Tegra APX, 682 Tegra 6xx and Tegra 2 series). 683 684config ARCH_PICOXCELL 685 bool "Picochip picoXcell" 686 select ARCH_REQUIRE_GPIOLIB 687 select ARM_PATCH_PHYS_VIRT 688 select ARM_VIC 689 select CPU_V6K 690 select DW_APB_TIMER 691 select GENERIC_CLOCKEVENTS 692 select GENERIC_GPIO 693 select HAVE_TCM 694 select NO_IOPORT 695 select SPARSE_IRQ 696 select USE_OF 697 help 698 This enables support for systems based on the Picochip picoXcell 699 family of Femtocell devices. The picoxcell support requires device tree 700 for all boards. 701 702config ARCH_PNX4008 703 bool "Philips Nexperia PNX4008 Mobile" 704 select CPU_ARM926T 705 select CLKDEV_LOOKUP 706 select ARCH_USES_GETTIMEOFFSET 707 help 708 This enables support for Philips PNX4008 mobile platform. 709 710config ARCH_PXA 711 bool "PXA2xx/PXA3xx-based" 712 depends on MMU 713 select ARCH_MTD_XIP 714 select ARCH_HAS_CPUFREQ 715 select CLKDEV_LOOKUP 716 select CLKSRC_MMIO 717 select ARCH_REQUIRE_GPIOLIB 718 select GENERIC_CLOCKEVENTS 719 select GPIO_PXA 720 select TICK_ONESHOT 721 select PLAT_PXA 722 select SPARSE_IRQ 723 select AUTO_ZRELADDR 724 select MULTI_IRQ_HANDLER 725 select ARM_CPU_SUSPEND if PM 726 select HAVE_IDE 727 help 728 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 729 730config ARCH_MSM 731 bool "Qualcomm MSM" 732 select HAVE_CLK 733 select GENERIC_CLOCKEVENTS 734 select ARCH_REQUIRE_GPIOLIB 735 select CLKDEV_LOOKUP 736 help 737 Support for Qualcomm MSM/QSD based systems. This runs on the 738 apps processor of the MSM/QSD and depends on a shared memory 739 interface to the modem processor which runs the baseband 740 stack and controls some vital subsystems 741 (clock and power control, etc). 742 743config ARCH_SHMOBILE 744 bool "Renesas SH-Mobile / R-Mobile" 745 select HAVE_CLK 746 select CLKDEV_LOOKUP 747 select HAVE_MACH_CLKDEV 748 select HAVE_SMP 749 select GENERIC_CLOCKEVENTS 750 select MIGHT_HAVE_CACHE_L2X0 751 select NO_IOPORT 752 select SPARSE_IRQ 753 select MULTI_IRQ_HANDLER 754 select PM_GENERIC_DOMAINS if PM 755 select NEED_MACH_MEMORY_H 756 help 757 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 758 759config ARCH_RPC 760 bool "RiscPC" 761 select ARCH_ACORN 762 select FIQ 763 select ARCH_MAY_HAVE_PC_FDC 764 select HAVE_PATA_PLATFORM 765 select ISA_DMA_API 766 select NO_IOPORT 767 select ARCH_SPARSEMEM_ENABLE 768 select ARCH_USES_GETTIMEOFFSET 769 select HAVE_IDE 770 select NEED_MACH_IO_H 771 select NEED_MACH_MEMORY_H 772 help 773 On the Acorn Risc-PC, Linux can support the internal IDE disk and 774 CD-ROM interface, serial and parallel port, and the floppy drive. 775 776config ARCH_SA1100 777 bool "SA1100-based" 778 select CLKSRC_MMIO 779 select CPU_SA1100 780 select ISA 781 select ARCH_SPARSEMEM_ENABLE 782 select ARCH_MTD_XIP 783 select ARCH_HAS_CPUFREQ 784 select CPU_FREQ 785 select GENERIC_CLOCKEVENTS 786 select CLKDEV_LOOKUP 787 select TICK_ONESHOT 788 select ARCH_REQUIRE_GPIOLIB 789 select HAVE_IDE 790 select NEED_MACH_MEMORY_H 791 select SPARSE_IRQ 792 help 793 Support for StrongARM 11x0 based boards. 794 795config ARCH_S3C24XX 796 bool "Samsung S3C24XX SoCs" 797 select GENERIC_GPIO 798 select ARCH_HAS_CPUFREQ 799 select HAVE_CLK 800 select CLKDEV_LOOKUP 801 select ARCH_USES_GETTIMEOFFSET 802 select HAVE_S3C2410_I2C if I2C 803 select HAVE_S3C_RTC if RTC_CLASS 804 select HAVE_S3C2410_WATCHDOG if WATCHDOG 805 select NEED_MACH_IO_H 806 help 807 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 808 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 809 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 810 Samsung SMDK2410 development board (and derivatives). 811 812config ARCH_S3C64XX 813 bool "Samsung S3C64XX" 814 select PLAT_SAMSUNG 815 select CPU_V6 816 select ARM_VIC 817 select HAVE_CLK 818 select HAVE_TCM 819 select CLKDEV_LOOKUP 820 select NO_IOPORT 821 select ARCH_USES_GETTIMEOFFSET 822 select ARCH_HAS_CPUFREQ 823 select ARCH_REQUIRE_GPIOLIB 824 select SAMSUNG_CLKSRC 825 select SAMSUNG_IRQ_VIC_TIMER 826 select S3C_GPIO_TRACK 827 select S3C_DEV_NAND 828 select USB_ARCH_HAS_OHCI 829 select SAMSUNG_GPIOLIB_4BIT 830 select HAVE_S3C2410_I2C if I2C 831 select HAVE_S3C2410_WATCHDOG if WATCHDOG 832 help 833 Samsung S3C64XX series based systems 834 835config ARCH_S5P64X0 836 bool "Samsung S5P6440 S5P6450" 837 select CPU_V6 838 select GENERIC_GPIO 839 select HAVE_CLK 840 select CLKDEV_LOOKUP 841 select CLKSRC_MMIO 842 select HAVE_S3C2410_WATCHDOG if WATCHDOG 843 select GENERIC_CLOCKEVENTS 844 select HAVE_S3C2410_I2C if I2C 845 select HAVE_S3C_RTC if RTC_CLASS 846 help 847 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 848 SMDK6450. 849 850config ARCH_S5PC100 851 bool "Samsung S5PC100" 852 select GENERIC_GPIO 853 select HAVE_CLK 854 select CLKDEV_LOOKUP 855 select CPU_V7 856 select ARCH_USES_GETTIMEOFFSET 857 select HAVE_S3C2410_I2C if I2C 858 select HAVE_S3C_RTC if RTC_CLASS 859 select HAVE_S3C2410_WATCHDOG if WATCHDOG 860 help 861 Samsung S5PC100 series based systems 862 863config ARCH_S5PV210 864 bool "Samsung S5PV210/S5PC110" 865 select CPU_V7 866 select ARCH_SPARSEMEM_ENABLE 867 select ARCH_HAS_HOLES_MEMORYMODEL 868 select GENERIC_GPIO 869 select HAVE_CLK 870 select CLKDEV_LOOKUP 871 select CLKSRC_MMIO 872 select ARCH_HAS_CPUFREQ 873 select GENERIC_CLOCKEVENTS 874 select HAVE_S3C2410_I2C if I2C 875 select HAVE_S3C_RTC if RTC_CLASS 876 select HAVE_S3C2410_WATCHDOG if WATCHDOG 877 select NEED_MACH_MEMORY_H 878 help 879 Samsung S5PV210/S5PC110 series based systems 880 881config ARCH_EXYNOS 882 bool "SAMSUNG EXYNOS" 883 select CPU_V7 884 select ARCH_SPARSEMEM_ENABLE 885 select ARCH_HAS_HOLES_MEMORYMODEL 886 select GENERIC_GPIO 887 select HAVE_CLK 888 select CLKDEV_LOOKUP 889 select ARCH_HAS_CPUFREQ 890 select GENERIC_CLOCKEVENTS 891 select HAVE_S3C_RTC if RTC_CLASS 892 select HAVE_S3C2410_I2C if I2C 893 select HAVE_S3C2410_WATCHDOG if WATCHDOG 894 select NEED_MACH_MEMORY_H 895 help 896 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 897 898config ARCH_SHARK 899 bool "Shark" 900 select CPU_SA110 901 select ISA 902 select ISA_DMA 903 select ZONE_DMA 904 select PCI 905 select ARCH_USES_GETTIMEOFFSET 906 select NEED_MACH_MEMORY_H 907 select NEED_MACH_IO_H 908 help 909 Support for the StrongARM based Digital DNARD machine, also known 910 as "Shark" (<http://www.shark-linux.de/shark.html>). 911 912config ARCH_U300 913 bool "ST-Ericsson U300 Series" 914 depends on MMU 915 select CLKSRC_MMIO 916 select CPU_ARM926T 917 select HAVE_TCM 918 select ARM_AMBA 919 select ARM_PATCH_PHYS_VIRT 920 select ARM_VIC 921 select GENERIC_CLOCKEVENTS 922 select CLKDEV_LOOKUP 923 select HAVE_MACH_CLKDEV 924 select GENERIC_GPIO 925 select ARCH_REQUIRE_GPIOLIB 926 help 927 Support for ST-Ericsson U300 series mobile platforms. 928 929config ARCH_U8500 930 bool "ST-Ericsson U8500 Series" 931 depends on MMU 932 select CPU_V7 933 select ARM_AMBA 934 select GENERIC_CLOCKEVENTS 935 select CLKDEV_LOOKUP 936 select ARCH_REQUIRE_GPIOLIB 937 select ARCH_HAS_CPUFREQ 938 select HAVE_SMP 939 select MIGHT_HAVE_CACHE_L2X0 940 help 941 Support for ST-Ericsson's Ux500 architecture 942 943config ARCH_NOMADIK 944 bool "STMicroelectronics Nomadik" 945 select ARM_AMBA 946 select ARM_VIC 947 select CPU_ARM926T 948 select CLKDEV_LOOKUP 949 select GENERIC_CLOCKEVENTS 950 select MIGHT_HAVE_CACHE_L2X0 951 select ARCH_REQUIRE_GPIOLIB 952 help 953 Support for the Nomadik platform by ST-Ericsson 954 955config ARCH_DAVINCI 956 bool "TI DaVinci" 957 select GENERIC_CLOCKEVENTS 958 select ARCH_REQUIRE_GPIOLIB 959 select ZONE_DMA 960 select HAVE_IDE 961 select CLKDEV_LOOKUP 962 select GENERIC_ALLOCATOR 963 select GENERIC_IRQ_CHIP 964 select ARCH_HAS_HOLES_MEMORYMODEL 965 help 966 Support for TI's DaVinci platform. 967 968config ARCH_OMAP 969 bool "TI OMAP" 970 select HAVE_CLK 971 select ARCH_REQUIRE_GPIOLIB 972 select ARCH_HAS_CPUFREQ 973 select CLKSRC_MMIO 974 select GENERIC_CLOCKEVENTS 975 select ARCH_HAS_HOLES_MEMORYMODEL 976 help 977 Support for TI's OMAP platform (OMAP1/2/3/4). 978 979config PLAT_SPEAR 980 bool "ST SPEAr" 981 select ARM_AMBA 982 select ARCH_REQUIRE_GPIOLIB 983 select CLKDEV_LOOKUP 984 select CLKSRC_MMIO 985 select GENERIC_CLOCKEVENTS 986 select HAVE_CLK 987 help 988 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 989 990config ARCH_VT8500 991 bool "VIA/WonderMedia 85xx" 992 select CPU_ARM926T 993 select GENERIC_GPIO 994 select ARCH_HAS_CPUFREQ 995 select GENERIC_CLOCKEVENTS 996 select ARCH_REQUIRE_GPIOLIB 997 select HAVE_PWM 998 help 999 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 1000 1001config ARCH_ZYNQ 1002 bool "Xilinx Zynq ARM Cortex A9 Platform" 1003 select CPU_V7 1004 select GENERIC_CLOCKEVENTS 1005 select CLKDEV_LOOKUP 1006 select ARM_GIC 1007 select ARM_AMBA 1008 select ICST 1009 select MIGHT_HAVE_CACHE_L2X0 1010 select USE_OF 1011 help 1012 Support for Xilinx Zynq ARM Cortex A9 Platform 1013endchoice 1014 1015# 1016# This is sorted alphabetically by mach-* pathname. However, plat-* 1017# Kconfigs may be included either alphabetically (according to the 1018# plat- suffix) or along side the corresponding mach-* source. 1019# 1020source "arch/arm/mach-at91/Kconfig" 1021 1022source "arch/arm/mach-bcmring/Kconfig" 1023 1024source "arch/arm/mach-clps711x/Kconfig" 1025 1026source "arch/arm/mach-cns3xxx/Kconfig" 1027 1028source "arch/arm/mach-davinci/Kconfig" 1029 1030source "arch/arm/mach-dove/Kconfig" 1031 1032source "arch/arm/mach-ep93xx/Kconfig" 1033 1034source "arch/arm/mach-footbridge/Kconfig" 1035 1036source "arch/arm/mach-gemini/Kconfig" 1037 1038source "arch/arm/mach-h720x/Kconfig" 1039 1040source "arch/arm/mach-integrator/Kconfig" 1041 1042source "arch/arm/mach-iop32x/Kconfig" 1043 1044source "arch/arm/mach-iop33x/Kconfig" 1045 1046source "arch/arm/mach-iop13xx/Kconfig" 1047 1048source "arch/arm/mach-ixp4xx/Kconfig" 1049 1050source "arch/arm/mach-ixp2000/Kconfig" 1051 1052source "arch/arm/mach-ixp23xx/Kconfig" 1053 1054source "arch/arm/mach-kirkwood/Kconfig" 1055 1056source "arch/arm/mach-ks8695/Kconfig" 1057 1058source "arch/arm/mach-lpc32xx/Kconfig" 1059 1060source "arch/arm/mach-msm/Kconfig" 1061 1062source "arch/arm/mach-mv78xx0/Kconfig" 1063 1064source "arch/arm/plat-mxc/Kconfig" 1065 1066source "arch/arm/mach-mxs/Kconfig" 1067 1068source "arch/arm/mach-netx/Kconfig" 1069 1070source "arch/arm/mach-nomadik/Kconfig" 1071source "arch/arm/plat-nomadik/Kconfig" 1072 1073source "arch/arm/plat-omap/Kconfig" 1074 1075source "arch/arm/mach-omap1/Kconfig" 1076 1077source "arch/arm/mach-omap2/Kconfig" 1078 1079source "arch/arm/mach-orion5x/Kconfig" 1080 1081source "arch/arm/mach-pxa/Kconfig" 1082source "arch/arm/plat-pxa/Kconfig" 1083 1084source "arch/arm/mach-mmp/Kconfig" 1085 1086source "arch/arm/mach-realview/Kconfig" 1087 1088source "arch/arm/mach-sa1100/Kconfig" 1089 1090source "arch/arm/plat-samsung/Kconfig" 1091source "arch/arm/plat-s3c24xx/Kconfig" 1092source "arch/arm/plat-s5p/Kconfig" 1093 1094source "arch/arm/plat-spear/Kconfig" 1095 1096source "arch/arm/mach-s3c24xx/Kconfig" 1097if ARCH_S3C24XX 1098source "arch/arm/mach-s3c2412/Kconfig" 1099source "arch/arm/mach-s3c2440/Kconfig" 1100endif 1101 1102if ARCH_S3C64XX 1103source "arch/arm/mach-s3c64xx/Kconfig" 1104endif 1105 1106source "arch/arm/mach-s5p64x0/Kconfig" 1107 1108source "arch/arm/mach-s5pc100/Kconfig" 1109 1110source "arch/arm/mach-s5pv210/Kconfig" 1111 1112source "arch/arm/mach-exynos/Kconfig" 1113 1114source "arch/arm/mach-shmobile/Kconfig" 1115 1116source "arch/arm/mach-tegra/Kconfig" 1117 1118source "arch/arm/mach-u300/Kconfig" 1119 1120source "arch/arm/mach-ux500/Kconfig" 1121 1122source "arch/arm/mach-versatile/Kconfig" 1123 1124source "arch/arm/mach-vexpress/Kconfig" 1125source "arch/arm/plat-versatile/Kconfig" 1126 1127source "arch/arm/mach-vt8500/Kconfig" 1128 1129source "arch/arm/mach-w90x900/Kconfig" 1130 1131# Definitions to make life easier 1132config ARCH_ACORN 1133 bool 1134 1135config PLAT_IOP 1136 bool 1137 select GENERIC_CLOCKEVENTS 1138 1139config PLAT_ORION 1140 bool 1141 select CLKSRC_MMIO 1142 select GENERIC_IRQ_CHIP 1143 1144config PLAT_PXA 1145 bool 1146 1147config PLAT_VERSATILE 1148 bool 1149 1150config ARM_TIMER_SP804 1151 bool 1152 select CLKSRC_MMIO 1153 select HAVE_SCHED_CLOCK 1154 1155source arch/arm/mm/Kconfig 1156 1157config ARM_NR_BANKS 1158 int 1159 default 16 if ARCH_EP93XX 1160 default 8 1161 1162config IWMMXT 1163 bool "Enable iWMMXt support" 1164 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1165 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1166 help 1167 Enable support for iWMMXt context switching at run time if 1168 running on a CPU that supports it. 1169 1170config XSCALE_PMU 1171 bool 1172 depends on CPU_XSCALE 1173 default y 1174 1175config CPU_HAS_PMU 1176 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1177 (!ARCH_OMAP3 || OMAP3_EMU) 1178 default y 1179 bool 1180 1181config MULTI_IRQ_HANDLER 1182 bool 1183 help 1184 Allow each machine to specify it's own IRQ handler at run time. 1185 1186if !MMU 1187source "arch/arm/Kconfig-nommu" 1188endif 1189 1190config ARM_ERRATA_326103 1191 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1192 depends on CPU_V6 1193 help 1194 Executing a SWP instruction to read-only memory does not set bit 11 1195 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1196 treat the access as a read, preventing a COW from occurring and 1197 causing the faulting task to livelock. 1198 1199config ARM_ERRATA_411920 1200 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1201 depends on CPU_V6 || CPU_V6K 1202 help 1203 Invalidation of the Instruction Cache operation can 1204 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1205 It does not affect the MPCore. This option enables the ARM Ltd. 1206 recommended workaround. 1207 1208config ARM_ERRATA_430973 1209 bool "ARM errata: Stale prediction on replaced interworking branch" 1210 depends on CPU_V7 1211 help 1212 This option enables the workaround for the 430973 Cortex-A8 1213 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1214 interworking branch is replaced with another code sequence at the 1215 same virtual address, whether due to self-modifying code or virtual 1216 to physical address re-mapping, Cortex-A8 does not recover from the 1217 stale interworking branch prediction. This results in Cortex-A8 1218 executing the new code sequence in the incorrect ARM or Thumb state. 1219 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1220 and also flushes the branch target cache at every context switch. 1221 Note that setting specific bits in the ACTLR register may not be 1222 available in non-secure mode. 1223 1224config ARM_ERRATA_458693 1225 bool "ARM errata: Processor deadlock when a false hazard is created" 1226 depends on CPU_V7 1227 help 1228 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1229 erratum. For very specific sequences of memory operations, it is 1230 possible for a hazard condition intended for a cache line to instead 1231 be incorrectly associated with a different cache line. This false 1232 hazard might then cause a processor deadlock. The workaround enables 1233 the L1 caching of the NEON accesses and disables the PLD instruction 1234 in the ACTLR register. Note that setting specific bits in the ACTLR 1235 register may not be available in non-secure mode. 1236 1237config ARM_ERRATA_460075 1238 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1239 depends on CPU_V7 1240 help 1241 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1242 erratum. Any asynchronous access to the L2 cache may encounter a 1243 situation in which recent store transactions to the L2 cache are lost 1244 and overwritten with stale memory contents from external memory. The 1245 workaround disables the write-allocate mode for the L2 cache via the 1246 ACTLR register. Note that setting specific bits in the ACTLR register 1247 may not be available in non-secure mode. 1248 1249config ARM_ERRATA_742230 1250 bool "ARM errata: DMB operation may be faulty" 1251 depends on CPU_V7 && SMP 1252 help 1253 This option enables the workaround for the 742230 Cortex-A9 1254 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1255 between two write operations may not ensure the correct visibility 1256 ordering of the two writes. This workaround sets a specific bit in 1257 the diagnostic register of the Cortex-A9 which causes the DMB 1258 instruction to behave as a DSB, ensuring the correct behaviour of 1259 the two writes. 1260 1261config ARM_ERRATA_742231 1262 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1263 depends on CPU_V7 && SMP 1264 help 1265 This option enables the workaround for the 742231 Cortex-A9 1266 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1267 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1268 accessing some data located in the same cache line, may get corrupted 1269 data due to bad handling of the address hazard when the line gets 1270 replaced from one of the CPUs at the same time as another CPU is 1271 accessing it. This workaround sets specific bits in the diagnostic 1272 register of the Cortex-A9 which reduces the linefill issuing 1273 capabilities of the processor. 1274 1275config PL310_ERRATA_588369 1276 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1277 depends on CACHE_L2X0 1278 help 1279 The PL310 L2 cache controller implements three types of Clean & 1280 Invalidate maintenance operations: by Physical Address 1281 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1282 They are architecturally defined to behave as the execution of a 1283 clean operation followed immediately by an invalidate operation, 1284 both performing to the same memory location. This functionality 1285 is not correctly implemented in PL310 as clean lines are not 1286 invalidated as a result of these operations. 1287 1288config ARM_ERRATA_720789 1289 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1290 depends on CPU_V7 1291 help 1292 This option enables the workaround for the 720789 Cortex-A9 (prior to 1293 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1294 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1295 As a consequence of this erratum, some TLB entries which should be 1296 invalidated are not, resulting in an incoherency in the system page 1297 tables. The workaround changes the TLB flushing routines to invalidate 1298 entries regardless of the ASID. 1299 1300config PL310_ERRATA_727915 1301 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1302 depends on CACHE_L2X0 1303 help 1304 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1305 operation (offset 0x7FC). This operation runs in background so that 1306 PL310 can handle normal accesses while it is in progress. Under very 1307 rare circumstances, due to this erratum, write data can be lost when 1308 PL310 treats a cacheable write transaction during a Clean & 1309 Invalidate by Way operation. 1310 1311config ARM_ERRATA_743622 1312 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1313 depends on CPU_V7 1314 help 1315 This option enables the workaround for the 743622 Cortex-A9 1316 (r2p*) erratum. Under very rare conditions, a faulty 1317 optimisation in the Cortex-A9 Store Buffer may lead to data 1318 corruption. This workaround sets a specific bit in the diagnostic 1319 register of the Cortex-A9 which disables the Store Buffer 1320 optimisation, preventing the defect from occurring. This has no 1321 visible impact on the overall performance or power consumption of the 1322 processor. 1323 1324config ARM_ERRATA_751472 1325 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1326 depends on CPU_V7 1327 help 1328 This option enables the workaround for the 751472 Cortex-A9 (prior 1329 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1330 completion of a following broadcasted operation if the second 1331 operation is received by a CPU before the ICIALLUIS has completed, 1332 potentially leading to corrupted entries in the cache or TLB. 1333 1334config PL310_ERRATA_753970 1335 bool "PL310 errata: cache sync operation may be faulty" 1336 depends on CACHE_PL310 1337 help 1338 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1339 1340 Under some condition the effect of cache sync operation on 1341 the store buffer still remains when the operation completes. 1342 This means that the store buffer is always asked to drain and 1343 this prevents it from merging any further writes. The workaround 1344 is to replace the normal offset of cache sync operation (0x730) 1345 by another offset targeting an unmapped PL310 register 0x740. 1346 This has the same effect as the cache sync operation: store buffer 1347 drain and waiting for all buffers empty. 1348 1349config ARM_ERRATA_754322 1350 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1351 depends on CPU_V7 1352 help 1353 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1354 r3p*) erratum. A speculative memory access may cause a page table walk 1355 which starts prior to an ASID switch but completes afterwards. This 1356 can populate the micro-TLB with a stale entry which may be hit with 1357 the new ASID. This workaround places two dsb instructions in the mm 1358 switching code so that no page table walks can cross the ASID switch. 1359 1360config ARM_ERRATA_754327 1361 bool "ARM errata: no automatic Store Buffer drain" 1362 depends on CPU_V7 && SMP 1363 help 1364 This option enables the workaround for the 754327 Cortex-A9 (prior to 1365 r2p0) erratum. The Store Buffer does not have any automatic draining 1366 mechanism and therefore a livelock may occur if an external agent 1367 continuously polls a memory location waiting to observe an update. 1368 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1369 written polling loops from denying visibility of updates to memory. 1370 1371config ARM_ERRATA_364296 1372 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1373 depends on CPU_V6 && !SMP 1374 help 1375 This options enables the workaround for the 364296 ARM1136 1376 r0p2 erratum (possible cache data corruption with 1377 hit-under-miss enabled). It sets the undocumented bit 31 in 1378 the auxiliary control register and the FI bit in the control 1379 register, thus disabling hit-under-miss without putting the 1380 processor into full low interrupt latency mode. ARM11MPCore 1381 is not affected. 1382 1383config ARM_ERRATA_764369 1384 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1385 depends on CPU_V7 && SMP 1386 help 1387 This option enables the workaround for erratum 764369 1388 affecting Cortex-A9 MPCore with two or more processors (all 1389 current revisions). Under certain timing circumstances, a data 1390 cache line maintenance operation by MVA targeting an Inner 1391 Shareable memory region may fail to proceed up to either the 1392 Point of Coherency or to the Point of Unification of the 1393 system. This workaround adds a DSB instruction before the 1394 relevant cache maintenance functions and sets a specific bit 1395 in the diagnostic control register of the SCU. 1396 1397config PL310_ERRATA_769419 1398 bool "PL310 errata: no automatic Store Buffer drain" 1399 depends on CACHE_L2X0 1400 help 1401 On revisions of the PL310 prior to r3p2, the Store Buffer does 1402 not automatically drain. This can cause normal, non-cacheable 1403 writes to be retained when the memory system is idle, leading 1404 to suboptimal I/O performance for drivers using coherent DMA. 1405 This option adds a write barrier to the cpu_idle loop so that, 1406 on systems with an outer cache, the store buffer is drained 1407 explicitly. 1408 1409endmenu 1410 1411source "arch/arm/common/Kconfig" 1412 1413menu "Bus support" 1414 1415config ARM_AMBA 1416 bool 1417 1418config ISA 1419 bool 1420 help 1421 Find out whether you have ISA slots on your motherboard. ISA is the 1422 name of a bus system, i.e. the way the CPU talks to the other stuff 1423 inside your box. Other bus systems are PCI, EISA, MicroChannel 1424 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1425 newer boards don't support it. If you have ISA, say Y, otherwise N. 1426 1427# Select ISA DMA controller support 1428config ISA_DMA 1429 bool 1430 select ISA_DMA_API 1431 1432# Select ISA DMA interface 1433config ISA_DMA_API 1434 bool 1435 1436config PCI 1437 bool "PCI support" if MIGHT_HAVE_PCI 1438 help 1439 Find out whether you have a PCI motherboard. PCI is the name of a 1440 bus system, i.e. the way the CPU talks to the other stuff inside 1441 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1442 VESA. If you have PCI, say Y, otherwise N. 1443 1444config PCI_DOMAINS 1445 bool 1446 depends on PCI 1447 1448config PCI_NANOENGINE 1449 bool "BSE nanoEngine PCI support" 1450 depends on SA1100_NANOENGINE 1451 help 1452 Enable PCI on the BSE nanoEngine board. 1453 1454config PCI_SYSCALL 1455 def_bool PCI 1456 1457# Select the host bridge type 1458config PCI_HOST_VIA82C505 1459 bool 1460 depends on PCI && ARCH_SHARK 1461 default y 1462 1463config PCI_HOST_ITE8152 1464 bool 1465 depends on PCI && MACH_ARMCORE 1466 default y 1467 select DMABOUNCE 1468 1469source "drivers/pci/Kconfig" 1470 1471source "drivers/pcmcia/Kconfig" 1472 1473endmenu 1474 1475menu "Kernel Features" 1476 1477source "kernel/time/Kconfig" 1478 1479config HAVE_SMP 1480 bool 1481 help 1482 This option should be selected by machines which have an SMP- 1483 capable CPU. 1484 1485 The only effect of this option is to make the SMP-related 1486 options available to the user for configuration. 1487 1488config SMP 1489 bool "Symmetric Multi-Processing" 1490 depends on CPU_V6K || CPU_V7 1491 depends on GENERIC_CLOCKEVENTS 1492 depends on HAVE_SMP 1493 depends on MMU 1494 select USE_GENERIC_SMP_HELPERS 1495 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1496 help 1497 This enables support for systems with more than one CPU. If you have 1498 a system with only one CPU, like most personal computers, say N. If 1499 you have a system with more than one CPU, say Y. 1500 1501 If you say N here, the kernel will run on single and multiprocessor 1502 machines, but will use only one CPU of a multiprocessor machine. If 1503 you say Y here, the kernel will run on many, but not all, single 1504 processor machines. On a single processor machine, the kernel will 1505 run faster if you say N here. 1506 1507 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1508 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1509 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1510 1511 If you don't know what to do here, say N. 1512 1513config SMP_ON_UP 1514 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1515 depends on EXPERIMENTAL 1516 depends on SMP && !XIP_KERNEL 1517 default y 1518 help 1519 SMP kernels contain instructions which fail on non-SMP processors. 1520 Enabling this option allows the kernel to modify itself to make 1521 these instructions safe. Disabling it allows about 1K of space 1522 savings. 1523 1524 If you don't know what to do here, say Y. 1525 1526config ARM_CPU_TOPOLOGY 1527 bool "Support cpu topology definition" 1528 depends on SMP && CPU_V7 1529 default y 1530 help 1531 Support ARM cpu topology definition. The MPIDR register defines 1532 affinity between processors which is then used to describe the cpu 1533 topology of an ARM System. 1534 1535config SCHED_MC 1536 bool "Multi-core scheduler support" 1537 depends on ARM_CPU_TOPOLOGY 1538 help 1539 Multi-core scheduler support improves the CPU scheduler's decision 1540 making when dealing with multi-core CPU chips at a cost of slightly 1541 increased overhead in some places. If unsure say N here. 1542 1543config SCHED_SMT 1544 bool "SMT scheduler support" 1545 depends on ARM_CPU_TOPOLOGY 1546 help 1547 Improves the CPU scheduler's decision making when dealing with 1548 MultiThreading at a cost of slightly increased overhead in some 1549 places. If unsure say N here. 1550 1551config HAVE_ARM_SCU 1552 bool 1553 help 1554 This option enables support for the ARM system coherency unit 1555 1556config HAVE_ARM_TWD 1557 bool 1558 depends on SMP 1559 select TICK_ONESHOT 1560 help 1561 This options enables support for the ARM timer and watchdog unit 1562 1563choice 1564 prompt "Memory split" 1565 default VMSPLIT_3G 1566 help 1567 Select the desired split between kernel and user memory. 1568 1569 If you are not absolutely sure what you are doing, leave this 1570 option alone! 1571 1572 config VMSPLIT_3G 1573 bool "3G/1G user/kernel split" 1574 config VMSPLIT_2G 1575 bool "2G/2G user/kernel split" 1576 config VMSPLIT_1G 1577 bool "1G/3G user/kernel split" 1578endchoice 1579 1580config PAGE_OFFSET 1581 hex 1582 default 0x40000000 if VMSPLIT_1G 1583 default 0x80000000 if VMSPLIT_2G 1584 default 0xC0000000 1585 1586config NR_CPUS 1587 int "Maximum number of CPUs (2-32)" 1588 range 2 32 1589 depends on SMP 1590 default "4" 1591 1592config HOTPLUG_CPU 1593 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1594 depends on SMP && HOTPLUG && EXPERIMENTAL 1595 help 1596 Say Y here to experiment with turning CPUs off and on. CPUs 1597 can be controlled through /sys/devices/system/cpu. 1598 1599config LOCAL_TIMERS 1600 bool "Use local timer interrupts" 1601 depends on SMP 1602 default y 1603 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1604 help 1605 Enable support for local timers on SMP platforms, rather then the 1606 legacy IPI broadcast method. Local timers allows the system 1607 accounting to be spread across the timer interval, preventing a 1608 "thundering herd" at every timer tick. 1609 1610config ARCH_NR_GPIO 1611 int 1612 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1613 default 355 if ARCH_U8500 1614 default 264 if MACH_H4700 1615 default 0 1616 help 1617 Maximum number of GPIOs in the system. 1618 1619 If unsure, leave the default value. 1620 1621source kernel/Kconfig.preempt 1622 1623config HZ 1624 int 1625 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1626 ARCH_S5PV210 || ARCH_EXYNOS4 1627 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1628 default AT91_TIMER_HZ if ARCH_AT91 1629 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1630 default 100 1631 1632config THUMB2_KERNEL 1633 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1634 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1635 select AEABI 1636 select ARM_ASM_UNIFIED 1637 select ARM_UNWIND 1638 help 1639 By enabling this option, the kernel will be compiled in 1640 Thumb-2 mode. A compiler/assembler that understand the unified 1641 ARM-Thumb syntax is needed. 1642 1643 If unsure, say N. 1644 1645config THUMB2_AVOID_R_ARM_THM_JUMP11 1646 bool "Work around buggy Thumb-2 short branch relocations in gas" 1647 depends on THUMB2_KERNEL && MODULES 1648 default y 1649 help 1650 Various binutils versions can resolve Thumb-2 branches to 1651 locally-defined, preemptible global symbols as short-range "b.n" 1652 branch instructions. 1653 1654 This is a problem, because there's no guarantee the final 1655 destination of the symbol, or any candidate locations for a 1656 trampoline, are within range of the branch. For this reason, the 1657 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1658 relocation in modules at all, and it makes little sense to add 1659 support. 1660 1661 The symptom is that the kernel fails with an "unsupported 1662 relocation" error when loading some modules. 1663 1664 Until fixed tools are available, passing 1665 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1666 code which hits this problem, at the cost of a bit of extra runtime 1667 stack usage in some cases. 1668 1669 The problem is described in more detail at: 1670 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1671 1672 Only Thumb-2 kernels are affected. 1673 1674 Unless you are sure your tools don't have this problem, say Y. 1675 1676config ARM_ASM_UNIFIED 1677 bool 1678 1679config AEABI 1680 bool "Use the ARM EABI to compile the kernel" 1681 help 1682 This option allows for the kernel to be compiled using the latest 1683 ARM ABI (aka EABI). This is only useful if you are using a user 1684 space environment that is also compiled with EABI. 1685 1686 Since there are major incompatibilities between the legacy ABI and 1687 EABI, especially with regard to structure member alignment, this 1688 option also changes the kernel syscall calling convention to 1689 disambiguate both ABIs and allow for backward compatibility support 1690 (selected with CONFIG_OABI_COMPAT). 1691 1692 To use this you need GCC version 4.0.0 or later. 1693 1694config OABI_COMPAT 1695 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1696 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1697 default y 1698 help 1699 This option preserves the old syscall interface along with the 1700 new (ARM EABI) one. It also provides a compatibility layer to 1701 intercept syscalls that have structure arguments which layout 1702 in memory differs between the legacy ABI and the new ARM EABI 1703 (only for non "thumb" binaries). This option adds a tiny 1704 overhead to all syscalls and produces a slightly larger kernel. 1705 If you know you'll be using only pure EABI user space then you 1706 can say N here. If this option is not selected and you attempt 1707 to execute a legacy ABI binary then the result will be 1708 UNPREDICTABLE (in fact it can be predicted that it won't work 1709 at all). If in doubt say Y. 1710 1711config ARCH_HAS_HOLES_MEMORYMODEL 1712 bool 1713 1714config ARCH_SPARSEMEM_ENABLE 1715 bool 1716 1717config ARCH_SPARSEMEM_DEFAULT 1718 def_bool ARCH_SPARSEMEM_ENABLE 1719 1720config ARCH_SELECT_MEMORY_MODEL 1721 def_bool ARCH_SPARSEMEM_ENABLE 1722 1723config HAVE_ARCH_PFN_VALID 1724 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1725 1726config HIGHMEM 1727 bool "High Memory Support" 1728 depends on MMU 1729 help 1730 The address space of ARM processors is only 4 Gigabytes large 1731 and it has to accommodate user address space, kernel address 1732 space as well as some memory mapped IO. That means that, if you 1733 have a large amount of physical memory and/or IO, not all of the 1734 memory can be "permanently mapped" by the kernel. The physical 1735 memory that is not permanently mapped is called "high memory". 1736 1737 Depending on the selected kernel/user memory split, minimum 1738 vmalloc space and actual amount of RAM, you may not need this 1739 option which should result in a slightly faster kernel. 1740 1741 If unsure, say n. 1742 1743config HIGHPTE 1744 bool "Allocate 2nd-level pagetables from highmem" 1745 depends on HIGHMEM 1746 1747config HW_PERF_EVENTS 1748 bool "Enable hardware performance counter support for perf events" 1749 depends on PERF_EVENTS && CPU_HAS_PMU 1750 default y 1751 help 1752 Enable hardware performance counter support for perf events. If 1753 disabled, perf events will use software events only. 1754 1755source "mm/Kconfig" 1756 1757config FORCE_MAX_ZONEORDER 1758 int "Maximum zone order" if ARCH_SHMOBILE 1759 range 11 64 if ARCH_SHMOBILE 1760 default "9" if SA1111 1761 default "11" 1762 help 1763 The kernel memory allocator divides physically contiguous memory 1764 blocks into "zones", where each zone is a power of two number of 1765 pages. This option selects the largest power of two that the kernel 1766 keeps in the memory allocator. If you need to allocate very large 1767 blocks of physically contiguous memory, then you may need to 1768 increase this value. 1769 1770 This config option is actually maximum order plus one. For example, 1771 a value of 11 means that the largest free memory block is 2^10 pages. 1772 1773config LEDS 1774 bool "Timer and CPU usage LEDs" 1775 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1776 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1777 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1778 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1779 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1780 ARCH_AT91 || ARCH_DAVINCI || \ 1781 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1782 help 1783 If you say Y here, the LEDs on your machine will be used 1784 to provide useful information about your current system status. 1785 1786 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1787 be able to select which LEDs are active using the options below. If 1788 you are compiling a kernel for the EBSA-110 or the LART however, the 1789 red LED will simply flash regularly to indicate that the system is 1790 still functional. It is safe to say Y here if you have a CATS 1791 system, but the driver will do nothing. 1792 1793config LEDS_TIMER 1794 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1795 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1796 || MACH_OMAP_PERSEUS2 1797 depends on LEDS 1798 depends on !GENERIC_CLOCKEVENTS 1799 default y if ARCH_EBSA110 1800 help 1801 If you say Y here, one of the system LEDs (the green one on the 1802 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1803 will flash regularly to indicate that the system is still 1804 operational. This is mainly useful to kernel hackers who are 1805 debugging unstable kernels. 1806 1807 The LART uses the same LED for both Timer LED and CPU usage LED 1808 functions. You may choose to use both, but the Timer LED function 1809 will overrule the CPU usage LED. 1810 1811config LEDS_CPU 1812 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1813 !ARCH_OMAP) \ 1814 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1815 || MACH_OMAP_PERSEUS2 1816 depends on LEDS 1817 help 1818 If you say Y here, the red LED will be used to give a good real 1819 time indication of CPU usage, by lighting whenever the idle task 1820 is not currently executing. 1821 1822 The LART uses the same LED for both Timer LED and CPU usage LED 1823 functions. You may choose to use both, but the Timer LED function 1824 will overrule the CPU usage LED. 1825 1826config ALIGNMENT_TRAP 1827 bool 1828 depends on CPU_CP15_MMU 1829 default y if !ARCH_EBSA110 1830 select HAVE_PROC_CPU if PROC_FS 1831 help 1832 ARM processors cannot fetch/store information which is not 1833 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1834 address divisible by 4. On 32-bit ARM processors, these non-aligned 1835 fetch/store instructions will be emulated in software if you say 1836 here, which has a severe performance impact. This is necessary for 1837 correct operation of some network protocols. With an IP-only 1838 configuration it is safe to say N, otherwise say Y. 1839 1840config UACCESS_WITH_MEMCPY 1841 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1842 depends on MMU && EXPERIMENTAL 1843 default y if CPU_FEROCEON 1844 help 1845 Implement faster copy_to_user and clear_user methods for CPU 1846 cores where a 8-word STM instruction give significantly higher 1847 memory write throughput than a sequence of individual 32bit stores. 1848 1849 A possible side effect is a slight increase in scheduling latency 1850 between threads sharing the same address space if they invoke 1851 such copy operations with large buffers. 1852 1853 However, if the CPU data cache is using a write-allocate mode, 1854 this option is unlikely to provide any performance gain. 1855 1856config SECCOMP 1857 bool 1858 prompt "Enable seccomp to safely compute untrusted bytecode" 1859 ---help--- 1860 This kernel feature is useful for number crunching applications 1861 that may need to compute untrusted bytecode during their 1862 execution. By using pipes or other transports made available to 1863 the process as file descriptors supporting the read/write 1864 syscalls, it's possible to isolate those applications in 1865 their own address space using seccomp. Once seccomp is 1866 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1867 and the task is only allowed to execute a few safe syscalls 1868 defined by each seccomp mode. 1869 1870config CC_STACKPROTECTOR 1871 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1872 depends on EXPERIMENTAL 1873 help 1874 This option turns on the -fstack-protector GCC feature. This 1875 feature puts, at the beginning of functions, a canary value on 1876 the stack just before the return address, and validates 1877 the value just before actually returning. Stack based buffer 1878 overflows (that need to overwrite this return address) now also 1879 overwrite the canary, which gets detected and the attack is then 1880 neutralized via a kernel panic. 1881 This feature requires gcc version 4.2 or above. 1882 1883config DEPRECATED_PARAM_STRUCT 1884 bool "Provide old way to pass kernel parameters" 1885 help 1886 This was deprecated in 2001 and announced to live on for 5 years. 1887 Some old boot loaders still use this way. 1888 1889endmenu 1890 1891menu "Boot options" 1892 1893config USE_OF 1894 bool "Flattened Device Tree support" 1895 select OF 1896 select OF_EARLY_FLATTREE 1897 select IRQ_DOMAIN 1898 help 1899 Include support for flattened device tree machine descriptions. 1900 1901# Compressed boot loader in ROM. Yes, we really want to ask about 1902# TEXT and BSS so we preserve their values in the config files. 1903config ZBOOT_ROM_TEXT 1904 hex "Compressed ROM boot loader base address" 1905 default "0" 1906 help 1907 The physical address at which the ROM-able zImage is to be 1908 placed in the target. Platforms which normally make use of 1909 ROM-able zImage formats normally set this to a suitable 1910 value in their defconfig file. 1911 1912 If ZBOOT_ROM is not enabled, this has no effect. 1913 1914config ZBOOT_ROM_BSS 1915 hex "Compressed ROM boot loader BSS address" 1916 default "0" 1917 help 1918 The base address of an area of read/write memory in the target 1919 for the ROM-able zImage which must be available while the 1920 decompressor is running. It must be large enough to hold the 1921 entire decompressed kernel plus an additional 128 KiB. 1922 Platforms which normally make use of ROM-able zImage formats 1923 normally set this to a suitable value in their defconfig file. 1924 1925 If ZBOOT_ROM is not enabled, this has no effect. 1926 1927config ZBOOT_ROM 1928 bool "Compressed boot loader in ROM/flash" 1929 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1930 help 1931 Say Y here if you intend to execute your compressed kernel image 1932 (zImage) directly from ROM or flash. If unsure, say N. 1933 1934choice 1935 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1936 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1937 default ZBOOT_ROM_NONE 1938 help 1939 Include experimental SD/MMC loading code in the ROM-able zImage. 1940 With this enabled it is possible to write the the ROM-able zImage 1941 kernel image to an MMC or SD card and boot the kernel straight 1942 from the reset vector. At reset the processor Mask ROM will load 1943 the first part of the the ROM-able zImage which in turn loads the 1944 rest the kernel image to RAM. 1945 1946config ZBOOT_ROM_NONE 1947 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1948 help 1949 Do not load image from SD or MMC 1950 1951config ZBOOT_ROM_MMCIF 1952 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1953 help 1954 Load image from MMCIF hardware block. 1955 1956config ZBOOT_ROM_SH_MOBILE_SDHI 1957 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1958 help 1959 Load image from SDHI hardware block 1960 1961endchoice 1962 1963config ARM_APPENDED_DTB 1964 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1965 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1966 help 1967 With this option, the boot code will look for a device tree binary 1968 (DTB) appended to zImage 1969 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1970 1971 This is meant as a backward compatibility convenience for those 1972 systems with a bootloader that can't be upgraded to accommodate 1973 the documented boot protocol using a device tree. 1974 1975 Beware that there is very little in terms of protection against 1976 this option being confused by leftover garbage in memory that might 1977 look like a DTB header after a reboot if no actual DTB is appended 1978 to zImage. Do not leave this option active in a production kernel 1979 if you don't intend to always append a DTB. Proper passing of the 1980 location into r2 of a bootloader provided DTB is always preferable 1981 to this option. 1982 1983config ARM_ATAG_DTB_COMPAT 1984 bool "Supplement the appended DTB with traditional ATAG information" 1985 depends on ARM_APPENDED_DTB 1986 help 1987 Some old bootloaders can't be updated to a DTB capable one, yet 1988 they provide ATAGs with memory configuration, the ramdisk address, 1989 the kernel cmdline string, etc. Such information is dynamically 1990 provided by the bootloader and can't always be stored in a static 1991 DTB. To allow a device tree enabled kernel to be used with such 1992 bootloaders, this option allows zImage to extract the information 1993 from the ATAG list and store it at run time into the appended DTB. 1994 1995config CMDLINE 1996 string "Default kernel command string" 1997 default "" 1998 help 1999 On some architectures (EBSA110 and CATS), there is currently no way 2000 for the boot loader to pass arguments to the kernel. For these 2001 architectures, you should supply some command-line options at build 2002 time by entering them here. As a minimum, you should specify the 2003 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2004 2005choice 2006 prompt "Kernel command line type" if CMDLINE != "" 2007 default CMDLINE_FROM_BOOTLOADER 2008 2009config CMDLINE_FROM_BOOTLOADER 2010 bool "Use bootloader kernel arguments if available" 2011 help 2012 Uses the command-line options passed by the boot loader. If 2013 the boot loader doesn't provide any, the default kernel command 2014 string provided in CMDLINE will be used. 2015 2016config CMDLINE_EXTEND 2017 bool "Extend bootloader kernel arguments" 2018 help 2019 The command-line arguments provided by the boot loader will be 2020 appended to the default kernel command string. 2021 2022config CMDLINE_FORCE 2023 bool "Always use the default kernel command string" 2024 help 2025 Always use the default kernel command string, even if the boot 2026 loader passes other arguments to the kernel. 2027 This is useful if you cannot or don't want to change the 2028 command-line options your boot loader passes to the kernel. 2029endchoice 2030 2031config XIP_KERNEL 2032 bool "Kernel Execute-In-Place from ROM" 2033 depends on !ZBOOT_ROM && !ARM_LPAE 2034 help 2035 Execute-In-Place allows the kernel to run from non-volatile storage 2036 directly addressable by the CPU, such as NOR flash. This saves RAM 2037 space since the text section of the kernel is not loaded from flash 2038 to RAM. Read-write sections, such as the data section and stack, 2039 are still copied to RAM. The XIP kernel is not compressed since 2040 it has to run directly from flash, so it will take more space to 2041 store it. The flash address used to link the kernel object files, 2042 and for storing it, is configuration dependent. Therefore, if you 2043 say Y here, you must know the proper physical address where to 2044 store the kernel image depending on your own flash memory usage. 2045 2046 Also note that the make target becomes "make xipImage" rather than 2047 "make zImage" or "make Image". The final kernel binary to put in 2048 ROM memory will be arch/arm/boot/xipImage. 2049 2050 If unsure, say N. 2051 2052config XIP_PHYS_ADDR 2053 hex "XIP Kernel Physical Location" 2054 depends on XIP_KERNEL 2055 default "0x00080000" 2056 help 2057 This is the physical address in your flash memory the kernel will 2058 be linked for and stored to. This address is dependent on your 2059 own flash usage. 2060 2061config KEXEC 2062 bool "Kexec system call (EXPERIMENTAL)" 2063 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2064 help 2065 kexec is a system call that implements the ability to shutdown your 2066 current kernel, and to start another kernel. It is like a reboot 2067 but it is independent of the system firmware. And like a reboot 2068 you can start any kernel with it, not just Linux. 2069 2070 It is an ongoing process to be certain the hardware in a machine 2071 is properly shutdown, so do not be surprised if this code does not 2072 initially work for you. It may help to enable device hotplugging 2073 support. 2074 2075config ATAGS_PROC 2076 bool "Export atags in procfs" 2077 depends on KEXEC 2078 default y 2079 help 2080 Should the atags used to boot the kernel be exported in an "atags" 2081 file in procfs. Useful with kexec. 2082 2083config CRASH_DUMP 2084 bool "Build kdump crash kernel (EXPERIMENTAL)" 2085 depends on EXPERIMENTAL 2086 help 2087 Generate crash dump after being started by kexec. This should 2088 be normally only set in special crash dump kernels which are 2089 loaded in the main kernel with kexec-tools into a specially 2090 reserved region and then later executed after a crash by 2091 kdump/kexec. The crash dump kernel must be compiled to a 2092 memory address not used by the main kernel 2093 2094 For more details see Documentation/kdump/kdump.txt 2095 2096config AUTO_ZRELADDR 2097 bool "Auto calculation of the decompressed kernel image address" 2098 depends on !ZBOOT_ROM && !ARCH_U300 2099 help 2100 ZRELADDR is the physical address where the decompressed kernel 2101 image will be placed. If AUTO_ZRELADDR is selected, the address 2102 will be determined at run-time by masking the current IP with 2103 0xf8000000. This assumes the zImage being placed in the first 128MB 2104 from start of memory. 2105 2106endmenu 2107 2108menu "CPU Power Management" 2109 2110if ARCH_HAS_CPUFREQ 2111 2112source "drivers/cpufreq/Kconfig" 2113 2114config CPU_FREQ_IMX 2115 tristate "CPUfreq driver for i.MX CPUs" 2116 depends on ARCH_MXC && CPU_FREQ 2117 help 2118 This enables the CPUfreq driver for i.MX CPUs. 2119 2120config CPU_FREQ_SA1100 2121 bool 2122 2123config CPU_FREQ_SA1110 2124 bool 2125 2126config CPU_FREQ_INTEGRATOR 2127 tristate "CPUfreq driver for ARM Integrator CPUs" 2128 depends on ARCH_INTEGRATOR && CPU_FREQ 2129 default y 2130 help 2131 This enables the CPUfreq driver for ARM Integrator CPUs. 2132 2133 For details, take a look at <file:Documentation/cpu-freq>. 2134 2135 If in doubt, say Y. 2136 2137config CPU_FREQ_PXA 2138 bool 2139 depends on CPU_FREQ && ARCH_PXA && PXA25x 2140 default y 2141 select CPU_FREQ_TABLE 2142 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2143 2144config CPU_FREQ_S3C 2145 bool 2146 help 2147 Internal configuration node for common cpufreq on Samsung SoC 2148 2149config CPU_FREQ_S3C24XX 2150 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2151 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL 2152 select CPU_FREQ_S3C 2153 help 2154 This enables the CPUfreq driver for the Samsung S3C24XX family 2155 of CPUs. 2156 2157 For details, take a look at <file:Documentation/cpu-freq>. 2158 2159 If in doubt, say N. 2160 2161config CPU_FREQ_S3C24XX_PLL 2162 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2163 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2164 help 2165 Compile in support for changing the PLL frequency from the 2166 S3C24XX series CPUfreq driver. The PLL takes time to settle 2167 after a frequency change, so by default it is not enabled. 2168 2169 This also means that the PLL tables for the selected CPU(s) will 2170 be built which may increase the size of the kernel image. 2171 2172config CPU_FREQ_S3C24XX_DEBUG 2173 bool "Debug CPUfreq Samsung driver core" 2174 depends on CPU_FREQ_S3C24XX 2175 help 2176 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2177 2178config CPU_FREQ_S3C24XX_IODEBUG 2179 bool "Debug CPUfreq Samsung driver IO timing" 2180 depends on CPU_FREQ_S3C24XX 2181 help 2182 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2183 2184config CPU_FREQ_S3C24XX_DEBUGFS 2185 bool "Export debugfs for CPUFreq" 2186 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2187 help 2188 Export status information via debugfs. 2189 2190endif 2191 2192source "drivers/cpuidle/Kconfig" 2193 2194endmenu 2195 2196menu "Floating point emulation" 2197 2198comment "At least one emulation must be selected" 2199 2200config FPE_NWFPE 2201 bool "NWFPE math emulation" 2202 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2203 ---help--- 2204 Say Y to include the NWFPE floating point emulator in the kernel. 2205 This is necessary to run most binaries. Linux does not currently 2206 support floating point hardware so you need to say Y here even if 2207 your machine has an FPA or floating point co-processor podule. 2208 2209 You may say N here if you are going to load the Acorn FPEmulator 2210 early in the bootup. 2211 2212config FPE_NWFPE_XP 2213 bool "Support extended precision" 2214 depends on FPE_NWFPE 2215 help 2216 Say Y to include 80-bit support in the kernel floating-point 2217 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2218 Note that gcc does not generate 80-bit operations by default, 2219 so in most cases this option only enlarges the size of the 2220 floating point emulator without any good reason. 2221 2222 You almost surely want to say N here. 2223 2224config FPE_FASTFPE 2225 bool "FastFPE math emulation (EXPERIMENTAL)" 2226 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2227 ---help--- 2228 Say Y here to include the FAST floating point emulator in the kernel. 2229 This is an experimental much faster emulator which now also has full 2230 precision for the mantissa. It does not support any exceptions. 2231 It is very simple, and approximately 3-6 times faster than NWFPE. 2232 2233 It should be sufficient for most programs. It may be not suitable 2234 for scientific calculations, but you have to check this for yourself. 2235 If you do not feel you need a faster FP emulation you should better 2236 choose NWFPE. 2237 2238config VFP 2239 bool "VFP-format floating point maths" 2240 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2241 help 2242 Say Y to include VFP support code in the kernel. This is needed 2243 if your hardware includes a VFP unit. 2244 2245 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2246 release notes and additional status information. 2247 2248 Say N if your target does not have VFP hardware. 2249 2250config VFPv3 2251 bool 2252 depends on VFP 2253 default y if CPU_V7 2254 2255config NEON 2256 bool "Advanced SIMD (NEON) Extension support" 2257 depends on VFPv3 && CPU_V7 2258 help 2259 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2260 Extension. 2261 2262endmenu 2263 2264menu "Userspace binary formats" 2265 2266source "fs/Kconfig.binfmt" 2267 2268config ARTHUR 2269 tristate "RISC OS personality" 2270 depends on !AEABI 2271 help 2272 Say Y here to include the kernel code necessary if you want to run 2273 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2274 experimental; if this sounds frightening, say N and sleep in peace. 2275 You can also say M here to compile this support as a module (which 2276 will be called arthur). 2277 2278endmenu 2279 2280menu "Power management options" 2281 2282source "kernel/power/Kconfig" 2283 2284config ARCH_SUSPEND_POSSIBLE 2285 depends on !ARCH_S5PC100 2286 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2287 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2288 def_bool y 2289 2290config ARM_CPU_SUSPEND 2291 def_bool PM_SLEEP 2292 2293endmenu 2294 2295source "net/Kconfig" 2296 2297source "drivers/Kconfig" 2298 2299source "fs/Kconfig" 2300 2301source "arch/arm/Kconfig.debug" 2302 2303source "security/Kconfig" 2304 2305source "crypto/Kconfig" 2306 2307source "lib/Kconfig" 2308