1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 13 select HAVE_ARCH_KGDB 14 select HAVE_KPROBES if !XIP_KERNEL 15 select HAVE_KRETPROBES if (HAVE_KPROBES) 16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 21 select HAVE_GENERIC_DMA_COHERENT 22 select HAVE_KERNEL_GZIP 23 select HAVE_KERNEL_LZO 24 select HAVE_KERNEL_LZMA 25 select HAVE_KERNEL_XZ 26 select HAVE_IRQ_WORK 27 select HAVE_PERF_EVENTS 28 select PERF_USE_VMALLOC 29 select HAVE_REGS_AND_STACK_ACCESS_API 30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 31 select HAVE_C_RECORDMCOUNT 32 select HAVE_GENERIC_HARDIRQS 33 select GENERIC_IRQ_SHOW 34 select CPU_PM if (SUSPEND || CPU_IDLE) 35 select GENERIC_PCI_IOMAP 36 select HAVE_BPF_JIT if NET 37 help 38 The ARM series is a line of low-power-consumption RISC chip designs 39 licensed by ARM Ltd and targeted at embedded applications and 40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 41 manufactured, but legacy ARM-based PC hardware remains popular in 42 Europe. There is an ARM Linux project with a web page at 43 <http://www.arm.linux.org.uk/>. 44 45config ARM_HAS_SG_CHAIN 46 bool 47 48config HAVE_PWM 49 bool 50 51config MIGHT_HAVE_PCI 52 bool 53 54config SYS_SUPPORTS_APM_EMULATION 55 bool 56 57config GENERIC_GPIO 58 bool 59 60config ARCH_USES_GETTIMEOFFSET 61 bool 62 default n 63 64config GENERIC_CLOCKEVENTS 65 bool 66 67config GENERIC_CLOCKEVENTS_BROADCAST 68 bool 69 depends on GENERIC_CLOCKEVENTS 70 default y if SMP 71 72config KTIME_SCALAR 73 bool 74 default y 75 76config HAVE_TCM 77 bool 78 select GENERIC_ALLOCATOR 79 80config HAVE_PROC_CPU 81 bool 82 83config NO_IOPORT 84 bool 85 86config EISA 87 bool 88 ---help--- 89 The Extended Industry Standard Architecture (EISA) bus was 90 developed as an open alternative to the IBM MicroChannel bus. 91 92 The EISA bus provided some of the features of the IBM MicroChannel 93 bus while maintaining backward compatibility with cards made for 94 the older ISA bus. The EISA bus saw limited use between 1988 and 95 1995 when it was made obsolete by the PCI bus. 96 97 Say Y here if you are building a kernel for an EISA-based machine. 98 99 Otherwise, say N. 100 101config SBUS 102 bool 103 104config MCA 105 bool 106 help 107 MicroChannel Architecture is found in some IBM PS/2 machines and 108 laptops. It is a bus system similar to PCI or ISA. See 109 <file:Documentation/mca.txt> (and especially the web page given 110 there) before attempting to build an MCA bus kernel. 111 112config STACKTRACE_SUPPORT 113 bool 114 default y 115 116config HAVE_LATENCYTOP_SUPPORT 117 bool 118 depends on !SMP 119 default y 120 121config LOCKDEP_SUPPORT 122 bool 123 default y 124 125config TRACE_IRQFLAGS_SUPPORT 126 bool 127 default y 128 129config HARDIRQS_SW_RESEND 130 bool 131 default y 132 133config GENERIC_IRQ_PROBE 134 bool 135 default y 136 137config GENERIC_LOCKBREAK 138 bool 139 default y 140 depends on SMP && PREEMPT 141 142config RWSEM_GENERIC_SPINLOCK 143 bool 144 default y 145 146config RWSEM_XCHGADD_ALGORITHM 147 bool 148 149config ARCH_HAS_ILOG2_U32 150 bool 151 152config ARCH_HAS_ILOG2_U64 153 bool 154 155config ARCH_HAS_CPUFREQ 156 bool 157 help 158 Internal node to signify that the ARCH has CPUFREQ support 159 and that the relevant menu configurations are displayed for 160 it. 161 162config ARCH_HAS_CPU_IDLE_WAIT 163 def_bool y 164 165config GENERIC_HWEIGHT 166 bool 167 default y 168 169config GENERIC_CALIBRATE_DELAY 170 bool 171 default y 172 173config ARCH_MAY_HAVE_PC_FDC 174 bool 175 176config ZONE_DMA 177 bool 178 179config NEED_DMA_MAP_STATE 180 def_bool y 181 182config ARCH_HAS_DMA_SET_COHERENT_MASK 183 bool 184 185config GENERIC_ISA_DMA 186 bool 187 188config FIQ 189 bool 190 191config NEED_RET_TO_USER 192 bool 193 194config ARCH_MTD_XIP 195 bool 196 197config VECTORS_BASE 198 hex 199 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 200 default DRAM_BASE if REMAP_VECTORS_TO_RAM 201 default 0x00000000 202 help 203 The base address of exception vectors. 204 205config ARM_PATCH_PHYS_VIRT 206 bool "Patch physical to virtual translations at runtime" if EMBEDDED 207 default y 208 depends on !XIP_KERNEL && MMU 209 depends on !ARCH_REALVIEW || !SPARSEMEM 210 help 211 Patch phys-to-virt and virt-to-phys translation functions at 212 boot and module load time according to the position of the 213 kernel in system memory. 214 215 This can only be used with non-XIP MMU kernels where the base 216 of physical memory is at a 16MB boundary. 217 218 Only disable this option if you know that you do not require 219 this feature (eg, building a kernel for a single machine) and 220 you need to shrink the kernel to the minimal size. 221 222config NEED_MACH_IO_H 223 bool 224 help 225 Select this when mach/io.h is required to provide special 226 definitions for this platform. The need for mach/io.h should 227 be avoided when possible. 228 229config NEED_MACH_MEMORY_H 230 bool 231 help 232 Select this when mach/memory.h is required to provide special 233 definitions for this platform. The need for mach/memory.h should 234 be avoided when possible. 235 236config PHYS_OFFSET 237 hex "Physical address of main memory" if MMU 238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 239 default DRAM_BASE if !MMU 240 help 241 Please provide the physical address corresponding to the 242 location of main memory in your system. 243 244config GENERIC_BUG 245 def_bool y 246 depends on BUG 247 248source "init/Kconfig" 249 250source "kernel/Kconfig.freezer" 251 252menu "System Type" 253 254config MMU 255 bool "MMU-based Paged Memory Management Support" 256 default y 257 help 258 Select if you want MMU-based virtualised addressing space 259 support by paged memory management. If unsure, say 'Y'. 260 261# 262# The "ARM system type" choice list is ordered alphabetically by option 263# text. Please add new entries in the option alphabetic order. 264# 265choice 266 prompt "ARM system type" 267 default ARCH_VERSATILE 268 269config ARCH_INTEGRATOR 270 bool "ARM Ltd. Integrator family" 271 select ARM_AMBA 272 select ARCH_HAS_CPUFREQ 273 select CLKDEV_LOOKUP 274 select HAVE_MACH_CLKDEV 275 select HAVE_TCM 276 select ICST 277 select GENERIC_CLOCKEVENTS 278 select PLAT_VERSATILE 279 select PLAT_VERSATILE_FPGA_IRQ 280 select NEED_MACH_IO_H 281 select NEED_MACH_MEMORY_H 282 select SPARSE_IRQ 283 help 284 Support for ARM's Integrator platform. 285 286config ARCH_REALVIEW 287 bool "ARM Ltd. RealView family" 288 select ARM_AMBA 289 select CLKDEV_LOOKUP 290 select HAVE_MACH_CLKDEV 291 select ICST 292 select GENERIC_CLOCKEVENTS 293 select ARCH_WANT_OPTIONAL_GPIOLIB 294 select PLAT_VERSATILE 295 select PLAT_VERSATILE_CLCD 296 select ARM_TIMER_SP804 297 select GPIO_PL061 if GPIOLIB 298 select NEED_MACH_MEMORY_H 299 help 300 This enables support for ARM Ltd RealView boards. 301 302config ARCH_VERSATILE 303 bool "ARM Ltd. Versatile family" 304 select ARM_AMBA 305 select ARM_VIC 306 select CLKDEV_LOOKUP 307 select HAVE_MACH_CLKDEV 308 select ICST 309 select GENERIC_CLOCKEVENTS 310 select ARCH_WANT_OPTIONAL_GPIOLIB 311 select PLAT_VERSATILE 312 select PLAT_VERSATILE_CLCD 313 select PLAT_VERSATILE_FPGA_IRQ 314 select ARM_TIMER_SP804 315 help 316 This enables support for ARM Ltd Versatile board. 317 318config ARCH_VEXPRESS 319 bool "ARM Ltd. Versatile Express family" 320 select ARCH_WANT_OPTIONAL_GPIOLIB 321 select ARM_AMBA 322 select ARM_TIMER_SP804 323 select CLKDEV_LOOKUP 324 select HAVE_MACH_CLKDEV 325 select GENERIC_CLOCKEVENTS 326 select HAVE_CLK 327 select HAVE_PATA_PLATFORM 328 select ICST 329 select NO_IOPORT 330 select PLAT_VERSATILE 331 select PLAT_VERSATILE_CLCD 332 help 333 This enables support for the ARM Ltd Versatile Express boards. 334 335config ARCH_AT91 336 bool "Atmel AT91" 337 select ARCH_REQUIRE_GPIOLIB 338 select HAVE_CLK 339 select CLKDEV_LOOKUP 340 select IRQ_DOMAIN 341 select NEED_MACH_IO_H if PCCARD 342 help 343 This enables support for systems based on the Atmel AT91RM9200, 344 AT91SAM9 processors. 345 346config ARCH_BCMRING 347 bool "Broadcom BCMRING" 348 depends on MMU 349 select CPU_V6 350 select ARM_AMBA 351 select ARM_TIMER_SP804 352 select CLKDEV_LOOKUP 353 select GENERIC_CLOCKEVENTS 354 select ARCH_WANT_OPTIONAL_GPIOLIB 355 help 356 Support for Broadcom's BCMRing platform. 357 358config ARCH_HIGHBANK 359 bool "Calxeda Highbank-based" 360 select ARCH_WANT_OPTIONAL_GPIOLIB 361 select ARM_AMBA 362 select ARM_GIC 363 select ARM_TIMER_SP804 364 select CACHE_L2X0 365 select CLKDEV_LOOKUP 366 select CPU_V7 367 select GENERIC_CLOCKEVENTS 368 select HAVE_ARM_SCU 369 select HAVE_SMP 370 select SPARSE_IRQ 371 select USE_OF 372 help 373 Support for the Calxeda Highbank SoC based boards. 374 375config ARCH_CLPS711X 376 bool "Cirrus Logic CLPS711x/EP721x-based" 377 select CPU_ARM720T 378 select ARCH_USES_GETTIMEOFFSET 379 select NEED_MACH_MEMORY_H 380 help 381 Support for Cirrus Logic 711x/721x based boards. 382 383config ARCH_CNS3XXX 384 bool "Cavium Networks CNS3XXX family" 385 select CPU_V6K 386 select GENERIC_CLOCKEVENTS 387 select ARM_GIC 388 select MIGHT_HAVE_CACHE_L2X0 389 select MIGHT_HAVE_PCI 390 select PCI_DOMAINS if PCI 391 help 392 Support for Cavium Networks CNS3XXX platform. 393 394config ARCH_GEMINI 395 bool "Cortina Systems Gemini" 396 select CPU_FA526 397 select ARCH_REQUIRE_GPIOLIB 398 select ARCH_USES_GETTIMEOFFSET 399 help 400 Support for the Cortina Systems Gemini family SoCs 401 402config ARCH_PRIMA2 403 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 404 select CPU_V7 405 select NO_IOPORT 406 select GENERIC_CLOCKEVENTS 407 select CLKDEV_LOOKUP 408 select GENERIC_IRQ_CHIP 409 select MIGHT_HAVE_CACHE_L2X0 410 select USE_OF 411 select ZONE_DMA 412 help 413 Support for CSR SiRFSoC ARM Cortex A9 Platform 414 415config ARCH_EBSA110 416 bool "EBSA-110" 417 select CPU_SA110 418 select ISA 419 select NO_IOPORT 420 select ARCH_USES_GETTIMEOFFSET 421 select NEED_MACH_IO_H 422 select NEED_MACH_MEMORY_H 423 help 424 This is an evaluation board for the StrongARM processor available 425 from Digital. It has limited hardware on-board, including an 426 Ethernet interface, two PCMCIA sockets, two serial ports and a 427 parallel port. 428 429config ARCH_EP93XX 430 bool "EP93xx-based" 431 select CPU_ARM920T 432 select ARM_AMBA 433 select ARM_VIC 434 select CLKDEV_LOOKUP 435 select ARCH_REQUIRE_GPIOLIB 436 select ARCH_HAS_HOLES_MEMORYMODEL 437 select ARCH_USES_GETTIMEOFFSET 438 select NEED_MACH_MEMORY_H 439 help 440 This enables support for the Cirrus EP93xx series of CPUs. 441 442config ARCH_FOOTBRIDGE 443 bool "FootBridge" 444 select CPU_SA110 445 select FOOTBRIDGE 446 select GENERIC_CLOCKEVENTS 447 select HAVE_IDE 448 select NEED_MACH_IO_H 449 select NEED_MACH_MEMORY_H 450 help 451 Support for systems based on the DC21285 companion chip 452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 453 454config ARCH_MXC 455 bool "Freescale MXC/iMX-based" 456 select GENERIC_CLOCKEVENTS 457 select ARCH_REQUIRE_GPIOLIB 458 select CLKDEV_LOOKUP 459 select CLKSRC_MMIO 460 select GENERIC_IRQ_CHIP 461 select MULTI_IRQ_HANDLER 462 help 463 Support for Freescale MXC/iMX-based family of processors 464 465config ARCH_MXS 466 bool "Freescale MXS-based" 467 select GENERIC_CLOCKEVENTS 468 select ARCH_REQUIRE_GPIOLIB 469 select CLKDEV_LOOKUP 470 select CLKSRC_MMIO 471 select HAVE_CLK_PREPARE 472 help 473 Support for Freescale MXS-based family of processors 474 475config ARCH_NETX 476 bool "Hilscher NetX based" 477 select CLKSRC_MMIO 478 select CPU_ARM926T 479 select ARM_VIC 480 select GENERIC_CLOCKEVENTS 481 help 482 This enables support for systems based on the Hilscher NetX Soc 483 484config ARCH_H720X 485 bool "Hynix HMS720x-based" 486 select CPU_ARM720T 487 select ISA_DMA_API 488 select ARCH_USES_GETTIMEOFFSET 489 help 490 This enables support for systems based on the Hynix HMS720x 491 492config ARCH_IOP13XX 493 bool "IOP13xx-based" 494 depends on MMU 495 select CPU_XSC3 496 select PLAT_IOP 497 select PCI 498 select ARCH_SUPPORTS_MSI 499 select VMSPLIT_1G 500 select NEED_MACH_IO_H 501 select NEED_MACH_MEMORY_H 502 select NEED_RET_TO_USER 503 help 504 Support for Intel's IOP13XX (XScale) family of processors. 505 506config ARCH_IOP32X 507 bool "IOP32x-based" 508 depends on MMU 509 select CPU_XSCALE 510 select NEED_MACH_IO_H 511 select NEED_RET_TO_USER 512 select PLAT_IOP 513 select PCI 514 select ARCH_REQUIRE_GPIOLIB 515 help 516 Support for Intel's 80219 and IOP32X (XScale) family of 517 processors. 518 519config ARCH_IOP33X 520 bool "IOP33x-based" 521 depends on MMU 522 select CPU_XSCALE 523 select NEED_MACH_IO_H 524 select NEED_RET_TO_USER 525 select PLAT_IOP 526 select PCI 527 select ARCH_REQUIRE_GPIOLIB 528 help 529 Support for Intel's IOP33X (XScale) family of processors. 530 531config ARCH_IXP23XX 532 bool "IXP23XX-based" 533 depends on MMU 534 select CPU_XSC3 535 select PCI 536 select ARCH_USES_GETTIMEOFFSET 537 select NEED_MACH_IO_H 538 select NEED_MACH_MEMORY_H 539 help 540 Support for Intel's IXP23xx (XScale) family of processors. 541 542config ARCH_IXP2000 543 bool "IXP2400/2800-based" 544 depends on MMU 545 select CPU_XSCALE 546 select PCI 547 select ARCH_USES_GETTIMEOFFSET 548 select NEED_MACH_IO_H 549 select NEED_MACH_MEMORY_H 550 help 551 Support for Intel's IXP2400/2800 (XScale) family of processors. 552 553config ARCH_IXP4XX 554 bool "IXP4xx-based" 555 depends on MMU 556 select ARCH_HAS_DMA_SET_COHERENT_MASK 557 select CLKSRC_MMIO 558 select CPU_XSCALE 559 select GENERIC_GPIO 560 select GENERIC_CLOCKEVENTS 561 select MIGHT_HAVE_PCI 562 select NEED_MACH_IO_H 563 select DMABOUNCE if PCI 564 help 565 Support for Intel's IXP4XX (XScale) family of processors. 566 567config ARCH_DOVE 568 bool "Marvell Dove" 569 select CPU_V7 570 select PCI 571 select ARCH_REQUIRE_GPIOLIB 572 select GENERIC_CLOCKEVENTS 573 select NEED_MACH_IO_H 574 select PLAT_ORION 575 help 576 Support for the Marvell Dove SoC 88AP510 577 578config ARCH_KIRKWOOD 579 bool "Marvell Kirkwood" 580 select CPU_FEROCEON 581 select PCI 582 select ARCH_REQUIRE_GPIOLIB 583 select GENERIC_CLOCKEVENTS 584 select NEED_MACH_IO_H 585 select PLAT_ORION 586 help 587 Support for the following Marvell Kirkwood series SoCs: 588 88F6180, 88F6192 and 88F6281. 589 590config ARCH_LPC32XX 591 bool "NXP LPC32XX" 592 select CLKSRC_MMIO 593 select CPU_ARM926T 594 select ARCH_REQUIRE_GPIOLIB 595 select HAVE_IDE 596 select ARM_AMBA 597 select USB_ARCH_HAS_OHCI 598 select CLKDEV_LOOKUP 599 select GENERIC_CLOCKEVENTS 600 help 601 Support for the NXP LPC32XX family of processors 602 603config ARCH_MV78XX0 604 bool "Marvell MV78xx0" 605 select CPU_FEROCEON 606 select PCI 607 select ARCH_REQUIRE_GPIOLIB 608 select GENERIC_CLOCKEVENTS 609 select NEED_MACH_IO_H 610 select PLAT_ORION 611 help 612 Support for the following Marvell MV78xx0 series SoCs: 613 MV781x0, MV782x0. 614 615config ARCH_ORION5X 616 bool "Marvell Orion" 617 depends on MMU 618 select CPU_FEROCEON 619 select PCI 620 select ARCH_REQUIRE_GPIOLIB 621 select GENERIC_CLOCKEVENTS 622 select PLAT_ORION 623 help 624 Support for the following Marvell Orion 5x series SoCs: 625 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 626 Orion-2 (5281), Orion-1-90 (6183). 627 628config ARCH_MMP 629 bool "Marvell PXA168/910/MMP2" 630 depends on MMU 631 select ARCH_REQUIRE_GPIOLIB 632 select CLKDEV_LOOKUP 633 select GENERIC_CLOCKEVENTS 634 select GPIO_PXA 635 select TICK_ONESHOT 636 select PLAT_PXA 637 select SPARSE_IRQ 638 select GENERIC_ALLOCATOR 639 help 640 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 641 642config ARCH_KS8695 643 bool "Micrel/Kendin KS8695" 644 select CPU_ARM922T 645 select ARCH_REQUIRE_GPIOLIB 646 select ARCH_USES_GETTIMEOFFSET 647 select NEED_MACH_MEMORY_H 648 help 649 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 650 System-on-Chip devices. 651 652config ARCH_W90X900 653 bool "Nuvoton W90X900 CPU" 654 select CPU_ARM926T 655 select ARCH_REQUIRE_GPIOLIB 656 select CLKDEV_LOOKUP 657 select CLKSRC_MMIO 658 select GENERIC_CLOCKEVENTS 659 help 660 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 661 At present, the w90x900 has been renamed nuc900, regarding 662 the ARM series product line, you can login the following 663 link address to know more. 664 665 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 666 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 667 668config ARCH_TEGRA 669 bool "NVIDIA Tegra" 670 select CLKDEV_LOOKUP 671 select CLKSRC_MMIO 672 select GENERIC_CLOCKEVENTS 673 select GENERIC_GPIO 674 select HAVE_CLK 675 select HAVE_SMP 676 select MIGHT_HAVE_CACHE_L2X0 677 select NEED_MACH_IO_H if PCI 678 select ARCH_HAS_CPUFREQ 679 help 680 This enables support for NVIDIA Tegra based systems (Tegra APX, 681 Tegra 6xx and Tegra 2 series). 682 683config ARCH_PICOXCELL 684 bool "Picochip picoXcell" 685 select ARCH_REQUIRE_GPIOLIB 686 select ARM_PATCH_PHYS_VIRT 687 select ARM_VIC 688 select CPU_V6K 689 select DW_APB_TIMER 690 select GENERIC_CLOCKEVENTS 691 select GENERIC_GPIO 692 select HAVE_TCM 693 select NO_IOPORT 694 select SPARSE_IRQ 695 select USE_OF 696 help 697 This enables support for systems based on the Picochip picoXcell 698 family of Femtocell devices. The picoxcell support requires device tree 699 for all boards. 700 701config ARCH_PNX4008 702 bool "Philips Nexperia PNX4008 Mobile" 703 select CPU_ARM926T 704 select CLKDEV_LOOKUP 705 select ARCH_USES_GETTIMEOFFSET 706 help 707 This enables support for Philips PNX4008 mobile platform. 708 709config ARCH_PXA 710 bool "PXA2xx/PXA3xx-based" 711 depends on MMU 712 select ARCH_MTD_XIP 713 select ARCH_HAS_CPUFREQ 714 select CLKDEV_LOOKUP 715 select CLKSRC_MMIO 716 select ARCH_REQUIRE_GPIOLIB 717 select GENERIC_CLOCKEVENTS 718 select GPIO_PXA 719 select TICK_ONESHOT 720 select PLAT_PXA 721 select SPARSE_IRQ 722 select AUTO_ZRELADDR 723 select MULTI_IRQ_HANDLER 724 select ARM_CPU_SUSPEND if PM 725 select HAVE_IDE 726 help 727 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 728 729config ARCH_MSM 730 bool "Qualcomm MSM" 731 select HAVE_CLK 732 select GENERIC_CLOCKEVENTS 733 select ARCH_REQUIRE_GPIOLIB 734 select CLKDEV_LOOKUP 735 help 736 Support for Qualcomm MSM/QSD based systems. This runs on the 737 apps processor of the MSM/QSD and depends on a shared memory 738 interface to the modem processor which runs the baseband 739 stack and controls some vital subsystems 740 (clock and power control, etc). 741 742config ARCH_SHMOBILE 743 bool "Renesas SH-Mobile / R-Mobile" 744 select HAVE_CLK 745 select CLKDEV_LOOKUP 746 select HAVE_MACH_CLKDEV 747 select HAVE_SMP 748 select GENERIC_CLOCKEVENTS 749 select MIGHT_HAVE_CACHE_L2X0 750 select NO_IOPORT 751 select SPARSE_IRQ 752 select MULTI_IRQ_HANDLER 753 select PM_GENERIC_DOMAINS if PM 754 select NEED_MACH_MEMORY_H 755 help 756 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 757 758config ARCH_RPC 759 bool "RiscPC" 760 select ARCH_ACORN 761 select FIQ 762 select ARCH_MAY_HAVE_PC_FDC 763 select HAVE_PATA_PLATFORM 764 select ISA_DMA_API 765 select NO_IOPORT 766 select ARCH_SPARSEMEM_ENABLE 767 select ARCH_USES_GETTIMEOFFSET 768 select HAVE_IDE 769 select NEED_MACH_IO_H 770 select NEED_MACH_MEMORY_H 771 help 772 On the Acorn Risc-PC, Linux can support the internal IDE disk and 773 CD-ROM interface, serial and parallel port, and the floppy drive. 774 775config ARCH_SA1100 776 bool "SA1100-based" 777 select CLKSRC_MMIO 778 select CPU_SA1100 779 select ISA 780 select ARCH_SPARSEMEM_ENABLE 781 select ARCH_MTD_XIP 782 select ARCH_HAS_CPUFREQ 783 select CPU_FREQ 784 select GENERIC_CLOCKEVENTS 785 select CLKDEV_LOOKUP 786 select TICK_ONESHOT 787 select ARCH_REQUIRE_GPIOLIB 788 select HAVE_IDE 789 select NEED_MACH_MEMORY_H 790 select SPARSE_IRQ 791 help 792 Support for StrongARM 11x0 based boards. 793 794config ARCH_S3C24XX 795 bool "Samsung S3C24XX SoCs" 796 select GENERIC_GPIO 797 select ARCH_HAS_CPUFREQ 798 select HAVE_CLK 799 select CLKDEV_LOOKUP 800 select ARCH_USES_GETTIMEOFFSET 801 select HAVE_S3C2410_I2C if I2C 802 select HAVE_S3C_RTC if RTC_CLASS 803 select HAVE_S3C2410_WATCHDOG if WATCHDOG 804 select NEED_MACH_IO_H 805 help 806 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 807 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 808 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 809 Samsung SMDK2410 development board (and derivatives). 810 811config ARCH_S3C64XX 812 bool "Samsung S3C64XX" 813 select PLAT_SAMSUNG 814 select CPU_V6 815 select ARM_VIC 816 select HAVE_CLK 817 select HAVE_TCM 818 select CLKDEV_LOOKUP 819 select NO_IOPORT 820 select ARCH_USES_GETTIMEOFFSET 821 select ARCH_HAS_CPUFREQ 822 select ARCH_REQUIRE_GPIOLIB 823 select SAMSUNG_CLKSRC 824 select SAMSUNG_IRQ_VIC_TIMER 825 select S3C_GPIO_TRACK 826 select S3C_DEV_NAND 827 select USB_ARCH_HAS_OHCI 828 select SAMSUNG_GPIOLIB_4BIT 829 select HAVE_S3C2410_I2C if I2C 830 select HAVE_S3C2410_WATCHDOG if WATCHDOG 831 help 832 Samsung S3C64XX series based systems 833 834config ARCH_S5P64X0 835 bool "Samsung S5P6440 S5P6450" 836 select CPU_V6 837 select GENERIC_GPIO 838 select HAVE_CLK 839 select CLKDEV_LOOKUP 840 select CLKSRC_MMIO 841 select HAVE_S3C2410_WATCHDOG if WATCHDOG 842 select GENERIC_CLOCKEVENTS 843 select HAVE_S3C2410_I2C if I2C 844 select HAVE_S3C_RTC if RTC_CLASS 845 help 846 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 847 SMDK6450. 848 849config ARCH_S5PC100 850 bool "Samsung S5PC100" 851 select GENERIC_GPIO 852 select HAVE_CLK 853 select CLKDEV_LOOKUP 854 select CPU_V7 855 select ARCH_USES_GETTIMEOFFSET 856 select HAVE_S3C2410_I2C if I2C 857 select HAVE_S3C_RTC if RTC_CLASS 858 select HAVE_S3C2410_WATCHDOG if WATCHDOG 859 help 860 Samsung S5PC100 series based systems 861 862config ARCH_S5PV210 863 bool "Samsung S5PV210/S5PC110" 864 select CPU_V7 865 select ARCH_SPARSEMEM_ENABLE 866 select ARCH_HAS_HOLES_MEMORYMODEL 867 select GENERIC_GPIO 868 select HAVE_CLK 869 select CLKDEV_LOOKUP 870 select CLKSRC_MMIO 871 select ARCH_HAS_CPUFREQ 872 select GENERIC_CLOCKEVENTS 873 select HAVE_S3C2410_I2C if I2C 874 select HAVE_S3C_RTC if RTC_CLASS 875 select HAVE_S3C2410_WATCHDOG if WATCHDOG 876 select NEED_MACH_MEMORY_H 877 help 878 Samsung S5PV210/S5PC110 series based systems 879 880config ARCH_EXYNOS 881 bool "SAMSUNG EXYNOS" 882 select CPU_V7 883 select ARCH_SPARSEMEM_ENABLE 884 select ARCH_HAS_HOLES_MEMORYMODEL 885 select GENERIC_GPIO 886 select HAVE_CLK 887 select CLKDEV_LOOKUP 888 select ARCH_HAS_CPUFREQ 889 select GENERIC_CLOCKEVENTS 890 select HAVE_S3C_RTC if RTC_CLASS 891 select HAVE_S3C2410_I2C if I2C 892 select HAVE_S3C2410_WATCHDOG if WATCHDOG 893 select NEED_MACH_MEMORY_H 894 help 895 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 896 897config ARCH_SHARK 898 bool "Shark" 899 select CPU_SA110 900 select ISA 901 select ISA_DMA 902 select ZONE_DMA 903 select PCI 904 select ARCH_USES_GETTIMEOFFSET 905 select NEED_MACH_MEMORY_H 906 select NEED_MACH_IO_H 907 help 908 Support for the StrongARM based Digital DNARD machine, also known 909 as "Shark" (<http://www.shark-linux.de/shark.html>). 910 911config ARCH_U300 912 bool "ST-Ericsson U300 Series" 913 depends on MMU 914 select CLKSRC_MMIO 915 select CPU_ARM926T 916 select HAVE_TCM 917 select ARM_AMBA 918 select ARM_PATCH_PHYS_VIRT 919 select ARM_VIC 920 select GENERIC_CLOCKEVENTS 921 select CLKDEV_LOOKUP 922 select HAVE_MACH_CLKDEV 923 select GENERIC_GPIO 924 select ARCH_REQUIRE_GPIOLIB 925 help 926 Support for ST-Ericsson U300 series mobile platforms. 927 928config ARCH_U8500 929 bool "ST-Ericsson U8500 Series" 930 depends on MMU 931 select CPU_V7 932 select ARM_AMBA 933 select GENERIC_CLOCKEVENTS 934 select CLKDEV_LOOKUP 935 select ARCH_REQUIRE_GPIOLIB 936 select ARCH_HAS_CPUFREQ 937 select HAVE_SMP 938 select MIGHT_HAVE_CACHE_L2X0 939 help 940 Support for ST-Ericsson's Ux500 architecture 941 942config ARCH_NOMADIK 943 bool "STMicroelectronics Nomadik" 944 select ARM_AMBA 945 select ARM_VIC 946 select CPU_ARM926T 947 select CLKDEV_LOOKUP 948 select GENERIC_CLOCKEVENTS 949 select MIGHT_HAVE_CACHE_L2X0 950 select ARCH_REQUIRE_GPIOLIB 951 help 952 Support for the Nomadik platform by ST-Ericsson 953 954config ARCH_DAVINCI 955 bool "TI DaVinci" 956 select GENERIC_CLOCKEVENTS 957 select ARCH_REQUIRE_GPIOLIB 958 select ZONE_DMA 959 select HAVE_IDE 960 select CLKDEV_LOOKUP 961 select GENERIC_ALLOCATOR 962 select GENERIC_IRQ_CHIP 963 select ARCH_HAS_HOLES_MEMORYMODEL 964 help 965 Support for TI's DaVinci platform. 966 967config ARCH_OMAP 968 bool "TI OMAP" 969 select HAVE_CLK 970 select ARCH_REQUIRE_GPIOLIB 971 select ARCH_HAS_CPUFREQ 972 select CLKSRC_MMIO 973 select GENERIC_CLOCKEVENTS 974 select ARCH_HAS_HOLES_MEMORYMODEL 975 help 976 Support for TI's OMAP platform (OMAP1/2/3/4). 977 978config PLAT_SPEAR 979 bool "ST SPEAr" 980 select ARM_AMBA 981 select ARCH_REQUIRE_GPIOLIB 982 select CLKDEV_LOOKUP 983 select CLKSRC_MMIO 984 select GENERIC_CLOCKEVENTS 985 select HAVE_CLK 986 help 987 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 988 989config ARCH_VT8500 990 bool "VIA/WonderMedia 85xx" 991 select CPU_ARM926T 992 select GENERIC_GPIO 993 select ARCH_HAS_CPUFREQ 994 select GENERIC_CLOCKEVENTS 995 select ARCH_REQUIRE_GPIOLIB 996 select HAVE_PWM 997 help 998 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 999 1000config ARCH_ZYNQ 1001 bool "Xilinx Zynq ARM Cortex A9 Platform" 1002 select CPU_V7 1003 select GENERIC_CLOCKEVENTS 1004 select CLKDEV_LOOKUP 1005 select ARM_GIC 1006 select ARM_AMBA 1007 select ICST 1008 select MIGHT_HAVE_CACHE_L2X0 1009 select USE_OF 1010 help 1011 Support for Xilinx Zynq ARM Cortex A9 Platform 1012endchoice 1013 1014# 1015# This is sorted alphabetically by mach-* pathname. However, plat-* 1016# Kconfigs may be included either alphabetically (according to the 1017# plat- suffix) or along side the corresponding mach-* source. 1018# 1019source "arch/arm/mach-at91/Kconfig" 1020 1021source "arch/arm/mach-bcmring/Kconfig" 1022 1023source "arch/arm/mach-clps711x/Kconfig" 1024 1025source "arch/arm/mach-cns3xxx/Kconfig" 1026 1027source "arch/arm/mach-davinci/Kconfig" 1028 1029source "arch/arm/mach-dove/Kconfig" 1030 1031source "arch/arm/mach-ep93xx/Kconfig" 1032 1033source "arch/arm/mach-footbridge/Kconfig" 1034 1035source "arch/arm/mach-gemini/Kconfig" 1036 1037source "arch/arm/mach-h720x/Kconfig" 1038 1039source "arch/arm/mach-integrator/Kconfig" 1040 1041source "arch/arm/mach-iop32x/Kconfig" 1042 1043source "arch/arm/mach-iop33x/Kconfig" 1044 1045source "arch/arm/mach-iop13xx/Kconfig" 1046 1047source "arch/arm/mach-ixp4xx/Kconfig" 1048 1049source "arch/arm/mach-ixp2000/Kconfig" 1050 1051source "arch/arm/mach-ixp23xx/Kconfig" 1052 1053source "arch/arm/mach-kirkwood/Kconfig" 1054 1055source "arch/arm/mach-ks8695/Kconfig" 1056 1057source "arch/arm/mach-lpc32xx/Kconfig" 1058 1059source "arch/arm/mach-msm/Kconfig" 1060 1061source "arch/arm/mach-mv78xx0/Kconfig" 1062 1063source "arch/arm/plat-mxc/Kconfig" 1064 1065source "arch/arm/mach-mxs/Kconfig" 1066 1067source "arch/arm/mach-netx/Kconfig" 1068 1069source "arch/arm/mach-nomadik/Kconfig" 1070source "arch/arm/plat-nomadik/Kconfig" 1071 1072source "arch/arm/plat-omap/Kconfig" 1073 1074source "arch/arm/mach-omap1/Kconfig" 1075 1076source "arch/arm/mach-omap2/Kconfig" 1077 1078source "arch/arm/mach-orion5x/Kconfig" 1079 1080source "arch/arm/mach-pxa/Kconfig" 1081source "arch/arm/plat-pxa/Kconfig" 1082 1083source "arch/arm/mach-mmp/Kconfig" 1084 1085source "arch/arm/mach-realview/Kconfig" 1086 1087source "arch/arm/mach-sa1100/Kconfig" 1088 1089source "arch/arm/plat-samsung/Kconfig" 1090source "arch/arm/plat-s3c24xx/Kconfig" 1091source "arch/arm/plat-s5p/Kconfig" 1092 1093source "arch/arm/plat-spear/Kconfig" 1094 1095source "arch/arm/mach-s3c24xx/Kconfig" 1096if ARCH_S3C24XX 1097source "arch/arm/mach-s3c2412/Kconfig" 1098source "arch/arm/mach-s3c2440/Kconfig" 1099endif 1100 1101if ARCH_S3C64XX 1102source "arch/arm/mach-s3c64xx/Kconfig" 1103endif 1104 1105source "arch/arm/mach-s5p64x0/Kconfig" 1106 1107source "arch/arm/mach-s5pc100/Kconfig" 1108 1109source "arch/arm/mach-s5pv210/Kconfig" 1110 1111source "arch/arm/mach-exynos/Kconfig" 1112 1113source "arch/arm/mach-shmobile/Kconfig" 1114 1115source "arch/arm/mach-tegra/Kconfig" 1116 1117source "arch/arm/mach-u300/Kconfig" 1118 1119source "arch/arm/mach-ux500/Kconfig" 1120 1121source "arch/arm/mach-versatile/Kconfig" 1122 1123source "arch/arm/mach-vexpress/Kconfig" 1124source "arch/arm/plat-versatile/Kconfig" 1125 1126source "arch/arm/mach-vt8500/Kconfig" 1127 1128source "arch/arm/mach-w90x900/Kconfig" 1129 1130# Definitions to make life easier 1131config ARCH_ACORN 1132 bool 1133 1134config PLAT_IOP 1135 bool 1136 select GENERIC_CLOCKEVENTS 1137 1138config PLAT_ORION 1139 bool 1140 select CLKSRC_MMIO 1141 select GENERIC_IRQ_CHIP 1142 1143config PLAT_PXA 1144 bool 1145 1146config PLAT_VERSATILE 1147 bool 1148 1149config ARM_TIMER_SP804 1150 bool 1151 select CLKSRC_MMIO 1152 select HAVE_SCHED_CLOCK 1153 1154source arch/arm/mm/Kconfig 1155 1156config ARM_NR_BANKS 1157 int 1158 default 16 if ARCH_EP93XX 1159 default 8 1160 1161config IWMMXT 1162 bool "Enable iWMMXt support" 1163 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1164 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1165 help 1166 Enable support for iWMMXt context switching at run time if 1167 running on a CPU that supports it. 1168 1169config XSCALE_PMU 1170 bool 1171 depends on CPU_XSCALE 1172 default y 1173 1174config CPU_HAS_PMU 1175 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1176 (!ARCH_OMAP3 || OMAP3_EMU) 1177 default y 1178 bool 1179 1180config MULTI_IRQ_HANDLER 1181 bool 1182 help 1183 Allow each machine to specify it's own IRQ handler at run time. 1184 1185if !MMU 1186source "arch/arm/Kconfig-nommu" 1187endif 1188 1189config ARM_ERRATA_326103 1190 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1191 depends on CPU_V6 1192 help 1193 Executing a SWP instruction to read-only memory does not set bit 11 1194 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1195 treat the access as a read, preventing a COW from occurring and 1196 causing the faulting task to livelock. 1197 1198config ARM_ERRATA_411920 1199 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1200 depends on CPU_V6 || CPU_V6K 1201 help 1202 Invalidation of the Instruction Cache operation can 1203 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1204 It does not affect the MPCore. This option enables the ARM Ltd. 1205 recommended workaround. 1206 1207config ARM_ERRATA_430973 1208 bool "ARM errata: Stale prediction on replaced interworking branch" 1209 depends on CPU_V7 1210 help 1211 This option enables the workaround for the 430973 Cortex-A8 1212 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1213 interworking branch is replaced with another code sequence at the 1214 same virtual address, whether due to self-modifying code or virtual 1215 to physical address re-mapping, Cortex-A8 does not recover from the 1216 stale interworking branch prediction. This results in Cortex-A8 1217 executing the new code sequence in the incorrect ARM or Thumb state. 1218 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1219 and also flushes the branch target cache at every context switch. 1220 Note that setting specific bits in the ACTLR register may not be 1221 available in non-secure mode. 1222 1223config ARM_ERRATA_458693 1224 bool "ARM errata: Processor deadlock when a false hazard is created" 1225 depends on CPU_V7 1226 help 1227 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1228 erratum. For very specific sequences of memory operations, it is 1229 possible for a hazard condition intended for a cache line to instead 1230 be incorrectly associated with a different cache line. This false 1231 hazard might then cause a processor deadlock. The workaround enables 1232 the L1 caching of the NEON accesses and disables the PLD instruction 1233 in the ACTLR register. Note that setting specific bits in the ACTLR 1234 register may not be available in non-secure mode. 1235 1236config ARM_ERRATA_460075 1237 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1238 depends on CPU_V7 1239 help 1240 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1241 erratum. Any asynchronous access to the L2 cache may encounter a 1242 situation in which recent store transactions to the L2 cache are lost 1243 and overwritten with stale memory contents from external memory. The 1244 workaround disables the write-allocate mode for the L2 cache via the 1245 ACTLR register. Note that setting specific bits in the ACTLR register 1246 may not be available in non-secure mode. 1247 1248config ARM_ERRATA_742230 1249 bool "ARM errata: DMB operation may be faulty" 1250 depends on CPU_V7 && SMP 1251 help 1252 This option enables the workaround for the 742230 Cortex-A9 1253 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1254 between two write operations may not ensure the correct visibility 1255 ordering of the two writes. This workaround sets a specific bit in 1256 the diagnostic register of the Cortex-A9 which causes the DMB 1257 instruction to behave as a DSB, ensuring the correct behaviour of 1258 the two writes. 1259 1260config ARM_ERRATA_742231 1261 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1262 depends on CPU_V7 && SMP 1263 help 1264 This option enables the workaround for the 742231 Cortex-A9 1265 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1266 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1267 accessing some data located in the same cache line, may get corrupted 1268 data due to bad handling of the address hazard when the line gets 1269 replaced from one of the CPUs at the same time as another CPU is 1270 accessing it. This workaround sets specific bits in the diagnostic 1271 register of the Cortex-A9 which reduces the linefill issuing 1272 capabilities of the processor. 1273 1274config PL310_ERRATA_588369 1275 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1276 depends on CACHE_L2X0 1277 help 1278 The PL310 L2 cache controller implements three types of Clean & 1279 Invalidate maintenance operations: by Physical Address 1280 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1281 They are architecturally defined to behave as the execution of a 1282 clean operation followed immediately by an invalidate operation, 1283 both performing to the same memory location. This functionality 1284 is not correctly implemented in PL310 as clean lines are not 1285 invalidated as a result of these operations. 1286 1287config ARM_ERRATA_720789 1288 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1289 depends on CPU_V7 1290 help 1291 This option enables the workaround for the 720789 Cortex-A9 (prior to 1292 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1293 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1294 As a consequence of this erratum, some TLB entries which should be 1295 invalidated are not, resulting in an incoherency in the system page 1296 tables. The workaround changes the TLB flushing routines to invalidate 1297 entries regardless of the ASID. 1298 1299config PL310_ERRATA_727915 1300 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1301 depends on CACHE_L2X0 1302 help 1303 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1304 operation (offset 0x7FC). This operation runs in background so that 1305 PL310 can handle normal accesses while it is in progress. Under very 1306 rare circumstances, due to this erratum, write data can be lost when 1307 PL310 treats a cacheable write transaction during a Clean & 1308 Invalidate by Way operation. 1309 1310config ARM_ERRATA_743622 1311 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1312 depends on CPU_V7 1313 help 1314 This option enables the workaround for the 743622 Cortex-A9 1315 (r2p*) erratum. Under very rare conditions, a faulty 1316 optimisation in the Cortex-A9 Store Buffer may lead to data 1317 corruption. This workaround sets a specific bit in the diagnostic 1318 register of the Cortex-A9 which disables the Store Buffer 1319 optimisation, preventing the defect from occurring. This has no 1320 visible impact on the overall performance or power consumption of the 1321 processor. 1322 1323config ARM_ERRATA_751472 1324 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1325 depends on CPU_V7 1326 help 1327 This option enables the workaround for the 751472 Cortex-A9 (prior 1328 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1329 completion of a following broadcasted operation if the second 1330 operation is received by a CPU before the ICIALLUIS has completed, 1331 potentially leading to corrupted entries in the cache or TLB. 1332 1333config PL310_ERRATA_753970 1334 bool "PL310 errata: cache sync operation may be faulty" 1335 depends on CACHE_PL310 1336 help 1337 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1338 1339 Under some condition the effect of cache sync operation on 1340 the store buffer still remains when the operation completes. 1341 This means that the store buffer is always asked to drain and 1342 this prevents it from merging any further writes. The workaround 1343 is to replace the normal offset of cache sync operation (0x730) 1344 by another offset targeting an unmapped PL310 register 0x740. 1345 This has the same effect as the cache sync operation: store buffer 1346 drain and waiting for all buffers empty. 1347 1348config ARM_ERRATA_754322 1349 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1350 depends on CPU_V7 1351 help 1352 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1353 r3p*) erratum. A speculative memory access may cause a page table walk 1354 which starts prior to an ASID switch but completes afterwards. This 1355 can populate the micro-TLB with a stale entry which may be hit with 1356 the new ASID. This workaround places two dsb instructions in the mm 1357 switching code so that no page table walks can cross the ASID switch. 1358 1359config ARM_ERRATA_754327 1360 bool "ARM errata: no automatic Store Buffer drain" 1361 depends on CPU_V7 && SMP 1362 help 1363 This option enables the workaround for the 754327 Cortex-A9 (prior to 1364 r2p0) erratum. The Store Buffer does not have any automatic draining 1365 mechanism and therefore a livelock may occur if an external agent 1366 continuously polls a memory location waiting to observe an update. 1367 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1368 written polling loops from denying visibility of updates to memory. 1369 1370config ARM_ERRATA_364296 1371 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1372 depends on CPU_V6 && !SMP 1373 help 1374 This options enables the workaround for the 364296 ARM1136 1375 r0p2 erratum (possible cache data corruption with 1376 hit-under-miss enabled). It sets the undocumented bit 31 in 1377 the auxiliary control register and the FI bit in the control 1378 register, thus disabling hit-under-miss without putting the 1379 processor into full low interrupt latency mode. ARM11MPCore 1380 is not affected. 1381 1382config ARM_ERRATA_764369 1383 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1384 depends on CPU_V7 && SMP 1385 help 1386 This option enables the workaround for erratum 764369 1387 affecting Cortex-A9 MPCore with two or more processors (all 1388 current revisions). Under certain timing circumstances, a data 1389 cache line maintenance operation by MVA targeting an Inner 1390 Shareable memory region may fail to proceed up to either the 1391 Point of Coherency or to the Point of Unification of the 1392 system. This workaround adds a DSB instruction before the 1393 relevant cache maintenance functions and sets a specific bit 1394 in the diagnostic control register of the SCU. 1395 1396config PL310_ERRATA_769419 1397 bool "PL310 errata: no automatic Store Buffer drain" 1398 depends on CACHE_L2X0 1399 help 1400 On revisions of the PL310 prior to r3p2, the Store Buffer does 1401 not automatically drain. This can cause normal, non-cacheable 1402 writes to be retained when the memory system is idle, leading 1403 to suboptimal I/O performance for drivers using coherent DMA. 1404 This option adds a write barrier to the cpu_idle loop so that, 1405 on systems with an outer cache, the store buffer is drained 1406 explicitly. 1407 1408endmenu 1409 1410source "arch/arm/common/Kconfig" 1411 1412menu "Bus support" 1413 1414config ARM_AMBA 1415 bool 1416 1417config ISA 1418 bool 1419 help 1420 Find out whether you have ISA slots on your motherboard. ISA is the 1421 name of a bus system, i.e. the way the CPU talks to the other stuff 1422 inside your box. Other bus systems are PCI, EISA, MicroChannel 1423 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1424 newer boards don't support it. If you have ISA, say Y, otherwise N. 1425 1426# Select ISA DMA controller support 1427config ISA_DMA 1428 bool 1429 select ISA_DMA_API 1430 1431# Select ISA DMA interface 1432config ISA_DMA_API 1433 bool 1434 1435config PCI 1436 bool "PCI support" if MIGHT_HAVE_PCI 1437 help 1438 Find out whether you have a PCI motherboard. PCI is the name of a 1439 bus system, i.e. the way the CPU talks to the other stuff inside 1440 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1441 VESA. If you have PCI, say Y, otherwise N. 1442 1443config PCI_DOMAINS 1444 bool 1445 depends on PCI 1446 1447config PCI_NANOENGINE 1448 bool "BSE nanoEngine PCI support" 1449 depends on SA1100_NANOENGINE 1450 help 1451 Enable PCI on the BSE nanoEngine board. 1452 1453config PCI_SYSCALL 1454 def_bool PCI 1455 1456# Select the host bridge type 1457config PCI_HOST_VIA82C505 1458 bool 1459 depends on PCI && ARCH_SHARK 1460 default y 1461 1462config PCI_HOST_ITE8152 1463 bool 1464 depends on PCI && MACH_ARMCORE 1465 default y 1466 select DMABOUNCE 1467 1468source "drivers/pci/Kconfig" 1469 1470source "drivers/pcmcia/Kconfig" 1471 1472endmenu 1473 1474menu "Kernel Features" 1475 1476source "kernel/time/Kconfig" 1477 1478config HAVE_SMP 1479 bool 1480 help 1481 This option should be selected by machines which have an SMP- 1482 capable CPU. 1483 1484 The only effect of this option is to make the SMP-related 1485 options available to the user for configuration. 1486 1487config SMP 1488 bool "Symmetric Multi-Processing" 1489 depends on CPU_V6K || CPU_V7 1490 depends on GENERIC_CLOCKEVENTS 1491 depends on HAVE_SMP 1492 depends on MMU 1493 select USE_GENERIC_SMP_HELPERS 1494 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1495 help 1496 This enables support for systems with more than one CPU. If you have 1497 a system with only one CPU, like most personal computers, say N. If 1498 you have a system with more than one CPU, say Y. 1499 1500 If you say N here, the kernel will run on single and multiprocessor 1501 machines, but will use only one CPU of a multiprocessor machine. If 1502 you say Y here, the kernel will run on many, but not all, single 1503 processor machines. On a single processor machine, the kernel will 1504 run faster if you say N here. 1505 1506 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1507 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1508 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1509 1510 If you don't know what to do here, say N. 1511 1512config SMP_ON_UP 1513 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1514 depends on EXPERIMENTAL 1515 depends on SMP && !XIP_KERNEL 1516 default y 1517 help 1518 SMP kernels contain instructions which fail on non-SMP processors. 1519 Enabling this option allows the kernel to modify itself to make 1520 these instructions safe. Disabling it allows about 1K of space 1521 savings. 1522 1523 If you don't know what to do here, say Y. 1524 1525config ARM_CPU_TOPOLOGY 1526 bool "Support cpu topology definition" 1527 depends on SMP && CPU_V7 1528 default y 1529 help 1530 Support ARM cpu topology definition. The MPIDR register defines 1531 affinity between processors which is then used to describe the cpu 1532 topology of an ARM System. 1533 1534config SCHED_MC 1535 bool "Multi-core scheduler support" 1536 depends on ARM_CPU_TOPOLOGY 1537 help 1538 Multi-core scheduler support improves the CPU scheduler's decision 1539 making when dealing with multi-core CPU chips at a cost of slightly 1540 increased overhead in some places. If unsure say N here. 1541 1542config SCHED_SMT 1543 bool "SMT scheduler support" 1544 depends on ARM_CPU_TOPOLOGY 1545 help 1546 Improves the CPU scheduler's decision making when dealing with 1547 MultiThreading at a cost of slightly increased overhead in some 1548 places. If unsure say N here. 1549 1550config HAVE_ARM_SCU 1551 bool 1552 help 1553 This option enables support for the ARM system coherency unit 1554 1555config HAVE_ARM_TWD 1556 bool 1557 depends on SMP 1558 select TICK_ONESHOT 1559 help 1560 This options enables support for the ARM timer and watchdog unit 1561 1562choice 1563 prompt "Memory split" 1564 default VMSPLIT_3G 1565 help 1566 Select the desired split between kernel and user memory. 1567 1568 If you are not absolutely sure what you are doing, leave this 1569 option alone! 1570 1571 config VMSPLIT_3G 1572 bool "3G/1G user/kernel split" 1573 config VMSPLIT_2G 1574 bool "2G/2G user/kernel split" 1575 config VMSPLIT_1G 1576 bool "1G/3G user/kernel split" 1577endchoice 1578 1579config PAGE_OFFSET 1580 hex 1581 default 0x40000000 if VMSPLIT_1G 1582 default 0x80000000 if VMSPLIT_2G 1583 default 0xC0000000 1584 1585config NR_CPUS 1586 int "Maximum number of CPUs (2-32)" 1587 range 2 32 1588 depends on SMP 1589 default "4" 1590 1591config HOTPLUG_CPU 1592 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1593 depends on SMP && HOTPLUG && EXPERIMENTAL 1594 help 1595 Say Y here to experiment with turning CPUs off and on. CPUs 1596 can be controlled through /sys/devices/system/cpu. 1597 1598config LOCAL_TIMERS 1599 bool "Use local timer interrupts" 1600 depends on SMP 1601 default y 1602 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1603 help 1604 Enable support for local timers on SMP platforms, rather then the 1605 legacy IPI broadcast method. Local timers allows the system 1606 accounting to be spread across the timer interval, preventing a 1607 "thundering herd" at every timer tick. 1608 1609config ARCH_NR_GPIO 1610 int 1611 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1612 default 355 if ARCH_U8500 1613 default 264 if MACH_H4700 1614 default 0 1615 help 1616 Maximum number of GPIOs in the system. 1617 1618 If unsure, leave the default value. 1619 1620source kernel/Kconfig.preempt 1621 1622config HZ 1623 int 1624 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1625 ARCH_S5PV210 || ARCH_EXYNOS4 1626 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1627 default AT91_TIMER_HZ if ARCH_AT91 1628 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1629 default 100 1630 1631config THUMB2_KERNEL 1632 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1633 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1634 select AEABI 1635 select ARM_ASM_UNIFIED 1636 select ARM_UNWIND 1637 help 1638 By enabling this option, the kernel will be compiled in 1639 Thumb-2 mode. A compiler/assembler that understand the unified 1640 ARM-Thumb syntax is needed. 1641 1642 If unsure, say N. 1643 1644config THUMB2_AVOID_R_ARM_THM_JUMP11 1645 bool "Work around buggy Thumb-2 short branch relocations in gas" 1646 depends on THUMB2_KERNEL && MODULES 1647 default y 1648 help 1649 Various binutils versions can resolve Thumb-2 branches to 1650 locally-defined, preemptible global symbols as short-range "b.n" 1651 branch instructions. 1652 1653 This is a problem, because there's no guarantee the final 1654 destination of the symbol, or any candidate locations for a 1655 trampoline, are within range of the branch. For this reason, the 1656 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1657 relocation in modules at all, and it makes little sense to add 1658 support. 1659 1660 The symptom is that the kernel fails with an "unsupported 1661 relocation" error when loading some modules. 1662 1663 Until fixed tools are available, passing 1664 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1665 code which hits this problem, at the cost of a bit of extra runtime 1666 stack usage in some cases. 1667 1668 The problem is described in more detail at: 1669 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1670 1671 Only Thumb-2 kernels are affected. 1672 1673 Unless you are sure your tools don't have this problem, say Y. 1674 1675config ARM_ASM_UNIFIED 1676 bool 1677 1678config AEABI 1679 bool "Use the ARM EABI to compile the kernel" 1680 help 1681 This option allows for the kernel to be compiled using the latest 1682 ARM ABI (aka EABI). This is only useful if you are using a user 1683 space environment that is also compiled with EABI. 1684 1685 Since there are major incompatibilities between the legacy ABI and 1686 EABI, especially with regard to structure member alignment, this 1687 option also changes the kernel syscall calling convention to 1688 disambiguate both ABIs and allow for backward compatibility support 1689 (selected with CONFIG_OABI_COMPAT). 1690 1691 To use this you need GCC version 4.0.0 or later. 1692 1693config OABI_COMPAT 1694 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1695 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1696 default y 1697 help 1698 This option preserves the old syscall interface along with the 1699 new (ARM EABI) one. It also provides a compatibility layer to 1700 intercept syscalls that have structure arguments which layout 1701 in memory differs between the legacy ABI and the new ARM EABI 1702 (only for non "thumb" binaries). This option adds a tiny 1703 overhead to all syscalls and produces a slightly larger kernel. 1704 If you know you'll be using only pure EABI user space then you 1705 can say N here. If this option is not selected and you attempt 1706 to execute a legacy ABI binary then the result will be 1707 UNPREDICTABLE (in fact it can be predicted that it won't work 1708 at all). If in doubt say Y. 1709 1710config ARCH_HAS_HOLES_MEMORYMODEL 1711 bool 1712 1713config ARCH_SPARSEMEM_ENABLE 1714 bool 1715 1716config ARCH_SPARSEMEM_DEFAULT 1717 def_bool ARCH_SPARSEMEM_ENABLE 1718 1719config ARCH_SELECT_MEMORY_MODEL 1720 def_bool ARCH_SPARSEMEM_ENABLE 1721 1722config HAVE_ARCH_PFN_VALID 1723 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1724 1725config HIGHMEM 1726 bool "High Memory Support" 1727 depends on MMU 1728 help 1729 The address space of ARM processors is only 4 Gigabytes large 1730 and it has to accommodate user address space, kernel address 1731 space as well as some memory mapped IO. That means that, if you 1732 have a large amount of physical memory and/or IO, not all of the 1733 memory can be "permanently mapped" by the kernel. The physical 1734 memory that is not permanently mapped is called "high memory". 1735 1736 Depending on the selected kernel/user memory split, minimum 1737 vmalloc space and actual amount of RAM, you may not need this 1738 option which should result in a slightly faster kernel. 1739 1740 If unsure, say n. 1741 1742config HIGHPTE 1743 bool "Allocate 2nd-level pagetables from highmem" 1744 depends on HIGHMEM 1745 1746config HW_PERF_EVENTS 1747 bool "Enable hardware performance counter support for perf events" 1748 depends on PERF_EVENTS && CPU_HAS_PMU 1749 default y 1750 help 1751 Enable hardware performance counter support for perf events. If 1752 disabled, perf events will use software events only. 1753 1754source "mm/Kconfig" 1755 1756config FORCE_MAX_ZONEORDER 1757 int "Maximum zone order" if ARCH_SHMOBILE 1758 range 11 64 if ARCH_SHMOBILE 1759 default "9" if SA1111 1760 default "11" 1761 help 1762 The kernel memory allocator divides physically contiguous memory 1763 blocks into "zones", where each zone is a power of two number of 1764 pages. This option selects the largest power of two that the kernel 1765 keeps in the memory allocator. If you need to allocate very large 1766 blocks of physically contiguous memory, then you may need to 1767 increase this value. 1768 1769 This config option is actually maximum order plus one. For example, 1770 a value of 11 means that the largest free memory block is 2^10 pages. 1771 1772config LEDS 1773 bool "Timer and CPU usage LEDs" 1774 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1775 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1776 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1777 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1778 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1779 ARCH_AT91 || ARCH_DAVINCI || \ 1780 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1781 help 1782 If you say Y here, the LEDs on your machine will be used 1783 to provide useful information about your current system status. 1784 1785 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1786 be able to select which LEDs are active using the options below. If 1787 you are compiling a kernel for the EBSA-110 or the LART however, the 1788 red LED will simply flash regularly to indicate that the system is 1789 still functional. It is safe to say Y here if you have a CATS 1790 system, but the driver will do nothing. 1791 1792config LEDS_TIMER 1793 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1794 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1795 || MACH_OMAP_PERSEUS2 1796 depends on LEDS 1797 depends on !GENERIC_CLOCKEVENTS 1798 default y if ARCH_EBSA110 1799 help 1800 If you say Y here, one of the system LEDs (the green one on the 1801 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1802 will flash regularly to indicate that the system is still 1803 operational. This is mainly useful to kernel hackers who are 1804 debugging unstable kernels. 1805 1806 The LART uses the same LED for both Timer LED and CPU usage LED 1807 functions. You may choose to use both, but the Timer LED function 1808 will overrule the CPU usage LED. 1809 1810config LEDS_CPU 1811 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1812 !ARCH_OMAP) \ 1813 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1814 || MACH_OMAP_PERSEUS2 1815 depends on LEDS 1816 help 1817 If you say Y here, the red LED will be used to give a good real 1818 time indication of CPU usage, by lighting whenever the idle task 1819 is not currently executing. 1820 1821 The LART uses the same LED for both Timer LED and CPU usage LED 1822 functions. You may choose to use both, but the Timer LED function 1823 will overrule the CPU usage LED. 1824 1825config ALIGNMENT_TRAP 1826 bool 1827 depends on CPU_CP15_MMU 1828 default y if !ARCH_EBSA110 1829 select HAVE_PROC_CPU if PROC_FS 1830 help 1831 ARM processors cannot fetch/store information which is not 1832 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1833 address divisible by 4. On 32-bit ARM processors, these non-aligned 1834 fetch/store instructions will be emulated in software if you say 1835 here, which has a severe performance impact. This is necessary for 1836 correct operation of some network protocols. With an IP-only 1837 configuration it is safe to say N, otherwise say Y. 1838 1839config UACCESS_WITH_MEMCPY 1840 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1841 depends on MMU && EXPERIMENTAL 1842 default y if CPU_FEROCEON 1843 help 1844 Implement faster copy_to_user and clear_user methods for CPU 1845 cores where a 8-word STM instruction give significantly higher 1846 memory write throughput than a sequence of individual 32bit stores. 1847 1848 A possible side effect is a slight increase in scheduling latency 1849 between threads sharing the same address space if they invoke 1850 such copy operations with large buffers. 1851 1852 However, if the CPU data cache is using a write-allocate mode, 1853 this option is unlikely to provide any performance gain. 1854 1855config SECCOMP 1856 bool 1857 prompt "Enable seccomp to safely compute untrusted bytecode" 1858 ---help--- 1859 This kernel feature is useful for number crunching applications 1860 that may need to compute untrusted bytecode during their 1861 execution. By using pipes or other transports made available to 1862 the process as file descriptors supporting the read/write 1863 syscalls, it's possible to isolate those applications in 1864 their own address space using seccomp. Once seccomp is 1865 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1866 and the task is only allowed to execute a few safe syscalls 1867 defined by each seccomp mode. 1868 1869config CC_STACKPROTECTOR 1870 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1871 depends on EXPERIMENTAL 1872 help 1873 This option turns on the -fstack-protector GCC feature. This 1874 feature puts, at the beginning of functions, a canary value on 1875 the stack just before the return address, and validates 1876 the value just before actually returning. Stack based buffer 1877 overflows (that need to overwrite this return address) now also 1878 overwrite the canary, which gets detected and the attack is then 1879 neutralized via a kernel panic. 1880 This feature requires gcc version 4.2 or above. 1881 1882config DEPRECATED_PARAM_STRUCT 1883 bool "Provide old way to pass kernel parameters" 1884 help 1885 This was deprecated in 2001 and announced to live on for 5 years. 1886 Some old boot loaders still use this way. 1887 1888endmenu 1889 1890menu "Boot options" 1891 1892config USE_OF 1893 bool "Flattened Device Tree support" 1894 select OF 1895 select OF_EARLY_FLATTREE 1896 select IRQ_DOMAIN 1897 help 1898 Include support for flattened device tree machine descriptions. 1899 1900# Compressed boot loader in ROM. Yes, we really want to ask about 1901# TEXT and BSS so we preserve their values in the config files. 1902config ZBOOT_ROM_TEXT 1903 hex "Compressed ROM boot loader base address" 1904 default "0" 1905 help 1906 The physical address at which the ROM-able zImage is to be 1907 placed in the target. Platforms which normally make use of 1908 ROM-able zImage formats normally set this to a suitable 1909 value in their defconfig file. 1910 1911 If ZBOOT_ROM is not enabled, this has no effect. 1912 1913config ZBOOT_ROM_BSS 1914 hex "Compressed ROM boot loader BSS address" 1915 default "0" 1916 help 1917 The base address of an area of read/write memory in the target 1918 for the ROM-able zImage which must be available while the 1919 decompressor is running. It must be large enough to hold the 1920 entire decompressed kernel plus an additional 128 KiB. 1921 Platforms which normally make use of ROM-able zImage formats 1922 normally set this to a suitable value in their defconfig file. 1923 1924 If ZBOOT_ROM is not enabled, this has no effect. 1925 1926config ZBOOT_ROM 1927 bool "Compressed boot loader in ROM/flash" 1928 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1929 help 1930 Say Y here if you intend to execute your compressed kernel image 1931 (zImage) directly from ROM or flash. If unsure, say N. 1932 1933choice 1934 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1935 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1936 default ZBOOT_ROM_NONE 1937 help 1938 Include experimental SD/MMC loading code in the ROM-able zImage. 1939 With this enabled it is possible to write the the ROM-able zImage 1940 kernel image to an MMC or SD card and boot the kernel straight 1941 from the reset vector. At reset the processor Mask ROM will load 1942 the first part of the the ROM-able zImage which in turn loads the 1943 rest the kernel image to RAM. 1944 1945config ZBOOT_ROM_NONE 1946 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1947 help 1948 Do not load image from SD or MMC 1949 1950config ZBOOT_ROM_MMCIF 1951 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1952 help 1953 Load image from MMCIF hardware block. 1954 1955config ZBOOT_ROM_SH_MOBILE_SDHI 1956 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1957 help 1958 Load image from SDHI hardware block 1959 1960endchoice 1961 1962config ARM_APPENDED_DTB 1963 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1964 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1965 help 1966 With this option, the boot code will look for a device tree binary 1967 (DTB) appended to zImage 1968 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1969 1970 This is meant as a backward compatibility convenience for those 1971 systems with a bootloader that can't be upgraded to accommodate 1972 the documented boot protocol using a device tree. 1973 1974 Beware that there is very little in terms of protection against 1975 this option being confused by leftover garbage in memory that might 1976 look like a DTB header after a reboot if no actual DTB is appended 1977 to zImage. Do not leave this option active in a production kernel 1978 if you don't intend to always append a DTB. Proper passing of the 1979 location into r2 of a bootloader provided DTB is always preferable 1980 to this option. 1981 1982config ARM_ATAG_DTB_COMPAT 1983 bool "Supplement the appended DTB with traditional ATAG information" 1984 depends on ARM_APPENDED_DTB 1985 help 1986 Some old bootloaders can't be updated to a DTB capable one, yet 1987 they provide ATAGs with memory configuration, the ramdisk address, 1988 the kernel cmdline string, etc. Such information is dynamically 1989 provided by the bootloader and can't always be stored in a static 1990 DTB. To allow a device tree enabled kernel to be used with such 1991 bootloaders, this option allows zImage to extract the information 1992 from the ATAG list and store it at run time into the appended DTB. 1993 1994config CMDLINE 1995 string "Default kernel command string" 1996 default "" 1997 help 1998 On some architectures (EBSA110 and CATS), there is currently no way 1999 for the boot loader to pass arguments to the kernel. For these 2000 architectures, you should supply some command-line options at build 2001 time by entering them here. As a minimum, you should specify the 2002 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2003 2004choice 2005 prompt "Kernel command line type" if CMDLINE != "" 2006 default CMDLINE_FROM_BOOTLOADER 2007 2008config CMDLINE_FROM_BOOTLOADER 2009 bool "Use bootloader kernel arguments if available" 2010 help 2011 Uses the command-line options passed by the boot loader. If 2012 the boot loader doesn't provide any, the default kernel command 2013 string provided in CMDLINE will be used. 2014 2015config CMDLINE_EXTEND 2016 bool "Extend bootloader kernel arguments" 2017 help 2018 The command-line arguments provided by the boot loader will be 2019 appended to the default kernel command string. 2020 2021config CMDLINE_FORCE 2022 bool "Always use the default kernel command string" 2023 help 2024 Always use the default kernel command string, even if the boot 2025 loader passes other arguments to the kernel. 2026 This is useful if you cannot or don't want to change the 2027 command-line options your boot loader passes to the kernel. 2028endchoice 2029 2030config XIP_KERNEL 2031 bool "Kernel Execute-In-Place from ROM" 2032 depends on !ZBOOT_ROM && !ARM_LPAE 2033 help 2034 Execute-In-Place allows the kernel to run from non-volatile storage 2035 directly addressable by the CPU, such as NOR flash. This saves RAM 2036 space since the text section of the kernel is not loaded from flash 2037 to RAM. Read-write sections, such as the data section and stack, 2038 are still copied to RAM. The XIP kernel is not compressed since 2039 it has to run directly from flash, so it will take more space to 2040 store it. The flash address used to link the kernel object files, 2041 and for storing it, is configuration dependent. Therefore, if you 2042 say Y here, you must know the proper physical address where to 2043 store the kernel image depending on your own flash memory usage. 2044 2045 Also note that the make target becomes "make xipImage" rather than 2046 "make zImage" or "make Image". The final kernel binary to put in 2047 ROM memory will be arch/arm/boot/xipImage. 2048 2049 If unsure, say N. 2050 2051config XIP_PHYS_ADDR 2052 hex "XIP Kernel Physical Location" 2053 depends on XIP_KERNEL 2054 default "0x00080000" 2055 help 2056 This is the physical address in your flash memory the kernel will 2057 be linked for and stored to. This address is dependent on your 2058 own flash usage. 2059 2060config KEXEC 2061 bool "Kexec system call (EXPERIMENTAL)" 2062 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2063 help 2064 kexec is a system call that implements the ability to shutdown your 2065 current kernel, and to start another kernel. It is like a reboot 2066 but it is independent of the system firmware. And like a reboot 2067 you can start any kernel with it, not just Linux. 2068 2069 It is an ongoing process to be certain the hardware in a machine 2070 is properly shutdown, so do not be surprised if this code does not 2071 initially work for you. It may help to enable device hotplugging 2072 support. 2073 2074config ATAGS_PROC 2075 bool "Export atags in procfs" 2076 depends on KEXEC 2077 default y 2078 help 2079 Should the atags used to boot the kernel be exported in an "atags" 2080 file in procfs. Useful with kexec. 2081 2082config CRASH_DUMP 2083 bool "Build kdump crash kernel (EXPERIMENTAL)" 2084 depends on EXPERIMENTAL 2085 help 2086 Generate crash dump after being started by kexec. This should 2087 be normally only set in special crash dump kernels which are 2088 loaded in the main kernel with kexec-tools into a specially 2089 reserved region and then later executed after a crash by 2090 kdump/kexec. The crash dump kernel must be compiled to a 2091 memory address not used by the main kernel 2092 2093 For more details see Documentation/kdump/kdump.txt 2094 2095config AUTO_ZRELADDR 2096 bool "Auto calculation of the decompressed kernel image address" 2097 depends on !ZBOOT_ROM && !ARCH_U300 2098 help 2099 ZRELADDR is the physical address where the decompressed kernel 2100 image will be placed. If AUTO_ZRELADDR is selected, the address 2101 will be determined at run-time by masking the current IP with 2102 0xf8000000. This assumes the zImage being placed in the first 128MB 2103 from start of memory. 2104 2105endmenu 2106 2107menu "CPU Power Management" 2108 2109if ARCH_HAS_CPUFREQ 2110 2111source "drivers/cpufreq/Kconfig" 2112 2113config CPU_FREQ_IMX 2114 tristate "CPUfreq driver for i.MX CPUs" 2115 depends on ARCH_MXC && CPU_FREQ 2116 help 2117 This enables the CPUfreq driver for i.MX CPUs. 2118 2119config CPU_FREQ_SA1100 2120 bool 2121 2122config CPU_FREQ_SA1110 2123 bool 2124 2125config CPU_FREQ_INTEGRATOR 2126 tristate "CPUfreq driver for ARM Integrator CPUs" 2127 depends on ARCH_INTEGRATOR && CPU_FREQ 2128 default y 2129 help 2130 This enables the CPUfreq driver for ARM Integrator CPUs. 2131 2132 For details, take a look at <file:Documentation/cpu-freq>. 2133 2134 If in doubt, say Y. 2135 2136config CPU_FREQ_PXA 2137 bool 2138 depends on CPU_FREQ && ARCH_PXA && PXA25x 2139 default y 2140 select CPU_FREQ_TABLE 2141 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2142 2143config CPU_FREQ_S3C 2144 bool 2145 help 2146 Internal configuration node for common cpufreq on Samsung SoC 2147 2148config CPU_FREQ_S3C24XX 2149 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2150 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL 2151 select CPU_FREQ_S3C 2152 help 2153 This enables the CPUfreq driver for the Samsung S3C24XX family 2154 of CPUs. 2155 2156 For details, take a look at <file:Documentation/cpu-freq>. 2157 2158 If in doubt, say N. 2159 2160config CPU_FREQ_S3C24XX_PLL 2161 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2162 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2163 help 2164 Compile in support for changing the PLL frequency from the 2165 S3C24XX series CPUfreq driver. The PLL takes time to settle 2166 after a frequency change, so by default it is not enabled. 2167 2168 This also means that the PLL tables for the selected CPU(s) will 2169 be built which may increase the size of the kernel image. 2170 2171config CPU_FREQ_S3C24XX_DEBUG 2172 bool "Debug CPUfreq Samsung driver core" 2173 depends on CPU_FREQ_S3C24XX 2174 help 2175 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2176 2177config CPU_FREQ_S3C24XX_IODEBUG 2178 bool "Debug CPUfreq Samsung driver IO timing" 2179 depends on CPU_FREQ_S3C24XX 2180 help 2181 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2182 2183config CPU_FREQ_S3C24XX_DEBUGFS 2184 bool "Export debugfs for CPUFreq" 2185 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2186 help 2187 Export status information via debugfs. 2188 2189endif 2190 2191source "drivers/cpuidle/Kconfig" 2192 2193endmenu 2194 2195menu "Floating point emulation" 2196 2197comment "At least one emulation must be selected" 2198 2199config FPE_NWFPE 2200 bool "NWFPE math emulation" 2201 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2202 ---help--- 2203 Say Y to include the NWFPE floating point emulator in the kernel. 2204 This is necessary to run most binaries. Linux does not currently 2205 support floating point hardware so you need to say Y here even if 2206 your machine has an FPA or floating point co-processor podule. 2207 2208 You may say N here if you are going to load the Acorn FPEmulator 2209 early in the bootup. 2210 2211config FPE_NWFPE_XP 2212 bool "Support extended precision" 2213 depends on FPE_NWFPE 2214 help 2215 Say Y to include 80-bit support in the kernel floating-point 2216 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2217 Note that gcc does not generate 80-bit operations by default, 2218 so in most cases this option only enlarges the size of the 2219 floating point emulator without any good reason. 2220 2221 You almost surely want to say N here. 2222 2223config FPE_FASTFPE 2224 bool "FastFPE math emulation (EXPERIMENTAL)" 2225 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2226 ---help--- 2227 Say Y here to include the FAST floating point emulator in the kernel. 2228 This is an experimental much faster emulator which now also has full 2229 precision for the mantissa. It does not support any exceptions. 2230 It is very simple, and approximately 3-6 times faster than NWFPE. 2231 2232 It should be sufficient for most programs. It may be not suitable 2233 for scientific calculations, but you have to check this for yourself. 2234 If you do not feel you need a faster FP emulation you should better 2235 choose NWFPE. 2236 2237config VFP 2238 bool "VFP-format floating point maths" 2239 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2240 help 2241 Say Y to include VFP support code in the kernel. This is needed 2242 if your hardware includes a VFP unit. 2243 2244 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2245 release notes and additional status information. 2246 2247 Say N if your target does not have VFP hardware. 2248 2249config VFPv3 2250 bool 2251 depends on VFP 2252 default y if CPU_V7 2253 2254config NEON 2255 bool "Advanced SIMD (NEON) Extension support" 2256 depends on VFPv3 && CPU_V7 2257 help 2258 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2259 Extension. 2260 2261endmenu 2262 2263menu "Userspace binary formats" 2264 2265source "fs/Kconfig.binfmt" 2266 2267config ARTHUR 2268 tristate "RISC OS personality" 2269 depends on !AEABI 2270 help 2271 Say Y here to include the kernel code necessary if you want to run 2272 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2273 experimental; if this sounds frightening, say N and sleep in peace. 2274 You can also say M here to compile this support as a module (which 2275 will be called arthur). 2276 2277endmenu 2278 2279menu "Power management options" 2280 2281source "kernel/power/Kconfig" 2282 2283config ARCH_SUSPEND_POSSIBLE 2284 depends on !ARCH_S5PC100 2285 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2286 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2287 def_bool y 2288 2289config ARM_CPU_SUSPEND 2290 def_bool PM_SLEEP 2291 2292endmenu 2293 2294source "net/Kconfig" 2295 2296source "drivers/Kconfig" 2297 2298source "fs/Kconfig" 2299 2300source "arch/arm/Kconfig.debug" 2301 2302source "security/Kconfig" 2303 2304source "crypto/Kconfig" 2305 2306source "lib/Kconfig" 2307