1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP 72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 74 select HAVE_ARCH_TRACEHOOK 75 select HAVE_ARM_SMCCC if CPU_V7 76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 77 select HAVE_CONTEXT_TRACKING 78 select HAVE_C_RECORDMCOUNT 79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 80 select HAVE_DMA_CONTIGUOUS if MMU 81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 84 select HAVE_EXIT_THREAD 85 select HAVE_FAST_GUP if ARM_LPAE 86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 89 select HAVE_GCC_PLUGINS 90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 91 select HAVE_IDE if PCI || ISA || PCMCIA 92 select HAVE_IRQ_TIME_ACCOUNTING 93 select HAVE_KERNEL_GZIP 94 select HAVE_KERNEL_LZ4 95 select HAVE_KERNEL_LZMA 96 select HAVE_KERNEL_LZO 97 select HAVE_KERNEL_XZ 98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 99 select HAVE_KRETPROBES if HAVE_KPROBES 100 select HAVE_MOD_ARCH_SPECIFIC 101 select HAVE_NMI 102 select HAVE_OPROFILE if HAVE_PERF_EVENTS 103 select HAVE_OPTPROBES if !THUMB2_KERNEL 104 select HAVE_PERF_EVENTS 105 select HAVE_PERF_REGS 106 select HAVE_PERF_USER_STACK_DUMP 107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 108 select HAVE_REGS_AND_STACK_ACCESS_API 109 select HAVE_RSEQ 110 select HAVE_STACKPROTECTOR 111 select HAVE_SYSCALL_TRACEPOINTS 112 select HAVE_UID16 113 select HAVE_VIRT_CPU_ACCOUNTING_GEN 114 select IRQ_FORCED_THREADING 115 select MODULES_USE_ELF_REL 116 select NEED_DMA_MAP_STATE 117 select OF_EARLY_FLATTREE if OF 118 select OLD_SIGACTION 119 select OLD_SIGSUSPEND3 120 select PCI_SYSCALL if PCI 121 select PERF_USE_VMALLOC 122 select RTC_LIB 123 select SET_FS 124 select SYS_SUPPORTS_APM_EMULATION 125 # Above selects are sorted alphabetically; please add new ones 126 # according to that. Thanks. 127 help 128 The ARM series is a line of low-power-consumption RISC chip designs 129 licensed by ARM Ltd and targeted at embedded applications and 130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 131 manufactured, but legacy ARM-based PC hardware remains popular in 132 Europe. There is an ARM Linux project with a web page at 133 <http://www.arm.linux.org.uk/>. 134 135config ARM_HAS_SG_CHAIN 136 bool 137 138config ARM_DMA_USE_IOMMU 139 bool 140 select ARM_HAS_SG_CHAIN 141 select NEED_SG_DMA_LENGTH 142 143if ARM_DMA_USE_IOMMU 144 145config ARM_DMA_IOMMU_ALIGNMENT 146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 147 range 4 9 148 default 8 149 help 150 DMA mapping framework by default aligns all buffers to the smallest 151 PAGE_SIZE order which is greater than or equal to the requested buffer 152 size. This works well for buffers up to a few hundreds kilobytes, but 153 for larger buffers it just a waste of address space. Drivers which has 154 relatively small addressing window (like 64Mib) might run out of 155 virtual space with just a few allocations. 156 157 With this parameter you can specify the maximum PAGE_SIZE order for 158 DMA IOMMU buffers. Larger buffers will be aligned only to this 159 specified order. The order is expressed as a power of two multiplied 160 by the PAGE_SIZE. 161 162endif 163 164config SYS_SUPPORTS_APM_EMULATION 165 bool 166 167config HAVE_TCM 168 bool 169 select GENERIC_ALLOCATOR 170 171config HAVE_PROC_CPU 172 bool 173 174config NO_IOPORT_MAP 175 bool 176 177config SBUS 178 bool 179 180config STACKTRACE_SUPPORT 181 bool 182 default y 183 184config LOCKDEP_SUPPORT 185 bool 186 default y 187 188config TRACE_IRQFLAGS_SUPPORT 189 bool 190 default !CPU_V7M 191 192config ARCH_HAS_ILOG2_U32 193 bool 194 195config ARCH_HAS_ILOG2_U64 196 bool 197 198config ARCH_HAS_BANDGAP 199 bool 200 201config FIX_EARLYCON_MEM 202 def_bool y if MMU 203 204config GENERIC_HWEIGHT 205 bool 206 default y 207 208config GENERIC_CALIBRATE_DELAY 209 bool 210 default y 211 212config ARCH_MAY_HAVE_PC_FDC 213 bool 214 215config ZONE_DMA 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config ARM_PATCH_PHYS_VIRT 237 bool "Patch physical to virtual translations at runtime" if EMBEDDED 238 default y 239 depends on !XIP_KERNEL && MMU 240 help 241 Patch phys-to-virt and virt-to-phys translation functions at 242 boot and module load time according to the position of the 243 kernel in system memory. 244 245 This can only be used with non-XIP MMU kernels where the base 246 of physical memory is at a 16MB boundary. 247 248 Only disable this option if you know that you do not require 249 this feature (eg, building a kernel for a single machine) and 250 you need to shrink the kernel to the minimal size. 251 252config NEED_MACH_IO_H 253 bool 254 help 255 Select this when mach/io.h is required to provide special 256 definitions for this platform. The need for mach/io.h should 257 be avoided when possible. 258 259config NEED_MACH_MEMORY_H 260 bool 261 help 262 Select this when mach/memory.h is required to provide special 263 definitions for this platform. The need for mach/memory.h should 264 be avoided when possible. 265 266config PHYS_OFFSET 267 hex "Physical address of main memory" if MMU 268 depends on !ARM_PATCH_PHYS_VIRT 269 default DRAM_BASE if !MMU 270 default 0x00000000 if ARCH_FOOTBRIDGE 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x20000000 if ARCH_S5PV210 273 default 0xc0000000 if ARCH_SA1100 274 help 275 Please provide the physical address corresponding to the 276 location of main memory in your system. 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config PGTABLE_LEVELS 283 int 284 default 3 if ARM_LPAE 285 default 2 286 287menu "System Type" 288 289config MMU 290 bool "MMU-based Paged Memory Management Support" 291 default y 292 help 293 Select if you want MMU-based virtualised addressing space 294 support by paged memory management. If unsure, say 'Y'. 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 8 298 299config ARCH_MMAP_RND_BITS_MAX 300 default 14 if PAGE_OFFSET=0x40000000 301 default 15 if PAGE_OFFSET=0x80000000 302 default 16 303 304# 305# The "ARM system type" choice list is ordered alphabetically by option 306# text. Please add new entries in the option alphabetic order. 307# 308choice 309 prompt "ARM system type" 310 default ARM_SINGLE_ARMV7M if !MMU 311 default ARCH_MULTIPLATFORM if MMU 312 313config ARCH_MULTIPLATFORM 314 bool "Allow multiple platforms to be selected" 315 depends on MMU 316 select ARCH_FLATMEM_ENABLE 317 select ARCH_SPARSEMEM_ENABLE 318 select ARCH_SELECT_MEMORY_MODEL 319 select ARM_HAS_SG_CHAIN 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select TIMER_OF 323 select COMMON_CLK 324 select GENERIC_CLOCKEVENTS 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select GENERIC_CLOCKEVENTS 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EP93XX 345 bool "EP93xx-based" 346 select ARCH_SPARSEMEM_ENABLE 347 select ARM_AMBA 348 imply ARM_PATCH_PHYS_VIRT 349 select ARM_VIC 350 select AUTO_ZRELADDR 351 select CLKDEV_LOOKUP 352 select CLKSRC_MMIO 353 select CPU_ARM920T 354 select GENERIC_CLOCKEVENTS 355 select GPIOLIB 356 select HAVE_LEGACY_CLK 357 help 358 This enables support for the Cirrus EP93xx series of CPUs. 359 360config ARCH_FOOTBRIDGE 361 bool "FootBridge" 362 select CPU_SA110 363 select FOOTBRIDGE 364 select GENERIC_CLOCKEVENTS 365 select HAVE_IDE 366 select NEED_MACH_IO_H if !MMU 367 select NEED_MACH_MEMORY_H 368 help 369 Support for systems based on the DC21285 companion chip 370 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 371 372config ARCH_IOP32X 373 bool "IOP32x-based" 374 depends on MMU 375 select CPU_XSCALE 376 select GPIO_IOP 377 select GPIOLIB 378 select NEED_RET_TO_USER 379 select FORCE_PCI 380 select PLAT_IOP 381 help 382 Support for Intel's 80219 and IOP32X (XScale) family of 383 processors. 384 385config ARCH_IXP4XX 386 bool "IXP4xx-based" 387 depends on MMU 388 select ARCH_HAS_DMA_SET_COHERENT_MASK 389 select ARCH_SUPPORTS_BIG_ENDIAN 390 select CPU_XSCALE 391 select DMABOUNCE if PCI 392 select GENERIC_CLOCKEVENTS 393 select GENERIC_IRQ_MULTI_HANDLER 394 select GPIO_IXP4XX 395 select GPIOLIB 396 select HAVE_PCI 397 select IXP4XX_IRQ 398 select IXP4XX_TIMER 399 select NEED_MACH_IO_H 400 select USB_EHCI_BIG_ENDIAN_DESC 401 select USB_EHCI_BIG_ENDIAN_MMIO 402 help 403 Support for Intel's IXP4XX (XScale) family of processors. 404 405config ARCH_DOVE 406 bool "Marvell Dove" 407 select CPU_PJ4 408 select GENERIC_CLOCKEVENTS 409 select GENERIC_IRQ_MULTI_HANDLER 410 select GPIOLIB 411 select HAVE_PCI 412 select MVEBU_MBUS 413 select PINCTRL 414 select PINCTRL_DOVE 415 select PLAT_ORION_LEGACY 416 select SPARSE_IRQ 417 select PM_GENERIC_DOMAINS if PM 418 help 419 Support for the Marvell Dove SoC 88AP510 420 421config ARCH_PXA 422 bool "PXA2xx/PXA3xx-based" 423 depends on MMU 424 select ARCH_MTD_XIP 425 select ARM_CPU_SUSPEND if PM 426 select AUTO_ZRELADDR 427 select COMMON_CLK 428 select CLKSRC_PXA 429 select CLKSRC_MMIO 430 select TIMER_OF 431 select CPU_XSCALE if !CPU_XSC3 432 select GENERIC_CLOCKEVENTS 433 select GENERIC_IRQ_MULTI_HANDLER 434 select GPIO_PXA 435 select GPIOLIB 436 select HAVE_IDE 437 select IRQ_DOMAIN 438 select PLAT_PXA 439 select SPARSE_IRQ 440 help 441 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 442 443config ARCH_RPC 444 bool "RiscPC" 445 depends on MMU 446 select ARCH_ACORN 447 select ARCH_MAY_HAVE_PC_FDC 448 select ARCH_SPARSEMEM_ENABLE 449 select ARM_HAS_SG_CHAIN 450 select CPU_SA110 451 select FIQ 452 select HAVE_IDE 453 select HAVE_PATA_PLATFORM 454 select ISA_DMA_API 455 select LEGACY_TIMER_TICK 456 select NEED_MACH_IO_H 457 select NEED_MACH_MEMORY_H 458 select NO_IOPORT_MAP 459 help 460 On the Acorn Risc-PC, Linux can support the internal IDE disk and 461 CD-ROM interface, serial and parallel port, and the floppy drive. 462 463config ARCH_SA1100 464 bool "SA1100-based" 465 select ARCH_MTD_XIP 466 select ARCH_SPARSEMEM_ENABLE 467 select CLKSRC_MMIO 468 select CLKSRC_PXA 469 select TIMER_OF if OF 470 select COMMON_CLK 471 select CPU_FREQ 472 select CPU_SA1100 473 select GENERIC_CLOCKEVENTS 474 select GENERIC_IRQ_MULTI_HANDLER 475 select GPIOLIB 476 select HAVE_IDE 477 select IRQ_DOMAIN 478 select ISA 479 select NEED_MACH_MEMORY_H 480 select SPARSE_IRQ 481 help 482 Support for StrongARM 11x0 based boards. 483 484config ARCH_S3C24XX 485 bool "Samsung S3C24XX SoCs" 486 select ATAGS 487 select CLKSRC_SAMSUNG_PWM 488 select GENERIC_CLOCKEVENTS 489 select GPIO_SAMSUNG 490 select GPIOLIB 491 select GENERIC_IRQ_MULTI_HANDLER 492 select HAVE_S3C2410_I2C if I2C 493 select HAVE_S3C_RTC if RTC_CLASS 494 select NEED_MACH_IO_H 495 select S3C2410_WATCHDOG 496 select SAMSUNG_ATAGS 497 select USE_OF 498 select WATCHDOG 499 help 500 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 501 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 502 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 503 Samsung SMDK2410 development board (and derivatives). 504 505config ARCH_OMAP1 506 bool "TI OMAP1" 507 depends on MMU 508 select ARCH_HAS_HOLES_MEMORYMODEL 509 select ARCH_OMAP 510 select CLKDEV_LOOKUP 511 select CLKSRC_MMIO 512 select GENERIC_CLOCKEVENTS 513 select GENERIC_IRQ_CHIP 514 select GENERIC_IRQ_MULTI_HANDLER 515 select GPIOLIB 516 select HAVE_IDE 517 select HAVE_LEGACY_CLK 518 select IRQ_DOMAIN 519 select NEED_MACH_IO_H if PCCARD 520 select NEED_MACH_MEMORY_H 521 select SPARSE_IRQ 522 help 523 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 524 525endchoice 526 527menu "Multiple platform selection" 528 depends on ARCH_MULTIPLATFORM 529 530comment "CPU Core family selection" 531 532config ARCH_MULTI_V4 533 bool "ARMv4 based platforms (FA526)" 534 depends on !ARCH_MULTI_V6_V7 535 select ARCH_MULTI_V4_V5 536 select CPU_FA526 537 538config ARCH_MULTI_V4T 539 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 540 depends on !ARCH_MULTI_V6_V7 541 select ARCH_MULTI_V4_V5 542 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 543 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 544 CPU_ARM925T || CPU_ARM940T) 545 546config ARCH_MULTI_V5 547 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 548 depends on !ARCH_MULTI_V6_V7 549 select ARCH_MULTI_V4_V5 550 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 551 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 552 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 553 554config ARCH_MULTI_V4_V5 555 bool 556 557config ARCH_MULTI_V6 558 bool "ARMv6 based platforms (ARM11)" 559 select ARCH_MULTI_V6_V7 560 select CPU_V6K 561 562config ARCH_MULTI_V7 563 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 564 default y 565 select ARCH_MULTI_V6_V7 566 select CPU_V7 567 select HAVE_SMP 568 569config ARCH_MULTI_V6_V7 570 bool 571 select MIGHT_HAVE_CACHE_L2X0 572 573config ARCH_MULTI_CPU_AUTO 574 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 575 select ARCH_MULTI_V5 576 577endmenu 578 579config ARCH_VIRT 580 bool "Dummy Virtual Machine" 581 depends on ARCH_MULTI_V7 582 select ARM_AMBA 583 select ARM_GIC 584 select ARM_GIC_V2M if PCI 585 select ARM_GIC_V3 586 select ARM_GIC_V3_ITS if PCI 587 select ARM_PSCI 588 select HAVE_ARM_ARCH_TIMER 589 select ARCH_SUPPORTS_BIG_ENDIAN 590 591# 592# This is sorted alphabetically by mach-* pathname. However, plat-* 593# Kconfigs may be included either alphabetically (according to the 594# plat- suffix) or along side the corresponding mach-* source. 595# 596source "arch/arm/mach-actions/Kconfig" 597 598source "arch/arm/mach-alpine/Kconfig" 599 600source "arch/arm/mach-artpec/Kconfig" 601 602source "arch/arm/mach-asm9260/Kconfig" 603 604source "arch/arm/mach-aspeed/Kconfig" 605 606source "arch/arm/mach-at91/Kconfig" 607 608source "arch/arm/mach-axxia/Kconfig" 609 610source "arch/arm/mach-bcm/Kconfig" 611 612source "arch/arm/mach-berlin/Kconfig" 613 614source "arch/arm/mach-clps711x/Kconfig" 615 616source "arch/arm/mach-cns3xxx/Kconfig" 617 618source "arch/arm/mach-davinci/Kconfig" 619 620source "arch/arm/mach-digicolor/Kconfig" 621 622source "arch/arm/mach-dove/Kconfig" 623 624source "arch/arm/mach-ep93xx/Kconfig" 625 626source "arch/arm/mach-exynos/Kconfig" 627 628source "arch/arm/mach-footbridge/Kconfig" 629 630source "arch/arm/mach-gemini/Kconfig" 631 632source "arch/arm/mach-highbank/Kconfig" 633 634source "arch/arm/mach-hisi/Kconfig" 635 636source "arch/arm/mach-imx/Kconfig" 637 638source "arch/arm/mach-integrator/Kconfig" 639 640source "arch/arm/mach-iop32x/Kconfig" 641 642source "arch/arm/mach-ixp4xx/Kconfig" 643 644source "arch/arm/mach-keystone/Kconfig" 645 646source "arch/arm/mach-lpc32xx/Kconfig" 647 648source "arch/arm/mach-mediatek/Kconfig" 649 650source "arch/arm/mach-meson/Kconfig" 651 652source "arch/arm/mach-milbeaut/Kconfig" 653 654source "arch/arm/mach-mmp/Kconfig" 655 656source "arch/arm/mach-moxart/Kconfig" 657 658source "arch/arm/mach-mstar/Kconfig" 659 660source "arch/arm/mach-mv78xx0/Kconfig" 661 662source "arch/arm/mach-mvebu/Kconfig" 663 664source "arch/arm/mach-mxs/Kconfig" 665 666source "arch/arm/mach-nomadik/Kconfig" 667 668source "arch/arm/mach-npcm/Kconfig" 669 670source "arch/arm/mach-nspire/Kconfig" 671 672source "arch/arm/plat-omap/Kconfig" 673 674source "arch/arm/mach-omap1/Kconfig" 675 676source "arch/arm/mach-omap2/Kconfig" 677 678source "arch/arm/mach-orion5x/Kconfig" 679 680source "arch/arm/mach-oxnas/Kconfig" 681 682source "arch/arm/mach-picoxcell/Kconfig" 683 684source "arch/arm/mach-prima2/Kconfig" 685 686source "arch/arm/mach-pxa/Kconfig" 687source "arch/arm/plat-pxa/Kconfig" 688 689source "arch/arm/mach-qcom/Kconfig" 690 691source "arch/arm/mach-rda/Kconfig" 692 693source "arch/arm/mach-realtek/Kconfig" 694 695source "arch/arm/mach-realview/Kconfig" 696 697source "arch/arm/mach-rockchip/Kconfig" 698 699source "arch/arm/mach-s3c/Kconfig" 700 701source "arch/arm/mach-s5pv210/Kconfig" 702 703source "arch/arm/mach-sa1100/Kconfig" 704 705source "arch/arm/mach-shmobile/Kconfig" 706 707source "arch/arm/mach-socfpga/Kconfig" 708 709source "arch/arm/mach-spear/Kconfig" 710 711source "arch/arm/mach-sti/Kconfig" 712 713source "arch/arm/mach-stm32/Kconfig" 714 715source "arch/arm/mach-sunxi/Kconfig" 716 717source "arch/arm/mach-tango/Kconfig" 718 719source "arch/arm/mach-tegra/Kconfig" 720 721source "arch/arm/mach-u300/Kconfig" 722 723source "arch/arm/mach-uniphier/Kconfig" 724 725source "arch/arm/mach-ux500/Kconfig" 726 727source "arch/arm/mach-versatile/Kconfig" 728 729source "arch/arm/mach-vexpress/Kconfig" 730 731source "arch/arm/mach-vt8500/Kconfig" 732 733source "arch/arm/mach-zx/Kconfig" 734 735source "arch/arm/mach-zynq/Kconfig" 736 737# ARMv7-M architecture 738config ARCH_EFM32 739 bool "Energy Micro efm32" 740 depends on ARM_SINGLE_ARMV7M 741 select GPIOLIB 742 help 743 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 744 processors. 745 746config ARCH_LPC18XX 747 bool "NXP LPC18xx/LPC43xx" 748 depends on ARM_SINGLE_ARMV7M 749 select ARCH_HAS_RESET_CONTROLLER 750 select ARM_AMBA 751 select CLKSRC_LPC32XX 752 select PINCTRL 753 help 754 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 755 high performance microcontrollers. 756 757config ARCH_MPS2 758 bool "ARM MPS2 platform" 759 depends on ARM_SINGLE_ARMV7M 760 select ARM_AMBA 761 select CLKSRC_MPS2 762 help 763 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 764 with a range of available cores like Cortex-M3/M4/M7. 765 766 Please, note that depends which Application Note is used memory map 767 for the platform may vary, so adjustment of RAM base might be needed. 768 769# Definitions to make life easier 770config ARCH_ACORN 771 bool 772 773config PLAT_IOP 774 bool 775 select GENERIC_CLOCKEVENTS 776 777config PLAT_ORION 778 bool 779 select CLKSRC_MMIO 780 select COMMON_CLK 781 select GENERIC_IRQ_CHIP 782 select IRQ_DOMAIN 783 784config PLAT_ORION_LEGACY 785 bool 786 select PLAT_ORION 787 788config PLAT_PXA 789 bool 790 791config PLAT_VERSATILE 792 bool 793 794source "arch/arm/mm/Kconfig" 795 796config IWMMXT 797 bool "Enable iWMMXt support" 798 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 799 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 800 help 801 Enable support for iWMMXt context switching at run time if 802 running on a CPU that supports it. 803 804if !MMU 805source "arch/arm/Kconfig-nommu" 806endif 807 808config PJ4B_ERRATA_4742 809 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 810 depends on CPU_PJ4B && MACH_ARMADA_370 811 default y 812 help 813 When coming out of either a Wait for Interrupt (WFI) or a Wait for 814 Event (WFE) IDLE states, a specific timing sensitivity exists between 815 the retiring WFI/WFE instructions and the newly issued subsequent 816 instructions. This sensitivity can result in a CPU hang scenario. 817 Workaround: 818 The software must insert either a Data Synchronization Barrier (DSB) 819 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 820 instruction 821 822config ARM_ERRATA_326103 823 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 824 depends on CPU_V6 825 help 826 Executing a SWP instruction to read-only memory does not set bit 11 827 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 828 treat the access as a read, preventing a COW from occurring and 829 causing the faulting task to livelock. 830 831config ARM_ERRATA_411920 832 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 833 depends on CPU_V6 || CPU_V6K 834 help 835 Invalidation of the Instruction Cache operation can 836 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 837 It does not affect the MPCore. This option enables the ARM Ltd. 838 recommended workaround. 839 840config ARM_ERRATA_430973 841 bool "ARM errata: Stale prediction on replaced interworking branch" 842 depends on CPU_V7 843 help 844 This option enables the workaround for the 430973 Cortex-A8 845 r1p* erratum. If a code sequence containing an ARM/Thumb 846 interworking branch is replaced with another code sequence at the 847 same virtual address, whether due to self-modifying code or virtual 848 to physical address re-mapping, Cortex-A8 does not recover from the 849 stale interworking branch prediction. This results in Cortex-A8 850 executing the new code sequence in the incorrect ARM or Thumb state. 851 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 852 and also flushes the branch target cache at every context switch. 853 Note that setting specific bits in the ACTLR register may not be 854 available in non-secure mode. 855 856config ARM_ERRATA_458693 857 bool "ARM errata: Processor deadlock when a false hazard is created" 858 depends on CPU_V7 859 depends on !ARCH_MULTIPLATFORM 860 help 861 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 862 erratum. For very specific sequences of memory operations, it is 863 possible for a hazard condition intended for a cache line to instead 864 be incorrectly associated with a different cache line. This false 865 hazard might then cause a processor deadlock. The workaround enables 866 the L1 caching of the NEON accesses and disables the PLD instruction 867 in the ACTLR register. Note that setting specific bits in the ACTLR 868 register may not be available in non-secure mode. 869 870config ARM_ERRATA_460075 871 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 872 depends on CPU_V7 873 depends on !ARCH_MULTIPLATFORM 874 help 875 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 876 erratum. Any asynchronous access to the L2 cache may encounter a 877 situation in which recent store transactions to the L2 cache are lost 878 and overwritten with stale memory contents from external memory. The 879 workaround disables the write-allocate mode for the L2 cache via the 880 ACTLR register. Note that setting specific bits in the ACTLR register 881 may not be available in non-secure mode. 882 883config ARM_ERRATA_742230 884 bool "ARM errata: DMB operation may be faulty" 885 depends on CPU_V7 && SMP 886 depends on !ARCH_MULTIPLATFORM 887 help 888 This option enables the workaround for the 742230 Cortex-A9 889 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 890 between two write operations may not ensure the correct visibility 891 ordering of the two writes. This workaround sets a specific bit in 892 the diagnostic register of the Cortex-A9 which causes the DMB 893 instruction to behave as a DSB, ensuring the correct behaviour of 894 the two writes. 895 896config ARM_ERRATA_742231 897 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 898 depends on CPU_V7 && SMP 899 depends on !ARCH_MULTIPLATFORM 900 help 901 This option enables the workaround for the 742231 Cortex-A9 902 (r2p0..r2p2) erratum. Under certain conditions, specific to the 903 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 904 accessing some data located in the same cache line, may get corrupted 905 data due to bad handling of the address hazard when the line gets 906 replaced from one of the CPUs at the same time as another CPU is 907 accessing it. This workaround sets specific bits in the diagnostic 908 register of the Cortex-A9 which reduces the linefill issuing 909 capabilities of the processor. 910 911config ARM_ERRATA_643719 912 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 913 depends on CPU_V7 && SMP 914 default y 915 help 916 This option enables the workaround for the 643719 Cortex-A9 (prior to 917 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 918 register returns zero when it should return one. The workaround 919 corrects this value, ensuring cache maintenance operations which use 920 it behave as intended and avoiding data corruption. 921 922config ARM_ERRATA_720789 923 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 924 depends on CPU_V7 925 help 926 This option enables the workaround for the 720789 Cortex-A9 (prior to 927 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 928 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 929 As a consequence of this erratum, some TLB entries which should be 930 invalidated are not, resulting in an incoherency in the system page 931 tables. The workaround changes the TLB flushing routines to invalidate 932 entries regardless of the ASID. 933 934config ARM_ERRATA_743622 935 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 936 depends on CPU_V7 937 depends on !ARCH_MULTIPLATFORM 938 help 939 This option enables the workaround for the 743622 Cortex-A9 940 (r2p*) erratum. Under very rare conditions, a faulty 941 optimisation in the Cortex-A9 Store Buffer may lead to data 942 corruption. This workaround sets a specific bit in the diagnostic 943 register of the Cortex-A9 which disables the Store Buffer 944 optimisation, preventing the defect from occurring. This has no 945 visible impact on the overall performance or power consumption of the 946 processor. 947 948config ARM_ERRATA_751472 949 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 950 depends on CPU_V7 951 depends on !ARCH_MULTIPLATFORM 952 help 953 This option enables the workaround for the 751472 Cortex-A9 (prior 954 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 955 completion of a following broadcasted operation if the second 956 operation is received by a CPU before the ICIALLUIS has completed, 957 potentially leading to corrupted entries in the cache or TLB. 958 959config ARM_ERRATA_754322 960 bool "ARM errata: possible faulty MMU translations following an ASID switch" 961 depends on CPU_V7 962 help 963 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 964 r3p*) erratum. A speculative memory access may cause a page table walk 965 which starts prior to an ASID switch but completes afterwards. This 966 can populate the micro-TLB with a stale entry which may be hit with 967 the new ASID. This workaround places two dsb instructions in the mm 968 switching code so that no page table walks can cross the ASID switch. 969 970config ARM_ERRATA_754327 971 bool "ARM errata: no automatic Store Buffer drain" 972 depends on CPU_V7 && SMP 973 help 974 This option enables the workaround for the 754327 Cortex-A9 (prior to 975 r2p0) erratum. The Store Buffer does not have any automatic draining 976 mechanism and therefore a livelock may occur if an external agent 977 continuously polls a memory location waiting to observe an update. 978 This workaround defines cpu_relax() as smp_mb(), preventing correctly 979 written polling loops from denying visibility of updates to memory. 980 981config ARM_ERRATA_364296 982 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 983 depends on CPU_V6 984 help 985 This options enables the workaround for the 364296 ARM1136 986 r0p2 erratum (possible cache data corruption with 987 hit-under-miss enabled). It sets the undocumented bit 31 in 988 the auxiliary control register and the FI bit in the control 989 register, thus disabling hit-under-miss without putting the 990 processor into full low interrupt latency mode. ARM11MPCore 991 is not affected. 992 993config ARM_ERRATA_764369 994 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 995 depends on CPU_V7 && SMP 996 help 997 This option enables the workaround for erratum 764369 998 affecting Cortex-A9 MPCore with two or more processors (all 999 current revisions). Under certain timing circumstances, a data 1000 cache line maintenance operation by MVA targeting an Inner 1001 Shareable memory region may fail to proceed up to either the 1002 Point of Coherency or to the Point of Unification of the 1003 system. This workaround adds a DSB instruction before the 1004 relevant cache maintenance functions and sets a specific bit 1005 in the diagnostic control register of the SCU. 1006 1007config ARM_ERRATA_775420 1008 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1009 depends on CPU_V7 1010 help 1011 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1012 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1013 operation aborts with MMU exception, it might cause the processor 1014 to deadlock. This workaround puts DSB before executing ISB if 1015 an abort may occur on cache maintenance. 1016 1017config ARM_ERRATA_798181 1018 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1019 depends on CPU_V7 && SMP 1020 help 1021 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1022 adequately shooting down all use of the old entries. This 1023 option enables the Linux kernel workaround for this erratum 1024 which sends an IPI to the CPUs that are running the same ASID 1025 as the one being invalidated. 1026 1027config ARM_ERRATA_773022 1028 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1029 depends on CPU_V7 1030 help 1031 This option enables the workaround for the 773022 Cortex-A15 1032 (up to r0p4) erratum. In certain rare sequences of code, the 1033 loop buffer may deliver incorrect instructions. This 1034 workaround disables the loop buffer to avoid the erratum. 1035 1036config ARM_ERRATA_818325_852422 1037 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1038 depends on CPU_V7 1039 help 1040 This option enables the workaround for: 1041 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1042 instruction might deadlock. Fixed in r0p1. 1043 - Cortex-A12 852422: Execution of a sequence of instructions might 1044 lead to either a data corruption or a CPU deadlock. Not fixed in 1045 any Cortex-A12 cores yet. 1046 This workaround for all both errata involves setting bit[12] of the 1047 Feature Register. This bit disables an optimisation applied to a 1048 sequence of 2 instructions that use opposing condition codes. 1049 1050config ARM_ERRATA_821420 1051 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for the 821420 Cortex-A12 1055 (all revs) erratum. In very rare timing conditions, a sequence 1056 of VMOV to Core registers instructions, for which the second 1057 one is in the shadow of a branch or abort, can lead to a 1058 deadlock when the VMOV instructions are issued out-of-order. 1059 1060config ARM_ERRATA_825619 1061 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1062 depends on CPU_V7 1063 help 1064 This option enables the workaround for the 825619 Cortex-A12 1065 (all revs) erratum. Within rare timing constraints, executing a 1066 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1067 and Device/Strongly-Ordered loads and stores might cause deadlock 1068 1069config ARM_ERRATA_857271 1070 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1071 depends on CPU_V7 1072 help 1073 This option enables the workaround for the 857271 Cortex-A12 1074 (all revs) erratum. Under very rare timing conditions, the CPU might 1075 hang. The workaround is expected to have a < 1% performance impact. 1076 1077config ARM_ERRATA_852421 1078 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1079 depends on CPU_V7 1080 help 1081 This option enables the workaround for the 852421 Cortex-A17 1082 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1083 execution of a DMB ST instruction might fail to properly order 1084 stores from GroupA and stores from GroupB. 1085 1086config ARM_ERRATA_852423 1087 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1088 depends on CPU_V7 1089 help 1090 This option enables the workaround for: 1091 - Cortex-A17 852423: Execution of a sequence of instructions might 1092 lead to either a data corruption or a CPU deadlock. Not fixed in 1093 any Cortex-A17 cores yet. 1094 This is identical to Cortex-A12 erratum 852422. It is a separate 1095 config option from the A12 erratum due to the way errata are checked 1096 for and handled. 1097 1098config ARM_ERRATA_857272 1099 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1100 depends on CPU_V7 1101 help 1102 This option enables the workaround for the 857272 Cortex-A17 erratum. 1103 This erratum is not known to be fixed in any A17 revision. 1104 This is identical to Cortex-A12 erratum 857271. It is a separate 1105 config option from the A12 erratum due to the way errata are checked 1106 for and handled. 1107 1108endmenu 1109 1110source "arch/arm/common/Kconfig" 1111 1112menu "Bus support" 1113 1114config ISA 1115 bool 1116 help 1117 Find out whether you have ISA slots on your motherboard. ISA is the 1118 name of a bus system, i.e. the way the CPU talks to the other stuff 1119 inside your box. Other bus systems are PCI, EISA, MicroChannel 1120 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1121 newer boards don't support it. If you have ISA, say Y, otherwise N. 1122 1123# Select ISA DMA controller support 1124config ISA_DMA 1125 bool 1126 select ISA_DMA_API 1127 1128# Select ISA DMA interface 1129config ISA_DMA_API 1130 bool 1131 1132config PCI_NANOENGINE 1133 bool "BSE nanoEngine PCI support" 1134 depends on SA1100_NANOENGINE 1135 help 1136 Enable PCI on the BSE nanoEngine board. 1137 1138config ARM_ERRATA_814220 1139 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1140 depends on CPU_V7 1141 help 1142 The v7 ARM states that all cache and branch predictor maintenance 1143 operations that do not specify an address execute, relative to 1144 each other, in program order. 1145 However, because of this erratum, an L2 set/way cache maintenance 1146 operation can overtake an L1 set/way cache maintenance operation. 1147 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1148 r0p4, r0p5. 1149 1150endmenu 1151 1152menu "Kernel Features" 1153 1154config HAVE_SMP 1155 bool 1156 help 1157 This option should be selected by machines which have an SMP- 1158 capable CPU. 1159 1160 The only effect of this option is to make the SMP-related 1161 options available to the user for configuration. 1162 1163config SMP 1164 bool "Symmetric Multi-Processing" 1165 depends on CPU_V6K || CPU_V7 1166 depends on GENERIC_CLOCKEVENTS 1167 depends on HAVE_SMP 1168 depends on MMU || ARM_MPU 1169 select IRQ_WORK 1170 help 1171 This enables support for systems with more than one CPU. If you have 1172 a system with only one CPU, say N. If you have a system with more 1173 than one CPU, say Y. 1174 1175 If you say N here, the kernel will run on uni- and multiprocessor 1176 machines, but will use only one CPU of a multiprocessor machine. If 1177 you say Y here, the kernel will run on many, but not all, 1178 uniprocessor machines. On a uniprocessor machine, the kernel 1179 will run faster if you say N here. 1180 1181 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1182 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1183 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1184 1185 If you don't know what to do here, say N. 1186 1187config SMP_ON_UP 1188 bool "Allow booting SMP kernel on uniprocessor systems" 1189 depends on SMP && !XIP_KERNEL && MMU 1190 default y 1191 help 1192 SMP kernels contain instructions which fail on non-SMP processors. 1193 Enabling this option allows the kernel to modify itself to make 1194 these instructions safe. Disabling it allows about 1K of space 1195 savings. 1196 1197 If you don't know what to do here, say Y. 1198 1199config ARM_CPU_TOPOLOGY 1200 bool "Support cpu topology definition" 1201 depends on SMP && CPU_V7 1202 default y 1203 help 1204 Support ARM cpu topology definition. The MPIDR register defines 1205 affinity between processors which is then used to describe the cpu 1206 topology of an ARM System. 1207 1208config SCHED_MC 1209 bool "Multi-core scheduler support" 1210 depends on ARM_CPU_TOPOLOGY 1211 help 1212 Multi-core scheduler support improves the CPU scheduler's decision 1213 making when dealing with multi-core CPU chips at a cost of slightly 1214 increased overhead in some places. If unsure say N here. 1215 1216config SCHED_SMT 1217 bool "SMT scheduler support" 1218 depends on ARM_CPU_TOPOLOGY 1219 help 1220 Improves the CPU scheduler's decision making when dealing with 1221 MultiThreading at a cost of slightly increased overhead in some 1222 places. If unsure say N here. 1223 1224config HAVE_ARM_SCU 1225 bool 1226 help 1227 This option enables support for the ARM snoop control unit 1228 1229config HAVE_ARM_ARCH_TIMER 1230 bool "Architected timer support" 1231 depends on CPU_V7 1232 select ARM_ARCH_TIMER 1233 help 1234 This option enables support for the ARM architected timer 1235 1236config HAVE_ARM_TWD 1237 bool 1238 help 1239 This options enables support for the ARM timer and watchdog unit 1240 1241config MCPM 1242 bool "Multi-Cluster Power Management" 1243 depends on CPU_V7 && SMP 1244 help 1245 This option provides the common power management infrastructure 1246 for (multi-)cluster based systems, such as big.LITTLE based 1247 systems. 1248 1249config MCPM_QUAD_CLUSTER 1250 bool 1251 depends on MCPM 1252 help 1253 To avoid wasting resources unnecessarily, MCPM only supports up 1254 to 2 clusters by default. 1255 Platforms with 3 or 4 clusters that use MCPM must select this 1256 option to allow the additional clusters to be managed. 1257 1258config BIG_LITTLE 1259 bool "big.LITTLE support (Experimental)" 1260 depends on CPU_V7 && SMP 1261 select MCPM 1262 help 1263 This option enables support selections for the big.LITTLE 1264 system architecture. 1265 1266config BL_SWITCHER 1267 bool "big.LITTLE switcher support" 1268 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1269 select CPU_PM 1270 help 1271 The big.LITTLE "switcher" provides the core functionality to 1272 transparently handle transition between a cluster of A15's 1273 and a cluster of A7's in a big.LITTLE system. 1274 1275config BL_SWITCHER_DUMMY_IF 1276 tristate "Simple big.LITTLE switcher user interface" 1277 depends on BL_SWITCHER && DEBUG_KERNEL 1278 help 1279 This is a simple and dummy char dev interface to control 1280 the big.LITTLE switcher core code. It is meant for 1281 debugging purposes only. 1282 1283choice 1284 prompt "Memory split" 1285 depends on MMU 1286 default VMSPLIT_3G 1287 help 1288 Select the desired split between kernel and user memory. 1289 1290 If you are not absolutely sure what you are doing, leave this 1291 option alone! 1292 1293 config VMSPLIT_3G 1294 bool "3G/1G user/kernel split" 1295 config VMSPLIT_3G_OPT 1296 depends on !ARM_LPAE 1297 bool "3G/1G user/kernel split (for full 1G low memory)" 1298 config VMSPLIT_2G 1299 bool "2G/2G user/kernel split" 1300 config VMSPLIT_1G 1301 bool "1G/3G user/kernel split" 1302endchoice 1303 1304config PAGE_OFFSET 1305 hex 1306 default PHYS_OFFSET if !MMU 1307 default 0x40000000 if VMSPLIT_1G 1308 default 0x80000000 if VMSPLIT_2G 1309 default 0xB0000000 if VMSPLIT_3G_OPT 1310 default 0xC0000000 1311 1312config NR_CPUS 1313 int "Maximum number of CPUs (2-32)" 1314 range 2 32 1315 depends on SMP 1316 default "4" 1317 1318config HOTPLUG_CPU 1319 bool "Support for hot-pluggable CPUs" 1320 depends on SMP 1321 select GENERIC_IRQ_MIGRATION 1322 help 1323 Say Y here to experiment with turning CPUs off and on. CPUs 1324 can be controlled through /sys/devices/system/cpu. 1325 1326config ARM_PSCI 1327 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1328 depends on HAVE_ARM_SMCCC 1329 select ARM_PSCI_FW 1330 help 1331 Say Y here if you want Linux to communicate with system firmware 1332 implementing the PSCI specification for CPU-centric power 1333 management operations described in ARM document number ARM DEN 1334 0022A ("Power State Coordination Interface System Software on 1335 ARM processors"). 1336 1337# The GPIO number here must be sorted by descending number. In case of 1338# a multiplatform kernel, we just want the highest value required by the 1339# selected platforms. 1340config ARCH_NR_GPIO 1341 int 1342 default 2048 if ARCH_SOCFPGA 1343 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1344 ARCH_ZYNQ || ARCH_ASPEED 1345 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1346 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1347 default 416 if ARCH_SUNXI 1348 default 392 if ARCH_U8500 1349 default 352 if ARCH_VT8500 1350 default 288 if ARCH_ROCKCHIP 1351 default 264 if MACH_H4700 1352 default 0 1353 help 1354 Maximum number of GPIOs in the system. 1355 1356 If unsure, leave the default value. 1357 1358config HZ_FIXED 1359 int 1360 default 128 if SOC_AT91RM9200 1361 default 0 1362 1363choice 1364 depends on HZ_FIXED = 0 1365 prompt "Timer frequency" 1366 1367config HZ_100 1368 bool "100 Hz" 1369 1370config HZ_200 1371 bool "200 Hz" 1372 1373config HZ_250 1374 bool "250 Hz" 1375 1376config HZ_300 1377 bool "300 Hz" 1378 1379config HZ_500 1380 bool "500 Hz" 1381 1382config HZ_1000 1383 bool "1000 Hz" 1384 1385endchoice 1386 1387config HZ 1388 int 1389 default HZ_FIXED if HZ_FIXED != 0 1390 default 100 if HZ_100 1391 default 200 if HZ_200 1392 default 250 if HZ_250 1393 default 300 if HZ_300 1394 default 500 if HZ_500 1395 default 1000 1396 1397config SCHED_HRTICK 1398 def_bool HIGH_RES_TIMERS 1399 1400config THUMB2_KERNEL 1401 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1402 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1403 default y if CPU_THUMBONLY 1404 select ARM_UNWIND 1405 help 1406 By enabling this option, the kernel will be compiled in 1407 Thumb-2 mode. 1408 1409 If unsure, say N. 1410 1411config ARM_PATCH_IDIV 1412 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1413 depends on CPU_32v7 && !XIP_KERNEL 1414 default y 1415 help 1416 The ARM compiler inserts calls to __aeabi_idiv() and 1417 __aeabi_uidiv() when it needs to perform division on signed 1418 and unsigned integers. Some v7 CPUs have support for the sdiv 1419 and udiv instructions that can be used to implement those 1420 functions. 1421 1422 Enabling this option allows the kernel to modify itself to 1423 replace the first two instructions of these library functions 1424 with the sdiv or udiv plus "bx lr" instructions when the CPU 1425 it is running on supports them. Typically this will be faster 1426 and less power intensive than running the original library 1427 code to do integer division. 1428 1429config AEABI 1430 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1431 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1432 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1433 help 1434 This option allows for the kernel to be compiled using the latest 1435 ARM ABI (aka EABI). This is only useful if you are using a user 1436 space environment that is also compiled with EABI. 1437 1438 Since there are major incompatibilities between the legacy ABI and 1439 EABI, especially with regard to structure member alignment, this 1440 option also changes the kernel syscall calling convention to 1441 disambiguate both ABIs and allow for backward compatibility support 1442 (selected with CONFIG_OABI_COMPAT). 1443 1444 To use this you need GCC version 4.0.0 or later. 1445 1446config OABI_COMPAT 1447 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1448 depends on AEABI && !THUMB2_KERNEL 1449 help 1450 This option preserves the old syscall interface along with the 1451 new (ARM EABI) one. It also provides a compatibility layer to 1452 intercept syscalls that have structure arguments which layout 1453 in memory differs between the legacy ABI and the new ARM EABI 1454 (only for non "thumb" binaries). This option adds a tiny 1455 overhead to all syscalls and produces a slightly larger kernel. 1456 1457 The seccomp filter system will not be available when this is 1458 selected, since there is no way yet to sensibly distinguish 1459 between calling conventions during filtering. 1460 1461 If you know you'll be using only pure EABI user space then you 1462 can say N here. If this option is not selected and you attempt 1463 to execute a legacy ABI binary then the result will be 1464 UNPREDICTABLE (in fact it can be predicted that it won't work 1465 at all). If in doubt say N. 1466 1467config ARCH_HAS_HOLES_MEMORYMODEL 1468 bool 1469 1470config ARCH_SELECT_MEMORY_MODEL 1471 bool 1472 1473config ARCH_FLATMEM_ENABLE 1474 bool 1475 1476config ARCH_SPARSEMEM_ENABLE 1477 bool 1478 select SPARSEMEM_STATIC if SPARSEMEM 1479 1480config HAVE_ARCH_PFN_VALID 1481 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1482 1483config HIGHMEM 1484 bool "High Memory Support" 1485 depends on MMU 1486 help 1487 The address space of ARM processors is only 4 Gigabytes large 1488 and it has to accommodate user address space, kernel address 1489 space as well as some memory mapped IO. That means that, if you 1490 have a large amount of physical memory and/or IO, not all of the 1491 memory can be "permanently mapped" by the kernel. The physical 1492 memory that is not permanently mapped is called "high memory". 1493 1494 Depending on the selected kernel/user memory split, minimum 1495 vmalloc space and actual amount of RAM, you may not need this 1496 option which should result in a slightly faster kernel. 1497 1498 If unsure, say n. 1499 1500config HIGHPTE 1501 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1502 depends on HIGHMEM 1503 default y 1504 help 1505 The VM uses one page of physical memory for each page table. 1506 For systems with a lot of processes, this can use a lot of 1507 precious low memory, eventually leading to low memory being 1508 consumed by page tables. Setting this option will allow 1509 user-space 2nd level page tables to reside in high memory. 1510 1511config CPU_SW_DOMAIN_PAN 1512 bool "Enable use of CPU domains to implement privileged no-access" 1513 depends on MMU && !ARM_LPAE 1514 default y 1515 help 1516 Increase kernel security by ensuring that normal kernel accesses 1517 are unable to access userspace addresses. This can help prevent 1518 use-after-free bugs becoming an exploitable privilege escalation 1519 by ensuring that magic values (such as LIST_POISON) will always 1520 fault when dereferenced. 1521 1522 CPUs with low-vector mappings use a best-efforts implementation. 1523 Their lower 1MB needs to remain accessible for the vectors, but 1524 the remainder of userspace will become appropriately inaccessible. 1525 1526config HW_PERF_EVENTS 1527 def_bool y 1528 depends on ARM_PMU 1529 1530config SYS_SUPPORTS_HUGETLBFS 1531 def_bool y 1532 depends on ARM_LPAE 1533 1534config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1535 def_bool y 1536 depends on ARM_LPAE 1537 1538config ARCH_WANT_GENERAL_HUGETLB 1539 def_bool y 1540 1541config ARM_MODULE_PLTS 1542 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1543 depends on MODULES 1544 default y 1545 help 1546 Allocate PLTs when loading modules so that jumps and calls whose 1547 targets are too far away for their relative offsets to be encoded 1548 in the instructions themselves can be bounced via veneers in the 1549 module's PLT. This allows modules to be allocated in the generic 1550 vmalloc area after the dedicated module memory area has been 1551 exhausted. The modules will use slightly more memory, but after 1552 rounding up to page size, the actual memory footprint is usually 1553 the same. 1554 1555 Disabling this is usually safe for small single-platform 1556 configurations. If unsure, say y. 1557 1558config FORCE_MAX_ZONEORDER 1559 int "Maximum zone order" 1560 default "12" if SOC_AM33XX 1561 default "9" if SA1111 || ARCH_EFM32 1562 default "11" 1563 help 1564 The kernel memory allocator divides physically contiguous memory 1565 blocks into "zones", where each zone is a power of two number of 1566 pages. This option selects the largest power of two that the kernel 1567 keeps in the memory allocator. If you need to allocate very large 1568 blocks of physically contiguous memory, then you may need to 1569 increase this value. 1570 1571 This config option is actually maximum order plus one. For example, 1572 a value of 11 means that the largest free memory block is 2^10 pages. 1573 1574config ALIGNMENT_TRAP 1575 def_bool CPU_CP15_MMU 1576 select HAVE_PROC_CPU if PROC_FS 1577 help 1578 ARM processors cannot fetch/store information which is not 1579 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1580 address divisible by 4. On 32-bit ARM processors, these non-aligned 1581 fetch/store instructions will be emulated in software if you say 1582 here, which has a severe performance impact. This is necessary for 1583 correct operation of some network protocols. With an IP-only 1584 configuration it is safe to say N, otherwise say Y. 1585 1586config UACCESS_WITH_MEMCPY 1587 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1588 depends on MMU 1589 default y if CPU_FEROCEON 1590 help 1591 Implement faster copy_to_user and clear_user methods for CPU 1592 cores where a 8-word STM instruction give significantly higher 1593 memory write throughput than a sequence of individual 32bit stores. 1594 1595 A possible side effect is a slight increase in scheduling latency 1596 between threads sharing the same address space if they invoke 1597 such copy operations with large buffers. 1598 1599 However, if the CPU data cache is using a write-allocate mode, 1600 this option is unlikely to provide any performance gain. 1601 1602config PARAVIRT 1603 bool "Enable paravirtualization code" 1604 help 1605 This changes the kernel so it can modify itself when it is run 1606 under a hypervisor, potentially improving performance significantly 1607 over full virtualization. 1608 1609config PARAVIRT_TIME_ACCOUNTING 1610 bool "Paravirtual steal time accounting" 1611 select PARAVIRT 1612 help 1613 Select this option to enable fine granularity task steal time 1614 accounting. Time spent executing other tasks in parallel with 1615 the current vCPU is discounted from the vCPU power. To account for 1616 that, there can be a small performance impact. 1617 1618 If in doubt, say N here. 1619 1620config XEN_DOM0 1621 def_bool y 1622 depends on XEN 1623 1624config XEN 1625 bool "Xen guest support on ARM" 1626 depends on ARM && AEABI && OF 1627 depends on CPU_V7 && !CPU_V6 1628 depends on !GENERIC_ATOMIC64 1629 depends on MMU 1630 select ARCH_DMA_ADDR_T_64BIT 1631 select ARM_PSCI 1632 select SWIOTLB 1633 select SWIOTLB_XEN 1634 select PARAVIRT 1635 help 1636 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1637 1638config STACKPROTECTOR_PER_TASK 1639 bool "Use a unique stack canary value for each task" 1640 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1641 select GCC_PLUGIN_ARM_SSP_PER_TASK 1642 default y 1643 help 1644 Due to the fact that GCC uses an ordinary symbol reference from 1645 which to load the value of the stack canary, this value can only 1646 change at reboot time on SMP systems, and all tasks running in the 1647 kernel's address space are forced to use the same canary value for 1648 the entire duration that the system is up. 1649 1650 Enable this option to switch to a different method that uses a 1651 different canary value for each task. 1652 1653endmenu 1654 1655menu "Boot options" 1656 1657config USE_OF 1658 bool "Flattened Device Tree support" 1659 select IRQ_DOMAIN 1660 select OF 1661 help 1662 Include support for flattened device tree machine descriptions. 1663 1664config ATAGS 1665 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1666 default y 1667 help 1668 This is the traditional way of passing data to the kernel at boot 1669 time. If you are solely relying on the flattened device tree (or 1670 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1671 to remove ATAGS support from your kernel binary. If unsure, 1672 leave this to y. 1673 1674config DEPRECATED_PARAM_STRUCT 1675 bool "Provide old way to pass kernel parameters" 1676 depends on ATAGS 1677 help 1678 This was deprecated in 2001 and announced to live on for 5 years. 1679 Some old boot loaders still use this way. 1680 1681# Compressed boot loader in ROM. Yes, we really want to ask about 1682# TEXT and BSS so we preserve their values in the config files. 1683config ZBOOT_ROM_TEXT 1684 hex "Compressed ROM boot loader base address" 1685 default 0x0 1686 help 1687 The physical address at which the ROM-able zImage is to be 1688 placed in the target. Platforms which normally make use of 1689 ROM-able zImage formats normally set this to a suitable 1690 value in their defconfig file. 1691 1692 If ZBOOT_ROM is not enabled, this has no effect. 1693 1694config ZBOOT_ROM_BSS 1695 hex "Compressed ROM boot loader BSS address" 1696 default 0x0 1697 help 1698 The base address of an area of read/write memory in the target 1699 for the ROM-able zImage which must be available while the 1700 decompressor is running. It must be large enough to hold the 1701 entire decompressed kernel plus an additional 128 KiB. 1702 Platforms which normally make use of ROM-able zImage formats 1703 normally set this to a suitable value in their defconfig file. 1704 1705 If ZBOOT_ROM is not enabled, this has no effect. 1706 1707config ZBOOT_ROM 1708 bool "Compressed boot loader in ROM/flash" 1709 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1710 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1711 help 1712 Say Y here if you intend to execute your compressed kernel image 1713 (zImage) directly from ROM or flash. If unsure, say N. 1714 1715config ARM_APPENDED_DTB 1716 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1717 depends on OF 1718 help 1719 With this option, the boot code will look for a device tree binary 1720 (DTB) appended to zImage 1721 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1722 1723 This is meant as a backward compatibility convenience for those 1724 systems with a bootloader that can't be upgraded to accommodate 1725 the documented boot protocol using a device tree. 1726 1727 Beware that there is very little in terms of protection against 1728 this option being confused by leftover garbage in memory that might 1729 look like a DTB header after a reboot if no actual DTB is appended 1730 to zImage. Do not leave this option active in a production kernel 1731 if you don't intend to always append a DTB. Proper passing of the 1732 location into r2 of a bootloader provided DTB is always preferable 1733 to this option. 1734 1735config ARM_ATAG_DTB_COMPAT 1736 bool "Supplement the appended DTB with traditional ATAG information" 1737 depends on ARM_APPENDED_DTB 1738 help 1739 Some old bootloaders can't be updated to a DTB capable one, yet 1740 they provide ATAGs with memory configuration, the ramdisk address, 1741 the kernel cmdline string, etc. Such information is dynamically 1742 provided by the bootloader and can't always be stored in a static 1743 DTB. To allow a device tree enabled kernel to be used with such 1744 bootloaders, this option allows zImage to extract the information 1745 from the ATAG list and store it at run time into the appended DTB. 1746 1747choice 1748 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1749 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1750 1751config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1752 bool "Use bootloader kernel arguments if available" 1753 help 1754 Uses the command-line options passed by the boot loader instead of 1755 the device tree bootargs property. If the boot loader doesn't provide 1756 any, the device tree bootargs property will be used. 1757 1758config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1759 bool "Extend with bootloader kernel arguments" 1760 help 1761 The command-line arguments provided by the boot loader will be 1762 appended to the the device tree bootargs property. 1763 1764endchoice 1765 1766config CMDLINE 1767 string "Default kernel command string" 1768 default "" 1769 help 1770 On some architectures (e.g. CATS), there is currently no way 1771 for the boot loader to pass arguments to the kernel. For these 1772 architectures, you should supply some command-line options at build 1773 time by entering them here. As a minimum, you should specify the 1774 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1775 1776choice 1777 prompt "Kernel command line type" if CMDLINE != "" 1778 default CMDLINE_FROM_BOOTLOADER 1779 depends on ATAGS 1780 1781config CMDLINE_FROM_BOOTLOADER 1782 bool "Use bootloader kernel arguments if available" 1783 help 1784 Uses the command-line options passed by the boot loader. If 1785 the boot loader doesn't provide any, the default kernel command 1786 string provided in CMDLINE will be used. 1787 1788config CMDLINE_EXTEND 1789 bool "Extend bootloader kernel arguments" 1790 help 1791 The command-line arguments provided by the boot loader will be 1792 appended to the default kernel command string. 1793 1794config CMDLINE_FORCE 1795 bool "Always use the default kernel command string" 1796 help 1797 Always use the default kernel command string, even if the boot 1798 loader passes other arguments to the kernel. 1799 This is useful if you cannot or don't want to change the 1800 command-line options your boot loader passes to the kernel. 1801endchoice 1802 1803config XIP_KERNEL 1804 bool "Kernel Execute-In-Place from ROM" 1805 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1806 help 1807 Execute-In-Place allows the kernel to run from non-volatile storage 1808 directly addressable by the CPU, such as NOR flash. This saves RAM 1809 space since the text section of the kernel is not loaded from flash 1810 to RAM. Read-write sections, such as the data section and stack, 1811 are still copied to RAM. The XIP kernel is not compressed since 1812 it has to run directly from flash, so it will take more space to 1813 store it. The flash address used to link the kernel object files, 1814 and for storing it, is configuration dependent. Therefore, if you 1815 say Y here, you must know the proper physical address where to 1816 store the kernel image depending on your own flash memory usage. 1817 1818 Also note that the make target becomes "make xipImage" rather than 1819 "make zImage" or "make Image". The final kernel binary to put in 1820 ROM memory will be arch/arm/boot/xipImage. 1821 1822 If unsure, say N. 1823 1824config XIP_PHYS_ADDR 1825 hex "XIP Kernel Physical Location" 1826 depends on XIP_KERNEL 1827 default "0x00080000" 1828 help 1829 This is the physical address in your flash memory the kernel will 1830 be linked for and stored to. This address is dependent on your 1831 own flash usage. 1832 1833config XIP_DEFLATED_DATA 1834 bool "Store kernel .data section compressed in ROM" 1835 depends on XIP_KERNEL 1836 select ZLIB_INFLATE 1837 help 1838 Before the kernel is actually executed, its .data section has to be 1839 copied to RAM from ROM. This option allows for storing that data 1840 in compressed form and decompressed to RAM rather than merely being 1841 copied, saving some precious ROM space. A possible drawback is a 1842 slightly longer boot delay. 1843 1844config KEXEC 1845 bool "Kexec system call (EXPERIMENTAL)" 1846 depends on (!SMP || PM_SLEEP_SMP) 1847 depends on MMU 1848 select KEXEC_CORE 1849 help 1850 kexec is a system call that implements the ability to shutdown your 1851 current kernel, and to start another kernel. It is like a reboot 1852 but it is independent of the system firmware. And like a reboot 1853 you can start any kernel with it, not just Linux. 1854 1855 It is an ongoing process to be certain the hardware in a machine 1856 is properly shutdown, so do not be surprised if this code does not 1857 initially work for you. 1858 1859config ATAGS_PROC 1860 bool "Export atags in procfs" 1861 depends on ATAGS && KEXEC 1862 default y 1863 help 1864 Should the atags used to boot the kernel be exported in an "atags" 1865 file in procfs. Useful with kexec. 1866 1867config CRASH_DUMP 1868 bool "Build kdump crash kernel (EXPERIMENTAL)" 1869 help 1870 Generate crash dump after being started by kexec. This should 1871 be normally only set in special crash dump kernels which are 1872 loaded in the main kernel with kexec-tools into a specially 1873 reserved region and then later executed after a crash by 1874 kdump/kexec. The crash dump kernel must be compiled to a 1875 memory address not used by the main kernel 1876 1877 For more details see Documentation/admin-guide/kdump/kdump.rst 1878 1879config AUTO_ZRELADDR 1880 bool "Auto calculation of the decompressed kernel image address" 1881 help 1882 ZRELADDR is the physical address where the decompressed kernel 1883 image will be placed. If AUTO_ZRELADDR is selected, the address 1884 will be determined at run-time by masking the current IP with 1885 0xf8000000. This assumes the zImage being placed in the first 128MB 1886 from start of memory. 1887 1888config EFI_STUB 1889 bool 1890 1891config EFI 1892 bool "UEFI runtime support" 1893 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1894 select UCS2_STRING 1895 select EFI_PARAMS_FROM_FDT 1896 select EFI_STUB 1897 select EFI_GENERIC_STUB 1898 select EFI_RUNTIME_WRAPPERS 1899 help 1900 This option provides support for runtime services provided 1901 by UEFI firmware (such as non-volatile variables, realtime 1902 clock, and platform reset). A UEFI stub is also provided to 1903 allow the kernel to be booted as an EFI application. This 1904 is only useful for kernels that may run on systems that have 1905 UEFI firmware. 1906 1907config DMI 1908 bool "Enable support for SMBIOS (DMI) tables" 1909 depends on EFI 1910 default y 1911 help 1912 This enables SMBIOS/DMI feature for systems. 1913 1914 This option is only useful on systems that have UEFI firmware. 1915 However, even with this option, the resultant kernel should 1916 continue to boot on existing non-UEFI platforms. 1917 1918 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1919 i.e., the the practice of identifying the platform via DMI to 1920 decide whether certain workarounds for buggy hardware and/or 1921 firmware need to be enabled. This would require the DMI subsystem 1922 to be enabled much earlier than we do on ARM, which is non-trivial. 1923 1924endmenu 1925 1926menu "CPU Power Management" 1927 1928source "drivers/cpufreq/Kconfig" 1929 1930source "drivers/cpuidle/Kconfig" 1931 1932endmenu 1933 1934menu "Floating point emulation" 1935 1936comment "At least one emulation must be selected" 1937 1938config FPE_NWFPE 1939 bool "NWFPE math emulation" 1940 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1941 help 1942 Say Y to include the NWFPE floating point emulator in the kernel. 1943 This is necessary to run most binaries. Linux does not currently 1944 support floating point hardware so you need to say Y here even if 1945 your machine has an FPA or floating point co-processor podule. 1946 1947 You may say N here if you are going to load the Acorn FPEmulator 1948 early in the bootup. 1949 1950config FPE_NWFPE_XP 1951 bool "Support extended precision" 1952 depends on FPE_NWFPE 1953 help 1954 Say Y to include 80-bit support in the kernel floating-point 1955 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1956 Note that gcc does not generate 80-bit operations by default, 1957 so in most cases this option only enlarges the size of the 1958 floating point emulator without any good reason. 1959 1960 You almost surely want to say N here. 1961 1962config FPE_FASTFPE 1963 bool "FastFPE math emulation (EXPERIMENTAL)" 1964 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1965 help 1966 Say Y here to include the FAST floating point emulator in the kernel. 1967 This is an experimental much faster emulator which now also has full 1968 precision for the mantissa. It does not support any exceptions. 1969 It is very simple, and approximately 3-6 times faster than NWFPE. 1970 1971 It should be sufficient for most programs. It may be not suitable 1972 for scientific calculations, but you have to check this for yourself. 1973 If you do not feel you need a faster FP emulation you should better 1974 choose NWFPE. 1975 1976config VFP 1977 bool "VFP-format floating point maths" 1978 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1979 help 1980 Say Y to include VFP support code in the kernel. This is needed 1981 if your hardware includes a VFP unit. 1982 1983 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1984 release notes and additional status information. 1985 1986 Say N if your target does not have VFP hardware. 1987 1988config VFPv3 1989 bool 1990 depends on VFP 1991 default y if CPU_V7 1992 1993config NEON 1994 bool "Advanced SIMD (NEON) Extension support" 1995 depends on VFPv3 && CPU_V7 1996 help 1997 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1998 Extension. 1999 2000config KERNEL_MODE_NEON 2001 bool "Support for NEON in kernel mode" 2002 depends on NEON && AEABI 2003 help 2004 Say Y to include support for NEON in kernel mode. 2005 2006endmenu 2007 2008menu "Power management options" 2009 2010source "kernel/power/Kconfig" 2011 2012config ARCH_SUSPEND_POSSIBLE 2013 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2014 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2015 def_bool y 2016 2017config ARM_CPU_SUSPEND 2018 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2019 depends on ARCH_SUSPEND_POSSIBLE 2020 2021config ARCH_HIBERNATION_POSSIBLE 2022 bool 2023 depends on MMU 2024 default y if ARCH_SUSPEND_POSSIBLE 2025 2026endmenu 2027 2028source "drivers/firmware/Kconfig" 2029 2030if CRYPTO 2031source "arch/arm/crypto/Kconfig" 2032endif 2033 2034source "arch/arm/Kconfig.assembler" 2035