1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_ELF_RANDOMIZE 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_HAVE_CUSTOM_GPIO_H 8 select ARCH_HAS_GCOV_PROFILE_ALL 9 select ARCH_MIGHT_HAVE_PC_PARPORT 10 select ARCH_SUPPORTS_ATOMIC_RMW 11 select ARCH_USE_BUILTIN_BSWAP 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_EXTABLE_SORT if MMU 15 select CLONE_BACKWARDS 16 select CPU_PM if (SUSPEND || CPU_IDLE) 17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 18 select EDAC_SUPPORT 19 select EDAC_ATOMIC_SCRUB 20 select GENERIC_ALLOCATOR 21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 23 select GENERIC_IDLE_POLL_SETUP 24 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW_LEVEL 27 select GENERIC_PCI_IOMAP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select HANDLE_DOMAIN_IRQ 33 select HARDIRQS_SW_RESEND 34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 39 select HAVE_ARCH_TRACEHOOK 40 select HAVE_BPF_JIT 41 select HAVE_CC_STACKPROTECTOR 42 select HAVE_CONTEXT_TRACKING 43 select HAVE_C_RECORDMCOUNT 44 select HAVE_DEBUG_KMEMLEAK 45 select HAVE_DMA_API_DEBUG 46 select HAVE_DMA_ATTRS 47 select HAVE_DMA_CONTIGUOUS if MMU 48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 53 select HAVE_GENERIC_DMA_COHERENT 54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 55 select HAVE_IDE if PCI || ISA || PCMCIA 56 select HAVE_IRQ_TIME_ACCOUNTING 57 select HAVE_KERNEL_GZIP 58 select HAVE_KERNEL_LZ4 59 select HAVE_KERNEL_LZMA 60 select HAVE_KERNEL_LZO 61 select HAVE_KERNEL_XZ 62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 63 select HAVE_KRETPROBES if (HAVE_KPROBES) 64 select HAVE_MEMBLOCK 65 select HAVE_MOD_ARCH_SPECIFIC 66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 67 select HAVE_OPTPROBES if !THUMB2_KERNEL 68 select HAVE_PERF_EVENTS 69 select HAVE_PERF_REGS 70 select HAVE_PERF_USER_STACK_DUMP 71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 72 select HAVE_REGS_AND_STACK_ACCESS_API 73 select HAVE_SYSCALL_TRACEPOINTS 74 select HAVE_UID16 75 select HAVE_VIRT_CPU_ACCOUNTING_GEN 76 select IRQ_FORCED_THREADING 77 select MODULES_USE_ELF_REL 78 select NO_BOOTMEM 79 select OLD_SIGACTION 80 select OLD_SIGSUSPEND3 81 select PERF_USE_VMALLOC 82 select RTC_LIB 83 select SYS_SUPPORTS_APM_EMULATION 84 # Above selects are sorted alphabetically; please add new ones 85 # according to that. Thanks. 86 help 87 The ARM series is a line of low-power-consumption RISC chip designs 88 licensed by ARM Ltd and targeted at embedded applications and 89 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 90 manufactured, but legacy ARM-based PC hardware remains popular in 91 Europe. There is an ARM Linux project with a web page at 92 <http://www.arm.linux.org.uk/>. 93 94config ARM_HAS_SG_CHAIN 95 select ARCH_HAS_SG_CHAIN 96 bool 97 98config NEED_SG_DMA_LENGTH 99 bool 100 101config ARM_DMA_USE_IOMMU 102 bool 103 select ARM_HAS_SG_CHAIN 104 select NEED_SG_DMA_LENGTH 105 106if ARM_DMA_USE_IOMMU 107 108config ARM_DMA_IOMMU_ALIGNMENT 109 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 110 range 4 9 111 default 8 112 help 113 DMA mapping framework by default aligns all buffers to the smallest 114 PAGE_SIZE order which is greater than or equal to the requested buffer 115 size. This works well for buffers up to a few hundreds kilobytes, but 116 for larger buffers it just a waste of address space. Drivers which has 117 relatively small addressing window (like 64Mib) might run out of 118 virtual space with just a few allocations. 119 120 With this parameter you can specify the maximum PAGE_SIZE order for 121 DMA IOMMU buffers. Larger buffers will be aligned only to this 122 specified order. The order is expressed as a power of two multiplied 123 by the PAGE_SIZE. 124 125endif 126 127config MIGHT_HAVE_PCI 128 bool 129 130config SYS_SUPPORTS_APM_EMULATION 131 bool 132 133config HAVE_TCM 134 bool 135 select GENERIC_ALLOCATOR 136 137config HAVE_PROC_CPU 138 bool 139 140config NO_IOPORT_MAP 141 bool 142 143config EISA 144 bool 145 ---help--- 146 The Extended Industry Standard Architecture (EISA) bus was 147 developed as an open alternative to the IBM MicroChannel bus. 148 149 The EISA bus provided some of the features of the IBM MicroChannel 150 bus while maintaining backward compatibility with cards made for 151 the older ISA bus. The EISA bus saw limited use between 1988 and 152 1995 when it was made obsolete by the PCI bus. 153 154 Say Y here if you are building a kernel for an EISA-based machine. 155 156 Otherwise, say N. 157 158config SBUS 159 bool 160 161config STACKTRACE_SUPPORT 162 bool 163 default y 164 165config HAVE_LATENCYTOP_SUPPORT 166 bool 167 depends on !SMP 168 default y 169 170config LOCKDEP_SUPPORT 171 bool 172 default y 173 174config TRACE_IRQFLAGS_SUPPORT 175 bool 176 default !CPU_V7M 177 178config RWSEM_XCHGADD_ALGORITHM 179 bool 180 default y 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config NEED_DMA_MAP_STATE 209 def_bool y 210 211config ARCH_SUPPORTS_UPROBES 212 def_bool y 213 214config ARCH_HAS_DMA_SET_COHERENT_MASK 215 bool 216 217config GENERIC_ISA_DMA 218 bool 219 220config FIQ 221 bool 222 223config NEED_RET_TO_USER 224 bool 225 226config ARCH_MTD_XIP 227 bool 228 229config VECTORS_BASE 230 hex 231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 232 default DRAM_BASE if REMAP_VECTORS_TO_RAM 233 default 0x00000000 234 help 235 The base address of exception vectors. This must be two pages 236 in size. 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 depends on !ARCH_REALVIEW || !SPARSEMEM 243 help 244 Patch phys-to-virt and virt-to-phys translation functions at 245 boot and module load time according to the position of the 246 kernel in system memory. 247 248 This can only be used with non-XIP MMU kernels where the base 249 of physical memory is at a 16MB boundary. 250 251 Only disable this option if you know that you do not require 252 this feature (eg, building a kernel for a single machine) and 253 you need to shrink the kernel to the minimal size. 254 255config NEED_MACH_IO_H 256 bool 257 help 258 Select this when mach/io.h is required to provide special 259 definitions for this platform. The need for mach/io.h should 260 be avoided when possible. 261 262config NEED_MACH_MEMORY_H 263 bool 264 help 265 Select this when mach/memory.h is required to provide special 266 definitions for this platform. The need for mach/memory.h should 267 be avoided when possible. 268 269config PHYS_OFFSET 270 hex "Physical address of main memory" if MMU 271 depends on !ARM_PATCH_PHYS_VIRT 272 default DRAM_BASE if !MMU 273 default 0x00000000 if ARCH_EBSA110 || \ 274 ARCH_FOOTBRIDGE || \ 275 ARCH_INTEGRATOR || \ 276 ARCH_IOP13XX || \ 277 ARCH_KS8695 || \ 278 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 279 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 280 default 0x20000000 if ARCH_S5PV210 281 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 282 default 0xc0000000 if ARCH_SA1100 283 help 284 Please provide the physical address corresponding to the 285 location of main memory in your system. 286 287config GENERIC_BUG 288 def_bool y 289 depends on BUG 290 291config PGTABLE_LEVELS 292 int 293 default 3 if ARM_LPAE 294 default 2 295 296source "init/Kconfig" 297 298source "kernel/Kconfig.freezer" 299 300menu "System Type" 301 302config MMU 303 bool "MMU-based Paged Memory Management Support" 304 default y 305 help 306 Select if you want MMU-based virtualised addressing space 307 support by paged memory management. If unsure, say 'Y'. 308 309# 310# The "ARM system type" choice list is ordered alphabetically by option 311# text. Please add new entries in the option alphabetic order. 312# 313choice 314 prompt "ARM system type" 315 default ARCH_VERSATILE if !MMU 316 default ARCH_MULTIPLATFORM if MMU 317 318config ARCH_MULTIPLATFORM 319 bool "Allow multiple platforms to be selected" 320 depends on MMU 321 select ARCH_WANT_OPTIONAL_GPIOLIB 322 select ARM_HAS_SG_CHAIN 323 select ARM_PATCH_PHYS_VIRT 324 select AUTO_ZRELADDR 325 select CLKSRC_OF 326 select COMMON_CLK 327 select GENERIC_CLOCKEVENTS 328 select MIGHT_HAVE_PCI 329 select MULTI_IRQ_HANDLER 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARCH_WANT_OPTIONAL_GPIOLIB 337 select ARM_NVIC 338 select AUTO_ZRELADDR 339 select CLKSRC_OF 340 select COMMON_CLK 341 select CPU_V7M 342 select GENERIC_CLOCKEVENTS 343 select NO_IOPORT_MAP 344 select SPARSE_IRQ 345 select USE_OF 346 347config ARCH_REALVIEW 348 bool "ARM Ltd. RealView family" 349 select ARCH_WANT_OPTIONAL_GPIOLIB 350 select ARM_AMBA 351 select ARM_TIMER_SP804 352 select COMMON_CLK 353 select COMMON_CLK_VERSATILE 354 select GENERIC_CLOCKEVENTS 355 select GPIO_PL061 if GPIOLIB 356 select ICST 357 select NEED_MACH_MEMORY_H 358 select PLAT_VERSATILE 359 select PLAT_VERSATILE_SCHED_CLOCK 360 help 361 This enables support for ARM Ltd RealView boards. 362 363config ARCH_VERSATILE 364 bool "ARM Ltd. Versatile family" 365 select ARCH_WANT_OPTIONAL_GPIOLIB 366 select ARM_AMBA 367 select ARM_TIMER_SP804 368 select ARM_VIC 369 select CLKDEV_LOOKUP 370 select GENERIC_CLOCKEVENTS 371 select HAVE_MACH_CLKDEV 372 select ICST 373 select PLAT_VERSATILE 374 select PLAT_VERSATILE_CLOCK 375 select PLAT_VERSATILE_SCHED_CLOCK 376 select VERSATILE_FPGA_IRQ 377 help 378 This enables support for ARM Ltd Versatile board. 379 380config ARCH_CLPS711X 381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 382 select ARCH_REQUIRE_GPIOLIB 383 select AUTO_ZRELADDR 384 select CLKSRC_MMIO 385 select COMMON_CLK 386 select CPU_ARM720T 387 select GENERIC_CLOCKEVENTS 388 select MFD_SYSCON 389 select SOC_BUS 390 help 391 Support for Cirrus Logic 711x/721x/731x based boards. 392 393config ARCH_GEMINI 394 bool "Cortina Systems Gemini" 395 select ARCH_REQUIRE_GPIOLIB 396 select CLKSRC_MMIO 397 select CPU_FA526 398 select GENERIC_CLOCKEVENTS 399 help 400 Support for the Cortina Systems Gemini family SoCs 401 402config ARCH_EBSA110 403 bool "EBSA-110" 404 select ARCH_USES_GETTIMEOFFSET 405 select CPU_SA110 406 select ISA 407 select NEED_MACH_IO_H 408 select NEED_MACH_MEMORY_H 409 select NO_IOPORT_MAP 410 help 411 This is an evaluation board for the StrongARM processor available 412 from Digital. It has limited hardware on-board, including an 413 Ethernet interface, two PCMCIA sockets, two serial ports and a 414 parallel port. 415 416config ARCH_EP93XX 417 bool "EP93xx-based" 418 select ARCH_HAS_HOLES_MEMORYMODEL 419 select ARCH_REQUIRE_GPIOLIB 420 select ARM_AMBA 421 select ARM_PATCH_PHYS_VIRT 422 select ARM_VIC 423 select AUTO_ZRELADDR 424 select CLKDEV_LOOKUP 425 select CLKSRC_MMIO 426 select CPU_ARM920T 427 select GENERIC_CLOCKEVENTS 428 help 429 This enables support for the Cirrus EP93xx series of CPUs. 430 431config ARCH_FOOTBRIDGE 432 bool "FootBridge" 433 select CPU_SA110 434 select FOOTBRIDGE 435 select GENERIC_CLOCKEVENTS 436 select HAVE_IDE 437 select NEED_MACH_IO_H if !MMU 438 select NEED_MACH_MEMORY_H 439 help 440 Support for systems based on the DC21285 companion chip 441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 442 443config ARCH_NETX 444 bool "Hilscher NetX based" 445 select ARM_VIC 446 select CLKSRC_MMIO 447 select CPU_ARM926T 448 select GENERIC_CLOCKEVENTS 449 help 450 This enables support for systems based on the Hilscher NetX Soc 451 452config ARCH_IOP13XX 453 bool "IOP13xx-based" 454 depends on MMU 455 select CPU_XSC3 456 select NEED_MACH_MEMORY_H 457 select NEED_RET_TO_USER 458 select PCI 459 select PLAT_IOP 460 select VMSPLIT_1G 461 select SPARSE_IRQ 462 help 463 Support for Intel's IOP13XX (XScale) family of processors. 464 465config ARCH_IOP32X 466 bool "IOP32x-based" 467 depends on MMU 468 select ARCH_REQUIRE_GPIOLIB 469 select CPU_XSCALE 470 select GPIO_IOP 471 select NEED_RET_TO_USER 472 select PCI 473 select PLAT_IOP 474 help 475 Support for Intel's 80219 and IOP32X (XScale) family of 476 processors. 477 478config ARCH_IOP33X 479 bool "IOP33x-based" 480 depends on MMU 481 select ARCH_REQUIRE_GPIOLIB 482 select CPU_XSCALE 483 select GPIO_IOP 484 select NEED_RET_TO_USER 485 select PCI 486 select PLAT_IOP 487 help 488 Support for Intel's IOP33X (XScale) family of processors. 489 490config ARCH_IXP4XX 491 bool "IXP4xx-based" 492 depends on MMU 493 select ARCH_HAS_DMA_SET_COHERENT_MASK 494 select ARCH_REQUIRE_GPIOLIB 495 select ARCH_SUPPORTS_BIG_ENDIAN 496 select CLKSRC_MMIO 497 select CPU_XSCALE 498 select DMABOUNCE if PCI 499 select GENERIC_CLOCKEVENTS 500 select MIGHT_HAVE_PCI 501 select NEED_MACH_IO_H 502 select USB_EHCI_BIG_ENDIAN_DESC 503 select USB_EHCI_BIG_ENDIAN_MMIO 504 help 505 Support for Intel's IXP4XX (XScale) family of processors. 506 507config ARCH_DOVE 508 bool "Marvell Dove" 509 select ARCH_REQUIRE_GPIOLIB 510 select CPU_PJ4 511 select GENERIC_CLOCKEVENTS 512 select MIGHT_HAVE_PCI 513 select MULTI_IRQ_HANDLER 514 select MVEBU_MBUS 515 select PINCTRL 516 select PINCTRL_DOVE 517 select PLAT_ORION_LEGACY 518 select SPARSE_IRQ 519 help 520 Support for the Marvell Dove SoC 88AP510 521 522config ARCH_MMP 523 bool "Marvell PXA168/910/MMP2" 524 depends on MMU 525 select ARCH_REQUIRE_GPIOLIB 526 select CLKDEV_LOOKUP 527 select GENERIC_ALLOCATOR 528 select GENERIC_CLOCKEVENTS 529 select GPIO_PXA 530 select IRQ_DOMAIN 531 select MULTI_IRQ_HANDLER 532 select PINCTRL 533 select PLAT_PXA 534 select SPARSE_IRQ 535 help 536 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 537 538config ARCH_KS8695 539 bool "Micrel/Kendin KS8695" 540 select ARCH_REQUIRE_GPIOLIB 541 select CLKSRC_MMIO 542 select CPU_ARM922T 543 select GENERIC_CLOCKEVENTS 544 select NEED_MACH_MEMORY_H 545 help 546 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 547 System-on-Chip devices. 548 549config ARCH_W90X900 550 bool "Nuvoton W90X900 CPU" 551 select ARCH_REQUIRE_GPIOLIB 552 select CLKDEV_LOOKUP 553 select CLKSRC_MMIO 554 select CPU_ARM926T 555 select GENERIC_CLOCKEVENTS 556 help 557 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 558 At present, the w90x900 has been renamed nuc900, regarding 559 the ARM series product line, you can login the following 560 link address to know more. 561 562 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 563 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 564 565config ARCH_LPC32XX 566 bool "NXP LPC32XX" 567 select ARCH_REQUIRE_GPIOLIB 568 select ARM_AMBA 569 select CLKDEV_LOOKUP 570 select CLKSRC_MMIO 571 select CPU_ARM926T 572 select GENERIC_CLOCKEVENTS 573 select HAVE_IDE 574 select USE_OF 575 help 576 Support for the NXP LPC32XX family of processors 577 578config ARCH_PXA 579 bool "PXA2xx/PXA3xx-based" 580 depends on MMU 581 select ARCH_MTD_XIP 582 select ARCH_REQUIRE_GPIOLIB 583 select ARM_CPU_SUSPEND if PM 584 select AUTO_ZRELADDR 585 select COMMON_CLK 586 select CLKDEV_LOOKUP 587 select CLKSRC_MMIO 588 select CLKSRC_OF 589 select GENERIC_CLOCKEVENTS 590 select GPIO_PXA 591 select HAVE_IDE 592 select IRQ_DOMAIN 593 select MULTI_IRQ_HANDLER 594 select PLAT_PXA 595 select SPARSE_IRQ 596 help 597 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 598 599config ARCH_RPC 600 bool "RiscPC" 601 depends on MMU 602 select ARCH_ACORN 603 select ARCH_MAY_HAVE_PC_FDC 604 select ARCH_SPARSEMEM_ENABLE 605 select ARCH_USES_GETTIMEOFFSET 606 select CPU_SA110 607 select FIQ 608 select HAVE_IDE 609 select HAVE_PATA_PLATFORM 610 select ISA_DMA_API 611 select NEED_MACH_IO_H 612 select NEED_MACH_MEMORY_H 613 select NO_IOPORT_MAP 614 select VIRT_TO_BUS 615 help 616 On the Acorn Risc-PC, Linux can support the internal IDE disk and 617 CD-ROM interface, serial and parallel port, and the floppy drive. 618 619config ARCH_SA1100 620 bool "SA1100-based" 621 select ARCH_MTD_XIP 622 select ARCH_REQUIRE_GPIOLIB 623 select ARCH_SPARSEMEM_ENABLE 624 select CLKDEV_LOOKUP 625 select CLKSRC_MMIO 626 select CPU_FREQ 627 select CPU_SA1100 628 select GENERIC_CLOCKEVENTS 629 select HAVE_IDE 630 select IRQ_DOMAIN 631 select ISA 632 select MULTI_IRQ_HANDLER 633 select NEED_MACH_MEMORY_H 634 select SPARSE_IRQ 635 help 636 Support for StrongARM 11x0 based boards. 637 638config ARCH_S3C24XX 639 bool "Samsung S3C24XX SoCs" 640 select ARCH_REQUIRE_GPIOLIB 641 select ATAGS 642 select CLKDEV_LOOKUP 643 select CLKSRC_SAMSUNG_PWM 644 select GENERIC_CLOCKEVENTS 645 select GPIO_SAMSUNG 646 select HAVE_S3C2410_I2C if I2C 647 select HAVE_S3C2410_WATCHDOG if WATCHDOG 648 select HAVE_S3C_RTC if RTC_CLASS 649 select MULTI_IRQ_HANDLER 650 select NEED_MACH_IO_H 651 select SAMSUNG_ATAGS 652 help 653 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 654 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 655 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 656 Samsung SMDK2410 development board (and derivatives). 657 658config ARCH_S3C64XX 659 bool "Samsung S3C64XX" 660 select ARCH_REQUIRE_GPIOLIB 661 select ARM_AMBA 662 select ARM_VIC 663 select ATAGS 664 select CLKDEV_LOOKUP 665 select CLKSRC_SAMSUNG_PWM 666 select COMMON_CLK_SAMSUNG 667 select CPU_V6K 668 select GENERIC_CLOCKEVENTS 669 select GPIO_SAMSUNG 670 select HAVE_S3C2410_I2C if I2C 671 select HAVE_S3C2410_WATCHDOG if WATCHDOG 672 select HAVE_TCM 673 select NO_IOPORT_MAP 674 select PLAT_SAMSUNG 675 select PM_GENERIC_DOMAINS if PM 676 select S3C_DEV_NAND 677 select S3C_GPIO_TRACK 678 select SAMSUNG_ATAGS 679 select SAMSUNG_WAKEMASK 680 select SAMSUNG_WDT_RESET 681 help 682 Samsung S3C64XX series based systems 683 684config ARCH_DAVINCI 685 bool "TI DaVinci" 686 select ARCH_HAS_HOLES_MEMORYMODEL 687 select ARCH_REQUIRE_GPIOLIB 688 select CLKDEV_LOOKUP 689 select GENERIC_ALLOCATOR 690 select GENERIC_CLOCKEVENTS 691 select GENERIC_IRQ_CHIP 692 select HAVE_IDE 693 select USE_OF 694 select ZONE_DMA 695 help 696 Support for TI's DaVinci platform. 697 698config ARCH_OMAP1 699 bool "TI OMAP1" 700 depends on MMU 701 select ARCH_HAS_HOLES_MEMORYMODEL 702 select ARCH_OMAP 703 select ARCH_REQUIRE_GPIOLIB 704 select CLKDEV_LOOKUP 705 select CLKSRC_MMIO 706 select GENERIC_CLOCKEVENTS 707 select GENERIC_IRQ_CHIP 708 select HAVE_IDE 709 select IRQ_DOMAIN 710 select MULTI_IRQ_HANDLER 711 select NEED_MACH_IO_H if PCCARD 712 select NEED_MACH_MEMORY_H 713 select SPARSE_IRQ 714 help 715 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 716 717endchoice 718 719menu "Multiple platform selection" 720 depends on ARCH_MULTIPLATFORM 721 722comment "CPU Core family selection" 723 724config ARCH_MULTI_V4 725 bool "ARMv4 based platforms (FA526)" 726 depends on !ARCH_MULTI_V6_V7 727 select ARCH_MULTI_V4_V5 728 select CPU_FA526 729 730config ARCH_MULTI_V4T 731 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 732 depends on !ARCH_MULTI_V6_V7 733 select ARCH_MULTI_V4_V5 734 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 735 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 736 CPU_ARM925T || CPU_ARM940T) 737 738config ARCH_MULTI_V5 739 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 740 depends on !ARCH_MULTI_V6_V7 741 select ARCH_MULTI_V4_V5 742 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 743 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 744 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 745 746config ARCH_MULTI_V4_V5 747 bool 748 749config ARCH_MULTI_V6 750 bool "ARMv6 based platforms (ARM11)" 751 select ARCH_MULTI_V6_V7 752 select CPU_V6K 753 754config ARCH_MULTI_V7 755 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 756 default y 757 select ARCH_MULTI_V6_V7 758 select CPU_V7 759 select HAVE_SMP 760 761config ARCH_MULTI_V6_V7 762 bool 763 select MIGHT_HAVE_CACHE_L2X0 764 765config ARCH_MULTI_CPU_AUTO 766 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 767 select ARCH_MULTI_V5 768 769endmenu 770 771config ARCH_VIRT 772 bool "Dummy Virtual Machine" if ARCH_MULTI_V7 773 select ARM_AMBA 774 select ARM_GIC 775 select ARM_GIC_V3 776 select ARM_PSCI 777 select HAVE_ARM_ARCH_TIMER 778 779# 780# This is sorted alphabetically by mach-* pathname. However, plat-* 781# Kconfigs may be included either alphabetically (according to the 782# plat- suffix) or along side the corresponding mach-* source. 783# 784source "arch/arm/mach-mvebu/Kconfig" 785 786source "arch/arm/mach-alpine/Kconfig" 787 788source "arch/arm/mach-asm9260/Kconfig" 789 790source "arch/arm/mach-at91/Kconfig" 791 792source "arch/arm/mach-axxia/Kconfig" 793 794source "arch/arm/mach-bcm/Kconfig" 795 796source "arch/arm/mach-berlin/Kconfig" 797 798source "arch/arm/mach-clps711x/Kconfig" 799 800source "arch/arm/mach-cns3xxx/Kconfig" 801 802source "arch/arm/mach-davinci/Kconfig" 803 804source "arch/arm/mach-digicolor/Kconfig" 805 806source "arch/arm/mach-dove/Kconfig" 807 808source "arch/arm/mach-ep93xx/Kconfig" 809 810source "arch/arm/mach-footbridge/Kconfig" 811 812source "arch/arm/mach-gemini/Kconfig" 813 814source "arch/arm/mach-highbank/Kconfig" 815 816source "arch/arm/mach-hisi/Kconfig" 817 818source "arch/arm/mach-integrator/Kconfig" 819 820source "arch/arm/mach-iop32x/Kconfig" 821 822source "arch/arm/mach-iop33x/Kconfig" 823 824source "arch/arm/mach-iop13xx/Kconfig" 825 826source "arch/arm/mach-ixp4xx/Kconfig" 827 828source "arch/arm/mach-keystone/Kconfig" 829 830source "arch/arm/mach-ks8695/Kconfig" 831 832source "arch/arm/mach-meson/Kconfig" 833 834source "arch/arm/mach-moxart/Kconfig" 835 836source "arch/arm/mach-mv78xx0/Kconfig" 837 838source "arch/arm/mach-imx/Kconfig" 839 840source "arch/arm/mach-mediatek/Kconfig" 841 842source "arch/arm/mach-mxs/Kconfig" 843 844source "arch/arm/mach-netx/Kconfig" 845 846source "arch/arm/mach-nomadik/Kconfig" 847 848source "arch/arm/mach-nspire/Kconfig" 849 850source "arch/arm/plat-omap/Kconfig" 851 852source "arch/arm/mach-omap1/Kconfig" 853 854source "arch/arm/mach-omap2/Kconfig" 855 856source "arch/arm/mach-orion5x/Kconfig" 857 858source "arch/arm/mach-picoxcell/Kconfig" 859 860source "arch/arm/mach-pxa/Kconfig" 861source "arch/arm/plat-pxa/Kconfig" 862 863source "arch/arm/mach-mmp/Kconfig" 864 865source "arch/arm/mach-qcom/Kconfig" 866 867source "arch/arm/mach-realview/Kconfig" 868 869source "arch/arm/mach-rockchip/Kconfig" 870 871source "arch/arm/mach-sa1100/Kconfig" 872 873source "arch/arm/mach-socfpga/Kconfig" 874 875source "arch/arm/mach-spear/Kconfig" 876 877source "arch/arm/mach-sti/Kconfig" 878 879source "arch/arm/mach-s3c24xx/Kconfig" 880 881source "arch/arm/mach-s3c64xx/Kconfig" 882 883source "arch/arm/mach-s5pv210/Kconfig" 884 885source "arch/arm/mach-exynos/Kconfig" 886source "arch/arm/plat-samsung/Kconfig" 887 888source "arch/arm/mach-shmobile/Kconfig" 889 890source "arch/arm/mach-sunxi/Kconfig" 891 892source "arch/arm/mach-prima2/Kconfig" 893 894source "arch/arm/mach-tegra/Kconfig" 895 896source "arch/arm/mach-u300/Kconfig" 897 898source "arch/arm/mach-uniphier/Kconfig" 899 900source "arch/arm/mach-ux500/Kconfig" 901 902source "arch/arm/mach-versatile/Kconfig" 903 904source "arch/arm/mach-vexpress/Kconfig" 905source "arch/arm/plat-versatile/Kconfig" 906 907source "arch/arm/mach-vt8500/Kconfig" 908 909source "arch/arm/mach-w90x900/Kconfig" 910 911source "arch/arm/mach-zx/Kconfig" 912 913source "arch/arm/mach-zynq/Kconfig" 914 915# ARMv7-M architecture 916config ARCH_EFM32 917 bool "Energy Micro efm32" 918 depends on ARM_SINGLE_ARMV7M 919 select ARCH_REQUIRE_GPIOLIB 920 help 921 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 922 processors. 923 924config ARCH_LPC18XX 925 bool "NXP LPC18xx/LPC43xx" 926 depends on ARM_SINGLE_ARMV7M 927 select ARCH_HAS_RESET_CONTROLLER 928 select ARM_AMBA 929 select CLKSRC_LPC32XX 930 select PINCTRL 931 help 932 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 933 high performance microcontrollers. 934 935config ARCH_STM32 936 bool "STMicrolectronics STM32" 937 depends on ARM_SINGLE_ARMV7M 938 select ARCH_HAS_RESET_CONTROLLER 939 select ARMV7M_SYSTICK 940 select CLKSRC_STM32 941 select RESET_CONTROLLER 942 help 943 Support for STMicroelectronics STM32 processors. 944 945# Definitions to make life easier 946config ARCH_ACORN 947 bool 948 949config PLAT_IOP 950 bool 951 select GENERIC_CLOCKEVENTS 952 953config PLAT_ORION 954 bool 955 select CLKSRC_MMIO 956 select COMMON_CLK 957 select GENERIC_IRQ_CHIP 958 select IRQ_DOMAIN 959 960config PLAT_ORION_LEGACY 961 bool 962 select PLAT_ORION 963 964config PLAT_PXA 965 bool 966 967config PLAT_VERSATILE 968 bool 969 970source "arch/arm/firmware/Kconfig" 971 972source arch/arm/mm/Kconfig 973 974config IWMMXT 975 bool "Enable iWMMXt support" 976 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 977 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 978 help 979 Enable support for iWMMXt context switching at run time if 980 running on a CPU that supports it. 981 982config MULTI_IRQ_HANDLER 983 bool 984 help 985 Allow each machine to specify it's own IRQ handler at run time. 986 987if !MMU 988source "arch/arm/Kconfig-nommu" 989endif 990 991config PJ4B_ERRATA_4742 992 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 993 depends on CPU_PJ4B && MACH_ARMADA_370 994 default y 995 help 996 When coming out of either a Wait for Interrupt (WFI) or a Wait for 997 Event (WFE) IDLE states, a specific timing sensitivity exists between 998 the retiring WFI/WFE instructions and the newly issued subsequent 999 instructions. This sensitivity can result in a CPU hang scenario. 1000 Workaround: 1001 The software must insert either a Data Synchronization Barrier (DSB) 1002 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 1003 instruction 1004 1005config ARM_ERRATA_326103 1006 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1007 depends on CPU_V6 1008 help 1009 Executing a SWP instruction to read-only memory does not set bit 11 1010 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1011 treat the access as a read, preventing a COW from occurring and 1012 causing the faulting task to livelock. 1013 1014config ARM_ERRATA_411920 1015 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1016 depends on CPU_V6 || CPU_V6K 1017 help 1018 Invalidation of the Instruction Cache operation can 1019 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1020 It does not affect the MPCore. This option enables the ARM Ltd. 1021 recommended workaround. 1022 1023config ARM_ERRATA_430973 1024 bool "ARM errata: Stale prediction on replaced interworking branch" 1025 depends on CPU_V7 1026 help 1027 This option enables the workaround for the 430973 Cortex-A8 1028 r1p* erratum. If a code sequence containing an ARM/Thumb 1029 interworking branch is replaced with another code sequence at the 1030 same virtual address, whether due to self-modifying code or virtual 1031 to physical address re-mapping, Cortex-A8 does not recover from the 1032 stale interworking branch prediction. This results in Cortex-A8 1033 executing the new code sequence in the incorrect ARM or Thumb state. 1034 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1035 and also flushes the branch target cache at every context switch. 1036 Note that setting specific bits in the ACTLR register may not be 1037 available in non-secure mode. 1038 1039config ARM_ERRATA_458693 1040 bool "ARM errata: Processor deadlock when a false hazard is created" 1041 depends on CPU_V7 1042 depends on !ARCH_MULTIPLATFORM 1043 help 1044 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1045 erratum. For very specific sequences of memory operations, it is 1046 possible for a hazard condition intended for a cache line to instead 1047 be incorrectly associated with a different cache line. This false 1048 hazard might then cause a processor deadlock. The workaround enables 1049 the L1 caching of the NEON accesses and disables the PLD instruction 1050 in the ACTLR register. Note that setting specific bits in the ACTLR 1051 register may not be available in non-secure mode. 1052 1053config ARM_ERRATA_460075 1054 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1055 depends on CPU_V7 1056 depends on !ARCH_MULTIPLATFORM 1057 help 1058 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1059 erratum. Any asynchronous access to the L2 cache may encounter a 1060 situation in which recent store transactions to the L2 cache are lost 1061 and overwritten with stale memory contents from external memory. The 1062 workaround disables the write-allocate mode for the L2 cache via the 1063 ACTLR register. Note that setting specific bits in the ACTLR register 1064 may not be available in non-secure mode. 1065 1066config ARM_ERRATA_742230 1067 bool "ARM errata: DMB operation may be faulty" 1068 depends on CPU_V7 && SMP 1069 depends on !ARCH_MULTIPLATFORM 1070 help 1071 This option enables the workaround for the 742230 Cortex-A9 1072 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1073 between two write operations may not ensure the correct visibility 1074 ordering of the two writes. This workaround sets a specific bit in 1075 the diagnostic register of the Cortex-A9 which causes the DMB 1076 instruction to behave as a DSB, ensuring the correct behaviour of 1077 the two writes. 1078 1079config ARM_ERRATA_742231 1080 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1081 depends on CPU_V7 && SMP 1082 depends on !ARCH_MULTIPLATFORM 1083 help 1084 This option enables the workaround for the 742231 Cortex-A9 1085 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1086 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1087 accessing some data located in the same cache line, may get corrupted 1088 data due to bad handling of the address hazard when the line gets 1089 replaced from one of the CPUs at the same time as another CPU is 1090 accessing it. This workaround sets specific bits in the diagnostic 1091 register of the Cortex-A9 which reduces the linefill issuing 1092 capabilities of the processor. 1093 1094config ARM_ERRATA_643719 1095 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1096 depends on CPU_V7 && SMP 1097 default y 1098 help 1099 This option enables the workaround for the 643719 Cortex-A9 (prior to 1100 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1101 register returns zero when it should return one. The workaround 1102 corrects this value, ensuring cache maintenance operations which use 1103 it behave as intended and avoiding data corruption. 1104 1105config ARM_ERRATA_720789 1106 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1107 depends on CPU_V7 1108 help 1109 This option enables the workaround for the 720789 Cortex-A9 (prior to 1110 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1111 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1112 As a consequence of this erratum, some TLB entries which should be 1113 invalidated are not, resulting in an incoherency in the system page 1114 tables. The workaround changes the TLB flushing routines to invalidate 1115 entries regardless of the ASID. 1116 1117config ARM_ERRATA_743622 1118 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1119 depends on CPU_V7 1120 depends on !ARCH_MULTIPLATFORM 1121 help 1122 This option enables the workaround for the 743622 Cortex-A9 1123 (r2p*) erratum. Under very rare conditions, a faulty 1124 optimisation in the Cortex-A9 Store Buffer may lead to data 1125 corruption. This workaround sets a specific bit in the diagnostic 1126 register of the Cortex-A9 which disables the Store Buffer 1127 optimisation, preventing the defect from occurring. This has no 1128 visible impact on the overall performance or power consumption of the 1129 processor. 1130 1131config ARM_ERRATA_751472 1132 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1133 depends on CPU_V7 1134 depends on !ARCH_MULTIPLATFORM 1135 help 1136 This option enables the workaround for the 751472 Cortex-A9 (prior 1137 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1138 completion of a following broadcasted operation if the second 1139 operation is received by a CPU before the ICIALLUIS has completed, 1140 potentially leading to corrupted entries in the cache or TLB. 1141 1142config ARM_ERRATA_754322 1143 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1144 depends on CPU_V7 1145 help 1146 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1147 r3p*) erratum. A speculative memory access may cause a page table walk 1148 which starts prior to an ASID switch but completes afterwards. This 1149 can populate the micro-TLB with a stale entry which may be hit with 1150 the new ASID. This workaround places two dsb instructions in the mm 1151 switching code so that no page table walks can cross the ASID switch. 1152 1153config ARM_ERRATA_754327 1154 bool "ARM errata: no automatic Store Buffer drain" 1155 depends on CPU_V7 && SMP 1156 help 1157 This option enables the workaround for the 754327 Cortex-A9 (prior to 1158 r2p0) erratum. The Store Buffer does not have any automatic draining 1159 mechanism and therefore a livelock may occur if an external agent 1160 continuously polls a memory location waiting to observe an update. 1161 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1162 written polling loops from denying visibility of updates to memory. 1163 1164config ARM_ERRATA_364296 1165 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1166 depends on CPU_V6 1167 help 1168 This options enables the workaround for the 364296 ARM1136 1169 r0p2 erratum (possible cache data corruption with 1170 hit-under-miss enabled). It sets the undocumented bit 31 in 1171 the auxiliary control register and the FI bit in the control 1172 register, thus disabling hit-under-miss without putting the 1173 processor into full low interrupt latency mode. ARM11MPCore 1174 is not affected. 1175 1176config ARM_ERRATA_764369 1177 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1178 depends on CPU_V7 && SMP 1179 help 1180 This option enables the workaround for erratum 764369 1181 affecting Cortex-A9 MPCore with two or more processors (all 1182 current revisions). Under certain timing circumstances, a data 1183 cache line maintenance operation by MVA targeting an Inner 1184 Shareable memory region may fail to proceed up to either the 1185 Point of Coherency or to the Point of Unification of the 1186 system. This workaround adds a DSB instruction before the 1187 relevant cache maintenance functions and sets a specific bit 1188 in the diagnostic control register of the SCU. 1189 1190config ARM_ERRATA_775420 1191 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1192 depends on CPU_V7 1193 help 1194 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1195 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1196 operation aborts with MMU exception, it might cause the processor 1197 to deadlock. This workaround puts DSB before executing ISB if 1198 an abort may occur on cache maintenance. 1199 1200config ARM_ERRATA_798181 1201 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1202 depends on CPU_V7 && SMP 1203 help 1204 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1205 adequately shooting down all use of the old entries. This 1206 option enables the Linux kernel workaround for this erratum 1207 which sends an IPI to the CPUs that are running the same ASID 1208 as the one being invalidated. 1209 1210config ARM_ERRATA_773022 1211 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1212 depends on CPU_V7 1213 help 1214 This option enables the workaround for the 773022 Cortex-A15 1215 (up to r0p4) erratum. In certain rare sequences of code, the 1216 loop buffer may deliver incorrect instructions. This 1217 workaround disables the loop buffer to avoid the erratum. 1218 1219endmenu 1220 1221source "arch/arm/common/Kconfig" 1222 1223menu "Bus support" 1224 1225config ISA 1226 bool 1227 help 1228 Find out whether you have ISA slots on your motherboard. ISA is the 1229 name of a bus system, i.e. the way the CPU talks to the other stuff 1230 inside your box. Other bus systems are PCI, EISA, MicroChannel 1231 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1232 newer boards don't support it. If you have ISA, say Y, otherwise N. 1233 1234# Select ISA DMA controller support 1235config ISA_DMA 1236 bool 1237 select ISA_DMA_API 1238 1239# Select ISA DMA interface 1240config ISA_DMA_API 1241 bool 1242 1243config PCI 1244 bool "PCI support" if MIGHT_HAVE_PCI 1245 help 1246 Find out whether you have a PCI motherboard. PCI is the name of a 1247 bus system, i.e. the way the CPU talks to the other stuff inside 1248 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1249 VESA. If you have PCI, say Y, otherwise N. 1250 1251config PCI_DOMAINS 1252 bool 1253 depends on PCI 1254 1255config PCI_DOMAINS_GENERIC 1256 def_bool PCI_DOMAINS 1257 1258config PCI_NANOENGINE 1259 bool "BSE nanoEngine PCI support" 1260 depends on SA1100_NANOENGINE 1261 help 1262 Enable PCI on the BSE nanoEngine board. 1263 1264config PCI_SYSCALL 1265 def_bool PCI 1266 1267config PCI_HOST_ITE8152 1268 bool 1269 depends on PCI && MACH_ARMCORE 1270 default y 1271 select DMABOUNCE 1272 1273source "drivers/pci/Kconfig" 1274source "drivers/pci/pcie/Kconfig" 1275 1276source "drivers/pcmcia/Kconfig" 1277 1278endmenu 1279 1280menu "Kernel Features" 1281 1282config HAVE_SMP 1283 bool 1284 help 1285 This option should be selected by machines which have an SMP- 1286 capable CPU. 1287 1288 The only effect of this option is to make the SMP-related 1289 options available to the user for configuration. 1290 1291config SMP 1292 bool "Symmetric Multi-Processing" 1293 depends on CPU_V6K || CPU_V7 1294 depends on GENERIC_CLOCKEVENTS 1295 depends on HAVE_SMP 1296 depends on MMU || ARM_MPU 1297 select IRQ_WORK 1298 help 1299 This enables support for systems with more than one CPU. If you have 1300 a system with only one CPU, say N. If you have a system with more 1301 than one CPU, say Y. 1302 1303 If you say N here, the kernel will run on uni- and multiprocessor 1304 machines, but will use only one CPU of a multiprocessor machine. If 1305 you say Y here, the kernel will run on many, but not all, 1306 uniprocessor machines. On a uniprocessor machine, the kernel 1307 will run faster if you say N here. 1308 1309 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1310 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1311 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1312 1313 If you don't know what to do here, say N. 1314 1315config SMP_ON_UP 1316 bool "Allow booting SMP kernel on uniprocessor systems" 1317 depends on SMP && !XIP_KERNEL && MMU 1318 default y 1319 help 1320 SMP kernels contain instructions which fail on non-SMP processors. 1321 Enabling this option allows the kernel to modify itself to make 1322 these instructions safe. Disabling it allows about 1K of space 1323 savings. 1324 1325 If you don't know what to do here, say Y. 1326 1327config ARM_CPU_TOPOLOGY 1328 bool "Support cpu topology definition" 1329 depends on SMP && CPU_V7 1330 default y 1331 help 1332 Support ARM cpu topology definition. The MPIDR register defines 1333 affinity between processors which is then used to describe the cpu 1334 topology of an ARM System. 1335 1336config SCHED_MC 1337 bool "Multi-core scheduler support" 1338 depends on ARM_CPU_TOPOLOGY 1339 help 1340 Multi-core scheduler support improves the CPU scheduler's decision 1341 making when dealing with multi-core CPU chips at a cost of slightly 1342 increased overhead in some places. If unsure say N here. 1343 1344config SCHED_SMT 1345 bool "SMT scheduler support" 1346 depends on ARM_CPU_TOPOLOGY 1347 help 1348 Improves the CPU scheduler's decision making when dealing with 1349 MultiThreading at a cost of slightly increased overhead in some 1350 places. If unsure say N here. 1351 1352config HAVE_ARM_SCU 1353 bool 1354 help 1355 This option enables support for the ARM system coherency unit 1356 1357config HAVE_ARM_ARCH_TIMER 1358 bool "Architected timer support" 1359 depends on CPU_V7 1360 select ARM_ARCH_TIMER 1361 select GENERIC_CLOCKEVENTS 1362 help 1363 This option enables support for the ARM architected timer 1364 1365config HAVE_ARM_TWD 1366 bool 1367 select CLKSRC_OF if OF 1368 help 1369 This options enables support for the ARM timer and watchdog unit 1370 1371config MCPM 1372 bool "Multi-Cluster Power Management" 1373 depends on CPU_V7 && SMP 1374 help 1375 This option provides the common power management infrastructure 1376 for (multi-)cluster based systems, such as big.LITTLE based 1377 systems. 1378 1379config MCPM_QUAD_CLUSTER 1380 bool 1381 depends on MCPM 1382 help 1383 To avoid wasting resources unnecessarily, MCPM only supports up 1384 to 2 clusters by default. 1385 Platforms with 3 or 4 clusters that use MCPM must select this 1386 option to allow the additional clusters to be managed. 1387 1388config BIG_LITTLE 1389 bool "big.LITTLE support (Experimental)" 1390 depends on CPU_V7 && SMP 1391 select MCPM 1392 help 1393 This option enables support selections for the big.LITTLE 1394 system architecture. 1395 1396config BL_SWITCHER 1397 bool "big.LITTLE switcher support" 1398 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU 1399 select ARM_CPU_SUSPEND 1400 select CPU_PM 1401 help 1402 The big.LITTLE "switcher" provides the core functionality to 1403 transparently handle transition between a cluster of A15's 1404 and a cluster of A7's in a big.LITTLE system. 1405 1406config BL_SWITCHER_DUMMY_IF 1407 tristate "Simple big.LITTLE switcher user interface" 1408 depends on BL_SWITCHER && DEBUG_KERNEL 1409 help 1410 This is a simple and dummy char dev interface to control 1411 the big.LITTLE switcher core code. It is meant for 1412 debugging purposes only. 1413 1414choice 1415 prompt "Memory split" 1416 depends on MMU 1417 default VMSPLIT_3G 1418 help 1419 Select the desired split between kernel and user memory. 1420 1421 If you are not absolutely sure what you are doing, leave this 1422 option alone! 1423 1424 config VMSPLIT_3G 1425 bool "3G/1G user/kernel split" 1426 config VMSPLIT_3G_OPT 1427 bool "3G/1G user/kernel split (for full 1G low memory)" 1428 config VMSPLIT_2G 1429 bool "2G/2G user/kernel split" 1430 config VMSPLIT_1G 1431 bool "1G/3G user/kernel split" 1432endchoice 1433 1434config PAGE_OFFSET 1435 hex 1436 default PHYS_OFFSET if !MMU 1437 default 0x40000000 if VMSPLIT_1G 1438 default 0x80000000 if VMSPLIT_2G 1439 default 0xB0000000 if VMSPLIT_3G_OPT 1440 default 0xC0000000 1441 1442config NR_CPUS 1443 int "Maximum number of CPUs (2-32)" 1444 range 2 32 1445 depends on SMP 1446 default "4" 1447 1448config HOTPLUG_CPU 1449 bool "Support for hot-pluggable CPUs" 1450 depends on SMP 1451 help 1452 Say Y here to experiment with turning CPUs off and on. CPUs 1453 can be controlled through /sys/devices/system/cpu. 1454 1455config ARM_PSCI 1456 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1457 depends on CPU_V7 1458 select ARM_PSCI_FW 1459 help 1460 Say Y here if you want Linux to communicate with system firmware 1461 implementing the PSCI specification for CPU-centric power 1462 management operations described in ARM document number ARM DEN 1463 0022A ("Power State Coordination Interface System Software on 1464 ARM processors"). 1465 1466# The GPIO number here must be sorted by descending number. In case of 1467# a multiplatform kernel, we just want the highest value required by the 1468# selected platforms. 1469config ARCH_NR_GPIO 1470 int 1471 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1472 ARCH_ZYNQ 1473 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1474 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1475 default 416 if ARCH_SUNXI 1476 default 392 if ARCH_U8500 1477 default 352 if ARCH_VT8500 1478 default 288 if ARCH_ROCKCHIP 1479 default 264 if MACH_H4700 1480 default 0 1481 help 1482 Maximum number of GPIOs in the system. 1483 1484 If unsure, leave the default value. 1485 1486source kernel/Kconfig.preempt 1487 1488config HZ_FIXED 1489 int 1490 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1491 ARCH_S5PV210 || ARCH_EXYNOS4 1492 default 128 if SOC_AT91RM9200 1493 default 0 1494 1495choice 1496 depends on HZ_FIXED = 0 1497 prompt "Timer frequency" 1498 1499config HZ_100 1500 bool "100 Hz" 1501 1502config HZ_200 1503 bool "200 Hz" 1504 1505config HZ_250 1506 bool "250 Hz" 1507 1508config HZ_300 1509 bool "300 Hz" 1510 1511config HZ_500 1512 bool "500 Hz" 1513 1514config HZ_1000 1515 bool "1000 Hz" 1516 1517endchoice 1518 1519config HZ 1520 int 1521 default HZ_FIXED if HZ_FIXED != 0 1522 default 100 if HZ_100 1523 default 200 if HZ_200 1524 default 250 if HZ_250 1525 default 300 if HZ_300 1526 default 500 if HZ_500 1527 default 1000 1528 1529config SCHED_HRTICK 1530 def_bool HIGH_RES_TIMERS 1531 1532config THUMB2_KERNEL 1533 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1534 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1535 default y if CPU_THUMBONLY 1536 select AEABI 1537 select ARM_ASM_UNIFIED 1538 select ARM_UNWIND 1539 help 1540 By enabling this option, the kernel will be compiled in 1541 Thumb-2 mode. A compiler/assembler that understand the unified 1542 ARM-Thumb syntax is needed. 1543 1544 If unsure, say N. 1545 1546config THUMB2_AVOID_R_ARM_THM_JUMP11 1547 bool "Work around buggy Thumb-2 short branch relocations in gas" 1548 depends on THUMB2_KERNEL && MODULES 1549 default y 1550 help 1551 Various binutils versions can resolve Thumb-2 branches to 1552 locally-defined, preemptible global symbols as short-range "b.n" 1553 branch instructions. 1554 1555 This is a problem, because there's no guarantee the final 1556 destination of the symbol, or any candidate locations for a 1557 trampoline, are within range of the branch. For this reason, the 1558 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1559 relocation in modules at all, and it makes little sense to add 1560 support. 1561 1562 The symptom is that the kernel fails with an "unsupported 1563 relocation" error when loading some modules. 1564 1565 Until fixed tools are available, passing 1566 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1567 code which hits this problem, at the cost of a bit of extra runtime 1568 stack usage in some cases. 1569 1570 The problem is described in more detail at: 1571 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1572 1573 Only Thumb-2 kernels are affected. 1574 1575 Unless you are sure your tools don't have this problem, say Y. 1576 1577config ARM_ASM_UNIFIED 1578 bool 1579 1580config AEABI 1581 bool "Use the ARM EABI to compile the kernel" 1582 help 1583 This option allows for the kernel to be compiled using the latest 1584 ARM ABI (aka EABI). This is only useful if you are using a user 1585 space environment that is also compiled with EABI. 1586 1587 Since there are major incompatibilities between the legacy ABI and 1588 EABI, especially with regard to structure member alignment, this 1589 option also changes the kernel syscall calling convention to 1590 disambiguate both ABIs and allow for backward compatibility support 1591 (selected with CONFIG_OABI_COMPAT). 1592 1593 To use this you need GCC version 4.0.0 or later. 1594 1595config OABI_COMPAT 1596 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1597 depends on AEABI && !THUMB2_KERNEL 1598 help 1599 This option preserves the old syscall interface along with the 1600 new (ARM EABI) one. It also provides a compatibility layer to 1601 intercept syscalls that have structure arguments which layout 1602 in memory differs between the legacy ABI and the new ARM EABI 1603 (only for non "thumb" binaries). This option adds a tiny 1604 overhead to all syscalls and produces a slightly larger kernel. 1605 1606 The seccomp filter system will not be available when this is 1607 selected, since there is no way yet to sensibly distinguish 1608 between calling conventions during filtering. 1609 1610 If you know you'll be using only pure EABI user space then you 1611 can say N here. If this option is not selected and you attempt 1612 to execute a legacy ABI binary then the result will be 1613 UNPREDICTABLE (in fact it can be predicted that it won't work 1614 at all). If in doubt say N. 1615 1616config ARCH_HAS_HOLES_MEMORYMODEL 1617 bool 1618 1619config ARCH_SPARSEMEM_ENABLE 1620 bool 1621 1622config ARCH_SPARSEMEM_DEFAULT 1623 def_bool ARCH_SPARSEMEM_ENABLE 1624 1625config ARCH_SELECT_MEMORY_MODEL 1626 def_bool ARCH_SPARSEMEM_ENABLE 1627 1628config HAVE_ARCH_PFN_VALID 1629 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1630 1631config HAVE_GENERIC_RCU_GUP 1632 def_bool y 1633 depends on ARM_LPAE 1634 1635config HIGHMEM 1636 bool "High Memory Support" 1637 depends on MMU 1638 help 1639 The address space of ARM processors is only 4 Gigabytes large 1640 and it has to accommodate user address space, kernel address 1641 space as well as some memory mapped IO. That means that, if you 1642 have a large amount of physical memory and/or IO, not all of the 1643 memory can be "permanently mapped" by the kernel. The physical 1644 memory that is not permanently mapped is called "high memory". 1645 1646 Depending on the selected kernel/user memory split, minimum 1647 vmalloc space and actual amount of RAM, you may not need this 1648 option which should result in a slightly faster kernel. 1649 1650 If unsure, say n. 1651 1652config HIGHPTE 1653 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1654 depends on HIGHMEM 1655 default y 1656 help 1657 The VM uses one page of physical memory for each page table. 1658 For systems with a lot of processes, this can use a lot of 1659 precious low memory, eventually leading to low memory being 1660 consumed by page tables. Setting this option will allow 1661 user-space 2nd level page tables to reside in high memory. 1662 1663config CPU_SW_DOMAIN_PAN 1664 bool "Enable use of CPU domains to implement privileged no-access" 1665 depends on MMU && !ARM_LPAE 1666 default y 1667 help 1668 Increase kernel security by ensuring that normal kernel accesses 1669 are unable to access userspace addresses. This can help prevent 1670 use-after-free bugs becoming an exploitable privilege escalation 1671 by ensuring that magic values (such as LIST_POISON) will always 1672 fault when dereferenced. 1673 1674 CPUs with low-vector mappings use a best-efforts implementation. 1675 Their lower 1MB needs to remain accessible for the vectors, but 1676 the remainder of userspace will become appropriately inaccessible. 1677 1678config HW_PERF_EVENTS 1679 def_bool y 1680 depends on ARM_PMU 1681 1682config SYS_SUPPORTS_HUGETLBFS 1683 def_bool y 1684 depends on ARM_LPAE 1685 1686config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1687 def_bool y 1688 depends on ARM_LPAE 1689 1690config ARCH_WANT_GENERAL_HUGETLB 1691 def_bool y 1692 1693config ARM_MODULE_PLTS 1694 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1695 depends on MODULES 1696 help 1697 Allocate PLTs when loading modules so that jumps and calls whose 1698 targets are too far away for their relative offsets to be encoded 1699 in the instructions themselves can be bounced via veneers in the 1700 module's PLT. This allows modules to be allocated in the generic 1701 vmalloc area after the dedicated module memory area has been 1702 exhausted. The modules will use slightly more memory, but after 1703 rounding up to page size, the actual memory footprint is usually 1704 the same. 1705 1706 Say y if you are getting out of memory errors while loading modules 1707 1708source "mm/Kconfig" 1709 1710config FORCE_MAX_ZONEORDER 1711 int "Maximum zone order" 1712 default "12" if SOC_AM33XX 1713 default "9" if SA1111 || ARCH_EFM32 1714 default "11" 1715 help 1716 The kernel memory allocator divides physically contiguous memory 1717 blocks into "zones", where each zone is a power of two number of 1718 pages. This option selects the largest power of two that the kernel 1719 keeps in the memory allocator. If you need to allocate very large 1720 blocks of physically contiguous memory, then you may need to 1721 increase this value. 1722 1723 This config option is actually maximum order plus one. For example, 1724 a value of 11 means that the largest free memory block is 2^10 pages. 1725 1726config ALIGNMENT_TRAP 1727 bool 1728 depends on CPU_CP15_MMU 1729 default y if !ARCH_EBSA110 1730 select HAVE_PROC_CPU if PROC_FS 1731 help 1732 ARM processors cannot fetch/store information which is not 1733 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1734 address divisible by 4. On 32-bit ARM processors, these non-aligned 1735 fetch/store instructions will be emulated in software if you say 1736 here, which has a severe performance impact. This is necessary for 1737 correct operation of some network protocols. With an IP-only 1738 configuration it is safe to say N, otherwise say Y. 1739 1740config UACCESS_WITH_MEMCPY 1741 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1742 depends on MMU 1743 default y if CPU_FEROCEON 1744 help 1745 Implement faster copy_to_user and clear_user methods for CPU 1746 cores where a 8-word STM instruction give significantly higher 1747 memory write throughput than a sequence of individual 32bit stores. 1748 1749 A possible side effect is a slight increase in scheduling latency 1750 between threads sharing the same address space if they invoke 1751 such copy operations with large buffers. 1752 1753 However, if the CPU data cache is using a write-allocate mode, 1754 this option is unlikely to provide any performance gain. 1755 1756config SECCOMP 1757 bool 1758 prompt "Enable seccomp to safely compute untrusted bytecode" 1759 ---help--- 1760 This kernel feature is useful for number crunching applications 1761 that may need to compute untrusted bytecode during their 1762 execution. By using pipes or other transports made available to 1763 the process as file descriptors supporting the read/write 1764 syscalls, it's possible to isolate those applications in 1765 their own address space using seccomp. Once seccomp is 1766 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1767 and the task is only allowed to execute a few safe syscalls 1768 defined by each seccomp mode. 1769 1770config SWIOTLB 1771 def_bool y 1772 1773config IOMMU_HELPER 1774 def_bool SWIOTLB 1775 1776config XEN_DOM0 1777 def_bool y 1778 depends on XEN 1779 1780config XEN 1781 bool "Xen guest support on ARM" 1782 depends on ARM && AEABI && OF 1783 depends on CPU_V7 && !CPU_V6 1784 depends on !GENERIC_ATOMIC64 1785 depends on MMU 1786 select ARCH_DMA_ADDR_T_64BIT 1787 select ARM_PSCI 1788 select SWIOTLB_XEN 1789 help 1790 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1791 1792endmenu 1793 1794menu "Boot options" 1795 1796config USE_OF 1797 bool "Flattened Device Tree support" 1798 select IRQ_DOMAIN 1799 select OF 1800 select OF_EARLY_FLATTREE 1801 select OF_RESERVED_MEM 1802 help 1803 Include support for flattened device tree machine descriptions. 1804 1805config ATAGS 1806 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1807 default y 1808 help 1809 This is the traditional way of passing data to the kernel at boot 1810 time. If you are solely relying on the flattened device tree (or 1811 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1812 to remove ATAGS support from your kernel binary. If unsure, 1813 leave this to y. 1814 1815config DEPRECATED_PARAM_STRUCT 1816 bool "Provide old way to pass kernel parameters" 1817 depends on ATAGS 1818 help 1819 This was deprecated in 2001 and announced to live on for 5 years. 1820 Some old boot loaders still use this way. 1821 1822# Compressed boot loader in ROM. Yes, we really want to ask about 1823# TEXT and BSS so we preserve their values in the config files. 1824config ZBOOT_ROM_TEXT 1825 hex "Compressed ROM boot loader base address" 1826 default "0" 1827 help 1828 The physical address at which the ROM-able zImage is to be 1829 placed in the target. Platforms which normally make use of 1830 ROM-able zImage formats normally set this to a suitable 1831 value in their defconfig file. 1832 1833 If ZBOOT_ROM is not enabled, this has no effect. 1834 1835config ZBOOT_ROM_BSS 1836 hex "Compressed ROM boot loader BSS address" 1837 default "0" 1838 help 1839 The base address of an area of read/write memory in the target 1840 for the ROM-able zImage which must be available while the 1841 decompressor is running. It must be large enough to hold the 1842 entire decompressed kernel plus an additional 128 KiB. 1843 Platforms which normally make use of ROM-able zImage formats 1844 normally set this to a suitable value in their defconfig file. 1845 1846 If ZBOOT_ROM is not enabled, this has no effect. 1847 1848config ZBOOT_ROM 1849 bool "Compressed boot loader in ROM/flash" 1850 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1851 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1852 help 1853 Say Y here if you intend to execute your compressed kernel image 1854 (zImage) directly from ROM or flash. If unsure, say N. 1855 1856config ARM_APPENDED_DTB 1857 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1858 depends on OF 1859 help 1860 With this option, the boot code will look for a device tree binary 1861 (DTB) appended to zImage 1862 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1863 1864 This is meant as a backward compatibility convenience for those 1865 systems with a bootloader that can't be upgraded to accommodate 1866 the documented boot protocol using a device tree. 1867 1868 Beware that there is very little in terms of protection against 1869 this option being confused by leftover garbage in memory that might 1870 look like a DTB header after a reboot if no actual DTB is appended 1871 to zImage. Do not leave this option active in a production kernel 1872 if you don't intend to always append a DTB. Proper passing of the 1873 location into r2 of a bootloader provided DTB is always preferable 1874 to this option. 1875 1876config ARM_ATAG_DTB_COMPAT 1877 bool "Supplement the appended DTB with traditional ATAG information" 1878 depends on ARM_APPENDED_DTB 1879 help 1880 Some old bootloaders can't be updated to a DTB capable one, yet 1881 they provide ATAGs with memory configuration, the ramdisk address, 1882 the kernel cmdline string, etc. Such information is dynamically 1883 provided by the bootloader and can't always be stored in a static 1884 DTB. To allow a device tree enabled kernel to be used with such 1885 bootloaders, this option allows zImage to extract the information 1886 from the ATAG list and store it at run time into the appended DTB. 1887 1888choice 1889 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1890 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1891 1892config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1893 bool "Use bootloader kernel arguments if available" 1894 help 1895 Uses the command-line options passed by the boot loader instead of 1896 the device tree bootargs property. If the boot loader doesn't provide 1897 any, the device tree bootargs property will be used. 1898 1899config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1900 bool "Extend with bootloader kernel arguments" 1901 help 1902 The command-line arguments provided by the boot loader will be 1903 appended to the the device tree bootargs property. 1904 1905endchoice 1906 1907config CMDLINE 1908 string "Default kernel command string" 1909 default "" 1910 help 1911 On some architectures (EBSA110 and CATS), there is currently no way 1912 for the boot loader to pass arguments to the kernel. For these 1913 architectures, you should supply some command-line options at build 1914 time by entering them here. As a minimum, you should specify the 1915 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1916 1917choice 1918 prompt "Kernel command line type" if CMDLINE != "" 1919 default CMDLINE_FROM_BOOTLOADER 1920 depends on ATAGS 1921 1922config CMDLINE_FROM_BOOTLOADER 1923 bool "Use bootloader kernel arguments if available" 1924 help 1925 Uses the command-line options passed by the boot loader. If 1926 the boot loader doesn't provide any, the default kernel command 1927 string provided in CMDLINE will be used. 1928 1929config CMDLINE_EXTEND 1930 bool "Extend bootloader kernel arguments" 1931 help 1932 The command-line arguments provided by the boot loader will be 1933 appended to the default kernel command string. 1934 1935config CMDLINE_FORCE 1936 bool "Always use the default kernel command string" 1937 help 1938 Always use the default kernel command string, even if the boot 1939 loader passes other arguments to the kernel. 1940 This is useful if you cannot or don't want to change the 1941 command-line options your boot loader passes to the kernel. 1942endchoice 1943 1944config XIP_KERNEL 1945 bool "Kernel Execute-In-Place from ROM" 1946 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1947 help 1948 Execute-In-Place allows the kernel to run from non-volatile storage 1949 directly addressable by the CPU, such as NOR flash. This saves RAM 1950 space since the text section of the kernel is not loaded from flash 1951 to RAM. Read-write sections, such as the data section and stack, 1952 are still copied to RAM. The XIP kernel is not compressed since 1953 it has to run directly from flash, so it will take more space to 1954 store it. The flash address used to link the kernel object files, 1955 and for storing it, is configuration dependent. Therefore, if you 1956 say Y here, you must know the proper physical address where to 1957 store the kernel image depending on your own flash memory usage. 1958 1959 Also note that the make target becomes "make xipImage" rather than 1960 "make zImage" or "make Image". The final kernel binary to put in 1961 ROM memory will be arch/arm/boot/xipImage. 1962 1963 If unsure, say N. 1964 1965config XIP_PHYS_ADDR 1966 hex "XIP Kernel Physical Location" 1967 depends on XIP_KERNEL 1968 default "0x00080000" 1969 help 1970 This is the physical address in your flash memory the kernel will 1971 be linked for and stored to. This address is dependent on your 1972 own flash usage. 1973 1974config KEXEC 1975 bool "Kexec system call (EXPERIMENTAL)" 1976 depends on (!SMP || PM_SLEEP_SMP) 1977 depends on !CPU_V7M 1978 select KEXEC_CORE 1979 help 1980 kexec is a system call that implements the ability to shutdown your 1981 current kernel, and to start another kernel. It is like a reboot 1982 but it is independent of the system firmware. And like a reboot 1983 you can start any kernel with it, not just Linux. 1984 1985 It is an ongoing process to be certain the hardware in a machine 1986 is properly shutdown, so do not be surprised if this code does not 1987 initially work for you. 1988 1989config ATAGS_PROC 1990 bool "Export atags in procfs" 1991 depends on ATAGS && KEXEC 1992 default y 1993 help 1994 Should the atags used to boot the kernel be exported in an "atags" 1995 file in procfs. Useful with kexec. 1996 1997config CRASH_DUMP 1998 bool "Build kdump crash kernel (EXPERIMENTAL)" 1999 help 2000 Generate crash dump after being started by kexec. This should 2001 be normally only set in special crash dump kernels which are 2002 loaded in the main kernel with kexec-tools into a specially 2003 reserved region and then later executed after a crash by 2004 kdump/kexec. The crash dump kernel must be compiled to a 2005 memory address not used by the main kernel 2006 2007 For more details see Documentation/kdump/kdump.txt 2008 2009config AUTO_ZRELADDR 2010 bool "Auto calculation of the decompressed kernel image address" 2011 help 2012 ZRELADDR is the physical address where the decompressed kernel 2013 image will be placed. If AUTO_ZRELADDR is selected, the address 2014 will be determined at run-time by masking the current IP with 2015 0xf8000000. This assumes the zImage being placed in the first 128MB 2016 from start of memory. 2017 2018endmenu 2019 2020menu "CPU Power Management" 2021 2022source "drivers/cpufreq/Kconfig" 2023 2024source "drivers/cpuidle/Kconfig" 2025 2026endmenu 2027 2028menu "Floating point emulation" 2029 2030comment "At least one emulation must be selected" 2031 2032config FPE_NWFPE 2033 bool "NWFPE math emulation" 2034 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2035 ---help--- 2036 Say Y to include the NWFPE floating point emulator in the kernel. 2037 This is necessary to run most binaries. Linux does not currently 2038 support floating point hardware so you need to say Y here even if 2039 your machine has an FPA or floating point co-processor podule. 2040 2041 You may say N here if you are going to load the Acorn FPEmulator 2042 early in the bootup. 2043 2044config FPE_NWFPE_XP 2045 bool "Support extended precision" 2046 depends on FPE_NWFPE 2047 help 2048 Say Y to include 80-bit support in the kernel floating-point 2049 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2050 Note that gcc does not generate 80-bit operations by default, 2051 so in most cases this option only enlarges the size of the 2052 floating point emulator without any good reason. 2053 2054 You almost surely want to say N here. 2055 2056config FPE_FASTFPE 2057 bool "FastFPE math emulation (EXPERIMENTAL)" 2058 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2059 ---help--- 2060 Say Y here to include the FAST floating point emulator in the kernel. 2061 This is an experimental much faster emulator which now also has full 2062 precision for the mantissa. It does not support any exceptions. 2063 It is very simple, and approximately 3-6 times faster than NWFPE. 2064 2065 It should be sufficient for most programs. It may be not suitable 2066 for scientific calculations, but you have to check this for yourself. 2067 If you do not feel you need a faster FP emulation you should better 2068 choose NWFPE. 2069 2070config VFP 2071 bool "VFP-format floating point maths" 2072 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2073 help 2074 Say Y to include VFP support code in the kernel. This is needed 2075 if your hardware includes a VFP unit. 2076 2077 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2078 release notes and additional status information. 2079 2080 Say N if your target does not have VFP hardware. 2081 2082config VFPv3 2083 bool 2084 depends on VFP 2085 default y if CPU_V7 2086 2087config NEON 2088 bool "Advanced SIMD (NEON) Extension support" 2089 depends on VFPv3 && CPU_V7 2090 help 2091 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2092 Extension. 2093 2094config KERNEL_MODE_NEON 2095 bool "Support for NEON in kernel mode" 2096 depends on NEON && AEABI 2097 help 2098 Say Y to include support for NEON in kernel mode. 2099 2100endmenu 2101 2102menu "Userspace binary formats" 2103 2104source "fs/Kconfig.binfmt" 2105 2106endmenu 2107 2108menu "Power management options" 2109 2110source "kernel/power/Kconfig" 2111 2112config ARCH_SUSPEND_POSSIBLE 2113 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2114 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2115 def_bool y 2116 2117config ARM_CPU_SUSPEND 2118 def_bool PM_SLEEP 2119 2120config ARCH_HIBERNATION_POSSIBLE 2121 bool 2122 depends on MMU 2123 default y if ARCH_SUSPEND_POSSIBLE 2124 2125endmenu 2126 2127source "net/Kconfig" 2128 2129source "drivers/Kconfig" 2130 2131source "drivers/firmware/Kconfig" 2132 2133source "fs/Kconfig" 2134 2135source "arch/arm/Kconfig.debug" 2136 2137source "security/Kconfig" 2138 2139source "crypto/Kconfig" 2140if CRYPTO 2141source "arch/arm/crypto/Kconfig" 2142endif 2143 2144source "lib/Kconfig" 2145 2146source "arch/arm/kvm/Kconfig" 2147