xref: /linux/arch/arm/Kconfig (revision 5d292ebf4bc62107f298de2dbabe9c4ef17753fd)
1config ARM
2	bool
3	default y
4	select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6	select ARCH_HAVE_CUSTOM_GPIO_H
7	select ARCH_WANT_IPC_PARSE_VERSION
8	select BUILDTIME_EXTABLE_SORT if MMU
9	select CPU_PM if (SUSPEND || CPU_IDLE)
10	select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13	select GENERIC_IRQ_PROBE
14	select GENERIC_IRQ_SHOW
15	select GENERIC_PCI_IOMAP
16	select GENERIC_SMP_IDLE_THREAD
17	select GENERIC_STRNCPY_FROM_USER
18	select GENERIC_STRNLEN_USER
19	select HARDIRQS_SW_RESEND
20	select HAVE_AOUT
21	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
22	select HAVE_ARCH_KGDB
23	select HAVE_ARCH_SECCOMP_FILTER
24	select HAVE_ARCH_TRACEHOOK
25	select HAVE_BPF_JIT
26	select HAVE_C_RECORDMCOUNT
27	select HAVE_DEBUG_KMEMLEAK
28	select HAVE_DMA_API_DEBUG
29	select HAVE_DMA_ATTRS
30	select HAVE_DMA_CONTIGUOUS if MMU
31	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35	select HAVE_GENERIC_DMA_COHERENT
36	select HAVE_GENERIC_HARDIRQS
37	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38	select HAVE_IDE if PCI || ISA || PCMCIA
39	select HAVE_IRQ_WORK
40	select HAVE_KERNEL_GZIP
41	select HAVE_KERNEL_LZMA
42	select HAVE_KERNEL_LZO
43	select HAVE_KERNEL_XZ
44	select HAVE_KPROBES if !XIP_KERNEL
45	select HAVE_KRETPROBES if (HAVE_KPROBES)
46	select HAVE_MEMBLOCK
47	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48	select HAVE_PERF_EVENTS
49	select HAVE_REGS_AND_STACK_ACCESS_API
50	select HAVE_SYSCALL_TRACEPOINTS
51	select HAVE_UID16
52	select KTIME_SCALAR
53	select PERF_USE_VMALLOC
54	select RTC_LIB
55	select SYS_SUPPORTS_APM_EMULATION
56	select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57	select MODULES_USE_ELF_REL
58	select CLONE_BACKWARDS
59	help
60	  The ARM series is a line of low-power-consumption RISC chip designs
61	  licensed by ARM Ltd and targeted at embedded applications and
62	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
63	  manufactured, but legacy ARM-based PC hardware remains popular in
64	  Europe.  There is an ARM Linux project with a web page at
65	  <http://www.arm.linux.org.uk/>.
66
67config ARM_HAS_SG_CHAIN
68	bool
69
70config NEED_SG_DMA_LENGTH
71	bool
72
73config ARM_DMA_USE_IOMMU
74	bool
75	select ARM_HAS_SG_CHAIN
76	select NEED_SG_DMA_LENGTH
77
78config HAVE_PWM
79	bool
80
81config MIGHT_HAVE_PCI
82	bool
83
84config SYS_SUPPORTS_APM_EMULATION
85	bool
86
87config GENERIC_GPIO
88	bool
89
90config HAVE_TCM
91	bool
92	select GENERIC_ALLOCATOR
93
94config HAVE_PROC_CPU
95	bool
96
97config NO_IOPORT
98	bool
99
100config EISA
101	bool
102	---help---
103	  The Extended Industry Standard Architecture (EISA) bus was
104	  developed as an open alternative to the IBM MicroChannel bus.
105
106	  The EISA bus provided some of the features of the IBM MicroChannel
107	  bus while maintaining backward compatibility with cards made for
108	  the older ISA bus.  The EISA bus saw limited use between 1988 and
109	  1995 when it was made obsolete by the PCI bus.
110
111	  Say Y here if you are building a kernel for an EISA-based machine.
112
113	  Otherwise, say N.
114
115config SBUS
116	bool
117
118config STACKTRACE_SUPPORT
119	bool
120	default y
121
122config HAVE_LATENCYTOP_SUPPORT
123	bool
124	depends on !SMP
125	default y
126
127config LOCKDEP_SUPPORT
128	bool
129	default y
130
131config TRACE_IRQFLAGS_SUPPORT
132	bool
133	default y
134
135config RWSEM_GENERIC_SPINLOCK
136	bool
137	default y
138
139config RWSEM_XCHGADD_ALGORITHM
140	bool
141
142config ARCH_HAS_ILOG2_U32
143	bool
144
145config ARCH_HAS_ILOG2_U64
146	bool
147
148config ARCH_HAS_CPUFREQ
149	bool
150	help
151	  Internal node to signify that the ARCH has CPUFREQ support
152	  and that the relevant menu configurations are displayed for
153	  it.
154
155config GENERIC_HWEIGHT
156	bool
157	default y
158
159config GENERIC_CALIBRATE_DELAY
160	bool
161	default y
162
163config ARCH_MAY_HAVE_PC_FDC
164	bool
165
166config ZONE_DMA
167	bool
168
169config NEED_DMA_MAP_STATE
170       def_bool y
171
172config ARCH_HAS_DMA_SET_COHERENT_MASK
173	bool
174
175config GENERIC_ISA_DMA
176	bool
177
178config FIQ
179	bool
180
181config NEED_RET_TO_USER
182	bool
183
184config ARCH_MTD_XIP
185	bool
186
187config VECTORS_BASE
188	hex
189	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190	default DRAM_BASE if REMAP_VECTORS_TO_RAM
191	default 0x00000000
192	help
193	  The base address of exception vectors.
194
195config ARM_PATCH_PHYS_VIRT
196	bool "Patch physical to virtual translations at runtime" if EMBEDDED
197	default y
198	depends on !XIP_KERNEL && MMU
199	depends on !ARCH_REALVIEW || !SPARSEMEM
200	help
201	  Patch phys-to-virt and virt-to-phys translation functions at
202	  boot and module load time according to the position of the
203	  kernel in system memory.
204
205	  This can only be used with non-XIP MMU kernels where the base
206	  of physical memory is at a 16MB boundary.
207
208	  Only disable this option if you know that you do not require
209	  this feature (eg, building a kernel for a single machine) and
210	  you need to shrink the kernel to the minimal size.
211
212config NEED_MACH_GPIO_H
213	bool
214	help
215	  Select this when mach/gpio.h is required to provide special
216	  definitions for this platform. The need for mach/gpio.h should
217	  be avoided when possible.
218
219config NEED_MACH_IO_H
220	bool
221	help
222	  Select this when mach/io.h is required to provide special
223	  definitions for this platform.  The need for mach/io.h should
224	  be avoided when possible.
225
226config NEED_MACH_MEMORY_H
227	bool
228	help
229	  Select this when mach/memory.h is required to provide special
230	  definitions for this platform.  The need for mach/memory.h should
231	  be avoided when possible.
232
233config PHYS_OFFSET
234	hex "Physical address of main memory" if MMU
235	depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236	default DRAM_BASE if !MMU
237	help
238	  Please provide the physical address corresponding to the
239	  location of main memory in your system.
240
241config GENERIC_BUG
242	def_bool y
243	depends on BUG
244
245source "init/Kconfig"
246
247source "kernel/Kconfig.freezer"
248
249menu "System Type"
250
251config MMU
252	bool "MMU-based Paged Memory Management Support"
253	default y
254	help
255	  Select if you want MMU-based virtualised addressing space
256	  support by paged memory management. If unsure, say 'Y'.
257
258#
259# The "ARM system type" choice list is ordered alphabetically by option
260# text.  Please add new entries in the option alphabetic order.
261#
262choice
263	prompt "ARM system type"
264	default ARCH_MULTIPLATFORM
265
266config ARCH_MULTIPLATFORM
267	bool "Allow multiple platforms to be selected"
268	depends on MMU
269	select ARM_PATCH_PHYS_VIRT
270	select AUTO_ZRELADDR
271	select COMMON_CLK
272	select MULTI_IRQ_HANDLER
273	select SPARSE_IRQ
274	select USE_OF
275
276config ARCH_INTEGRATOR
277	bool "ARM Ltd. Integrator family"
278	select ARCH_HAS_CPUFREQ
279	select ARM_AMBA
280	select COMMON_CLK
281	select COMMON_CLK_VERSATILE
282	select GENERIC_CLOCKEVENTS
283	select HAVE_TCM
284	select ICST
285	select MULTI_IRQ_HANDLER
286	select NEED_MACH_MEMORY_H
287	select PLAT_VERSATILE
288	select SPARSE_IRQ
289	select VERSATILE_FPGA_IRQ
290	help
291	  Support for ARM's Integrator platform.
292
293config ARCH_REALVIEW
294	bool "ARM Ltd. RealView family"
295	select ARCH_WANT_OPTIONAL_GPIOLIB
296	select ARM_AMBA
297	select ARM_TIMER_SP804
298	select COMMON_CLK
299	select COMMON_CLK_VERSATILE
300	select GENERIC_CLOCKEVENTS
301	select GPIO_PL061 if GPIOLIB
302	select ICST
303	select NEED_MACH_MEMORY_H
304	select PLAT_VERSATILE
305	select PLAT_VERSATILE_CLCD
306	help
307	  This enables support for ARM Ltd RealView boards.
308
309config ARCH_VERSATILE
310	bool "ARM Ltd. Versatile family"
311	select ARCH_WANT_OPTIONAL_GPIOLIB
312	select ARM_AMBA
313	select ARM_TIMER_SP804
314	select ARM_VIC
315	select CLKDEV_LOOKUP
316	select GENERIC_CLOCKEVENTS
317	select HAVE_MACH_CLKDEV
318	select ICST
319	select PLAT_VERSATILE
320	select PLAT_VERSATILE_CLCD
321	select PLAT_VERSATILE_CLOCK
322	select VERSATILE_FPGA_IRQ
323	help
324	  This enables support for ARM Ltd Versatile board.
325
326config ARCH_AT91
327	bool "Atmel AT91"
328	select ARCH_REQUIRE_GPIOLIB
329	select CLKDEV_LOOKUP
330	select HAVE_CLK
331	select IRQ_DOMAIN
332	select NEED_MACH_GPIO_H
333	select NEED_MACH_IO_H if PCCARD
334	select PINCTRL
335	select PINCTRL_AT91 if USE_OF
336	help
337	  This enables support for systems based on Atmel
338	  AT91RM9200 and AT91SAM9* processors.
339
340config ARCH_BCM2835
341	bool "Broadcom BCM2835 family"
342	select ARCH_REQUIRE_GPIOLIB
343	select ARM_AMBA
344	select ARM_ERRATA_411920
345	select ARM_TIMER_SP804
346	select CLKDEV_LOOKUP
347	select CLKSRC_OF
348	select COMMON_CLK
349	select CPU_V6
350	select GENERIC_CLOCKEVENTS
351	select MULTI_IRQ_HANDLER
352	select PINCTRL
353	select PINCTRL_BCM2835
354	select SPARSE_IRQ
355	select USE_OF
356	help
357	  This enables support for the Broadcom BCM2835 SoC. This SoC is
358	  use in the Raspberry Pi, and Roku 2 devices.
359
360config ARCH_CNS3XXX
361	bool "Cavium Networks CNS3XXX family"
362	select ARM_GIC
363	select CPU_V6K
364	select GENERIC_CLOCKEVENTS
365	select MIGHT_HAVE_CACHE_L2X0
366	select MIGHT_HAVE_PCI
367	select PCI_DOMAINS if PCI
368	help
369	  Support for Cavium Networks CNS3XXX platform.
370
371config ARCH_CLPS711X
372	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373	select ARCH_REQUIRE_GPIOLIB
374	select AUTO_ZRELADDR
375	select CLKDEV_LOOKUP
376	select COMMON_CLK
377	select CPU_ARM720T
378	select GENERIC_CLOCKEVENTS
379	select MULTI_IRQ_HANDLER
380	select NEED_MACH_MEMORY_H
381	select SPARSE_IRQ
382	help
383	  Support for Cirrus Logic 711x/721x/731x based boards.
384
385config ARCH_GEMINI
386	bool "Cortina Systems Gemini"
387	select ARCH_REQUIRE_GPIOLIB
388	select ARCH_USES_GETTIMEOFFSET
389	select CPU_FA526
390	help
391	  Support for the Cortina Systems Gemini family SoCs
392
393config ARCH_SIRF
394	bool "CSR SiRF"
395	select ARCH_REQUIRE_GPIOLIB
396	select COMMON_CLK
397	select GENERIC_CLOCKEVENTS
398	select GENERIC_IRQ_CHIP
399	select MIGHT_HAVE_CACHE_L2X0
400	select NO_IOPORT
401	select PINCTRL
402	select PINCTRL_SIRF
403	select USE_OF
404	help
405	  Support for CSR SiRFprimaII/Marco/Polo platforms
406
407config ARCH_EBSA110
408	bool "EBSA-110"
409	select ARCH_USES_GETTIMEOFFSET
410	select CPU_SA110
411	select ISA
412	select NEED_MACH_IO_H
413	select NEED_MACH_MEMORY_H
414	select NO_IOPORT
415	help
416	  This is an evaluation board for the StrongARM processor available
417	  from Digital. It has limited hardware on-board, including an
418	  Ethernet interface, two PCMCIA sockets, two serial ports and a
419	  parallel port.
420
421config ARCH_EP93XX
422	bool "EP93xx-based"
423	select ARCH_HAS_HOLES_MEMORYMODEL
424	select ARCH_REQUIRE_GPIOLIB
425	select ARCH_USES_GETTIMEOFFSET
426	select ARM_AMBA
427	select ARM_VIC
428	select CLKDEV_LOOKUP
429	select CPU_ARM920T
430	select NEED_MACH_MEMORY_H
431	help
432	  This enables support for the Cirrus EP93xx series of CPUs.
433
434config ARCH_FOOTBRIDGE
435	bool "FootBridge"
436	select CPU_SA110
437	select FOOTBRIDGE
438	select GENERIC_CLOCKEVENTS
439	select HAVE_IDE
440	select NEED_MACH_IO_H if !MMU
441	select NEED_MACH_MEMORY_H
442	help
443	  Support for systems based on the DC21285 companion chip
444	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
445
446config ARCH_MXS
447	bool "Freescale MXS-based"
448	select ARCH_REQUIRE_GPIOLIB
449	select CLKDEV_LOOKUP
450	select CLKSRC_MMIO
451	select COMMON_CLK
452	select GENERIC_CLOCKEVENTS
453	select HAVE_CLK_PREPARE
454	select MULTI_IRQ_HANDLER
455	select PINCTRL
456	select SPARSE_IRQ
457	select USE_OF
458	help
459	  Support for Freescale MXS-based family of processors
460
461config ARCH_NETX
462	bool "Hilscher NetX based"
463	select ARM_VIC
464	select CLKSRC_MMIO
465	select CPU_ARM926T
466	select GENERIC_CLOCKEVENTS
467	help
468	  This enables support for systems based on the Hilscher NetX Soc
469
470config ARCH_H720X
471	bool "Hynix HMS720x-based"
472	select ARCH_USES_GETTIMEOFFSET
473	select CPU_ARM720T
474	select ISA_DMA_API
475	help
476	  This enables support for systems based on the Hynix HMS720x
477
478config ARCH_IOP13XX
479	bool "IOP13xx-based"
480	depends on MMU
481	select ARCH_SUPPORTS_MSI
482	select CPU_XSC3
483	select NEED_MACH_MEMORY_H
484	select NEED_RET_TO_USER
485	select PCI
486	select PLAT_IOP
487	select VMSPLIT_1G
488	help
489	  Support for Intel's IOP13XX (XScale) family of processors.
490
491config ARCH_IOP32X
492	bool "IOP32x-based"
493	depends on MMU
494	select ARCH_REQUIRE_GPIOLIB
495	select CPU_XSCALE
496	select NEED_MACH_GPIO_H
497	select NEED_RET_TO_USER
498	select PCI
499	select PLAT_IOP
500	help
501	  Support for Intel's 80219 and IOP32X (XScale) family of
502	  processors.
503
504config ARCH_IOP33X
505	bool "IOP33x-based"
506	depends on MMU
507	select ARCH_REQUIRE_GPIOLIB
508	select CPU_XSCALE
509	select NEED_MACH_GPIO_H
510	select NEED_RET_TO_USER
511	select PCI
512	select PLAT_IOP
513	help
514	  Support for Intel's IOP33X (XScale) family of processors.
515
516config ARCH_IXP4XX
517	bool "IXP4xx-based"
518	depends on MMU
519	select ARCH_HAS_DMA_SET_COHERENT_MASK
520	select ARCH_REQUIRE_GPIOLIB
521	select CLKSRC_MMIO
522	select CPU_XSCALE
523	select DMABOUNCE if PCI
524	select GENERIC_CLOCKEVENTS
525	select MIGHT_HAVE_PCI
526	select NEED_MACH_IO_H
527	help
528	  Support for Intel's IXP4XX (XScale) family of processors.
529
530config ARCH_DOVE
531	bool "Marvell Dove"
532	select ARCH_REQUIRE_GPIOLIB
533	select COMMON_CLK_DOVE
534	select CPU_V7
535	select GENERIC_CLOCKEVENTS
536	select MIGHT_HAVE_PCI
537	select PINCTRL
538	select PINCTRL_DOVE
539	select PLAT_ORION_LEGACY
540	select USB_ARCH_HAS_EHCI
541	help
542	  Support for the Marvell Dove SoC 88AP510
543
544config ARCH_KIRKWOOD
545	bool "Marvell Kirkwood"
546	select ARCH_REQUIRE_GPIOLIB
547	select CPU_FEROCEON
548	select GENERIC_CLOCKEVENTS
549	select PCI
550	select PCI_QUIRKS
551	select PINCTRL
552	select PINCTRL_KIRKWOOD
553	select PLAT_ORION_LEGACY
554	help
555	  Support for the following Marvell Kirkwood series SoCs:
556	  88F6180, 88F6192 and 88F6281.
557
558config ARCH_MV78XX0
559	bool "Marvell MV78xx0"
560	select ARCH_REQUIRE_GPIOLIB
561	select CPU_FEROCEON
562	select GENERIC_CLOCKEVENTS
563	select PCI
564	select PLAT_ORION_LEGACY
565	help
566	  Support for the following Marvell MV78xx0 series SoCs:
567	  MV781x0, MV782x0.
568
569config ARCH_ORION5X
570	bool "Marvell Orion"
571	depends on MMU
572	select ARCH_REQUIRE_GPIOLIB
573	select CPU_FEROCEON
574	select GENERIC_CLOCKEVENTS
575	select PCI
576	select PLAT_ORION_LEGACY
577	help
578	  Support for the following Marvell Orion 5x series SoCs:
579	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580	  Orion-2 (5281), Orion-1-90 (6183).
581
582config ARCH_MMP
583	bool "Marvell PXA168/910/MMP2"
584	depends on MMU
585	select ARCH_REQUIRE_GPIOLIB
586	select CLKDEV_LOOKUP
587	select GENERIC_ALLOCATOR
588	select GENERIC_CLOCKEVENTS
589	select GPIO_PXA
590	select IRQ_DOMAIN
591	select NEED_MACH_GPIO_H
592	select PINCTRL
593	select PLAT_PXA
594	select SPARSE_IRQ
595	help
596	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
597
598config ARCH_KS8695
599	bool "Micrel/Kendin KS8695"
600	select ARCH_REQUIRE_GPIOLIB
601	select CLKSRC_MMIO
602	select CPU_ARM922T
603	select GENERIC_CLOCKEVENTS
604	select NEED_MACH_MEMORY_H
605	help
606	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607	  System-on-Chip devices.
608
609config ARCH_W90X900
610	bool "Nuvoton W90X900 CPU"
611	select ARCH_REQUIRE_GPIOLIB
612	select CLKDEV_LOOKUP
613	select CLKSRC_MMIO
614	select CPU_ARM926T
615	select GENERIC_CLOCKEVENTS
616	help
617	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618	  At present, the w90x900 has been renamed nuc900, regarding
619	  the ARM series product line, you can login the following
620	  link address to know more.
621
622	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
624
625config ARCH_LPC32XX
626	bool "NXP LPC32XX"
627	select ARCH_REQUIRE_GPIOLIB
628	select ARM_AMBA
629	select CLKDEV_LOOKUP
630	select CLKSRC_MMIO
631	select CPU_ARM926T
632	select GENERIC_CLOCKEVENTS
633	select HAVE_IDE
634	select HAVE_PWM
635	select USB_ARCH_HAS_OHCI
636	select USE_OF
637	help
638	  Support for the NXP LPC32XX family of processors
639
640config ARCH_TEGRA
641	bool "NVIDIA Tegra"
642	select ARCH_HAS_CPUFREQ
643	select CLKDEV_LOOKUP
644	select CLKSRC_MMIO
645	select COMMON_CLK
646	select GENERIC_CLOCKEVENTS
647	select HAVE_CLK
648	select HAVE_SMP
649	select MIGHT_HAVE_CACHE_L2X0
650	select SPARSE_IRQ
651	select USE_OF
652	help
653	  This enables support for NVIDIA Tegra based systems (Tegra APX,
654	  Tegra 6xx and Tegra 2 series).
655
656config ARCH_PXA
657	bool "PXA2xx/PXA3xx-based"
658	depends on MMU
659	select ARCH_HAS_CPUFREQ
660	select ARCH_MTD_XIP
661	select ARCH_REQUIRE_GPIOLIB
662	select ARM_CPU_SUSPEND if PM
663	select AUTO_ZRELADDR
664	select CLKDEV_LOOKUP
665	select CLKSRC_MMIO
666	select GENERIC_CLOCKEVENTS
667	select GPIO_PXA
668	select HAVE_IDE
669	select MULTI_IRQ_HANDLER
670	select NEED_MACH_GPIO_H
671	select PLAT_PXA
672	select SPARSE_IRQ
673	help
674	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
675
676config ARCH_MSM
677	bool "Qualcomm MSM"
678	select ARCH_REQUIRE_GPIOLIB
679	select CLKDEV_LOOKUP
680	select GENERIC_CLOCKEVENTS
681	select HAVE_CLK
682	help
683	  Support for Qualcomm MSM/QSD based systems.  This runs on the
684	  apps processor of the MSM/QSD and depends on a shared memory
685	  interface to the modem processor which runs the baseband
686	  stack and controls some vital subsystems
687	  (clock and power control, etc).
688
689config ARCH_SHMOBILE
690	bool "Renesas SH-Mobile / R-Mobile"
691	select CLKDEV_LOOKUP
692	select GENERIC_CLOCKEVENTS
693	select HAVE_CLK
694	select HAVE_MACH_CLKDEV
695	select HAVE_SMP
696	select MIGHT_HAVE_CACHE_L2X0
697	select MULTI_IRQ_HANDLER
698	select NEED_MACH_MEMORY_H
699	select NO_IOPORT
700	select PM_GENERIC_DOMAINS if PM
701	select SPARSE_IRQ
702	help
703	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
704
705config ARCH_RPC
706	bool "RiscPC"
707	select ARCH_ACORN
708	select ARCH_MAY_HAVE_PC_FDC
709	select ARCH_SPARSEMEM_ENABLE
710	select ARCH_USES_GETTIMEOFFSET
711	select FIQ
712	select HAVE_IDE
713	select HAVE_PATA_PLATFORM
714	select ISA_DMA_API
715	select NEED_MACH_IO_H
716	select NEED_MACH_MEMORY_H
717	select NO_IOPORT
718	help
719	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
720	  CD-ROM interface, serial and parallel port, and the floppy drive.
721
722config ARCH_SA1100
723	bool "SA1100-based"
724	select ARCH_HAS_CPUFREQ
725	select ARCH_MTD_XIP
726	select ARCH_REQUIRE_GPIOLIB
727	select ARCH_SPARSEMEM_ENABLE
728	select CLKDEV_LOOKUP
729	select CLKSRC_MMIO
730	select CPU_FREQ
731	select CPU_SA1100
732	select GENERIC_CLOCKEVENTS
733	select HAVE_IDE
734	select ISA
735	select NEED_MACH_GPIO_H
736	select NEED_MACH_MEMORY_H
737	select SPARSE_IRQ
738	help
739	  Support for StrongARM 11x0 based boards.
740
741config ARCH_S3C24XX
742	bool "Samsung S3C24XX SoCs"
743	select ARCH_HAS_CPUFREQ
744	select ARCH_USES_GETTIMEOFFSET
745	select CLKDEV_LOOKUP
746	select HAVE_CLK
747	select HAVE_S3C2410_I2C if I2C
748	select HAVE_S3C2410_WATCHDOG if WATCHDOG
749	select HAVE_S3C_RTC if RTC_CLASS
750	select NEED_MACH_GPIO_H
751	select NEED_MACH_IO_H
752	help
753	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
754	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
755	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
756	  Samsung SMDK2410 development board (and derivatives).
757
758config ARCH_S3C64XX
759	bool "Samsung S3C64XX"
760	select ARCH_HAS_CPUFREQ
761	select ARCH_REQUIRE_GPIOLIB
762	select ARCH_USES_GETTIMEOFFSET
763	select ARM_VIC
764	select CLKDEV_LOOKUP
765	select CPU_V6
766	select HAVE_CLK
767	select HAVE_S3C2410_I2C if I2C
768	select HAVE_S3C2410_WATCHDOG if WATCHDOG
769	select HAVE_TCM
770	select NEED_MACH_GPIO_H
771	select NO_IOPORT
772	select PLAT_SAMSUNG
773	select S3C_DEV_NAND
774	select S3C_GPIO_TRACK
775	select SAMSUNG_CLKSRC
776	select SAMSUNG_GPIOLIB_4BIT
777	select SAMSUNG_IRQ_VIC_TIMER
778	select USB_ARCH_HAS_OHCI
779	help
780	  Samsung S3C64XX series based systems
781
782config ARCH_S5P64X0
783	bool "Samsung S5P6440 S5P6450"
784	select CLKDEV_LOOKUP
785	select CLKSRC_MMIO
786	select CPU_V6
787	select GENERIC_CLOCKEVENTS
788	select HAVE_CLK
789	select HAVE_S3C2410_I2C if I2C
790	select HAVE_S3C2410_WATCHDOG if WATCHDOG
791	select HAVE_S3C_RTC if RTC_CLASS
792	select NEED_MACH_GPIO_H
793	help
794	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
795	  SMDK6450.
796
797config ARCH_S5PC100
798	bool "Samsung S5PC100"
799	select ARCH_USES_GETTIMEOFFSET
800	select CLKDEV_LOOKUP
801	select CPU_V7
802	select HAVE_CLK
803	select HAVE_S3C2410_I2C if I2C
804	select HAVE_S3C2410_WATCHDOG if WATCHDOG
805	select HAVE_S3C_RTC if RTC_CLASS
806	select NEED_MACH_GPIO_H
807	help
808	  Samsung S5PC100 series based systems
809
810config ARCH_S5PV210
811	bool "Samsung S5PV210/S5PC110"
812	select ARCH_HAS_CPUFREQ
813	select ARCH_HAS_HOLES_MEMORYMODEL
814	select ARCH_SPARSEMEM_ENABLE
815	select CLKDEV_LOOKUP
816	select CLKSRC_MMIO
817	select CPU_V7
818	select GENERIC_CLOCKEVENTS
819	select HAVE_CLK
820	select HAVE_S3C2410_I2C if I2C
821	select HAVE_S3C2410_WATCHDOG if WATCHDOG
822	select HAVE_S3C_RTC if RTC_CLASS
823	select NEED_MACH_GPIO_H
824	select NEED_MACH_MEMORY_H
825	help
826	  Samsung S5PV210/S5PC110 series based systems
827
828config ARCH_EXYNOS
829	bool "Samsung EXYNOS"
830	select ARCH_HAS_CPUFREQ
831	select ARCH_HAS_HOLES_MEMORYMODEL
832	select ARCH_SPARSEMEM_ENABLE
833	select CLKDEV_LOOKUP
834	select CPU_V7
835	select GENERIC_CLOCKEVENTS
836	select HAVE_CLK
837	select HAVE_S3C2410_I2C if I2C
838	select HAVE_S3C2410_WATCHDOG if WATCHDOG
839	select HAVE_S3C_RTC if RTC_CLASS
840	select NEED_MACH_GPIO_H
841	select NEED_MACH_MEMORY_H
842	help
843	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
844
845config ARCH_SHARK
846	bool "Shark"
847	select ARCH_USES_GETTIMEOFFSET
848	select CPU_SA110
849	select ISA
850	select ISA_DMA
851	select NEED_MACH_MEMORY_H
852	select PCI
853	select ZONE_DMA
854	help
855	  Support for the StrongARM based Digital DNARD machine, also known
856	  as "Shark" (<http://www.shark-linux.de/shark.html>).
857
858config ARCH_U300
859	bool "ST-Ericsson U300 Series"
860	depends on MMU
861	select ARCH_REQUIRE_GPIOLIB
862	select ARM_AMBA
863	select ARM_PATCH_PHYS_VIRT
864	select ARM_VIC
865	select CLKDEV_LOOKUP
866	select CLKSRC_MMIO
867	select COMMON_CLK
868	select CPU_ARM926T
869	select GENERIC_CLOCKEVENTS
870	select HAVE_TCM
871	select SPARSE_IRQ
872	help
873	  Support for ST-Ericsson U300 series mobile platforms.
874
875config ARCH_U8500
876	bool "ST-Ericsson U8500 Series"
877	depends on MMU
878	select ARCH_HAS_CPUFREQ
879	select ARCH_REQUIRE_GPIOLIB
880	select ARM_AMBA
881	select CLKDEV_LOOKUP
882	select CPU_V7
883	select GENERIC_CLOCKEVENTS
884	select HAVE_SMP
885	select MIGHT_HAVE_CACHE_L2X0
886	select SPARSE_IRQ
887	help
888	  Support for ST-Ericsson's Ux500 architecture
889
890config ARCH_NOMADIK
891	bool "STMicroelectronics Nomadik"
892	select ARCH_REQUIRE_GPIOLIB
893	select ARM_AMBA
894	select ARM_VIC
895	select COMMON_CLK
896	select CPU_ARM926T
897	select GENERIC_CLOCKEVENTS
898	select MIGHT_HAVE_CACHE_L2X0
899	select PINCTRL
900	select PINCTRL_STN8815
901	select SPARSE_IRQ
902	help
903	  Support for the Nomadik platform by ST-Ericsson
904
905config PLAT_SPEAR
906	bool "ST SPEAr"
907	select ARCH_HAS_CPUFREQ
908	select ARCH_REQUIRE_GPIOLIB
909	select ARM_AMBA
910	select CLKDEV_LOOKUP
911	select CLKSRC_MMIO
912	select COMMON_CLK
913	select GENERIC_CLOCKEVENTS
914	select HAVE_CLK
915	help
916	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
917
918config ARCH_DAVINCI
919	bool "TI DaVinci"
920	select ARCH_HAS_HOLES_MEMORYMODEL
921	select ARCH_REQUIRE_GPIOLIB
922	select CLKDEV_LOOKUP
923	select GENERIC_ALLOCATOR
924	select GENERIC_CLOCKEVENTS
925	select GENERIC_IRQ_CHIP
926	select HAVE_IDE
927	select NEED_MACH_GPIO_H
928	select USE_OF
929	select ZONE_DMA
930	help
931	  Support for TI's DaVinci platform.
932
933config ARCH_OMAP
934	bool "TI OMAP"
935	depends on MMU
936	select ARCH_HAS_CPUFREQ
937	select ARCH_HAS_HOLES_MEMORYMODEL
938	select ARCH_REQUIRE_GPIOLIB
939	select CLKSRC_MMIO
940	select GENERIC_CLOCKEVENTS
941	select HAVE_CLK
942	help
943	  Support for TI's OMAP platform (OMAP1/2/3/4).
944
945config ARCH_VT8500_SINGLE
946	bool "VIA/WonderMedia 85xx"
947	select ARCH_HAS_CPUFREQ
948	select ARCH_REQUIRE_GPIOLIB
949	select CLKDEV_LOOKUP
950	select COMMON_CLK
951	select CPU_ARM926T
952	select GENERIC_CLOCKEVENTS
953	select HAVE_CLK
954	select MULTI_IRQ_HANDLER
955	select SPARSE_IRQ
956	select USE_OF
957	help
958	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
959
960endchoice
961
962menu "Multiple platform selection"
963	depends on ARCH_MULTIPLATFORM
964
965comment "CPU Core family selection"
966
967config ARCH_MULTI_V4
968	bool "ARMv4 based platforms (FA526, StrongARM)"
969	depends on !ARCH_MULTI_V6_V7
970	select ARCH_MULTI_V4_V5
971
972config ARCH_MULTI_V4T
973	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
974	depends on !ARCH_MULTI_V6_V7
975	select ARCH_MULTI_V4_V5
976
977config ARCH_MULTI_V5
978	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
979	depends on !ARCH_MULTI_V6_V7
980	select ARCH_MULTI_V4_V5
981
982config ARCH_MULTI_V4_V5
983	bool
984
985config ARCH_MULTI_V6
986	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
987	select ARCH_MULTI_V6_V7
988	select CPU_V6
989
990config ARCH_MULTI_V7
991	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
992	default y
993	select ARCH_MULTI_V6_V7
994	select ARCH_VEXPRESS
995	select CPU_V7
996
997config ARCH_MULTI_V6_V7
998	bool
999
1000config ARCH_MULTI_CPU_AUTO
1001	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1002	select ARCH_MULTI_V5
1003
1004endmenu
1005
1006#
1007# This is sorted alphabetically by mach-* pathname.  However, plat-*
1008# Kconfigs may be included either alphabetically (according to the
1009# plat- suffix) or along side the corresponding mach-* source.
1010#
1011source "arch/arm/mach-mvebu/Kconfig"
1012
1013source "arch/arm/mach-at91/Kconfig"
1014
1015source "arch/arm/mach-bcm/Kconfig"
1016
1017source "arch/arm/mach-clps711x/Kconfig"
1018
1019source "arch/arm/mach-cns3xxx/Kconfig"
1020
1021source "arch/arm/mach-davinci/Kconfig"
1022
1023source "arch/arm/mach-dove/Kconfig"
1024
1025source "arch/arm/mach-ep93xx/Kconfig"
1026
1027source "arch/arm/mach-footbridge/Kconfig"
1028
1029source "arch/arm/mach-gemini/Kconfig"
1030
1031source "arch/arm/mach-h720x/Kconfig"
1032
1033source "arch/arm/mach-highbank/Kconfig"
1034
1035source "arch/arm/mach-integrator/Kconfig"
1036
1037source "arch/arm/mach-iop32x/Kconfig"
1038
1039source "arch/arm/mach-iop33x/Kconfig"
1040
1041source "arch/arm/mach-iop13xx/Kconfig"
1042
1043source "arch/arm/mach-ixp4xx/Kconfig"
1044
1045source "arch/arm/mach-kirkwood/Kconfig"
1046
1047source "arch/arm/mach-ks8695/Kconfig"
1048
1049source "arch/arm/mach-msm/Kconfig"
1050
1051source "arch/arm/mach-mv78xx0/Kconfig"
1052
1053source "arch/arm/mach-imx/Kconfig"
1054
1055source "arch/arm/mach-mxs/Kconfig"
1056
1057source "arch/arm/mach-netx/Kconfig"
1058
1059source "arch/arm/mach-nomadik/Kconfig"
1060
1061source "arch/arm/plat-omap/Kconfig"
1062
1063source "arch/arm/mach-omap1/Kconfig"
1064
1065source "arch/arm/mach-omap2/Kconfig"
1066
1067source "arch/arm/mach-orion5x/Kconfig"
1068
1069source "arch/arm/mach-picoxcell/Kconfig"
1070
1071source "arch/arm/mach-pxa/Kconfig"
1072source "arch/arm/plat-pxa/Kconfig"
1073
1074source "arch/arm/mach-mmp/Kconfig"
1075
1076source "arch/arm/mach-realview/Kconfig"
1077
1078source "arch/arm/mach-sa1100/Kconfig"
1079
1080source "arch/arm/plat-samsung/Kconfig"
1081source "arch/arm/plat-s3c24xx/Kconfig"
1082
1083source "arch/arm/mach-socfpga/Kconfig"
1084
1085source "arch/arm/plat-spear/Kconfig"
1086
1087source "arch/arm/mach-s3c24xx/Kconfig"
1088if ARCH_S3C24XX
1089source "arch/arm/mach-s3c2412/Kconfig"
1090source "arch/arm/mach-s3c2440/Kconfig"
1091endif
1092
1093if ARCH_S3C64XX
1094source "arch/arm/mach-s3c64xx/Kconfig"
1095endif
1096
1097source "arch/arm/mach-s5p64x0/Kconfig"
1098
1099source "arch/arm/mach-s5pc100/Kconfig"
1100
1101source "arch/arm/mach-s5pv210/Kconfig"
1102
1103source "arch/arm/mach-exynos/Kconfig"
1104
1105source "arch/arm/mach-shmobile/Kconfig"
1106
1107source "arch/arm/mach-sunxi/Kconfig"
1108
1109source "arch/arm/mach-prima2/Kconfig"
1110
1111source "arch/arm/mach-tegra/Kconfig"
1112
1113source "arch/arm/mach-u300/Kconfig"
1114
1115source "arch/arm/mach-ux500/Kconfig"
1116
1117source "arch/arm/mach-versatile/Kconfig"
1118
1119source "arch/arm/mach-vexpress/Kconfig"
1120source "arch/arm/plat-versatile/Kconfig"
1121
1122source "arch/arm/mach-vt8500/Kconfig"
1123
1124source "arch/arm/mach-w90x900/Kconfig"
1125
1126source "arch/arm/mach-zynq/Kconfig"
1127
1128# Definitions to make life easier
1129config ARCH_ACORN
1130	bool
1131
1132config PLAT_IOP
1133	bool
1134	select GENERIC_CLOCKEVENTS
1135
1136config PLAT_ORION
1137	bool
1138	select CLKSRC_MMIO
1139	select COMMON_CLK
1140	select GENERIC_IRQ_CHIP
1141	select IRQ_DOMAIN
1142
1143config PLAT_ORION_LEGACY
1144	bool
1145	select PLAT_ORION
1146
1147config PLAT_PXA
1148	bool
1149
1150config PLAT_VERSATILE
1151	bool
1152
1153config ARM_TIMER_SP804
1154	bool
1155	select CLKSRC_MMIO
1156	select HAVE_SCHED_CLOCK
1157
1158source arch/arm/mm/Kconfig
1159
1160config ARM_NR_BANKS
1161	int
1162	default 16 if ARCH_EP93XX
1163	default 8
1164
1165config IWMMXT
1166	bool "Enable iWMMXt support"
1167	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1168	default y if PXA27x || PXA3xx || ARCH_MMP
1169	help
1170	  Enable support for iWMMXt context switching at run time if
1171	  running on a CPU that supports it.
1172
1173config XSCALE_PMU
1174	bool
1175	depends on CPU_XSCALE
1176	default y
1177
1178config MULTI_IRQ_HANDLER
1179	bool
1180	help
1181	  Allow each machine to specify it's own IRQ handler at run time.
1182
1183if !MMU
1184source "arch/arm/Kconfig-nommu"
1185endif
1186
1187config ARM_ERRATA_326103
1188	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1189	depends on CPU_V6
1190	help
1191	  Executing a SWP instruction to read-only memory does not set bit 11
1192	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1193	  treat the access as a read, preventing a COW from occurring and
1194	  causing the faulting task to livelock.
1195
1196config ARM_ERRATA_411920
1197	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1198	depends on CPU_V6 || CPU_V6K
1199	help
1200	  Invalidation of the Instruction Cache operation can
1201	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1202	  It does not affect the MPCore. This option enables the ARM Ltd.
1203	  recommended workaround.
1204
1205config ARM_ERRATA_430973
1206	bool "ARM errata: Stale prediction on replaced interworking branch"
1207	depends on CPU_V7
1208	help
1209	  This option enables the workaround for the 430973 Cortex-A8
1210	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1211	  interworking branch is replaced with another code sequence at the
1212	  same virtual address, whether due to self-modifying code or virtual
1213	  to physical address re-mapping, Cortex-A8 does not recover from the
1214	  stale interworking branch prediction. This results in Cortex-A8
1215	  executing the new code sequence in the incorrect ARM or Thumb state.
1216	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1217	  and also flushes the branch target cache at every context switch.
1218	  Note that setting specific bits in the ACTLR register may not be
1219	  available in non-secure mode.
1220
1221config ARM_ERRATA_458693
1222	bool "ARM errata: Processor deadlock when a false hazard is created"
1223	depends on CPU_V7
1224	depends on !ARCH_MULTIPLATFORM
1225	help
1226	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1227	  erratum. For very specific sequences of memory operations, it is
1228	  possible for a hazard condition intended for a cache line to instead
1229	  be incorrectly associated with a different cache line. This false
1230	  hazard might then cause a processor deadlock. The workaround enables
1231	  the L1 caching of the NEON accesses and disables the PLD instruction
1232	  in the ACTLR register. Note that setting specific bits in the ACTLR
1233	  register may not be available in non-secure mode.
1234
1235config ARM_ERRATA_460075
1236	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1237	depends on CPU_V7
1238	depends on !ARCH_MULTIPLATFORM
1239	help
1240	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1241	  erratum. Any asynchronous access to the L2 cache may encounter a
1242	  situation in which recent store transactions to the L2 cache are lost
1243	  and overwritten with stale memory contents from external memory. The
1244	  workaround disables the write-allocate mode for the L2 cache via the
1245	  ACTLR register. Note that setting specific bits in the ACTLR register
1246	  may not be available in non-secure mode.
1247
1248config ARM_ERRATA_742230
1249	bool "ARM errata: DMB operation may be faulty"
1250	depends on CPU_V7 && SMP
1251	depends on !ARCH_MULTIPLATFORM
1252	help
1253	  This option enables the workaround for the 742230 Cortex-A9
1254	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1255	  between two write operations may not ensure the correct visibility
1256	  ordering of the two writes. This workaround sets a specific bit in
1257	  the diagnostic register of the Cortex-A9 which causes the DMB
1258	  instruction to behave as a DSB, ensuring the correct behaviour of
1259	  the two writes.
1260
1261config ARM_ERRATA_742231
1262	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1263	depends on CPU_V7 && SMP
1264	depends on !ARCH_MULTIPLATFORM
1265	help
1266	  This option enables the workaround for the 742231 Cortex-A9
1267	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1268	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1269	  accessing some data located in the same cache line, may get corrupted
1270	  data due to bad handling of the address hazard when the line gets
1271	  replaced from one of the CPUs at the same time as another CPU is
1272	  accessing it. This workaround sets specific bits in the diagnostic
1273	  register of the Cortex-A9 which reduces the linefill issuing
1274	  capabilities of the processor.
1275
1276config PL310_ERRATA_588369
1277	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1278	depends on CACHE_L2X0
1279	help
1280	   The PL310 L2 cache controller implements three types of Clean &
1281	   Invalidate maintenance operations: by Physical Address
1282	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1283	   They are architecturally defined to behave as the execution of a
1284	   clean operation followed immediately by an invalidate operation,
1285	   both performing to the same memory location. This functionality
1286	   is not correctly implemented in PL310 as clean lines are not
1287	   invalidated as a result of these operations.
1288
1289config ARM_ERRATA_720789
1290	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1291	depends on CPU_V7
1292	help
1293	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1294	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1295	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1296	  As a consequence of this erratum, some TLB entries which should be
1297	  invalidated are not, resulting in an incoherency in the system page
1298	  tables. The workaround changes the TLB flushing routines to invalidate
1299	  entries regardless of the ASID.
1300
1301config PL310_ERRATA_727915
1302	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1303	depends on CACHE_L2X0
1304	help
1305	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1306	  operation (offset 0x7FC). This operation runs in background so that
1307	  PL310 can handle normal accesses while it is in progress. Under very
1308	  rare circumstances, due to this erratum, write data can be lost when
1309	  PL310 treats a cacheable write transaction during a Clean &
1310	  Invalidate by Way operation.
1311
1312config ARM_ERRATA_743622
1313	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1314	depends on CPU_V7
1315	depends on !ARCH_MULTIPLATFORM
1316	help
1317	  This option enables the workaround for the 743622 Cortex-A9
1318	  (r2p*) erratum. Under very rare conditions, a faulty
1319	  optimisation in the Cortex-A9 Store Buffer may lead to data
1320	  corruption. This workaround sets a specific bit in the diagnostic
1321	  register of the Cortex-A9 which disables the Store Buffer
1322	  optimisation, preventing the defect from occurring. This has no
1323	  visible impact on the overall performance or power consumption of the
1324	  processor.
1325
1326config ARM_ERRATA_751472
1327	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1328	depends on CPU_V7
1329	depends on !ARCH_MULTIPLATFORM
1330	help
1331	  This option enables the workaround for the 751472 Cortex-A9 (prior
1332	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1333	  completion of a following broadcasted operation if the second
1334	  operation is received by a CPU before the ICIALLUIS has completed,
1335	  potentially leading to corrupted entries in the cache or TLB.
1336
1337config PL310_ERRATA_753970
1338	bool "PL310 errata: cache sync operation may be faulty"
1339	depends on CACHE_PL310
1340	help
1341	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1342
1343	  Under some condition the effect of cache sync operation on
1344	  the store buffer still remains when the operation completes.
1345	  This means that the store buffer is always asked to drain and
1346	  this prevents it from merging any further writes. The workaround
1347	  is to replace the normal offset of cache sync operation (0x730)
1348	  by another offset targeting an unmapped PL310 register 0x740.
1349	  This has the same effect as the cache sync operation: store buffer
1350	  drain and waiting for all buffers empty.
1351
1352config ARM_ERRATA_754322
1353	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1354	depends on CPU_V7
1355	help
1356	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1357	  r3p*) erratum. A speculative memory access may cause a page table walk
1358	  which starts prior to an ASID switch but completes afterwards. This
1359	  can populate the micro-TLB with a stale entry which may be hit with
1360	  the new ASID. This workaround places two dsb instructions in the mm
1361	  switching code so that no page table walks can cross the ASID switch.
1362
1363config ARM_ERRATA_754327
1364	bool "ARM errata: no automatic Store Buffer drain"
1365	depends on CPU_V7 && SMP
1366	help
1367	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1368	  r2p0) erratum. The Store Buffer does not have any automatic draining
1369	  mechanism and therefore a livelock may occur if an external agent
1370	  continuously polls a memory location waiting to observe an update.
1371	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1372	  written polling loops from denying visibility of updates to memory.
1373
1374config ARM_ERRATA_364296
1375	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1376	depends on CPU_V6 && !SMP
1377	help
1378	  This options enables the workaround for the 364296 ARM1136
1379	  r0p2 erratum (possible cache data corruption with
1380	  hit-under-miss enabled). It sets the undocumented bit 31 in
1381	  the auxiliary control register and the FI bit in the control
1382	  register, thus disabling hit-under-miss without putting the
1383	  processor into full low interrupt latency mode. ARM11MPCore
1384	  is not affected.
1385
1386config ARM_ERRATA_764369
1387	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1388	depends on CPU_V7 && SMP
1389	help
1390	  This option enables the workaround for erratum 764369
1391	  affecting Cortex-A9 MPCore with two or more processors (all
1392	  current revisions). Under certain timing circumstances, a data
1393	  cache line maintenance operation by MVA targeting an Inner
1394	  Shareable memory region may fail to proceed up to either the
1395	  Point of Coherency or to the Point of Unification of the
1396	  system. This workaround adds a DSB instruction before the
1397	  relevant cache maintenance functions and sets a specific bit
1398	  in the diagnostic control register of the SCU.
1399
1400config PL310_ERRATA_769419
1401	bool "PL310 errata: no automatic Store Buffer drain"
1402	depends on CACHE_L2X0
1403	help
1404	  On revisions of the PL310 prior to r3p2, the Store Buffer does
1405	  not automatically drain. This can cause normal, non-cacheable
1406	  writes to be retained when the memory system is idle, leading
1407	  to suboptimal I/O performance for drivers using coherent DMA.
1408	  This option adds a write barrier to the cpu_idle loop so that,
1409	  on systems with an outer cache, the store buffer is drained
1410	  explicitly.
1411
1412config ARM_ERRATA_775420
1413       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1414       depends on CPU_V7
1415       help
1416	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1417	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1418	 operation aborts with MMU exception, it might cause the processor
1419	 to deadlock. This workaround puts DSB before executing ISB if
1420	 an abort may occur on cache maintenance.
1421
1422endmenu
1423
1424source "arch/arm/common/Kconfig"
1425
1426menu "Bus support"
1427
1428config ARM_AMBA
1429	bool
1430
1431config ISA
1432	bool
1433	help
1434	  Find out whether you have ISA slots on your motherboard.  ISA is the
1435	  name of a bus system, i.e. the way the CPU talks to the other stuff
1436	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1437	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1438	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1439
1440# Select ISA DMA controller support
1441config ISA_DMA
1442	bool
1443	select ISA_DMA_API
1444
1445# Select ISA DMA interface
1446config ISA_DMA_API
1447	bool
1448
1449config PCI
1450	bool "PCI support" if MIGHT_HAVE_PCI
1451	help
1452	  Find out whether you have a PCI motherboard. PCI is the name of a
1453	  bus system, i.e. the way the CPU talks to the other stuff inside
1454	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1455	  VESA. If you have PCI, say Y, otherwise N.
1456
1457config PCI_DOMAINS
1458	bool
1459	depends on PCI
1460
1461config PCI_NANOENGINE
1462	bool "BSE nanoEngine PCI support"
1463	depends on SA1100_NANOENGINE
1464	help
1465	  Enable PCI on the BSE nanoEngine board.
1466
1467config PCI_SYSCALL
1468	def_bool PCI
1469
1470# Select the host bridge type
1471config PCI_HOST_VIA82C505
1472	bool
1473	depends on PCI && ARCH_SHARK
1474	default y
1475
1476config PCI_HOST_ITE8152
1477	bool
1478	depends on PCI && MACH_ARMCORE
1479	default y
1480	select DMABOUNCE
1481
1482source "drivers/pci/Kconfig"
1483
1484source "drivers/pcmcia/Kconfig"
1485
1486endmenu
1487
1488menu "Kernel Features"
1489
1490config HAVE_SMP
1491	bool
1492	help
1493	  This option should be selected by machines which have an SMP-
1494	  capable CPU.
1495
1496	  The only effect of this option is to make the SMP-related
1497	  options available to the user for configuration.
1498
1499config SMP
1500	bool "Symmetric Multi-Processing"
1501	depends on CPU_V6K || CPU_V7
1502	depends on GENERIC_CLOCKEVENTS
1503	depends on HAVE_SMP
1504	depends on MMU
1505	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1506	select USE_GENERIC_SMP_HELPERS
1507	help
1508	  This enables support for systems with more than one CPU. If you have
1509	  a system with only one CPU, like most personal computers, say N. If
1510	  you have a system with more than one CPU, say Y.
1511
1512	  If you say N here, the kernel will run on single and multiprocessor
1513	  machines, but will use only one CPU of a multiprocessor machine. If
1514	  you say Y here, the kernel will run on many, but not all, single
1515	  processor machines. On a single processor machine, the kernel will
1516	  run faster if you say N here.
1517
1518	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1519	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1520	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1521
1522	  If you don't know what to do here, say N.
1523
1524config SMP_ON_UP
1525	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1526	depends on EXPERIMENTAL
1527	depends on SMP && !XIP_KERNEL
1528	default y
1529	help
1530	  SMP kernels contain instructions which fail on non-SMP processors.
1531	  Enabling this option allows the kernel to modify itself to make
1532	  these instructions safe.  Disabling it allows about 1K of space
1533	  savings.
1534
1535	  If you don't know what to do here, say Y.
1536
1537config ARM_CPU_TOPOLOGY
1538	bool "Support cpu topology definition"
1539	depends on SMP && CPU_V7
1540	default y
1541	help
1542	  Support ARM cpu topology definition. The MPIDR register defines
1543	  affinity between processors which is then used to describe the cpu
1544	  topology of an ARM System.
1545
1546config SCHED_MC
1547	bool "Multi-core scheduler support"
1548	depends on ARM_CPU_TOPOLOGY
1549	help
1550	  Multi-core scheduler support improves the CPU scheduler's decision
1551	  making when dealing with multi-core CPU chips at a cost of slightly
1552	  increased overhead in some places. If unsure say N here.
1553
1554config SCHED_SMT
1555	bool "SMT scheduler support"
1556	depends on ARM_CPU_TOPOLOGY
1557	help
1558	  Improves the CPU scheduler's decision making when dealing with
1559	  MultiThreading at a cost of slightly increased overhead in some
1560	  places. If unsure say N here.
1561
1562config HAVE_ARM_SCU
1563	bool
1564	help
1565	  This option enables support for the ARM system coherency unit
1566
1567config ARM_ARCH_TIMER
1568	bool "Architected timer support"
1569	depends on CPU_V7
1570	help
1571	  This option enables support for the ARM architected timer
1572
1573config HAVE_ARM_TWD
1574	bool
1575	depends on SMP
1576	help
1577	  This options enables support for the ARM timer and watchdog unit
1578
1579choice
1580	prompt "Memory split"
1581	default VMSPLIT_3G
1582	help
1583	  Select the desired split between kernel and user memory.
1584
1585	  If you are not absolutely sure what you are doing, leave this
1586	  option alone!
1587
1588	config VMSPLIT_3G
1589		bool "3G/1G user/kernel split"
1590	config VMSPLIT_2G
1591		bool "2G/2G user/kernel split"
1592	config VMSPLIT_1G
1593		bool "1G/3G user/kernel split"
1594endchoice
1595
1596config PAGE_OFFSET
1597	hex
1598	default 0x40000000 if VMSPLIT_1G
1599	default 0x80000000 if VMSPLIT_2G
1600	default 0xC0000000
1601
1602config NR_CPUS
1603	int "Maximum number of CPUs (2-32)"
1604	range 2 32
1605	depends on SMP
1606	default "4"
1607
1608config HOTPLUG_CPU
1609	bool "Support for hot-pluggable CPUs"
1610	depends on SMP && HOTPLUG
1611	help
1612	  Say Y here to experiment with turning CPUs off and on.  CPUs
1613	  can be controlled through /sys/devices/system/cpu.
1614
1615config LOCAL_TIMERS
1616	bool "Use local timer interrupts"
1617	depends on SMP
1618	default y
1619	select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1620	help
1621	  Enable support for local timers on SMP platforms, rather then the
1622	  legacy IPI broadcast method.  Local timers allows the system
1623	  accounting to be spread across the timer interval, preventing a
1624	  "thundering herd" at every timer tick.
1625
1626config ARCH_NR_GPIO
1627	int
1628	default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1629	default 355 if ARCH_U8500
1630	default 264 if MACH_H4700
1631	default 512 if SOC_OMAP5
1632	default 288 if ARCH_VT8500
1633	default 0
1634	help
1635	  Maximum number of GPIOs in the system.
1636
1637	  If unsure, leave the default value.
1638
1639source kernel/Kconfig.preempt
1640
1641config HZ
1642	int
1643	default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1644		ARCH_S5PV210 || ARCH_EXYNOS4
1645	default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1646	default AT91_TIMER_HZ if ARCH_AT91
1647	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1648	default 100
1649
1650config THUMB2_KERNEL
1651	bool "Compile the kernel in Thumb-2 mode"
1652	depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1653	select AEABI
1654	select ARM_ASM_UNIFIED
1655	select ARM_UNWIND
1656	help
1657	  By enabling this option, the kernel will be compiled in
1658	  Thumb-2 mode. A compiler/assembler that understand the unified
1659	  ARM-Thumb syntax is needed.
1660
1661	  If unsure, say N.
1662
1663config THUMB2_AVOID_R_ARM_THM_JUMP11
1664	bool "Work around buggy Thumb-2 short branch relocations in gas"
1665	depends on THUMB2_KERNEL && MODULES
1666	default y
1667	help
1668	  Various binutils versions can resolve Thumb-2 branches to
1669	  locally-defined, preemptible global symbols as short-range "b.n"
1670	  branch instructions.
1671
1672	  This is a problem, because there's no guarantee the final
1673	  destination of the symbol, or any candidate locations for a
1674	  trampoline, are within range of the branch.  For this reason, the
1675	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1676	  relocation in modules at all, and it makes little sense to add
1677	  support.
1678
1679	  The symptom is that the kernel fails with an "unsupported
1680	  relocation" error when loading some modules.
1681
1682	  Until fixed tools are available, passing
1683	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1684	  code which hits this problem, at the cost of a bit of extra runtime
1685	  stack usage in some cases.
1686
1687	  The problem is described in more detail at:
1688	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1689
1690	  Only Thumb-2 kernels are affected.
1691
1692	  Unless you are sure your tools don't have this problem, say Y.
1693
1694config ARM_ASM_UNIFIED
1695	bool
1696
1697config AEABI
1698	bool "Use the ARM EABI to compile the kernel"
1699	help
1700	  This option allows for the kernel to be compiled using the latest
1701	  ARM ABI (aka EABI).  This is only useful if you are using a user
1702	  space environment that is also compiled with EABI.
1703
1704	  Since there are major incompatibilities between the legacy ABI and
1705	  EABI, especially with regard to structure member alignment, this
1706	  option also changes the kernel syscall calling convention to
1707	  disambiguate both ABIs and allow for backward compatibility support
1708	  (selected with CONFIG_OABI_COMPAT).
1709
1710	  To use this you need GCC version 4.0.0 or later.
1711
1712config OABI_COMPAT
1713	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1714	depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1715	default y
1716	help
1717	  This option preserves the old syscall interface along with the
1718	  new (ARM EABI) one. It also provides a compatibility layer to
1719	  intercept syscalls that have structure arguments which layout
1720	  in memory differs between the legacy ABI and the new ARM EABI
1721	  (only for non "thumb" binaries). This option adds a tiny
1722	  overhead to all syscalls and produces a slightly larger kernel.
1723	  If you know you'll be using only pure EABI user space then you
1724	  can say N here. If this option is not selected and you attempt
1725	  to execute a legacy ABI binary then the result will be
1726	  UNPREDICTABLE (in fact it can be predicted that it won't work
1727	  at all). If in doubt say Y.
1728
1729config ARCH_HAS_HOLES_MEMORYMODEL
1730	bool
1731
1732config ARCH_SPARSEMEM_ENABLE
1733	bool
1734
1735config ARCH_SPARSEMEM_DEFAULT
1736	def_bool ARCH_SPARSEMEM_ENABLE
1737
1738config ARCH_SELECT_MEMORY_MODEL
1739	def_bool ARCH_SPARSEMEM_ENABLE
1740
1741config HAVE_ARCH_PFN_VALID
1742	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1743
1744config HIGHMEM
1745	bool "High Memory Support"
1746	depends on MMU
1747	help
1748	  The address space of ARM processors is only 4 Gigabytes large
1749	  and it has to accommodate user address space, kernel address
1750	  space as well as some memory mapped IO. That means that, if you
1751	  have a large amount of physical memory and/or IO, not all of the
1752	  memory can be "permanently mapped" by the kernel. The physical
1753	  memory that is not permanently mapped is called "high memory".
1754
1755	  Depending on the selected kernel/user memory split, minimum
1756	  vmalloc space and actual amount of RAM, you may not need this
1757	  option which should result in a slightly faster kernel.
1758
1759	  If unsure, say n.
1760
1761config HIGHPTE
1762	bool "Allocate 2nd-level pagetables from highmem"
1763	depends on HIGHMEM
1764
1765config HW_PERF_EVENTS
1766	bool "Enable hardware performance counter support for perf events"
1767	depends on PERF_EVENTS
1768	default y
1769	help
1770	  Enable hardware performance counter support for perf events. If
1771	  disabled, perf events will use software events only.
1772
1773source "mm/Kconfig"
1774
1775config FORCE_MAX_ZONEORDER
1776	int "Maximum zone order" if ARCH_SHMOBILE
1777	range 11 64 if ARCH_SHMOBILE
1778	default "12" if SOC_AM33XX
1779	default "9" if SA1111
1780	default "11"
1781	help
1782	  The kernel memory allocator divides physically contiguous memory
1783	  blocks into "zones", where each zone is a power of two number of
1784	  pages.  This option selects the largest power of two that the kernel
1785	  keeps in the memory allocator.  If you need to allocate very large
1786	  blocks of physically contiguous memory, then you may need to
1787	  increase this value.
1788
1789	  This config option is actually maximum order plus one. For example,
1790	  a value of 11 means that the largest free memory block is 2^10 pages.
1791
1792config ALIGNMENT_TRAP
1793	bool
1794	depends on CPU_CP15_MMU
1795	default y if !ARCH_EBSA110
1796	select HAVE_PROC_CPU if PROC_FS
1797	help
1798	  ARM processors cannot fetch/store information which is not
1799	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1800	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1801	  fetch/store instructions will be emulated in software if you say
1802	  here, which has a severe performance impact. This is necessary for
1803	  correct operation of some network protocols. With an IP-only
1804	  configuration it is safe to say N, otherwise say Y.
1805
1806config UACCESS_WITH_MEMCPY
1807	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1808	depends on MMU
1809	default y if CPU_FEROCEON
1810	help
1811	  Implement faster copy_to_user and clear_user methods for CPU
1812	  cores where a 8-word STM instruction give significantly higher
1813	  memory write throughput than a sequence of individual 32bit stores.
1814
1815	  A possible side effect is a slight increase in scheduling latency
1816	  between threads sharing the same address space if they invoke
1817	  such copy operations with large buffers.
1818
1819	  However, if the CPU data cache is using a write-allocate mode,
1820	  this option is unlikely to provide any performance gain.
1821
1822config SECCOMP
1823	bool
1824	prompt "Enable seccomp to safely compute untrusted bytecode"
1825	---help---
1826	  This kernel feature is useful for number crunching applications
1827	  that may need to compute untrusted bytecode during their
1828	  execution. By using pipes or other transports made available to
1829	  the process as file descriptors supporting the read/write
1830	  syscalls, it's possible to isolate those applications in
1831	  their own address space using seccomp. Once seccomp is
1832	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1833	  and the task is only allowed to execute a few safe syscalls
1834	  defined by each seccomp mode.
1835
1836config CC_STACKPROTECTOR
1837	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1838	depends on EXPERIMENTAL
1839	help
1840	  This option turns on the -fstack-protector GCC feature. This
1841	  feature puts, at the beginning of functions, a canary value on
1842	  the stack just before the return address, and validates
1843	  the value just before actually returning.  Stack based buffer
1844	  overflows (that need to overwrite this return address) now also
1845	  overwrite the canary, which gets detected and the attack is then
1846	  neutralized via a kernel panic.
1847	  This feature requires gcc version 4.2 or above.
1848
1849config XEN_DOM0
1850	def_bool y
1851	depends on XEN
1852
1853config XEN
1854	bool "Xen guest support on ARM (EXPERIMENTAL)"
1855	depends on EXPERIMENTAL && ARM && OF
1856	depends on CPU_V7 && !CPU_V6
1857	help
1858	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1859
1860endmenu
1861
1862menu "Boot options"
1863
1864config USE_OF
1865	bool "Flattened Device Tree support"
1866	select IRQ_DOMAIN
1867	select OF
1868	select OF_EARLY_FLATTREE
1869	help
1870	  Include support for flattened device tree machine descriptions.
1871
1872config ATAGS
1873	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1874	default y
1875	help
1876	  This is the traditional way of passing data to the kernel at boot
1877	  time. If you are solely relying on the flattened device tree (or
1878	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1879	  to remove ATAGS support from your kernel binary.  If unsure,
1880	  leave this to y.
1881
1882config DEPRECATED_PARAM_STRUCT
1883	bool "Provide old way to pass kernel parameters"
1884	depends on ATAGS
1885	help
1886	  This was deprecated in 2001 and announced to live on for 5 years.
1887	  Some old boot loaders still use this way.
1888
1889# Compressed boot loader in ROM.  Yes, we really want to ask about
1890# TEXT and BSS so we preserve their values in the config files.
1891config ZBOOT_ROM_TEXT
1892	hex "Compressed ROM boot loader base address"
1893	default "0"
1894	help
1895	  The physical address at which the ROM-able zImage is to be
1896	  placed in the target.  Platforms which normally make use of
1897	  ROM-able zImage formats normally set this to a suitable
1898	  value in their defconfig file.
1899
1900	  If ZBOOT_ROM is not enabled, this has no effect.
1901
1902config ZBOOT_ROM_BSS
1903	hex "Compressed ROM boot loader BSS address"
1904	default "0"
1905	help
1906	  The base address of an area of read/write memory in the target
1907	  for the ROM-able zImage which must be available while the
1908	  decompressor is running. It must be large enough to hold the
1909	  entire decompressed kernel plus an additional 128 KiB.
1910	  Platforms which normally make use of ROM-able zImage formats
1911	  normally set this to a suitable value in their defconfig file.
1912
1913	  If ZBOOT_ROM is not enabled, this has no effect.
1914
1915config ZBOOT_ROM
1916	bool "Compressed boot loader in ROM/flash"
1917	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1918	help
1919	  Say Y here if you intend to execute your compressed kernel image
1920	  (zImage) directly from ROM or flash.  If unsure, say N.
1921
1922choice
1923	prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1924	depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1925	default ZBOOT_ROM_NONE
1926	help
1927	  Include experimental SD/MMC loading code in the ROM-able zImage.
1928	  With this enabled it is possible to write the ROM-able zImage
1929	  kernel image to an MMC or SD card and boot the kernel straight
1930	  from the reset vector. At reset the processor Mask ROM will load
1931	  the first part of the ROM-able zImage which in turn loads the
1932	  rest the kernel image to RAM.
1933
1934config ZBOOT_ROM_NONE
1935	bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1936	help
1937	  Do not load image from SD or MMC
1938
1939config ZBOOT_ROM_MMCIF
1940	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1941	help
1942	  Load image from MMCIF hardware block.
1943
1944config ZBOOT_ROM_SH_MOBILE_SDHI
1945	bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1946	help
1947	  Load image from SDHI hardware block
1948
1949endchoice
1950
1951config ARM_APPENDED_DTB
1952	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1953	depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1954	help
1955	  With this option, the boot code will look for a device tree binary
1956	  (DTB) appended to zImage
1957	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1958
1959	  This is meant as a backward compatibility convenience for those
1960	  systems with a bootloader that can't be upgraded to accommodate
1961	  the documented boot protocol using a device tree.
1962
1963	  Beware that there is very little in terms of protection against
1964	  this option being confused by leftover garbage in memory that might
1965	  look like a DTB header after a reboot if no actual DTB is appended
1966	  to zImage.  Do not leave this option active in a production kernel
1967	  if you don't intend to always append a DTB.  Proper passing of the
1968	  location into r2 of a bootloader provided DTB is always preferable
1969	  to this option.
1970
1971config ARM_ATAG_DTB_COMPAT
1972	bool "Supplement the appended DTB with traditional ATAG information"
1973	depends on ARM_APPENDED_DTB
1974	help
1975	  Some old bootloaders can't be updated to a DTB capable one, yet
1976	  they provide ATAGs with memory configuration, the ramdisk address,
1977	  the kernel cmdline string, etc.  Such information is dynamically
1978	  provided by the bootloader and can't always be stored in a static
1979	  DTB.  To allow a device tree enabled kernel to be used with such
1980	  bootloaders, this option allows zImage to extract the information
1981	  from the ATAG list and store it at run time into the appended DTB.
1982
1983choice
1984	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1985	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1986
1987config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1988	bool "Use bootloader kernel arguments if available"
1989	help
1990	  Uses the command-line options passed by the boot loader instead of
1991	  the device tree bootargs property. If the boot loader doesn't provide
1992	  any, the device tree bootargs property will be used.
1993
1994config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1995	bool "Extend with bootloader kernel arguments"
1996	help
1997	  The command-line arguments provided by the boot loader will be
1998	  appended to the the device tree bootargs property.
1999
2000endchoice
2001
2002config CMDLINE
2003	string "Default kernel command string"
2004	default ""
2005	help
2006	  On some architectures (EBSA110 and CATS), there is currently no way
2007	  for the boot loader to pass arguments to the kernel. For these
2008	  architectures, you should supply some command-line options at build
2009	  time by entering them here. As a minimum, you should specify the
2010	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
2011
2012choice
2013	prompt "Kernel command line type" if CMDLINE != ""
2014	default CMDLINE_FROM_BOOTLOADER
2015	depends on ATAGS
2016
2017config CMDLINE_FROM_BOOTLOADER
2018	bool "Use bootloader kernel arguments if available"
2019	help
2020	  Uses the command-line options passed by the boot loader. If
2021	  the boot loader doesn't provide any, the default kernel command
2022	  string provided in CMDLINE will be used.
2023
2024config CMDLINE_EXTEND
2025	bool "Extend bootloader kernel arguments"
2026	help
2027	  The command-line arguments provided by the boot loader will be
2028	  appended to the default kernel command string.
2029
2030config CMDLINE_FORCE
2031	bool "Always use the default kernel command string"
2032	help
2033	  Always use the default kernel command string, even if the boot
2034	  loader passes other arguments to the kernel.
2035	  This is useful if you cannot or don't want to change the
2036	  command-line options your boot loader passes to the kernel.
2037endchoice
2038
2039config XIP_KERNEL
2040	bool "Kernel Execute-In-Place from ROM"
2041	depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2042	help
2043	  Execute-In-Place allows the kernel to run from non-volatile storage
2044	  directly addressable by the CPU, such as NOR flash. This saves RAM
2045	  space since the text section of the kernel is not loaded from flash
2046	  to RAM.  Read-write sections, such as the data section and stack,
2047	  are still copied to RAM.  The XIP kernel is not compressed since
2048	  it has to run directly from flash, so it will take more space to
2049	  store it.  The flash address used to link the kernel object files,
2050	  and for storing it, is configuration dependent. Therefore, if you
2051	  say Y here, you must know the proper physical address where to
2052	  store the kernel image depending on your own flash memory usage.
2053
2054	  Also note that the make target becomes "make xipImage" rather than
2055	  "make zImage" or "make Image".  The final kernel binary to put in
2056	  ROM memory will be arch/arm/boot/xipImage.
2057
2058	  If unsure, say N.
2059
2060config XIP_PHYS_ADDR
2061	hex "XIP Kernel Physical Location"
2062	depends on XIP_KERNEL
2063	default "0x00080000"
2064	help
2065	  This is the physical address in your flash memory the kernel will
2066	  be linked for and stored to.  This address is dependent on your
2067	  own flash usage.
2068
2069config KEXEC
2070	bool "Kexec system call (EXPERIMENTAL)"
2071	depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2072	help
2073	  kexec is a system call that implements the ability to shutdown your
2074	  current kernel, and to start another kernel.  It is like a reboot
2075	  but it is independent of the system firmware.   And like a reboot
2076	  you can start any kernel with it, not just Linux.
2077
2078	  It is an ongoing process to be certain the hardware in a machine
2079	  is properly shutdown, so do not be surprised if this code does not
2080	  initially work for you.  It may help to enable device hotplugging
2081	  support.
2082
2083config ATAGS_PROC
2084	bool "Export atags in procfs"
2085	depends on ATAGS && KEXEC
2086	default y
2087	help
2088	  Should the atags used to boot the kernel be exported in an "atags"
2089	  file in procfs. Useful with kexec.
2090
2091config CRASH_DUMP
2092	bool "Build kdump crash kernel (EXPERIMENTAL)"
2093	depends on EXPERIMENTAL
2094	help
2095	  Generate crash dump after being started by kexec. This should
2096	  be normally only set in special crash dump kernels which are
2097	  loaded in the main kernel with kexec-tools into a specially
2098	  reserved region and then later executed after a crash by
2099	  kdump/kexec. The crash dump kernel must be compiled to a
2100	  memory address not used by the main kernel
2101
2102	  For more details see Documentation/kdump/kdump.txt
2103
2104config AUTO_ZRELADDR
2105	bool "Auto calculation of the decompressed kernel image address"
2106	depends on !ZBOOT_ROM && !ARCH_U300
2107	help
2108	  ZRELADDR is the physical address where the decompressed kernel
2109	  image will be placed. If AUTO_ZRELADDR is selected, the address
2110	  will be determined at run-time by masking the current IP with
2111	  0xf8000000. This assumes the zImage being placed in the first 128MB
2112	  from start of memory.
2113
2114endmenu
2115
2116menu "CPU Power Management"
2117
2118if ARCH_HAS_CPUFREQ
2119
2120source "drivers/cpufreq/Kconfig"
2121
2122config CPU_FREQ_IMX
2123	tristate "CPUfreq driver for i.MX CPUs"
2124	depends on ARCH_MXC && CPU_FREQ
2125	select CPU_FREQ_TABLE
2126	help
2127	  This enables the CPUfreq driver for i.MX CPUs.
2128
2129config CPU_FREQ_SA1100
2130	bool
2131
2132config CPU_FREQ_SA1110
2133	bool
2134
2135config CPU_FREQ_INTEGRATOR
2136	tristate "CPUfreq driver for ARM Integrator CPUs"
2137	depends on ARCH_INTEGRATOR && CPU_FREQ
2138	default y
2139	help
2140	  This enables the CPUfreq driver for ARM Integrator CPUs.
2141
2142	  For details, take a look at <file:Documentation/cpu-freq>.
2143
2144	  If in doubt, say Y.
2145
2146config CPU_FREQ_PXA
2147	bool
2148	depends on CPU_FREQ && ARCH_PXA && PXA25x
2149	default y
2150	select CPU_FREQ_DEFAULT_GOV_USERSPACE
2151	select CPU_FREQ_TABLE
2152
2153config CPU_FREQ_S3C
2154	bool
2155	help
2156	  Internal configuration node for common cpufreq on Samsung SoC
2157
2158config CPU_FREQ_S3C24XX
2159	bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2160	depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2161	select CPU_FREQ_S3C
2162	help
2163	  This enables the CPUfreq driver for the Samsung S3C24XX family
2164	  of CPUs.
2165
2166	  For details, take a look at <file:Documentation/cpu-freq>.
2167
2168	  If in doubt, say N.
2169
2170config CPU_FREQ_S3C24XX_PLL
2171	bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2172	depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2173	help
2174	  Compile in support for changing the PLL frequency from the
2175	  S3C24XX series CPUfreq driver. The PLL takes time to settle
2176	  after a frequency change, so by default it is not enabled.
2177
2178	  This also means that the PLL tables for the selected CPU(s) will
2179	  be built which may increase the size of the kernel image.
2180
2181config CPU_FREQ_S3C24XX_DEBUG
2182	bool "Debug CPUfreq Samsung driver core"
2183	depends on CPU_FREQ_S3C24XX
2184	help
2185	  Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2186
2187config CPU_FREQ_S3C24XX_IODEBUG
2188	bool "Debug CPUfreq Samsung driver IO timing"
2189	depends on CPU_FREQ_S3C24XX
2190	help
2191	  Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2192
2193config CPU_FREQ_S3C24XX_DEBUGFS
2194	bool "Export debugfs for CPUFreq"
2195	depends on CPU_FREQ_S3C24XX && DEBUG_FS
2196	help
2197	  Export status information via debugfs.
2198
2199endif
2200
2201source "drivers/cpuidle/Kconfig"
2202
2203endmenu
2204
2205menu "Floating point emulation"
2206
2207comment "At least one emulation must be selected"
2208
2209config FPE_NWFPE
2210	bool "NWFPE math emulation"
2211	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2212	---help---
2213	  Say Y to include the NWFPE floating point emulator in the kernel.
2214	  This is necessary to run most binaries. Linux does not currently
2215	  support floating point hardware so you need to say Y here even if
2216	  your machine has an FPA or floating point co-processor podule.
2217
2218	  You may say N here if you are going to load the Acorn FPEmulator
2219	  early in the bootup.
2220
2221config FPE_NWFPE_XP
2222	bool "Support extended precision"
2223	depends on FPE_NWFPE
2224	help
2225	  Say Y to include 80-bit support in the kernel floating-point
2226	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2227	  Note that gcc does not generate 80-bit operations by default,
2228	  so in most cases this option only enlarges the size of the
2229	  floating point emulator without any good reason.
2230
2231	  You almost surely want to say N here.
2232
2233config FPE_FASTFPE
2234	bool "FastFPE math emulation (EXPERIMENTAL)"
2235	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2236	---help---
2237	  Say Y here to include the FAST floating point emulator in the kernel.
2238	  This is an experimental much faster emulator which now also has full
2239	  precision for the mantissa.  It does not support any exceptions.
2240	  It is very simple, and approximately 3-6 times faster than NWFPE.
2241
2242	  It should be sufficient for most programs.  It may be not suitable
2243	  for scientific calculations, but you have to check this for yourself.
2244	  If you do not feel you need a faster FP emulation you should better
2245	  choose NWFPE.
2246
2247config VFP
2248	bool "VFP-format floating point maths"
2249	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2250	help
2251	  Say Y to include VFP support code in the kernel. This is needed
2252	  if your hardware includes a VFP unit.
2253
2254	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2255	  release notes and additional status information.
2256
2257	  Say N if your target does not have VFP hardware.
2258
2259config VFPv3
2260	bool
2261	depends on VFP
2262	default y if CPU_V7
2263
2264config NEON
2265	bool "Advanced SIMD (NEON) Extension support"
2266	depends on VFPv3 && CPU_V7
2267	help
2268	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2269	  Extension.
2270
2271endmenu
2272
2273menu "Userspace binary formats"
2274
2275source "fs/Kconfig.binfmt"
2276
2277config ARTHUR
2278	tristate "RISC OS personality"
2279	depends on !AEABI
2280	help
2281	  Say Y here to include the kernel code necessary if you want to run
2282	  Acorn RISC OS/Arthur binaries under Linux. This code is still very
2283	  experimental; if this sounds frightening, say N and sleep in peace.
2284	  You can also say M here to compile this support as a module (which
2285	  will be called arthur).
2286
2287endmenu
2288
2289menu "Power management options"
2290
2291source "kernel/power/Kconfig"
2292
2293config ARCH_SUSPEND_POSSIBLE
2294	depends on !ARCH_S5PC100
2295	depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2296		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2297	def_bool y
2298
2299config ARM_CPU_SUSPEND
2300	def_bool PM_SLEEP
2301
2302endmenu
2303
2304source "net/Kconfig"
2305
2306source "drivers/Kconfig"
2307
2308source "fs/Kconfig"
2309
2310source "arch/arm/Kconfig.debug"
2311
2312source "security/Kconfig"
2313
2314source "crypto/Kconfig"
2315
2316source "lib/Kconfig"
2317