1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_CURRENT_STACK_POINTER 10 select ARCH_HAS_DEBUG_VIRTUAL if MMU 11 select ARCH_HAS_DMA_ALLOC if MMU 12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_FORTIFY_SOURCE 15 select ARCH_HAS_KEEPINITRD 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_MEMBARRIER_SYNC_CORE 18 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 19 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 20 select ARCH_HAS_SETUP_DMA_OPS 21 select ARCH_HAS_SET_MEMORY 22 select ARCH_STACKWALK 23 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 24 select ARCH_HAS_STRICT_MODULE_RWX if MMU 25 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 26 select ARCH_HAS_SYNC_DMA_FOR_CPU 27 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 29 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_KEEP_MEMBLOCK 32 select ARCH_HAS_UBSAN_SANITIZE_ALL 33 select ARCH_MIGHT_HAVE_PC_PARPORT 34 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 35 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 36 select ARCH_SUPPORTS_ATOMIC_RMW 37 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 38 select ARCH_USE_BUILTIN_BSWAP 39 select ARCH_USE_CMPXCHG_LOCKREF 40 select ARCH_USE_MEMTEST 41 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 42 select ARCH_WANT_GENERAL_HUGETLB 43 select ARCH_WANT_IPC_PARSE_VERSION 44 select ARCH_WANT_LD_ORPHAN_WARN 45 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 46 select BUILDTIME_TABLE_SORT if MMU 47 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 48 select CLONE_BACKWARDS 49 select CPU_PM if SUSPEND || CPU_IDLE 50 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 51 select DMA_DECLARE_COHERENT 52 select DMA_GLOBAL_POOL if !MMU 53 select DMA_OPS 54 select DMA_NONCOHERENT_MMAP if MMU 55 select EDAC_SUPPORT 56 select EDAC_ATOMIC_SCRUB 57 select GENERIC_ALLOCATOR 58 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 59 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 60 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 61 select GENERIC_IRQ_IPI if SMP 62 select GENERIC_CPU_AUTOPROBE 63 select GENERIC_EARLY_IOREMAP 64 select GENERIC_IDLE_POLL_SETUP 65 select GENERIC_IRQ_MULTI_HANDLER 66 select GENERIC_IRQ_PROBE 67 select GENERIC_IRQ_SHOW 68 select GENERIC_IRQ_SHOW_LEVEL 69 select GENERIC_LIB_DEVMEM_IS_ALLOWED 70 select GENERIC_PCI_IOMAP 71 select GENERIC_SCHED_CLOCK 72 select GENERIC_SMP_IDLE_THREAD 73 select HARDIRQS_SW_RESEND 74 select HAS_IOPORT 75 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 76 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 77 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 80 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 81 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 82 select HAVE_ARCH_MMAP_RND_BITS if MMU 83 select HAVE_ARCH_PFN_VALID 84 select HAVE_ARCH_SECCOMP 85 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 86 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 87 select HAVE_ARCH_TRACEHOOK 88 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 89 select HAVE_ARM_SMCCC if CPU_V7 90 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 91 select HAVE_CONTEXT_TRACKING_USER 92 select HAVE_C_RECORDMCOUNT 93 select HAVE_BUILDTIME_MCOUNT_SORT 94 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 95 select HAVE_DMA_CONTIGUOUS if MMU 96 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 97 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 98 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 99 select HAVE_EXIT_THREAD 100 select HAVE_FAST_GUP if ARM_LPAE 101 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 102 select HAVE_FUNCTION_ERROR_INJECTION 103 select HAVE_FUNCTION_GRAPH_TRACER 104 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 105 select HAVE_GCC_PLUGINS 106 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 107 select HAVE_IRQ_TIME_ACCOUNTING 108 select HAVE_KERNEL_GZIP 109 select HAVE_KERNEL_LZ4 110 select HAVE_KERNEL_LZMA 111 select HAVE_KERNEL_LZO 112 select HAVE_KERNEL_XZ 113 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 114 select HAVE_KRETPROBES if HAVE_KPROBES 115 select HAVE_MOD_ARCH_SPECIFIC 116 select HAVE_NMI 117 select HAVE_OPTPROBES if !THUMB2_KERNEL 118 select HAVE_PCI if MMU 119 select HAVE_PERF_EVENTS 120 select HAVE_PERF_REGS 121 select HAVE_PERF_USER_STACK_DUMP 122 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 123 select HAVE_REGS_AND_STACK_ACCESS_API 124 select HAVE_RSEQ 125 select HAVE_STACKPROTECTOR 126 select HAVE_SYSCALL_TRACEPOINTS 127 select HAVE_UID16 128 select HAVE_VIRT_CPU_ACCOUNTING_GEN 129 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 130 select IRQ_FORCED_THREADING 131 select LOCK_MM_AND_FIND_VMA 132 select MODULES_USE_ELF_REL 133 select NEED_DMA_MAP_STATE 134 select OF_EARLY_FLATTREE if OF 135 select OLD_SIGACTION 136 select OLD_SIGSUSPEND3 137 select PCI_DOMAINS_GENERIC if PCI 138 select PCI_SYSCALL if PCI 139 select PERF_USE_VMALLOC 140 select RTC_LIB 141 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 142 select SYS_SUPPORTS_APM_EMULATION 143 select THREAD_INFO_IN_TASK 144 select TIMER_OF if OF 145 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 146 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 147 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 148 # Above selects are sorted alphabetically; please add new ones 149 # according to that. Thanks. 150 help 151 The ARM series is a line of low-power-consumption RISC chip designs 152 licensed by ARM Ltd and targeted at embedded applications and 153 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 154 manufactured, but legacy ARM-based PC hardware remains popular in 155 Europe. There is an ARM Linux project with a web page at 156 <http://www.arm.linux.org.uk/>. 157 158config ARM_HAS_GROUP_RELOCS 159 def_bool y 160 depends on !LD_IS_LLD || LLD_VERSION >= 140000 161 depends on !COMPILE_TEST 162 help 163 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 164 relocations, which have been around for a long time, but were not 165 supported in LLD until version 14. The combined range is -/+ 256 MiB, 166 which is usually sufficient, but not for allyesconfig, so we disable 167 this feature when doing compile testing. 168 169config ARM_DMA_USE_IOMMU 170 bool 171 select NEED_SG_DMA_LENGTH 172 173if ARM_DMA_USE_IOMMU 174 175config ARM_DMA_IOMMU_ALIGNMENT 176 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 177 range 4 9 178 default 8 179 help 180 DMA mapping framework by default aligns all buffers to the smallest 181 PAGE_SIZE order which is greater than or equal to the requested buffer 182 size. This works well for buffers up to a few hundreds kilobytes, but 183 for larger buffers it just a waste of address space. Drivers which has 184 relatively small addressing window (like 64Mib) might run out of 185 virtual space with just a few allocations. 186 187 With this parameter you can specify the maximum PAGE_SIZE order for 188 DMA IOMMU buffers. Larger buffers will be aligned only to this 189 specified order. The order is expressed as a power of two multiplied 190 by the PAGE_SIZE. 191 192endif 193 194config SYS_SUPPORTS_APM_EMULATION 195 bool 196 197config HAVE_TCM 198 bool 199 select GENERIC_ALLOCATOR 200 201config HAVE_PROC_CPU 202 bool 203 204config NO_IOPORT_MAP 205 bool 206 207config SBUS 208 bool 209 210config STACKTRACE_SUPPORT 211 bool 212 default y 213 214config LOCKDEP_SUPPORT 215 bool 216 default y 217 218config ARCH_HAS_ILOG2_U32 219 bool 220 221config ARCH_HAS_ILOG2_U64 222 bool 223 224config ARCH_HAS_BANDGAP 225 bool 226 227config FIX_EARLYCON_MEM 228 def_bool y if MMU 229 230config GENERIC_HWEIGHT 231 bool 232 default y 233 234config GENERIC_CALIBRATE_DELAY 235 bool 236 default y 237 238config ARCH_MAY_HAVE_PC_FDC 239 bool 240 241config ARCH_SUPPORTS_UPROBES 242 def_bool y 243 244config GENERIC_ISA_DMA 245 bool 246 247config FIQ 248 bool 249 250config ARCH_MTD_XIP 251 bool 252 253config ARM_PATCH_PHYS_VIRT 254 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 255 default y 256 depends on MMU 257 help 258 Patch phys-to-virt and virt-to-phys translation functions at 259 boot and module load time according to the position of the 260 kernel in system memory. 261 262 This can only be used with non-XIP MMU kernels where the base 263 of physical memory is at a 2 MiB boundary. 264 265 Only disable this option if you know that you do not require 266 this feature (eg, building a kernel for a single machine) and 267 you need to shrink the kernel to the minimal size. 268 269config NEED_MACH_IO_H 270 bool 271 help 272 Select this when mach/io.h is required to provide special 273 definitions for this platform. The need for mach/io.h should 274 be avoided when possible. 275 276config NEED_MACH_MEMORY_H 277 bool 278 help 279 Select this when mach/memory.h is required to provide special 280 definitions for this platform. The need for mach/memory.h should 281 be avoided when possible. 282 283config PHYS_OFFSET 284 hex "Physical address of main memory" if MMU 285 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 286 default DRAM_BASE if !MMU 287 default 0x00000000 if ARCH_FOOTBRIDGE 288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 289 default 0xa0000000 if ARCH_PXA 290 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 291 default 0 292 help 293 Please provide the physical address corresponding to the 294 location of main memory in your system. 295 296config GENERIC_BUG 297 def_bool y 298 depends on BUG 299 300config PGTABLE_LEVELS 301 int 302 default 3 if ARM_LPAE 303 default 2 304 305menu "System Type" 306 307config MMU 308 bool "MMU-based Paged Memory Management Support" 309 default y 310 help 311 Select if you want MMU-based virtualised addressing space 312 support by paged memory management. If unsure, say 'Y'. 313 314config ARM_SINGLE_ARMV7M 315 def_bool !MMU 316 select ARM_NVIC 317 select CPU_V7M 318 select NO_IOPORT_MAP 319 320config ARCH_MMAP_RND_BITS_MIN 321 default 8 322 323config ARCH_MMAP_RND_BITS_MAX 324 default 14 if PAGE_OFFSET=0x40000000 325 default 15 if PAGE_OFFSET=0x80000000 326 default 16 327 328config ARCH_MULTIPLATFORM 329 bool "Require kernel to be portable to multiple machines" if EXPERT 330 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 331 default y 332 help 333 In general, all Arm machines can be supported in a single 334 kernel image, covering either Armv4/v5 or Armv6/v7. 335 336 However, some configuration options require hardcoding machine 337 specific physical addresses or enable errata workarounds that may 338 break other machines. 339 340 Selecting N here allows using those options, including 341 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 342 343source "arch/arm/Kconfig.platforms" 344 345# 346# This is sorted alphabetically by mach-* pathname. However, plat-* 347# Kconfigs may be included either alphabetically (according to the 348# plat- suffix) or along side the corresponding mach-* source. 349# 350source "arch/arm/mach-actions/Kconfig" 351 352source "arch/arm/mach-alpine/Kconfig" 353 354source "arch/arm/mach-artpec/Kconfig" 355 356source "arch/arm/mach-aspeed/Kconfig" 357 358source "arch/arm/mach-at91/Kconfig" 359 360source "arch/arm/mach-axxia/Kconfig" 361 362source "arch/arm/mach-bcm/Kconfig" 363 364source "arch/arm/mach-berlin/Kconfig" 365 366source "arch/arm/mach-clps711x/Kconfig" 367 368source "arch/arm/mach-davinci/Kconfig" 369 370source "arch/arm/mach-digicolor/Kconfig" 371 372source "arch/arm/mach-dove/Kconfig" 373 374source "arch/arm/mach-ep93xx/Kconfig" 375 376source "arch/arm/mach-exynos/Kconfig" 377 378source "arch/arm/mach-footbridge/Kconfig" 379 380source "arch/arm/mach-gemini/Kconfig" 381 382source "arch/arm/mach-highbank/Kconfig" 383 384source "arch/arm/mach-hisi/Kconfig" 385 386source "arch/arm/mach-hpe/Kconfig" 387 388source "arch/arm/mach-imx/Kconfig" 389 390source "arch/arm/mach-ixp4xx/Kconfig" 391 392source "arch/arm/mach-keystone/Kconfig" 393 394source "arch/arm/mach-lpc32xx/Kconfig" 395 396source "arch/arm/mach-mediatek/Kconfig" 397 398source "arch/arm/mach-meson/Kconfig" 399 400source "arch/arm/mach-milbeaut/Kconfig" 401 402source "arch/arm/mach-mmp/Kconfig" 403 404source "arch/arm/mach-mstar/Kconfig" 405 406source "arch/arm/mach-mv78xx0/Kconfig" 407 408source "arch/arm/mach-mvebu/Kconfig" 409 410source "arch/arm/mach-mxs/Kconfig" 411 412source "arch/arm/mach-nomadik/Kconfig" 413 414source "arch/arm/mach-npcm/Kconfig" 415 416source "arch/arm/mach-omap1/Kconfig" 417 418source "arch/arm/mach-omap2/Kconfig" 419 420source "arch/arm/mach-orion5x/Kconfig" 421 422source "arch/arm/mach-pxa/Kconfig" 423 424source "arch/arm/mach-qcom/Kconfig" 425 426source "arch/arm/mach-realtek/Kconfig" 427 428source "arch/arm/mach-rpc/Kconfig" 429 430source "arch/arm/mach-rockchip/Kconfig" 431 432source "arch/arm/mach-s3c/Kconfig" 433 434source "arch/arm/mach-s5pv210/Kconfig" 435 436source "arch/arm/mach-sa1100/Kconfig" 437 438source "arch/arm/mach-shmobile/Kconfig" 439 440source "arch/arm/mach-socfpga/Kconfig" 441 442source "arch/arm/mach-spear/Kconfig" 443 444source "arch/arm/mach-sti/Kconfig" 445 446source "arch/arm/mach-stm32/Kconfig" 447 448source "arch/arm/mach-sunxi/Kconfig" 449 450source "arch/arm/mach-tegra/Kconfig" 451 452source "arch/arm/mach-ux500/Kconfig" 453 454source "arch/arm/mach-versatile/Kconfig" 455 456source "arch/arm/mach-vt8500/Kconfig" 457 458source "arch/arm/mach-zynq/Kconfig" 459 460# ARMv7-M architecture 461config ARCH_LPC18XX 462 bool "NXP LPC18xx/LPC43xx" 463 depends on ARM_SINGLE_ARMV7M 464 select ARCH_HAS_RESET_CONTROLLER 465 select ARM_AMBA 466 select CLKSRC_LPC32XX 467 select PINCTRL 468 help 469 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 470 high performance microcontrollers. 471 472config ARCH_MPS2 473 bool "ARM MPS2 platform" 474 depends on ARM_SINGLE_ARMV7M 475 select ARM_AMBA 476 select CLKSRC_MPS2 477 help 478 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 479 with a range of available cores like Cortex-M3/M4/M7. 480 481 Please, note that depends which Application Note is used memory map 482 for the platform may vary, so adjustment of RAM base might be needed. 483 484# Definitions to make life easier 485config ARCH_ACORN 486 bool 487 488config PLAT_ORION 489 bool 490 select CLKSRC_MMIO 491 select GENERIC_IRQ_CHIP 492 select IRQ_DOMAIN 493 494config PLAT_ORION_LEGACY 495 bool 496 select PLAT_ORION 497 498config PLAT_VERSATILE 499 bool 500 501source "arch/arm/mm/Kconfig" 502 503config IWMMXT 504 bool "Enable iWMMXt support" 505 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 506 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 507 help 508 Enable support for iWMMXt context switching at run time if 509 running on a CPU that supports it. 510 511if !MMU 512source "arch/arm/Kconfig-nommu" 513endif 514 515config PJ4B_ERRATA_4742 516 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 517 depends on CPU_PJ4B && MACH_ARMADA_370 518 default y 519 help 520 When coming out of either a Wait for Interrupt (WFI) or a Wait for 521 Event (WFE) IDLE states, a specific timing sensitivity exists between 522 the retiring WFI/WFE instructions and the newly issued subsequent 523 instructions. This sensitivity can result in a CPU hang scenario. 524 Workaround: 525 The software must insert either a Data Synchronization Barrier (DSB) 526 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 527 instruction 528 529config ARM_ERRATA_326103 530 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 531 depends on CPU_V6 532 help 533 Executing a SWP instruction to read-only memory does not set bit 11 534 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 535 treat the access as a read, preventing a COW from occurring and 536 causing the faulting task to livelock. 537 538config ARM_ERRATA_411920 539 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 540 depends on CPU_V6 || CPU_V6K 541 help 542 Invalidation of the Instruction Cache operation can 543 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 544 It does not affect the MPCore. This option enables the ARM Ltd. 545 recommended workaround. 546 547config ARM_ERRATA_430973 548 bool "ARM errata: Stale prediction on replaced interworking branch" 549 depends on CPU_V7 550 help 551 This option enables the workaround for the 430973 Cortex-A8 552 r1p* erratum. If a code sequence containing an ARM/Thumb 553 interworking branch is replaced with another code sequence at the 554 same virtual address, whether due to self-modifying code or virtual 555 to physical address re-mapping, Cortex-A8 does not recover from the 556 stale interworking branch prediction. This results in Cortex-A8 557 executing the new code sequence in the incorrect ARM or Thumb state. 558 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 559 and also flushes the branch target cache at every context switch. 560 Note that setting specific bits in the ACTLR register may not be 561 available in non-secure mode. 562 563config ARM_ERRATA_458693 564 bool "ARM errata: Processor deadlock when a false hazard is created" 565 depends on CPU_V7 566 depends on !ARCH_MULTIPLATFORM 567 help 568 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 569 erratum. For very specific sequences of memory operations, it is 570 possible for a hazard condition intended for a cache line to instead 571 be incorrectly associated with a different cache line. This false 572 hazard might then cause a processor deadlock. The workaround enables 573 the L1 caching of the NEON accesses and disables the PLD instruction 574 in the ACTLR register. Note that setting specific bits in the ACTLR 575 register may not be available in non-secure mode and thus is not 576 available on a multiplatform kernel. This should be applied by the 577 bootloader instead. 578 579config ARM_ERRATA_460075 580 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 581 depends on CPU_V7 582 depends on !ARCH_MULTIPLATFORM 583 help 584 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 585 erratum. Any asynchronous access to the L2 cache may encounter a 586 situation in which recent store transactions to the L2 cache are lost 587 and overwritten with stale memory contents from external memory. The 588 workaround disables the write-allocate mode for the L2 cache via the 589 ACTLR register. Note that setting specific bits in the ACTLR register 590 may not be available in non-secure mode and thus is not available on 591 a multiplatform kernel. This should be applied by the bootloader 592 instead. 593 594config ARM_ERRATA_742230 595 bool "ARM errata: DMB operation may be faulty" 596 depends on CPU_V7 && SMP 597 depends on !ARCH_MULTIPLATFORM 598 help 599 This option enables the workaround for the 742230 Cortex-A9 600 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 601 between two write operations may not ensure the correct visibility 602 ordering of the two writes. This workaround sets a specific bit in 603 the diagnostic register of the Cortex-A9 which causes the DMB 604 instruction to behave as a DSB, ensuring the correct behaviour of 605 the two writes. Note that setting specific bits in the diagnostics 606 register may not be available in non-secure mode and thus is not 607 available on a multiplatform kernel. This should be applied by the 608 bootloader instead. 609 610config ARM_ERRATA_742231 611 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 612 depends on CPU_V7 && SMP 613 depends on !ARCH_MULTIPLATFORM 614 help 615 This option enables the workaround for the 742231 Cortex-A9 616 (r2p0..r2p2) erratum. Under certain conditions, specific to the 617 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 618 accessing some data located in the same cache line, may get corrupted 619 data due to bad handling of the address hazard when the line gets 620 replaced from one of the CPUs at the same time as another CPU is 621 accessing it. This workaround sets specific bits in the diagnostic 622 register of the Cortex-A9 which reduces the linefill issuing 623 capabilities of the processor. Note that setting specific bits in the 624 diagnostics register may not be available in non-secure mode and thus 625 is not available on a multiplatform kernel. This should be applied by 626 the bootloader instead. 627 628config ARM_ERRATA_643719 629 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 630 depends on CPU_V7 && SMP 631 default y 632 help 633 This option enables the workaround for the 643719 Cortex-A9 (prior to 634 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 635 register returns zero when it should return one. The workaround 636 corrects this value, ensuring cache maintenance operations which use 637 it behave as intended and avoiding data corruption. 638 639config ARM_ERRATA_720789 640 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 641 depends on CPU_V7 642 help 643 This option enables the workaround for the 720789 Cortex-A9 (prior to 644 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 645 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 646 As a consequence of this erratum, some TLB entries which should be 647 invalidated are not, resulting in an incoherency in the system page 648 tables. The workaround changes the TLB flushing routines to invalidate 649 entries regardless of the ASID. 650 651config ARM_ERRATA_743622 652 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 653 depends on CPU_V7 654 depends on !ARCH_MULTIPLATFORM 655 help 656 This option enables the workaround for the 743622 Cortex-A9 657 (r2p*) erratum. Under very rare conditions, a faulty 658 optimisation in the Cortex-A9 Store Buffer may lead to data 659 corruption. This workaround sets a specific bit in the diagnostic 660 register of the Cortex-A9 which disables the Store Buffer 661 optimisation, preventing the defect from occurring. This has no 662 visible impact on the overall performance or power consumption of the 663 processor. Note that setting specific bits in the diagnostics register 664 may not be available in non-secure mode and thus is not available on a 665 multiplatform kernel. This should be applied by the bootloader instead. 666 667config ARM_ERRATA_751472 668 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 669 depends on CPU_V7 670 depends on !ARCH_MULTIPLATFORM 671 help 672 This option enables the workaround for the 751472 Cortex-A9 (prior 673 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 674 completion of a following broadcasted operation if the second 675 operation is received by a CPU before the ICIALLUIS has completed, 676 potentially leading to corrupted entries in the cache or TLB. 677 Note that setting specific bits in the diagnostics register may 678 not be available in non-secure mode and thus is not available on 679 a multiplatform kernel. This should be applied by the bootloader 680 instead. 681 682config ARM_ERRATA_754322 683 bool "ARM errata: possible faulty MMU translations following an ASID switch" 684 depends on CPU_V7 685 help 686 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 687 r3p*) erratum. A speculative memory access may cause a page table walk 688 which starts prior to an ASID switch but completes afterwards. This 689 can populate the micro-TLB with a stale entry which may be hit with 690 the new ASID. This workaround places two dsb instructions in the mm 691 switching code so that no page table walks can cross the ASID switch. 692 693config ARM_ERRATA_754327 694 bool "ARM errata: no automatic Store Buffer drain" 695 depends on CPU_V7 && SMP 696 help 697 This option enables the workaround for the 754327 Cortex-A9 (prior to 698 r2p0) erratum. The Store Buffer does not have any automatic draining 699 mechanism and therefore a livelock may occur if an external agent 700 continuously polls a memory location waiting to observe an update. 701 This workaround defines cpu_relax() as smp_mb(), preventing correctly 702 written polling loops from denying visibility of updates to memory. 703 704config ARM_ERRATA_364296 705 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 706 depends on CPU_V6 707 help 708 This options enables the workaround for the 364296 ARM1136 709 r0p2 erratum (possible cache data corruption with 710 hit-under-miss enabled). It sets the undocumented bit 31 in 711 the auxiliary control register and the FI bit in the control 712 register, thus disabling hit-under-miss without putting the 713 processor into full low interrupt latency mode. ARM11MPCore 714 is not affected. 715 716config ARM_ERRATA_764369 717 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 718 depends on CPU_V7 && SMP 719 help 720 This option enables the workaround for erratum 764369 721 affecting Cortex-A9 MPCore with two or more processors (all 722 current revisions). Under certain timing circumstances, a data 723 cache line maintenance operation by MVA targeting an Inner 724 Shareable memory region may fail to proceed up to either the 725 Point of Coherency or to the Point of Unification of the 726 system. This workaround adds a DSB instruction before the 727 relevant cache maintenance functions and sets a specific bit 728 in the diagnostic control register of the SCU. 729 730config ARM_ERRATA_764319 731 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 732 depends on CPU_V7 733 help 734 This option enables the workaround for the 764319 Cortex A-9 erratum. 735 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 736 unexpected Undefined Instruction exception when the DBGSWENABLE 737 external pin is set to 0, even when the CP14 accesses are performed 738 from a privileged mode. This work around catches the exception in a 739 way the kernel does not stop execution. 740 741config ARM_ERRATA_775420 742 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 743 depends on CPU_V7 744 help 745 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 746 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 747 operation aborts with MMU exception, it might cause the processor 748 to deadlock. This workaround puts DSB before executing ISB if 749 an abort may occur on cache maintenance. 750 751config ARM_ERRATA_798181 752 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 753 depends on CPU_V7 && SMP 754 help 755 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 756 adequately shooting down all use of the old entries. This 757 option enables the Linux kernel workaround for this erratum 758 which sends an IPI to the CPUs that are running the same ASID 759 as the one being invalidated. 760 761config ARM_ERRATA_773022 762 bool "ARM errata: incorrect instructions may be executed from loop buffer" 763 depends on CPU_V7 764 help 765 This option enables the workaround for the 773022 Cortex-A15 766 (up to r0p4) erratum. In certain rare sequences of code, the 767 loop buffer may deliver incorrect instructions. This 768 workaround disables the loop buffer to avoid the erratum. 769 770config ARM_ERRATA_818325_852422 771 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 772 depends on CPU_V7 773 help 774 This option enables the workaround for: 775 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 776 instruction might deadlock. Fixed in r0p1. 777 - Cortex-A12 852422: Execution of a sequence of instructions might 778 lead to either a data corruption or a CPU deadlock. Not fixed in 779 any Cortex-A12 cores yet. 780 This workaround for all both errata involves setting bit[12] of the 781 Feature Register. This bit disables an optimisation applied to a 782 sequence of 2 instructions that use opposing condition codes. 783 784config ARM_ERRATA_821420 785 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 786 depends on CPU_V7 787 help 788 This option enables the workaround for the 821420 Cortex-A12 789 (all revs) erratum. In very rare timing conditions, a sequence 790 of VMOV to Core registers instructions, for which the second 791 one is in the shadow of a branch or abort, can lead to a 792 deadlock when the VMOV instructions are issued out-of-order. 793 794config ARM_ERRATA_825619 795 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 796 depends on CPU_V7 797 help 798 This option enables the workaround for the 825619 Cortex-A12 799 (all revs) erratum. Within rare timing constraints, executing a 800 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 801 and Device/Strongly-Ordered loads and stores might cause deadlock 802 803config ARM_ERRATA_857271 804 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 805 depends on CPU_V7 806 help 807 This option enables the workaround for the 857271 Cortex-A12 808 (all revs) erratum. Under very rare timing conditions, the CPU might 809 hang. The workaround is expected to have a < 1% performance impact. 810 811config ARM_ERRATA_852421 812 bool "ARM errata: A17: DMB ST might fail to create order between stores" 813 depends on CPU_V7 814 help 815 This option enables the workaround for the 852421 Cortex-A17 816 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 817 execution of a DMB ST instruction might fail to properly order 818 stores from GroupA and stores from GroupB. 819 820config ARM_ERRATA_852423 821 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 822 depends on CPU_V7 823 help 824 This option enables the workaround for: 825 - Cortex-A17 852423: Execution of a sequence of instructions might 826 lead to either a data corruption or a CPU deadlock. Not fixed in 827 any Cortex-A17 cores yet. 828 This is identical to Cortex-A12 erratum 852422. It is a separate 829 config option from the A12 erratum due to the way errata are checked 830 for and handled. 831 832config ARM_ERRATA_857272 833 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 834 depends on CPU_V7 835 help 836 This option enables the workaround for the 857272 Cortex-A17 erratum. 837 This erratum is not known to be fixed in any A17 revision. 838 This is identical to Cortex-A12 erratum 857271. It is a separate 839 config option from the A12 erratum due to the way errata are checked 840 for and handled. 841 842endmenu 843 844source "arch/arm/common/Kconfig" 845 846menu "Bus support" 847 848config ISA 849 bool 850 help 851 Find out whether you have ISA slots on your motherboard. ISA is the 852 name of a bus system, i.e. the way the CPU talks to the other stuff 853 inside your box. Other bus systems are PCI, EISA, MicroChannel 854 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 855 newer boards don't support it. If you have ISA, say Y, otherwise N. 856 857# Select ISA DMA interface 858config ISA_DMA_API 859 bool 860 861config ARM_ERRATA_814220 862 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 863 depends on CPU_V7 864 help 865 The v7 ARM states that all cache and branch predictor maintenance 866 operations that do not specify an address execute, relative to 867 each other, in program order. 868 However, because of this erratum, an L2 set/way cache maintenance 869 operation can overtake an L1 set/way cache maintenance operation. 870 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 871 r0p4, r0p5. 872 873endmenu 874 875menu "Kernel Features" 876 877config HAVE_SMP 878 bool 879 help 880 This option should be selected by machines which have an SMP- 881 capable CPU. 882 883 The only effect of this option is to make the SMP-related 884 options available to the user for configuration. 885 886config SMP 887 bool "Symmetric Multi-Processing" 888 depends on CPU_V6K || CPU_V7 889 depends on HAVE_SMP 890 depends on MMU || ARM_MPU 891 select IRQ_WORK 892 help 893 This enables support for systems with more than one CPU. If you have 894 a system with only one CPU, say N. If you have a system with more 895 than one CPU, say Y. 896 897 If you say N here, the kernel will run on uni- and multiprocessor 898 machines, but will use only one CPU of a multiprocessor machine. If 899 you say Y here, the kernel will run on many, but not all, 900 uniprocessor machines. On a uniprocessor machine, the kernel 901 will run faster if you say N here. 902 903 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 904 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 905 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 906 907 If you don't know what to do here, say N. 908 909config SMP_ON_UP 910 bool "Allow booting SMP kernel on uniprocessor systems" 911 depends on SMP && MMU 912 default y 913 help 914 SMP kernels contain instructions which fail on non-SMP processors. 915 Enabling this option allows the kernel to modify itself to make 916 these instructions safe. Disabling it allows about 1K of space 917 savings. 918 919 If you don't know what to do here, say Y. 920 921 922config CURRENT_POINTER_IN_TPIDRURO 923 def_bool y 924 depends on CPU_32v6K && !CPU_V6 925 926config IRQSTACKS 927 def_bool y 928 select HAVE_IRQ_EXIT_ON_IRQ_STACK 929 select HAVE_SOFTIRQ_ON_OWN_STACK 930 931config ARM_CPU_TOPOLOGY 932 bool "Support cpu topology definition" 933 depends on SMP && CPU_V7 934 default y 935 help 936 Support ARM cpu topology definition. The MPIDR register defines 937 affinity between processors which is then used to describe the cpu 938 topology of an ARM System. 939 940config SCHED_MC 941 bool "Multi-core scheduler support" 942 depends on ARM_CPU_TOPOLOGY 943 help 944 Multi-core scheduler support improves the CPU scheduler's decision 945 making when dealing with multi-core CPU chips at a cost of slightly 946 increased overhead in some places. If unsure say N here. 947 948config SCHED_SMT 949 bool "SMT scheduler support" 950 depends on ARM_CPU_TOPOLOGY 951 help 952 Improves the CPU scheduler's decision making when dealing with 953 MultiThreading at a cost of slightly increased overhead in some 954 places. If unsure say N here. 955 956config HAVE_ARM_SCU 957 bool 958 help 959 This option enables support for the ARM snoop control unit 960 961config HAVE_ARM_ARCH_TIMER 962 bool "Architected timer support" 963 depends on CPU_V7 964 select ARM_ARCH_TIMER 965 help 966 This option enables support for the ARM architected timer 967 968config HAVE_ARM_TWD 969 bool 970 help 971 This options enables support for the ARM timer and watchdog unit 972 973config MCPM 974 bool "Multi-Cluster Power Management" 975 depends on CPU_V7 && SMP 976 help 977 This option provides the common power management infrastructure 978 for (multi-)cluster based systems, such as big.LITTLE based 979 systems. 980 981config MCPM_QUAD_CLUSTER 982 bool 983 depends on MCPM 984 help 985 To avoid wasting resources unnecessarily, MCPM only supports up 986 to 2 clusters by default. 987 Platforms with 3 or 4 clusters that use MCPM must select this 988 option to allow the additional clusters to be managed. 989 990config BIG_LITTLE 991 bool "big.LITTLE support (Experimental)" 992 depends on CPU_V7 && SMP 993 select MCPM 994 help 995 This option enables support selections for the big.LITTLE 996 system architecture. 997 998config BL_SWITCHER 999 bool "big.LITTLE switcher support" 1000 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1001 select CPU_PM 1002 help 1003 The big.LITTLE "switcher" provides the core functionality to 1004 transparently handle transition between a cluster of A15's 1005 and a cluster of A7's in a big.LITTLE system. 1006 1007config BL_SWITCHER_DUMMY_IF 1008 tristate "Simple big.LITTLE switcher user interface" 1009 depends on BL_SWITCHER && DEBUG_KERNEL 1010 help 1011 This is a simple and dummy char dev interface to control 1012 the big.LITTLE switcher core code. It is meant for 1013 debugging purposes only. 1014 1015choice 1016 prompt "Memory split" 1017 depends on MMU 1018 default VMSPLIT_3G 1019 help 1020 Select the desired split between kernel and user memory. 1021 1022 If you are not absolutely sure what you are doing, leave this 1023 option alone! 1024 1025 config VMSPLIT_3G 1026 bool "3G/1G user/kernel split" 1027 config VMSPLIT_3G_OPT 1028 depends on !ARM_LPAE 1029 bool "3G/1G user/kernel split (for full 1G low memory)" 1030 config VMSPLIT_2G 1031 bool "2G/2G user/kernel split" 1032 config VMSPLIT_1G 1033 bool "1G/3G user/kernel split" 1034endchoice 1035 1036config PAGE_OFFSET 1037 hex 1038 default PHYS_OFFSET if !MMU 1039 default 0x40000000 if VMSPLIT_1G 1040 default 0x80000000 if VMSPLIT_2G 1041 default 0xB0000000 if VMSPLIT_3G_OPT 1042 default 0xC0000000 1043 1044config KASAN_SHADOW_OFFSET 1045 hex 1046 depends on KASAN 1047 default 0x1f000000 if PAGE_OFFSET=0x40000000 1048 default 0x5f000000 if PAGE_OFFSET=0x80000000 1049 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1050 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1051 default 0xffffffff 1052 1053config NR_CPUS 1054 int "Maximum number of CPUs (2-32)" 1055 range 2 16 if DEBUG_KMAP_LOCAL 1056 range 2 32 if !DEBUG_KMAP_LOCAL 1057 depends on SMP 1058 default "4" 1059 help 1060 The maximum number of CPUs that the kernel can support. 1061 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1062 debugging is enabled, which uses half of the per-CPU fixmap 1063 slots as guard regions. 1064 1065config HOTPLUG_CPU 1066 bool "Support for hot-pluggable CPUs" 1067 depends on SMP 1068 select GENERIC_IRQ_MIGRATION 1069 help 1070 Say Y here to experiment with turning CPUs off and on. CPUs 1071 can be controlled through /sys/devices/system/cpu. 1072 1073config ARM_PSCI 1074 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1075 depends on HAVE_ARM_SMCCC 1076 select ARM_PSCI_FW 1077 help 1078 Say Y here if you want Linux to communicate with system firmware 1079 implementing the PSCI specification for CPU-centric power 1080 management operations described in ARM document number ARM DEN 1081 0022A ("Power State Coordination Interface System Software on 1082 ARM processors"). 1083 1084config HZ_FIXED 1085 int 1086 default 128 if SOC_AT91RM9200 1087 default 0 1088 1089choice 1090 depends on HZ_FIXED = 0 1091 prompt "Timer frequency" 1092 1093config HZ_100 1094 bool "100 Hz" 1095 1096config HZ_200 1097 bool "200 Hz" 1098 1099config HZ_250 1100 bool "250 Hz" 1101 1102config HZ_300 1103 bool "300 Hz" 1104 1105config HZ_500 1106 bool "500 Hz" 1107 1108config HZ_1000 1109 bool "1000 Hz" 1110 1111endchoice 1112 1113config HZ 1114 int 1115 default HZ_FIXED if HZ_FIXED != 0 1116 default 100 if HZ_100 1117 default 200 if HZ_200 1118 default 250 if HZ_250 1119 default 300 if HZ_300 1120 default 500 if HZ_500 1121 default 1000 1122 1123config SCHED_HRTICK 1124 def_bool HIGH_RES_TIMERS 1125 1126config THUMB2_KERNEL 1127 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1128 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1129 default y if CPU_THUMBONLY 1130 select ARM_UNWIND 1131 help 1132 By enabling this option, the kernel will be compiled in 1133 Thumb-2 mode. 1134 1135 If unsure, say N. 1136 1137config ARM_PATCH_IDIV 1138 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1139 depends on CPU_32v7 1140 default y 1141 help 1142 The ARM compiler inserts calls to __aeabi_idiv() and 1143 __aeabi_uidiv() when it needs to perform division on signed 1144 and unsigned integers. Some v7 CPUs have support for the sdiv 1145 and udiv instructions that can be used to implement those 1146 functions. 1147 1148 Enabling this option allows the kernel to modify itself to 1149 replace the first two instructions of these library functions 1150 with the sdiv or udiv plus "bx lr" instructions when the CPU 1151 it is running on supports them. Typically this will be faster 1152 and less power intensive than running the original library 1153 code to do integer division. 1154 1155config AEABI 1156 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1157 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1158 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1159 help 1160 This option allows for the kernel to be compiled using the latest 1161 ARM ABI (aka EABI). This is only useful if you are using a user 1162 space environment that is also compiled with EABI. 1163 1164 Since there are major incompatibilities between the legacy ABI and 1165 EABI, especially with regard to structure member alignment, this 1166 option also changes the kernel syscall calling convention to 1167 disambiguate both ABIs and allow for backward compatibility support 1168 (selected with CONFIG_OABI_COMPAT). 1169 1170 To use this you need GCC version 4.0.0 or later. 1171 1172config OABI_COMPAT 1173 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1174 depends on AEABI && !THUMB2_KERNEL 1175 help 1176 This option preserves the old syscall interface along with the 1177 new (ARM EABI) one. It also provides a compatibility layer to 1178 intercept syscalls that have structure arguments which layout 1179 in memory differs between the legacy ABI and the new ARM EABI 1180 (only for non "thumb" binaries). This option adds a tiny 1181 overhead to all syscalls and produces a slightly larger kernel. 1182 1183 The seccomp filter system will not be available when this is 1184 selected, since there is no way yet to sensibly distinguish 1185 between calling conventions during filtering. 1186 1187 If you know you'll be using only pure EABI user space then you 1188 can say N here. If this option is not selected and you attempt 1189 to execute a legacy ABI binary then the result will be 1190 UNPREDICTABLE (in fact it can be predicted that it won't work 1191 at all). If in doubt say N. 1192 1193config ARCH_SELECT_MEMORY_MODEL 1194 def_bool y 1195 1196config ARCH_FLATMEM_ENABLE 1197 def_bool !(ARCH_RPC || ARCH_SA1100) 1198 1199config ARCH_SPARSEMEM_ENABLE 1200 def_bool !ARCH_FOOTBRIDGE 1201 select SPARSEMEM_STATIC if SPARSEMEM 1202 1203config HIGHMEM 1204 bool "High Memory Support" 1205 depends on MMU 1206 select KMAP_LOCAL 1207 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1208 help 1209 The address space of ARM processors is only 4 Gigabytes large 1210 and it has to accommodate user address space, kernel address 1211 space as well as some memory mapped IO. That means that, if you 1212 have a large amount of physical memory and/or IO, not all of the 1213 memory can be "permanently mapped" by the kernel. The physical 1214 memory that is not permanently mapped is called "high memory". 1215 1216 Depending on the selected kernel/user memory split, minimum 1217 vmalloc space and actual amount of RAM, you may not need this 1218 option which should result in a slightly faster kernel. 1219 1220 If unsure, say n. 1221 1222config HIGHPTE 1223 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1224 depends on HIGHMEM 1225 default y 1226 help 1227 The VM uses one page of physical memory for each page table. 1228 For systems with a lot of processes, this can use a lot of 1229 precious low memory, eventually leading to low memory being 1230 consumed by page tables. Setting this option will allow 1231 user-space 2nd level page tables to reside in high memory. 1232 1233config CPU_SW_DOMAIN_PAN 1234 bool "Enable use of CPU domains to implement privileged no-access" 1235 depends on MMU && !ARM_LPAE 1236 default y 1237 help 1238 Increase kernel security by ensuring that normal kernel accesses 1239 are unable to access userspace addresses. This can help prevent 1240 use-after-free bugs becoming an exploitable privilege escalation 1241 by ensuring that magic values (such as LIST_POISON) will always 1242 fault when dereferenced. 1243 1244 CPUs with low-vector mappings use a best-efforts implementation. 1245 Their lower 1MB needs to remain accessible for the vectors, but 1246 the remainder of userspace will become appropriately inaccessible. 1247 1248config HW_PERF_EVENTS 1249 def_bool y 1250 depends on ARM_PMU 1251 1252config ARM_MODULE_PLTS 1253 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1254 depends on MODULES 1255 select KASAN_VMALLOC if KASAN 1256 default y 1257 help 1258 Allocate PLTs when loading modules so that jumps and calls whose 1259 targets are too far away for their relative offsets to be encoded 1260 in the instructions themselves can be bounced via veneers in the 1261 module's PLT. This allows modules to be allocated in the generic 1262 vmalloc area after the dedicated module memory area has been 1263 exhausted. The modules will use slightly more memory, but after 1264 rounding up to page size, the actual memory footprint is usually 1265 the same. 1266 1267 Disabling this is usually safe for small single-platform 1268 configurations. If unsure, say y. 1269 1270config ARCH_FORCE_MAX_ORDER 1271 int "Order of maximal physically contiguous allocations" 1272 default "11" if SOC_AM33XX 1273 default "8" if SA1111 1274 default "10" 1275 help 1276 The kernel page allocator limits the size of maximal physically 1277 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1278 defines the maximal power of two of number of pages that can be 1279 allocated as a single contiguous block. This option allows 1280 overriding the default setting when ability to allocate very 1281 large blocks of physically contiguous memory is required. 1282 1283 Don't change if unsure. 1284 1285config ALIGNMENT_TRAP 1286 def_bool CPU_CP15_MMU 1287 select HAVE_PROC_CPU if PROC_FS 1288 help 1289 ARM processors cannot fetch/store information which is not 1290 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1291 address divisible by 4. On 32-bit ARM processors, these non-aligned 1292 fetch/store instructions will be emulated in software if you say 1293 here, which has a severe performance impact. This is necessary for 1294 correct operation of some network protocols. With an IP-only 1295 configuration it is safe to say N, otherwise say Y. 1296 1297config UACCESS_WITH_MEMCPY 1298 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1299 depends on MMU 1300 default y if CPU_FEROCEON 1301 help 1302 Implement faster copy_to_user and clear_user methods for CPU 1303 cores where a 8-word STM instruction give significantly higher 1304 memory write throughput than a sequence of individual 32bit stores. 1305 1306 A possible side effect is a slight increase in scheduling latency 1307 between threads sharing the same address space if they invoke 1308 such copy operations with large buffers. 1309 1310 However, if the CPU data cache is using a write-allocate mode, 1311 this option is unlikely to provide any performance gain. 1312 1313config PARAVIRT 1314 bool "Enable paravirtualization code" 1315 help 1316 This changes the kernel so it can modify itself when it is run 1317 under a hypervisor, potentially improving performance significantly 1318 over full virtualization. 1319 1320config PARAVIRT_TIME_ACCOUNTING 1321 bool "Paravirtual steal time accounting" 1322 select PARAVIRT 1323 help 1324 Select this option to enable fine granularity task steal time 1325 accounting. Time spent executing other tasks in parallel with 1326 the current vCPU is discounted from the vCPU power. To account for 1327 that, there can be a small performance impact. 1328 1329 If in doubt, say N here. 1330 1331config XEN_DOM0 1332 def_bool y 1333 depends on XEN 1334 1335config XEN 1336 bool "Xen guest support on ARM" 1337 depends on ARM && AEABI && OF 1338 depends on CPU_V7 && !CPU_V6 1339 depends on !GENERIC_ATOMIC64 1340 depends on MMU 1341 select ARCH_DMA_ADDR_T_64BIT 1342 select ARM_PSCI 1343 select SWIOTLB 1344 select SWIOTLB_XEN 1345 select PARAVIRT 1346 help 1347 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1348 1349config CC_HAVE_STACKPROTECTOR_TLS 1350 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1351 1352config STACKPROTECTOR_PER_TASK 1353 bool "Use a unique stack canary value for each task" 1354 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1355 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1356 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1357 default y 1358 help 1359 Due to the fact that GCC uses an ordinary symbol reference from 1360 which to load the value of the stack canary, this value can only 1361 change at reboot time on SMP systems, and all tasks running in the 1362 kernel's address space are forced to use the same canary value for 1363 the entire duration that the system is up. 1364 1365 Enable this option to switch to a different method that uses a 1366 different canary value for each task. 1367 1368endmenu 1369 1370menu "Boot options" 1371 1372config USE_OF 1373 bool "Flattened Device Tree support" 1374 select IRQ_DOMAIN 1375 select OF 1376 help 1377 Include support for flattened device tree machine descriptions. 1378 1379config ARCH_WANT_FLAT_DTB_INSTALL 1380 def_bool y 1381 1382config ATAGS 1383 bool "Support for the traditional ATAGS boot data passing" 1384 default y 1385 help 1386 This is the traditional way of passing data to the kernel at boot 1387 time. If you are solely relying on the flattened device tree (or 1388 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1389 to remove ATAGS support from your kernel binary. 1390 1391config DEPRECATED_PARAM_STRUCT 1392 bool "Provide old way to pass kernel parameters" 1393 depends on ATAGS 1394 help 1395 This was deprecated in 2001 and announced to live on for 5 years. 1396 Some old boot loaders still use this way. 1397 1398# Compressed boot loader in ROM. Yes, we really want to ask about 1399# TEXT and BSS so we preserve their values in the config files. 1400config ZBOOT_ROM_TEXT 1401 hex "Compressed ROM boot loader base address" 1402 default 0x0 1403 help 1404 The physical address at which the ROM-able zImage is to be 1405 placed in the target. Platforms which normally make use of 1406 ROM-able zImage formats normally set this to a suitable 1407 value in their defconfig file. 1408 1409 If ZBOOT_ROM is not enabled, this has no effect. 1410 1411config ZBOOT_ROM_BSS 1412 hex "Compressed ROM boot loader BSS address" 1413 default 0x0 1414 help 1415 The base address of an area of read/write memory in the target 1416 for the ROM-able zImage which must be available while the 1417 decompressor is running. It must be large enough to hold the 1418 entire decompressed kernel plus an additional 128 KiB. 1419 Platforms which normally make use of ROM-able zImage formats 1420 normally set this to a suitable value in their defconfig file. 1421 1422 If ZBOOT_ROM is not enabled, this has no effect. 1423 1424config ZBOOT_ROM 1425 bool "Compressed boot loader in ROM/flash" 1426 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1427 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1428 help 1429 Say Y here if you intend to execute your compressed kernel image 1430 (zImage) directly from ROM or flash. If unsure, say N. 1431 1432config ARM_APPENDED_DTB 1433 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1434 depends on OF 1435 help 1436 With this option, the boot code will look for a device tree binary 1437 (DTB) appended to zImage 1438 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1439 1440 This is meant as a backward compatibility convenience for those 1441 systems with a bootloader that can't be upgraded to accommodate 1442 the documented boot protocol using a device tree. 1443 1444 Beware that there is very little in terms of protection against 1445 this option being confused by leftover garbage in memory that might 1446 look like a DTB header after a reboot if no actual DTB is appended 1447 to zImage. Do not leave this option active in a production kernel 1448 if you don't intend to always append a DTB. Proper passing of the 1449 location into r2 of a bootloader provided DTB is always preferable 1450 to this option. 1451 1452config ARM_ATAG_DTB_COMPAT 1453 bool "Supplement the appended DTB with traditional ATAG information" 1454 depends on ARM_APPENDED_DTB 1455 help 1456 Some old bootloaders can't be updated to a DTB capable one, yet 1457 they provide ATAGs with memory configuration, the ramdisk address, 1458 the kernel cmdline string, etc. Such information is dynamically 1459 provided by the bootloader and can't always be stored in a static 1460 DTB. To allow a device tree enabled kernel to be used with such 1461 bootloaders, this option allows zImage to extract the information 1462 from the ATAG list and store it at run time into the appended DTB. 1463 1464choice 1465 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1466 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1467 1468config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1469 bool "Use bootloader kernel arguments if available" 1470 help 1471 Uses the command-line options passed by the boot loader instead of 1472 the device tree bootargs property. If the boot loader doesn't provide 1473 any, the device tree bootargs property will be used. 1474 1475config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1476 bool "Extend with bootloader kernel arguments" 1477 help 1478 The command-line arguments provided by the boot loader will be 1479 appended to the the device tree bootargs property. 1480 1481endchoice 1482 1483config CMDLINE 1484 string "Default kernel command string" 1485 default "" 1486 help 1487 On some architectures (e.g. CATS), there is currently no way 1488 for the boot loader to pass arguments to the kernel. For these 1489 architectures, you should supply some command-line options at build 1490 time by entering them here. As a minimum, you should specify the 1491 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1492 1493choice 1494 prompt "Kernel command line type" if CMDLINE != "" 1495 default CMDLINE_FROM_BOOTLOADER 1496 1497config CMDLINE_FROM_BOOTLOADER 1498 bool "Use bootloader kernel arguments if available" 1499 help 1500 Uses the command-line options passed by the boot loader. If 1501 the boot loader doesn't provide any, the default kernel command 1502 string provided in CMDLINE will be used. 1503 1504config CMDLINE_EXTEND 1505 bool "Extend bootloader kernel arguments" 1506 help 1507 The command-line arguments provided by the boot loader will be 1508 appended to the default kernel command string. 1509 1510config CMDLINE_FORCE 1511 bool "Always use the default kernel command string" 1512 help 1513 Always use the default kernel command string, even if the boot 1514 loader passes other arguments to the kernel. 1515 This is useful if you cannot or don't want to change the 1516 command-line options your boot loader passes to the kernel. 1517endchoice 1518 1519config XIP_KERNEL 1520 bool "Kernel Execute-In-Place from ROM" 1521 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1522 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1523 help 1524 Execute-In-Place allows the kernel to run from non-volatile storage 1525 directly addressable by the CPU, such as NOR flash. This saves RAM 1526 space since the text section of the kernel is not loaded from flash 1527 to RAM. Read-write sections, such as the data section and stack, 1528 are still copied to RAM. The XIP kernel is not compressed since 1529 it has to run directly from flash, so it will take more space to 1530 store it. The flash address used to link the kernel object files, 1531 and for storing it, is configuration dependent. Therefore, if you 1532 say Y here, you must know the proper physical address where to 1533 store the kernel image depending on your own flash memory usage. 1534 1535 Also note that the make target becomes "make xipImage" rather than 1536 "make zImage" or "make Image". The final kernel binary to put in 1537 ROM memory will be arch/arm/boot/xipImage. 1538 1539 If unsure, say N. 1540 1541config XIP_PHYS_ADDR 1542 hex "XIP Kernel Physical Location" 1543 depends on XIP_KERNEL 1544 default "0x00080000" 1545 help 1546 This is the physical address in your flash memory the kernel will 1547 be linked for and stored to. This address is dependent on your 1548 own flash usage. 1549 1550config XIP_DEFLATED_DATA 1551 bool "Store kernel .data section compressed in ROM" 1552 depends on XIP_KERNEL 1553 select ZLIB_INFLATE 1554 help 1555 Before the kernel is actually executed, its .data section has to be 1556 copied to RAM from ROM. This option allows for storing that data 1557 in compressed form and decompressed to RAM rather than merely being 1558 copied, saving some precious ROM space. A possible drawback is a 1559 slightly longer boot delay. 1560 1561config ARCH_SUPPORTS_KEXEC 1562 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1563 1564config ATAGS_PROC 1565 bool "Export atags in procfs" 1566 depends on ATAGS && KEXEC 1567 default y 1568 help 1569 Should the atags used to boot the kernel be exported in an "atags" 1570 file in procfs. Useful with kexec. 1571 1572config ARCH_SUPPORTS_CRASH_DUMP 1573 def_bool y 1574 1575config AUTO_ZRELADDR 1576 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1577 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1578 help 1579 ZRELADDR is the physical address where the decompressed kernel 1580 image will be placed. If AUTO_ZRELADDR is selected, the address 1581 will be determined at run-time, either by masking the current IP 1582 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1583 This assumes the zImage being placed in the first 128MB from 1584 start of memory. 1585 1586config EFI_STUB 1587 bool 1588 1589config EFI 1590 bool "UEFI runtime support" 1591 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1592 select UCS2_STRING 1593 select EFI_PARAMS_FROM_FDT 1594 select EFI_STUB 1595 select EFI_GENERIC_STUB 1596 select EFI_RUNTIME_WRAPPERS 1597 help 1598 This option provides support for runtime services provided 1599 by UEFI firmware (such as non-volatile variables, realtime 1600 clock, and platform reset). A UEFI stub is also provided to 1601 allow the kernel to be booted as an EFI application. This 1602 is only useful for kernels that may run on systems that have 1603 UEFI firmware. 1604 1605config DMI 1606 bool "Enable support for SMBIOS (DMI) tables" 1607 depends on EFI 1608 default y 1609 help 1610 This enables SMBIOS/DMI feature for systems. 1611 1612 This option is only useful on systems that have UEFI firmware. 1613 However, even with this option, the resultant kernel should 1614 continue to boot on existing non-UEFI platforms. 1615 1616 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1617 i.e., the the practice of identifying the platform via DMI to 1618 decide whether certain workarounds for buggy hardware and/or 1619 firmware need to be enabled. This would require the DMI subsystem 1620 to be enabled much earlier than we do on ARM, which is non-trivial. 1621 1622endmenu 1623 1624menu "CPU Power Management" 1625 1626source "drivers/cpufreq/Kconfig" 1627 1628source "drivers/cpuidle/Kconfig" 1629 1630endmenu 1631 1632menu "Floating point emulation" 1633 1634comment "At least one emulation must be selected" 1635 1636config FPE_NWFPE 1637 bool "NWFPE math emulation" 1638 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1639 help 1640 Say Y to include the NWFPE floating point emulator in the kernel. 1641 This is necessary to run most binaries. Linux does not currently 1642 support floating point hardware so you need to say Y here even if 1643 your machine has an FPA or floating point co-processor podule. 1644 1645 You may say N here if you are going to load the Acorn FPEmulator 1646 early in the bootup. 1647 1648config FPE_NWFPE_XP 1649 bool "Support extended precision" 1650 depends on FPE_NWFPE 1651 help 1652 Say Y to include 80-bit support in the kernel floating-point 1653 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1654 Note that gcc does not generate 80-bit operations by default, 1655 so in most cases this option only enlarges the size of the 1656 floating point emulator without any good reason. 1657 1658 You almost surely want to say N here. 1659 1660config FPE_FASTFPE 1661 bool "FastFPE math emulation (EXPERIMENTAL)" 1662 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1663 help 1664 Say Y here to include the FAST floating point emulator in the kernel. 1665 This is an experimental much faster emulator which now also has full 1666 precision for the mantissa. It does not support any exceptions. 1667 It is very simple, and approximately 3-6 times faster than NWFPE. 1668 1669 It should be sufficient for most programs. It may be not suitable 1670 for scientific calculations, but you have to check this for yourself. 1671 If you do not feel you need a faster FP emulation you should better 1672 choose NWFPE. 1673 1674config VFP 1675 bool "VFP-format floating point maths" 1676 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1677 help 1678 Say Y to include VFP support code in the kernel. This is needed 1679 if your hardware includes a VFP unit. 1680 1681 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1682 release notes and additional status information. 1683 1684 Say N if your target does not have VFP hardware. 1685 1686config VFPv3 1687 bool 1688 depends on VFP 1689 default y if CPU_V7 1690 1691config NEON 1692 bool "Advanced SIMD (NEON) Extension support" 1693 depends on VFPv3 && CPU_V7 1694 help 1695 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1696 Extension. 1697 1698config KERNEL_MODE_NEON 1699 bool "Support for NEON in kernel mode" 1700 depends on NEON && AEABI 1701 help 1702 Say Y to include support for NEON in kernel mode. 1703 1704endmenu 1705 1706menu "Power management options" 1707 1708source "kernel/power/Kconfig" 1709 1710config ARCH_SUSPEND_POSSIBLE 1711 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1712 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1713 def_bool y 1714 1715config ARM_CPU_SUSPEND 1716 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1717 depends on ARCH_SUSPEND_POSSIBLE 1718 1719config ARCH_HIBERNATION_POSSIBLE 1720 bool 1721 depends on MMU 1722 default y if ARCH_SUSPEND_POSSIBLE 1723 1724endmenu 1725 1726source "arch/arm/Kconfig.assembler" 1727