1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_DEVMEM_IS_ALLOWED 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_HAVE_CUSTOM_GPIO_H 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_MIGHT_HAVE_PC_PARPORT 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_USE_BUILTIN_BSWAP 13 select ARCH_USE_CMPXCHG_LOCKREF 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_EXTABLE_SORT if MMU 16 select CLONE_BACKWARDS 17 select CPU_PM if (SUSPEND || CPU_IDLE) 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 19 select EDAC_SUPPORT 20 select EDAC_ATOMIC_SCRUB 21 select GENERIC_ALLOCATOR 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_EARLY_IOREMAP 25 select GENERIC_IDLE_POLL_SETUP 26 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW_LEVEL 29 select GENERIC_PCI_IOMAP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select HANDLE_DOMAIN_IRQ 35 select HARDIRQS_SW_RESEND 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 40 select HAVE_ARCH_MMAP_RND_BITS if MMU 41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 42 select HAVE_ARCH_TRACEHOOK 43 select HAVE_ARM_SMCCC if CPU_V7 44 select HAVE_CBPF_JIT 45 select HAVE_CC_STACKPROTECTOR 46 select HAVE_CONTEXT_TRACKING 47 select HAVE_C_RECORDMCOUNT 48 select HAVE_DEBUG_KMEMLEAK 49 select HAVE_DMA_API_DEBUG 50 select HAVE_DMA_CONTIGUOUS if MMU 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 53 select HAVE_EXIT_THREAD 54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 57 select HAVE_GCC_PLUGINS 58 select HAVE_GENERIC_DMA_COHERENT 59 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 60 select HAVE_IDE if PCI || ISA || PCMCIA 61 select HAVE_IRQ_TIME_ACCOUNTING 62 select HAVE_KERNEL_GZIP 63 select HAVE_KERNEL_LZ4 64 select HAVE_KERNEL_LZMA 65 select HAVE_KERNEL_LZO 66 select HAVE_KERNEL_XZ 67 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 68 select HAVE_KRETPROBES if (HAVE_KPROBES) 69 select HAVE_MEMBLOCK 70 select HAVE_MOD_ARCH_SPECIFIC 71 select HAVE_NMI 72 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 73 select HAVE_OPTPROBES if !THUMB2_KERNEL 74 select HAVE_PERF_EVENTS 75 select HAVE_PERF_REGS 76 select HAVE_PERF_USER_STACK_DUMP 77 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 78 select HAVE_REGS_AND_STACK_ACCESS_API 79 select HAVE_SYSCALL_TRACEPOINTS 80 select HAVE_UID16 81 select HAVE_VIRT_CPU_ACCOUNTING_GEN 82 select IRQ_FORCED_THREADING 83 select MODULES_USE_ELF_REL 84 select NO_BOOTMEM 85 select OF_EARLY_FLATTREE if OF 86 select OF_RESERVED_MEM if OF 87 select OLD_SIGACTION 88 select OLD_SIGSUSPEND3 89 select PERF_USE_VMALLOC 90 select RTC_LIB 91 select SYS_SUPPORTS_APM_EMULATION 92 # Above selects are sorted alphabetically; please add new ones 93 # according to that. Thanks. 94 help 95 The ARM series is a line of low-power-consumption RISC chip designs 96 licensed by ARM Ltd and targeted at embedded applications and 97 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 98 manufactured, but legacy ARM-based PC hardware remains popular in 99 Europe. There is an ARM Linux project with a web page at 100 <http://www.arm.linux.org.uk/>. 101 102config ARM_HAS_SG_CHAIN 103 select ARCH_HAS_SG_CHAIN 104 bool 105 106config NEED_SG_DMA_LENGTH 107 bool 108 109config ARM_DMA_USE_IOMMU 110 bool 111 select ARM_HAS_SG_CHAIN 112 select NEED_SG_DMA_LENGTH 113 114if ARM_DMA_USE_IOMMU 115 116config ARM_DMA_IOMMU_ALIGNMENT 117 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 118 range 4 9 119 default 8 120 help 121 DMA mapping framework by default aligns all buffers to the smallest 122 PAGE_SIZE order which is greater than or equal to the requested buffer 123 size. This works well for buffers up to a few hundreds kilobytes, but 124 for larger buffers it just a waste of address space. Drivers which has 125 relatively small addressing window (like 64Mib) might run out of 126 virtual space with just a few allocations. 127 128 With this parameter you can specify the maximum PAGE_SIZE order for 129 DMA IOMMU buffers. Larger buffers will be aligned only to this 130 specified order. The order is expressed as a power of two multiplied 131 by the PAGE_SIZE. 132 133endif 134 135config MIGHT_HAVE_PCI 136 bool 137 138config SYS_SUPPORTS_APM_EMULATION 139 bool 140 141config HAVE_TCM 142 bool 143 select GENERIC_ALLOCATOR 144 145config HAVE_PROC_CPU 146 bool 147 148config NO_IOPORT_MAP 149 bool 150 151config EISA 152 bool 153 ---help--- 154 The Extended Industry Standard Architecture (EISA) bus was 155 developed as an open alternative to the IBM MicroChannel bus. 156 157 The EISA bus provided some of the features of the IBM MicroChannel 158 bus while maintaining backward compatibility with cards made for 159 the older ISA bus. The EISA bus saw limited use between 1988 and 160 1995 when it was made obsolete by the PCI bus. 161 162 Say Y here if you are building a kernel for an EISA-based machine. 163 164 Otherwise, say N. 165 166config SBUS 167 bool 168 169config STACKTRACE_SUPPORT 170 bool 171 default y 172 173config LOCKDEP_SUPPORT 174 bool 175 default y 176 177config TRACE_IRQFLAGS_SUPPORT 178 bool 179 default !CPU_V7M 180 181config RWSEM_XCHGADD_ALGORITHM 182 bool 183 default y 184 185config ARCH_HAS_ILOG2_U32 186 bool 187 188config ARCH_HAS_ILOG2_U64 189 bool 190 191config ARCH_HAS_BANDGAP 192 bool 193 194config FIX_EARLYCON_MEM 195 def_bool y if MMU 196 197config GENERIC_HWEIGHT 198 bool 199 default y 200 201config GENERIC_CALIBRATE_DELAY 202 bool 203 default y 204 205config ARCH_MAY_HAVE_PC_FDC 206 bool 207 208config ZONE_DMA 209 bool 210 211config NEED_DMA_MAP_STATE 212 def_bool y 213 214config ARCH_SUPPORTS_UPROBES 215 def_bool y 216 217config ARCH_HAS_DMA_SET_COHERENT_MASK 218 bool 219 220config GENERIC_ISA_DMA 221 bool 222 223config FIQ 224 bool 225 226config NEED_RET_TO_USER 227 bool 228 229config ARCH_MTD_XIP 230 bool 231 232config VECTORS_BASE 233 hex 234 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 235 default DRAM_BASE if REMAP_VECTORS_TO_RAM 236 default 0x00000000 237 help 238 The base address of exception vectors. This must be two pages 239 in size. 240 241config ARM_PATCH_PHYS_VIRT 242 bool "Patch physical to virtual translations at runtime" if EMBEDDED 243 default y 244 depends on !XIP_KERNEL && MMU 245 help 246 Patch phys-to-virt and virt-to-phys translation functions at 247 boot and module load time according to the position of the 248 kernel in system memory. 249 250 This can only be used with non-XIP MMU kernels where the base 251 of physical memory is at a 16MB boundary. 252 253 Only disable this option if you know that you do not require 254 this feature (eg, building a kernel for a single machine) and 255 you need to shrink the kernel to the minimal size. 256 257config NEED_MACH_IO_H 258 bool 259 help 260 Select this when mach/io.h is required to provide special 261 definitions for this platform. The need for mach/io.h should 262 be avoided when possible. 263 264config NEED_MACH_MEMORY_H 265 bool 266 help 267 Select this when mach/memory.h is required to provide special 268 definitions for this platform. The need for mach/memory.h should 269 be avoided when possible. 270 271config PHYS_OFFSET 272 hex "Physical address of main memory" if MMU 273 depends on !ARM_PATCH_PHYS_VIRT 274 default DRAM_BASE if !MMU 275 default 0x00000000 if ARCH_EBSA110 || \ 276 ARCH_FOOTBRIDGE || \ 277 ARCH_INTEGRATOR || \ 278 ARCH_IOP13XX || \ 279 ARCH_KS8695 || \ 280 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 282 default 0x20000000 if ARCH_S5PV210 283 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 284 default 0xc0000000 if ARCH_SA1100 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298source "init/Kconfig" 299 300source "kernel/Kconfig.freezer" 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARCH_MMAP_RND_BITS_MIN 312 default 8 313 314config ARCH_MMAP_RND_BITS_MAX 315 default 14 if PAGE_OFFSET=0x40000000 316 default 15 if PAGE_OFFSET=0x80000000 317 default 16 318 319# 320# The "ARM system type" choice list is ordered alphabetically by option 321# text. Please add new entries in the option alphabetic order. 322# 323choice 324 prompt "ARM system type" 325 default ARM_SINGLE_ARMV7M if !MMU 326 default ARCH_MULTIPLATFORM if MMU 327 328config ARCH_MULTIPLATFORM 329 bool "Allow multiple platforms to be selected" 330 depends on MMU 331 select ARCH_WANT_OPTIONAL_GPIOLIB 332 select ARM_HAS_SG_CHAIN 333 select ARM_PATCH_PHYS_VIRT 334 select AUTO_ZRELADDR 335 select CLKSRC_OF 336 select COMMON_CLK 337 select GENERIC_CLOCKEVENTS 338 select MIGHT_HAVE_PCI 339 select MULTI_IRQ_HANDLER 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARM_SINGLE_ARMV7M 344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 345 depends on !MMU 346 select ARCH_WANT_OPTIONAL_GPIOLIB 347 select ARM_NVIC 348 select AUTO_ZRELADDR 349 select CLKSRC_OF 350 select COMMON_CLK 351 select CPU_V7M 352 select GENERIC_CLOCKEVENTS 353 select NO_IOPORT_MAP 354 select SPARSE_IRQ 355 select USE_OF 356 357 358config ARCH_CLPS711X 359 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 360 select ARCH_REQUIRE_GPIOLIB 361 select AUTO_ZRELADDR 362 select CLKSRC_MMIO 363 select COMMON_CLK 364 select CPU_ARM720T 365 select GENERIC_CLOCKEVENTS 366 select MFD_SYSCON 367 select SOC_BUS 368 help 369 Support for Cirrus Logic 711x/721x/731x based boards. 370 371config ARCH_GEMINI 372 bool "Cortina Systems Gemini" 373 select ARCH_REQUIRE_GPIOLIB 374 select CLKSRC_MMIO 375 select CPU_FA526 376 select GENERIC_CLOCKEVENTS 377 help 378 Support for the Cortina Systems Gemini family SoCs 379 380config ARCH_EBSA110 381 bool "EBSA-110" 382 select ARCH_USES_GETTIMEOFFSET 383 select CPU_SA110 384 select ISA 385 select NEED_MACH_IO_H 386 select NEED_MACH_MEMORY_H 387 select NO_IOPORT_MAP 388 help 389 This is an evaluation board for the StrongARM processor available 390 from Digital. It has limited hardware on-board, including an 391 Ethernet interface, two PCMCIA sockets, two serial ports and a 392 parallel port. 393 394config ARCH_EP93XX 395 bool "EP93xx-based" 396 select ARCH_HAS_HOLES_MEMORYMODEL 397 select ARCH_REQUIRE_GPIOLIB 398 select ARM_AMBA 399 select ARM_PATCH_PHYS_VIRT 400 select ARM_VIC 401 select AUTO_ZRELADDR 402 select CLKDEV_LOOKUP 403 select CLKSRC_MMIO 404 select CPU_ARM920T 405 select GENERIC_CLOCKEVENTS 406 help 407 This enables support for the Cirrus EP93xx series of CPUs. 408 409config ARCH_FOOTBRIDGE 410 bool "FootBridge" 411 select CPU_SA110 412 select FOOTBRIDGE 413 select GENERIC_CLOCKEVENTS 414 select HAVE_IDE 415 select NEED_MACH_IO_H if !MMU 416 select NEED_MACH_MEMORY_H 417 help 418 Support for systems based on the DC21285 companion chip 419 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 420 421config ARCH_NETX 422 bool "Hilscher NetX based" 423 select ARM_VIC 424 select CLKSRC_MMIO 425 select CPU_ARM926T 426 select GENERIC_CLOCKEVENTS 427 help 428 This enables support for systems based on the Hilscher NetX Soc 429 430config ARCH_IOP13XX 431 bool "IOP13xx-based" 432 depends on MMU 433 select CPU_XSC3 434 select NEED_MACH_MEMORY_H 435 select NEED_RET_TO_USER 436 select PCI 437 select PLAT_IOP 438 select VMSPLIT_1G 439 select SPARSE_IRQ 440 help 441 Support for Intel's IOP13XX (XScale) family of processors. 442 443config ARCH_IOP32X 444 bool "IOP32x-based" 445 depends on MMU 446 select ARCH_REQUIRE_GPIOLIB 447 select CPU_XSCALE 448 select GPIO_IOP 449 select NEED_RET_TO_USER 450 select PCI 451 select PLAT_IOP 452 help 453 Support for Intel's 80219 and IOP32X (XScale) family of 454 processors. 455 456config ARCH_IOP33X 457 bool "IOP33x-based" 458 depends on MMU 459 select ARCH_REQUIRE_GPIOLIB 460 select CPU_XSCALE 461 select GPIO_IOP 462 select NEED_RET_TO_USER 463 select PCI 464 select PLAT_IOP 465 help 466 Support for Intel's IOP33X (XScale) family of processors. 467 468config ARCH_IXP4XX 469 bool "IXP4xx-based" 470 depends on MMU 471 select ARCH_HAS_DMA_SET_COHERENT_MASK 472 select ARCH_REQUIRE_GPIOLIB 473 select ARCH_SUPPORTS_BIG_ENDIAN 474 select CLKSRC_MMIO 475 select CPU_XSCALE 476 select DMABOUNCE if PCI 477 select GENERIC_CLOCKEVENTS 478 select MIGHT_HAVE_PCI 479 select NEED_MACH_IO_H 480 select USB_EHCI_BIG_ENDIAN_DESC 481 select USB_EHCI_BIG_ENDIAN_MMIO 482 help 483 Support for Intel's IXP4XX (XScale) family of processors. 484 485config ARCH_DOVE 486 bool "Marvell Dove" 487 select ARCH_REQUIRE_GPIOLIB 488 select CPU_PJ4 489 select GENERIC_CLOCKEVENTS 490 select MIGHT_HAVE_PCI 491 select MULTI_IRQ_HANDLER 492 select MVEBU_MBUS 493 select PINCTRL 494 select PINCTRL_DOVE 495 select PLAT_ORION_LEGACY 496 select SPARSE_IRQ 497 select PM_GENERIC_DOMAINS if PM 498 help 499 Support for the Marvell Dove SoC 88AP510 500 501config ARCH_KS8695 502 bool "Micrel/Kendin KS8695" 503 select ARCH_REQUIRE_GPIOLIB 504 select CLKSRC_MMIO 505 select CPU_ARM922T 506 select GENERIC_CLOCKEVENTS 507 select NEED_MACH_MEMORY_H 508 help 509 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 510 System-on-Chip devices. 511 512config ARCH_W90X900 513 bool "Nuvoton W90X900 CPU" 514 select ARCH_REQUIRE_GPIOLIB 515 select CLKDEV_LOOKUP 516 select CLKSRC_MMIO 517 select CPU_ARM926T 518 select GENERIC_CLOCKEVENTS 519 help 520 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 521 At present, the w90x900 has been renamed nuc900, regarding 522 the ARM series product line, you can login the following 523 link address to know more. 524 525 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 526 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 527 528config ARCH_LPC32XX 529 bool "NXP LPC32XX" 530 select ARCH_REQUIRE_GPIOLIB 531 select ARM_AMBA 532 select CLKDEV_LOOKUP 533 select CLKSRC_LPC32XX 534 select COMMON_CLK 535 select CPU_ARM926T 536 select GENERIC_CLOCKEVENTS 537 select MULTI_IRQ_HANDLER 538 select SPARSE_IRQ 539 select USE_OF 540 help 541 Support for the NXP LPC32XX family of processors 542 543config ARCH_PXA 544 bool "PXA2xx/PXA3xx-based" 545 depends on MMU 546 select ARCH_MTD_XIP 547 select ARCH_REQUIRE_GPIOLIB 548 select ARM_CPU_SUSPEND if PM 549 select AUTO_ZRELADDR 550 select COMMON_CLK 551 select CLKDEV_LOOKUP 552 select CLKSRC_PXA 553 select CLKSRC_MMIO 554 select CLKSRC_OF 555 select CPU_XSCALE if !CPU_XSC3 556 select GENERIC_CLOCKEVENTS 557 select GPIO_PXA 558 select HAVE_IDE 559 select IRQ_DOMAIN 560 select MULTI_IRQ_HANDLER 561 select PLAT_PXA 562 select SPARSE_IRQ 563 help 564 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 565 566config ARCH_RPC 567 bool "RiscPC" 568 depends on MMU 569 select ARCH_ACORN 570 select ARCH_MAY_HAVE_PC_FDC 571 select ARCH_SPARSEMEM_ENABLE 572 select ARCH_USES_GETTIMEOFFSET 573 select CPU_SA110 574 select FIQ 575 select HAVE_IDE 576 select HAVE_PATA_PLATFORM 577 select ISA_DMA_API 578 select NEED_MACH_IO_H 579 select NEED_MACH_MEMORY_H 580 select NO_IOPORT_MAP 581 help 582 On the Acorn Risc-PC, Linux can support the internal IDE disk and 583 CD-ROM interface, serial and parallel port, and the floppy drive. 584 585config ARCH_SA1100 586 bool "SA1100-based" 587 select ARCH_MTD_XIP 588 select ARCH_REQUIRE_GPIOLIB 589 select ARCH_SPARSEMEM_ENABLE 590 select CLKDEV_LOOKUP 591 select CLKSRC_MMIO 592 select CLKSRC_PXA 593 select CLKSRC_OF if OF 594 select CPU_FREQ 595 select CPU_SA1100 596 select GENERIC_CLOCKEVENTS 597 select HAVE_IDE 598 select IRQ_DOMAIN 599 select ISA 600 select MULTI_IRQ_HANDLER 601 select NEED_MACH_MEMORY_H 602 select SPARSE_IRQ 603 help 604 Support for StrongARM 11x0 based boards. 605 606config ARCH_S3C24XX 607 bool "Samsung S3C24XX SoCs" 608 select ARCH_REQUIRE_GPIOLIB 609 select ATAGS 610 select CLKDEV_LOOKUP 611 select CLKSRC_SAMSUNG_PWM 612 select GENERIC_CLOCKEVENTS 613 select GPIO_SAMSUNG 614 select HAVE_S3C2410_I2C if I2C 615 select HAVE_S3C2410_WATCHDOG if WATCHDOG 616 select HAVE_S3C_RTC if RTC_CLASS 617 select MULTI_IRQ_HANDLER 618 select NEED_MACH_IO_H 619 select SAMSUNG_ATAGS 620 help 621 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 622 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 623 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 624 Samsung SMDK2410 development board (and derivatives). 625 626config ARCH_DAVINCI 627 bool "TI DaVinci" 628 select ARCH_HAS_HOLES_MEMORYMODEL 629 select ARCH_REQUIRE_GPIOLIB 630 select CLKDEV_LOOKUP 631 select CPU_ARM926T 632 select GENERIC_ALLOCATOR 633 select GENERIC_CLOCKEVENTS 634 select GENERIC_IRQ_CHIP 635 select HAVE_IDE 636 select USE_OF 637 select ZONE_DMA 638 help 639 Support for TI's DaVinci platform. 640 641config ARCH_OMAP1 642 bool "TI OMAP1" 643 depends on MMU 644 select ARCH_HAS_HOLES_MEMORYMODEL 645 select ARCH_OMAP 646 select ARCH_REQUIRE_GPIOLIB 647 select CLKDEV_LOOKUP 648 select CLKSRC_MMIO 649 select GENERIC_CLOCKEVENTS 650 select GENERIC_IRQ_CHIP 651 select HAVE_IDE 652 select IRQ_DOMAIN 653 select MULTI_IRQ_HANDLER 654 select NEED_MACH_IO_H if PCCARD 655 select NEED_MACH_MEMORY_H 656 select SPARSE_IRQ 657 help 658 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 659 660endchoice 661 662menu "Multiple platform selection" 663 depends on ARCH_MULTIPLATFORM 664 665comment "CPU Core family selection" 666 667config ARCH_MULTI_V4 668 bool "ARMv4 based platforms (FA526)" 669 depends on !ARCH_MULTI_V6_V7 670 select ARCH_MULTI_V4_V5 671 select CPU_FA526 672 673config ARCH_MULTI_V4T 674 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 675 depends on !ARCH_MULTI_V6_V7 676 select ARCH_MULTI_V4_V5 677 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 678 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 679 CPU_ARM925T || CPU_ARM940T) 680 681config ARCH_MULTI_V5 682 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 683 depends on !ARCH_MULTI_V6_V7 684 select ARCH_MULTI_V4_V5 685 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 686 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 687 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 688 689config ARCH_MULTI_V4_V5 690 bool 691 692config ARCH_MULTI_V6 693 bool "ARMv6 based platforms (ARM11)" 694 select ARCH_MULTI_V6_V7 695 select CPU_V6K 696 697config ARCH_MULTI_V7 698 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 699 default y 700 select ARCH_MULTI_V6_V7 701 select CPU_V7 702 select HAVE_SMP 703 704config ARCH_MULTI_V6_V7 705 bool 706 select MIGHT_HAVE_CACHE_L2X0 707 708config ARCH_MULTI_CPU_AUTO 709 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 710 select ARCH_MULTI_V5 711 712endmenu 713 714config ARCH_VIRT 715 bool "Dummy Virtual Machine" 716 depends on ARCH_MULTI_V7 717 select ARM_AMBA 718 select ARM_GIC 719 select ARM_GIC_V2M if PCI_MSI 720 select ARM_GIC_V3 721 select ARM_PSCI 722 select HAVE_ARM_ARCH_TIMER 723 724# 725# This is sorted alphabetically by mach-* pathname. However, plat-* 726# Kconfigs may be included either alphabetically (according to the 727# plat- suffix) or along side the corresponding mach-* source. 728# 729source "arch/arm/mach-mvebu/Kconfig" 730 731source "arch/arm/mach-alpine/Kconfig" 732 733source "arch/arm/mach-artpec/Kconfig" 734 735source "arch/arm/mach-asm9260/Kconfig" 736 737source "arch/arm/mach-at91/Kconfig" 738 739source "arch/arm/mach-axxia/Kconfig" 740 741source "arch/arm/mach-bcm/Kconfig" 742 743source "arch/arm/mach-berlin/Kconfig" 744 745source "arch/arm/mach-clps711x/Kconfig" 746 747source "arch/arm/mach-cns3xxx/Kconfig" 748 749source "arch/arm/mach-davinci/Kconfig" 750 751source "arch/arm/mach-digicolor/Kconfig" 752 753source "arch/arm/mach-dove/Kconfig" 754 755source "arch/arm/mach-ep93xx/Kconfig" 756 757source "arch/arm/mach-footbridge/Kconfig" 758 759source "arch/arm/mach-gemini/Kconfig" 760 761source "arch/arm/mach-highbank/Kconfig" 762 763source "arch/arm/mach-hisi/Kconfig" 764 765source "arch/arm/mach-integrator/Kconfig" 766 767source "arch/arm/mach-iop32x/Kconfig" 768 769source "arch/arm/mach-iop33x/Kconfig" 770 771source "arch/arm/mach-iop13xx/Kconfig" 772 773source "arch/arm/mach-ixp4xx/Kconfig" 774 775source "arch/arm/mach-keystone/Kconfig" 776 777source "arch/arm/mach-ks8695/Kconfig" 778 779source "arch/arm/mach-meson/Kconfig" 780 781source "arch/arm/mach-moxart/Kconfig" 782 783source "arch/arm/mach-aspeed/Kconfig" 784 785source "arch/arm/mach-mv78xx0/Kconfig" 786 787source "arch/arm/mach-imx/Kconfig" 788 789source "arch/arm/mach-mediatek/Kconfig" 790 791source "arch/arm/mach-mxs/Kconfig" 792 793source "arch/arm/mach-netx/Kconfig" 794 795source "arch/arm/mach-nomadik/Kconfig" 796 797source "arch/arm/mach-nspire/Kconfig" 798 799source "arch/arm/plat-omap/Kconfig" 800 801source "arch/arm/mach-omap1/Kconfig" 802 803source "arch/arm/mach-omap2/Kconfig" 804 805source "arch/arm/mach-orion5x/Kconfig" 806 807source "arch/arm/mach-picoxcell/Kconfig" 808 809source "arch/arm/mach-pxa/Kconfig" 810source "arch/arm/plat-pxa/Kconfig" 811 812source "arch/arm/mach-mmp/Kconfig" 813 814source "arch/arm/mach-oxnas/Kconfig" 815 816source "arch/arm/mach-qcom/Kconfig" 817 818source "arch/arm/mach-realview/Kconfig" 819 820source "arch/arm/mach-rockchip/Kconfig" 821 822source "arch/arm/mach-sa1100/Kconfig" 823 824source "arch/arm/mach-socfpga/Kconfig" 825 826source "arch/arm/mach-spear/Kconfig" 827 828source "arch/arm/mach-sti/Kconfig" 829 830source "arch/arm/mach-s3c24xx/Kconfig" 831 832source "arch/arm/mach-s3c64xx/Kconfig" 833 834source "arch/arm/mach-s5pv210/Kconfig" 835 836source "arch/arm/mach-exynos/Kconfig" 837source "arch/arm/plat-samsung/Kconfig" 838 839source "arch/arm/mach-shmobile/Kconfig" 840 841source "arch/arm/mach-sunxi/Kconfig" 842 843source "arch/arm/mach-prima2/Kconfig" 844 845source "arch/arm/mach-tango/Kconfig" 846 847source "arch/arm/mach-tegra/Kconfig" 848 849source "arch/arm/mach-u300/Kconfig" 850 851source "arch/arm/mach-uniphier/Kconfig" 852 853source "arch/arm/mach-ux500/Kconfig" 854 855source "arch/arm/mach-versatile/Kconfig" 856 857source "arch/arm/mach-vexpress/Kconfig" 858source "arch/arm/plat-versatile/Kconfig" 859 860source "arch/arm/mach-vt8500/Kconfig" 861 862source "arch/arm/mach-w90x900/Kconfig" 863 864source "arch/arm/mach-zx/Kconfig" 865 866source "arch/arm/mach-zynq/Kconfig" 867 868# ARMv7-M architecture 869config ARCH_EFM32 870 bool "Energy Micro efm32" 871 depends on ARM_SINGLE_ARMV7M 872 select ARCH_REQUIRE_GPIOLIB 873 help 874 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 875 processors. 876 877config ARCH_LPC18XX 878 bool "NXP LPC18xx/LPC43xx" 879 depends on ARM_SINGLE_ARMV7M 880 select ARCH_HAS_RESET_CONTROLLER 881 select ARM_AMBA 882 select CLKSRC_LPC32XX 883 select PINCTRL 884 help 885 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 886 high performance microcontrollers. 887 888config ARCH_STM32 889 bool "STMicrolectronics STM32" 890 depends on ARM_SINGLE_ARMV7M 891 select ARCH_HAS_RESET_CONTROLLER 892 select ARMV7M_SYSTICK 893 select CLKSRC_STM32 894 select PINCTRL 895 select RESET_CONTROLLER 896 help 897 Support for STMicroelectronics STM32 processors. 898 899config MACH_STM32F429 900 bool "STMicrolectronics STM32F429" 901 depends on ARCH_STM32 902 default y 903 904config ARCH_MPS2 905 bool "ARM MPS2 paltform" 906 depends on ARM_SINGLE_ARMV7M 907 select ARM_AMBA 908 select CLKSRC_MPS2 909 help 910 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 911 with a range of available cores like Cortex-M3/M4/M7. 912 913 Please, note that depends which Application Note is used memory map 914 for the platform may vary, so adjustment of RAM base might be needed. 915 916# Definitions to make life easier 917config ARCH_ACORN 918 bool 919 920config PLAT_IOP 921 bool 922 select GENERIC_CLOCKEVENTS 923 924config PLAT_ORION 925 bool 926 select CLKSRC_MMIO 927 select COMMON_CLK 928 select GENERIC_IRQ_CHIP 929 select IRQ_DOMAIN 930 931config PLAT_ORION_LEGACY 932 bool 933 select PLAT_ORION 934 935config PLAT_PXA 936 bool 937 938config PLAT_VERSATILE 939 bool 940 941source "arch/arm/firmware/Kconfig" 942 943source arch/arm/mm/Kconfig 944 945config IWMMXT 946 bool "Enable iWMMXt support" 947 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 948 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 949 help 950 Enable support for iWMMXt context switching at run time if 951 running on a CPU that supports it. 952 953config MULTI_IRQ_HANDLER 954 bool 955 help 956 Allow each machine to specify it's own IRQ handler at run time. 957 958if !MMU 959source "arch/arm/Kconfig-nommu" 960endif 961 962config PJ4B_ERRATA_4742 963 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 964 depends on CPU_PJ4B && MACH_ARMADA_370 965 default y 966 help 967 When coming out of either a Wait for Interrupt (WFI) or a Wait for 968 Event (WFE) IDLE states, a specific timing sensitivity exists between 969 the retiring WFI/WFE instructions and the newly issued subsequent 970 instructions. This sensitivity can result in a CPU hang scenario. 971 Workaround: 972 The software must insert either a Data Synchronization Barrier (DSB) 973 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 974 instruction 975 976config ARM_ERRATA_326103 977 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 978 depends on CPU_V6 979 help 980 Executing a SWP instruction to read-only memory does not set bit 11 981 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 982 treat the access as a read, preventing a COW from occurring and 983 causing the faulting task to livelock. 984 985config ARM_ERRATA_411920 986 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 987 depends on CPU_V6 || CPU_V6K 988 help 989 Invalidation of the Instruction Cache operation can 990 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 991 It does not affect the MPCore. This option enables the ARM Ltd. 992 recommended workaround. 993 994config ARM_ERRATA_430973 995 bool "ARM errata: Stale prediction on replaced interworking branch" 996 depends on CPU_V7 997 help 998 This option enables the workaround for the 430973 Cortex-A8 999 r1p* erratum. If a code sequence containing an ARM/Thumb 1000 interworking branch is replaced with another code sequence at the 1001 same virtual address, whether due to self-modifying code or virtual 1002 to physical address re-mapping, Cortex-A8 does not recover from the 1003 stale interworking branch prediction. This results in Cortex-A8 1004 executing the new code sequence in the incorrect ARM or Thumb state. 1005 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1006 and also flushes the branch target cache at every context switch. 1007 Note that setting specific bits in the ACTLR register may not be 1008 available in non-secure mode. 1009 1010config ARM_ERRATA_458693 1011 bool "ARM errata: Processor deadlock when a false hazard is created" 1012 depends on CPU_V7 1013 depends on !ARCH_MULTIPLATFORM 1014 help 1015 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1016 erratum. For very specific sequences of memory operations, it is 1017 possible for a hazard condition intended for a cache line to instead 1018 be incorrectly associated with a different cache line. This false 1019 hazard might then cause a processor deadlock. The workaround enables 1020 the L1 caching of the NEON accesses and disables the PLD instruction 1021 in the ACTLR register. Note that setting specific bits in the ACTLR 1022 register may not be available in non-secure mode. 1023 1024config ARM_ERRATA_460075 1025 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1026 depends on CPU_V7 1027 depends on !ARCH_MULTIPLATFORM 1028 help 1029 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1030 erratum. Any asynchronous access to the L2 cache may encounter a 1031 situation in which recent store transactions to the L2 cache are lost 1032 and overwritten with stale memory contents from external memory. The 1033 workaround disables the write-allocate mode for the L2 cache via the 1034 ACTLR register. Note that setting specific bits in the ACTLR register 1035 may not be available in non-secure mode. 1036 1037config ARM_ERRATA_742230 1038 bool "ARM errata: DMB operation may be faulty" 1039 depends on CPU_V7 && SMP 1040 depends on !ARCH_MULTIPLATFORM 1041 help 1042 This option enables the workaround for the 742230 Cortex-A9 1043 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1044 between two write operations may not ensure the correct visibility 1045 ordering of the two writes. This workaround sets a specific bit in 1046 the diagnostic register of the Cortex-A9 which causes the DMB 1047 instruction to behave as a DSB, ensuring the correct behaviour of 1048 the two writes. 1049 1050config ARM_ERRATA_742231 1051 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1052 depends on CPU_V7 && SMP 1053 depends on !ARCH_MULTIPLATFORM 1054 help 1055 This option enables the workaround for the 742231 Cortex-A9 1056 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1057 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1058 accessing some data located in the same cache line, may get corrupted 1059 data due to bad handling of the address hazard when the line gets 1060 replaced from one of the CPUs at the same time as another CPU is 1061 accessing it. This workaround sets specific bits in the diagnostic 1062 register of the Cortex-A9 which reduces the linefill issuing 1063 capabilities of the processor. 1064 1065config ARM_ERRATA_643719 1066 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1067 depends on CPU_V7 && SMP 1068 default y 1069 help 1070 This option enables the workaround for the 643719 Cortex-A9 (prior to 1071 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1072 register returns zero when it should return one. The workaround 1073 corrects this value, ensuring cache maintenance operations which use 1074 it behave as intended and avoiding data corruption. 1075 1076config ARM_ERRATA_720789 1077 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1078 depends on CPU_V7 1079 help 1080 This option enables the workaround for the 720789 Cortex-A9 (prior to 1081 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1082 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1083 As a consequence of this erratum, some TLB entries which should be 1084 invalidated are not, resulting in an incoherency in the system page 1085 tables. The workaround changes the TLB flushing routines to invalidate 1086 entries regardless of the ASID. 1087 1088config ARM_ERRATA_743622 1089 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1090 depends on CPU_V7 1091 depends on !ARCH_MULTIPLATFORM 1092 help 1093 This option enables the workaround for the 743622 Cortex-A9 1094 (r2p*) erratum. Under very rare conditions, a faulty 1095 optimisation in the Cortex-A9 Store Buffer may lead to data 1096 corruption. This workaround sets a specific bit in the diagnostic 1097 register of the Cortex-A9 which disables the Store Buffer 1098 optimisation, preventing the defect from occurring. This has no 1099 visible impact on the overall performance or power consumption of the 1100 processor. 1101 1102config ARM_ERRATA_751472 1103 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1104 depends on CPU_V7 1105 depends on !ARCH_MULTIPLATFORM 1106 help 1107 This option enables the workaround for the 751472 Cortex-A9 (prior 1108 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1109 completion of a following broadcasted operation if the second 1110 operation is received by a CPU before the ICIALLUIS has completed, 1111 potentially leading to corrupted entries in the cache or TLB. 1112 1113config ARM_ERRATA_754322 1114 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1115 depends on CPU_V7 1116 help 1117 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1118 r3p*) erratum. A speculative memory access may cause a page table walk 1119 which starts prior to an ASID switch but completes afterwards. This 1120 can populate the micro-TLB with a stale entry which may be hit with 1121 the new ASID. This workaround places two dsb instructions in the mm 1122 switching code so that no page table walks can cross the ASID switch. 1123 1124config ARM_ERRATA_754327 1125 bool "ARM errata: no automatic Store Buffer drain" 1126 depends on CPU_V7 && SMP 1127 help 1128 This option enables the workaround for the 754327 Cortex-A9 (prior to 1129 r2p0) erratum. The Store Buffer does not have any automatic draining 1130 mechanism and therefore a livelock may occur if an external agent 1131 continuously polls a memory location waiting to observe an update. 1132 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1133 written polling loops from denying visibility of updates to memory. 1134 1135config ARM_ERRATA_364296 1136 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1137 depends on CPU_V6 1138 help 1139 This options enables the workaround for the 364296 ARM1136 1140 r0p2 erratum (possible cache data corruption with 1141 hit-under-miss enabled). It sets the undocumented bit 31 in 1142 the auxiliary control register and the FI bit in the control 1143 register, thus disabling hit-under-miss without putting the 1144 processor into full low interrupt latency mode. ARM11MPCore 1145 is not affected. 1146 1147config ARM_ERRATA_764369 1148 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1149 depends on CPU_V7 && SMP 1150 help 1151 This option enables the workaround for erratum 764369 1152 affecting Cortex-A9 MPCore with two or more processors (all 1153 current revisions). Under certain timing circumstances, a data 1154 cache line maintenance operation by MVA targeting an Inner 1155 Shareable memory region may fail to proceed up to either the 1156 Point of Coherency or to the Point of Unification of the 1157 system. This workaround adds a DSB instruction before the 1158 relevant cache maintenance functions and sets a specific bit 1159 in the diagnostic control register of the SCU. 1160 1161config ARM_ERRATA_775420 1162 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1163 depends on CPU_V7 1164 help 1165 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1166 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1167 operation aborts with MMU exception, it might cause the processor 1168 to deadlock. This workaround puts DSB before executing ISB if 1169 an abort may occur on cache maintenance. 1170 1171config ARM_ERRATA_798181 1172 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1173 depends on CPU_V7 && SMP 1174 help 1175 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1176 adequately shooting down all use of the old entries. This 1177 option enables the Linux kernel workaround for this erratum 1178 which sends an IPI to the CPUs that are running the same ASID 1179 as the one being invalidated. 1180 1181config ARM_ERRATA_773022 1182 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1183 depends on CPU_V7 1184 help 1185 This option enables the workaround for the 773022 Cortex-A15 1186 (up to r0p4) erratum. In certain rare sequences of code, the 1187 loop buffer may deliver incorrect instructions. This 1188 workaround disables the loop buffer to avoid the erratum. 1189 1190endmenu 1191 1192source "arch/arm/common/Kconfig" 1193 1194menu "Bus support" 1195 1196config ISA 1197 bool 1198 help 1199 Find out whether you have ISA slots on your motherboard. ISA is the 1200 name of a bus system, i.e. the way the CPU talks to the other stuff 1201 inside your box. Other bus systems are PCI, EISA, MicroChannel 1202 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1203 newer boards don't support it. If you have ISA, say Y, otherwise N. 1204 1205# Select ISA DMA controller support 1206config ISA_DMA 1207 bool 1208 select ISA_DMA_API 1209 1210# Select ISA DMA interface 1211config ISA_DMA_API 1212 bool 1213 1214config PCI 1215 bool "PCI support" if MIGHT_HAVE_PCI 1216 help 1217 Find out whether you have a PCI motherboard. PCI is the name of a 1218 bus system, i.e. the way the CPU talks to the other stuff inside 1219 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1220 VESA. If you have PCI, say Y, otherwise N. 1221 1222config PCI_DOMAINS 1223 bool 1224 depends on PCI 1225 1226config PCI_DOMAINS_GENERIC 1227 def_bool PCI_DOMAINS 1228 1229config PCI_NANOENGINE 1230 bool "BSE nanoEngine PCI support" 1231 depends on SA1100_NANOENGINE 1232 help 1233 Enable PCI on the BSE nanoEngine board. 1234 1235config PCI_SYSCALL 1236 def_bool PCI 1237 1238config PCI_HOST_ITE8152 1239 bool 1240 depends on PCI && MACH_ARMCORE 1241 default y 1242 select DMABOUNCE 1243 1244source "drivers/pci/Kconfig" 1245 1246source "drivers/pcmcia/Kconfig" 1247 1248endmenu 1249 1250menu "Kernel Features" 1251 1252config HAVE_SMP 1253 bool 1254 help 1255 This option should be selected by machines which have an SMP- 1256 capable CPU. 1257 1258 The only effect of this option is to make the SMP-related 1259 options available to the user for configuration. 1260 1261config SMP 1262 bool "Symmetric Multi-Processing" 1263 depends on CPU_V6K || CPU_V7 1264 depends on GENERIC_CLOCKEVENTS 1265 depends on HAVE_SMP 1266 depends on MMU || ARM_MPU 1267 select IRQ_WORK 1268 help 1269 This enables support for systems with more than one CPU. If you have 1270 a system with only one CPU, say N. If you have a system with more 1271 than one CPU, say Y. 1272 1273 If you say N here, the kernel will run on uni- and multiprocessor 1274 machines, but will use only one CPU of a multiprocessor machine. If 1275 you say Y here, the kernel will run on many, but not all, 1276 uniprocessor machines. On a uniprocessor machine, the kernel 1277 will run faster if you say N here. 1278 1279 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1280 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1281 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1282 1283 If you don't know what to do here, say N. 1284 1285config SMP_ON_UP 1286 bool "Allow booting SMP kernel on uniprocessor systems" 1287 depends on SMP && !XIP_KERNEL && MMU 1288 default y 1289 help 1290 SMP kernels contain instructions which fail on non-SMP processors. 1291 Enabling this option allows the kernel to modify itself to make 1292 these instructions safe. Disabling it allows about 1K of space 1293 savings. 1294 1295 If you don't know what to do here, say Y. 1296 1297config ARM_CPU_TOPOLOGY 1298 bool "Support cpu topology definition" 1299 depends on SMP && CPU_V7 1300 default y 1301 help 1302 Support ARM cpu topology definition. The MPIDR register defines 1303 affinity between processors which is then used to describe the cpu 1304 topology of an ARM System. 1305 1306config SCHED_MC 1307 bool "Multi-core scheduler support" 1308 depends on ARM_CPU_TOPOLOGY 1309 help 1310 Multi-core scheduler support improves the CPU scheduler's decision 1311 making when dealing with multi-core CPU chips at a cost of slightly 1312 increased overhead in some places. If unsure say N here. 1313 1314config SCHED_SMT 1315 bool "SMT scheduler support" 1316 depends on ARM_CPU_TOPOLOGY 1317 help 1318 Improves the CPU scheduler's decision making when dealing with 1319 MultiThreading at a cost of slightly increased overhead in some 1320 places. If unsure say N here. 1321 1322config HAVE_ARM_SCU 1323 bool 1324 help 1325 This option enables support for the ARM system coherency unit 1326 1327config HAVE_ARM_ARCH_TIMER 1328 bool "Architected timer support" 1329 depends on CPU_V7 1330 select ARM_ARCH_TIMER 1331 select GENERIC_CLOCKEVENTS 1332 help 1333 This option enables support for the ARM architected timer 1334 1335config HAVE_ARM_TWD 1336 bool 1337 select CLKSRC_OF if OF 1338 help 1339 This options enables support for the ARM timer and watchdog unit 1340 1341config MCPM 1342 bool "Multi-Cluster Power Management" 1343 depends on CPU_V7 && SMP 1344 help 1345 This option provides the common power management infrastructure 1346 for (multi-)cluster based systems, such as big.LITTLE based 1347 systems. 1348 1349config MCPM_QUAD_CLUSTER 1350 bool 1351 depends on MCPM 1352 help 1353 To avoid wasting resources unnecessarily, MCPM only supports up 1354 to 2 clusters by default. 1355 Platforms with 3 or 4 clusters that use MCPM must select this 1356 option to allow the additional clusters to be managed. 1357 1358config BIG_LITTLE 1359 bool "big.LITTLE support (Experimental)" 1360 depends on CPU_V7 && SMP 1361 select MCPM 1362 help 1363 This option enables support selections for the big.LITTLE 1364 system architecture. 1365 1366config BL_SWITCHER 1367 bool "big.LITTLE switcher support" 1368 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1369 select CPU_PM 1370 help 1371 The big.LITTLE "switcher" provides the core functionality to 1372 transparently handle transition between a cluster of A15's 1373 and a cluster of A7's in a big.LITTLE system. 1374 1375config BL_SWITCHER_DUMMY_IF 1376 tristate "Simple big.LITTLE switcher user interface" 1377 depends on BL_SWITCHER && DEBUG_KERNEL 1378 help 1379 This is a simple and dummy char dev interface to control 1380 the big.LITTLE switcher core code. It is meant for 1381 debugging purposes only. 1382 1383choice 1384 prompt "Memory split" 1385 depends on MMU 1386 default VMSPLIT_3G 1387 help 1388 Select the desired split between kernel and user memory. 1389 1390 If you are not absolutely sure what you are doing, leave this 1391 option alone! 1392 1393 config VMSPLIT_3G 1394 bool "3G/1G user/kernel split" 1395 config VMSPLIT_3G_OPT 1396 bool "3G/1G user/kernel split (for full 1G low memory)" 1397 config VMSPLIT_2G 1398 bool "2G/2G user/kernel split" 1399 config VMSPLIT_1G 1400 bool "1G/3G user/kernel split" 1401endchoice 1402 1403config PAGE_OFFSET 1404 hex 1405 default PHYS_OFFSET if !MMU 1406 default 0x40000000 if VMSPLIT_1G 1407 default 0x80000000 if VMSPLIT_2G 1408 default 0xB0000000 if VMSPLIT_3G_OPT 1409 default 0xC0000000 1410 1411config NR_CPUS 1412 int "Maximum number of CPUs (2-32)" 1413 range 2 32 1414 depends on SMP 1415 default "4" 1416 1417config HOTPLUG_CPU 1418 bool "Support for hot-pluggable CPUs" 1419 depends on SMP 1420 help 1421 Say Y here to experiment with turning CPUs off and on. CPUs 1422 can be controlled through /sys/devices/system/cpu. 1423 1424config ARM_PSCI 1425 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1426 depends on HAVE_ARM_SMCCC 1427 select ARM_PSCI_FW 1428 help 1429 Say Y here if you want Linux to communicate with system firmware 1430 implementing the PSCI specification for CPU-centric power 1431 management operations described in ARM document number ARM DEN 1432 0022A ("Power State Coordination Interface System Software on 1433 ARM processors"). 1434 1435# The GPIO number here must be sorted by descending number. In case of 1436# a multiplatform kernel, we just want the highest value required by the 1437# selected platforms. 1438config ARCH_NR_GPIO 1439 int 1440 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1441 ARCH_ZYNQ 1442 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1443 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1444 default 416 if ARCH_SUNXI 1445 default 392 if ARCH_U8500 1446 default 352 if ARCH_VT8500 1447 default 288 if ARCH_ROCKCHIP 1448 default 264 if MACH_H4700 1449 default 0 1450 help 1451 Maximum number of GPIOs in the system. 1452 1453 If unsure, leave the default value. 1454 1455source kernel/Kconfig.preempt 1456 1457config HZ_FIXED 1458 int 1459 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1460 ARCH_S5PV210 || ARCH_EXYNOS4 1461 default 128 if SOC_AT91RM9200 1462 default 0 1463 1464choice 1465 depends on HZ_FIXED = 0 1466 prompt "Timer frequency" 1467 1468config HZ_100 1469 bool "100 Hz" 1470 1471config HZ_200 1472 bool "200 Hz" 1473 1474config HZ_250 1475 bool "250 Hz" 1476 1477config HZ_300 1478 bool "300 Hz" 1479 1480config HZ_500 1481 bool "500 Hz" 1482 1483config HZ_1000 1484 bool "1000 Hz" 1485 1486endchoice 1487 1488config HZ 1489 int 1490 default HZ_FIXED if HZ_FIXED != 0 1491 default 100 if HZ_100 1492 default 200 if HZ_200 1493 default 250 if HZ_250 1494 default 300 if HZ_300 1495 default 500 if HZ_500 1496 default 1000 1497 1498config SCHED_HRTICK 1499 def_bool HIGH_RES_TIMERS 1500 1501config THUMB2_KERNEL 1502 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1503 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1504 default y if CPU_THUMBONLY 1505 select AEABI 1506 select ARM_ASM_UNIFIED 1507 select ARM_UNWIND 1508 help 1509 By enabling this option, the kernel will be compiled in 1510 Thumb-2 mode. A compiler/assembler that understand the unified 1511 ARM-Thumb syntax is needed. 1512 1513 If unsure, say N. 1514 1515config THUMB2_AVOID_R_ARM_THM_JUMP11 1516 bool "Work around buggy Thumb-2 short branch relocations in gas" 1517 depends on THUMB2_KERNEL && MODULES 1518 default y 1519 help 1520 Various binutils versions can resolve Thumb-2 branches to 1521 locally-defined, preemptible global symbols as short-range "b.n" 1522 branch instructions. 1523 1524 This is a problem, because there's no guarantee the final 1525 destination of the symbol, or any candidate locations for a 1526 trampoline, are within range of the branch. For this reason, the 1527 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1528 relocation in modules at all, and it makes little sense to add 1529 support. 1530 1531 The symptom is that the kernel fails with an "unsupported 1532 relocation" error when loading some modules. 1533 1534 Until fixed tools are available, passing 1535 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1536 code which hits this problem, at the cost of a bit of extra runtime 1537 stack usage in some cases. 1538 1539 The problem is described in more detail at: 1540 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1541 1542 Only Thumb-2 kernels are affected. 1543 1544 Unless you are sure your tools don't have this problem, say Y. 1545 1546config ARM_ASM_UNIFIED 1547 bool 1548 1549config ARM_PATCH_IDIV 1550 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1551 depends on CPU_32v7 && !XIP_KERNEL 1552 default y 1553 help 1554 The ARM compiler inserts calls to __aeabi_idiv() and 1555 __aeabi_uidiv() when it needs to perform division on signed 1556 and unsigned integers. Some v7 CPUs have support for the sdiv 1557 and udiv instructions that can be used to implement those 1558 functions. 1559 1560 Enabling this option allows the kernel to modify itself to 1561 replace the first two instructions of these library functions 1562 with the sdiv or udiv plus "bx lr" instructions when the CPU 1563 it is running on supports them. Typically this will be faster 1564 and less power intensive than running the original library 1565 code to do integer division. 1566 1567config AEABI 1568 bool "Use the ARM EABI to compile the kernel" 1569 help 1570 This option allows for the kernel to be compiled using the latest 1571 ARM ABI (aka EABI). This is only useful if you are using a user 1572 space environment that is also compiled with EABI. 1573 1574 Since there are major incompatibilities between the legacy ABI and 1575 EABI, especially with regard to structure member alignment, this 1576 option also changes the kernel syscall calling convention to 1577 disambiguate both ABIs and allow for backward compatibility support 1578 (selected with CONFIG_OABI_COMPAT). 1579 1580 To use this you need GCC version 4.0.0 or later. 1581 1582config OABI_COMPAT 1583 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1584 depends on AEABI && !THUMB2_KERNEL 1585 help 1586 This option preserves the old syscall interface along with the 1587 new (ARM EABI) one. It also provides a compatibility layer to 1588 intercept syscalls that have structure arguments which layout 1589 in memory differs between the legacy ABI and the new ARM EABI 1590 (only for non "thumb" binaries). This option adds a tiny 1591 overhead to all syscalls and produces a slightly larger kernel. 1592 1593 The seccomp filter system will not be available when this is 1594 selected, since there is no way yet to sensibly distinguish 1595 between calling conventions during filtering. 1596 1597 If you know you'll be using only pure EABI user space then you 1598 can say N here. If this option is not selected and you attempt 1599 to execute a legacy ABI binary then the result will be 1600 UNPREDICTABLE (in fact it can be predicted that it won't work 1601 at all). If in doubt say N. 1602 1603config ARCH_HAS_HOLES_MEMORYMODEL 1604 bool 1605 1606config ARCH_SPARSEMEM_ENABLE 1607 bool 1608 1609config ARCH_SPARSEMEM_DEFAULT 1610 def_bool ARCH_SPARSEMEM_ENABLE 1611 1612config ARCH_SELECT_MEMORY_MODEL 1613 def_bool ARCH_SPARSEMEM_ENABLE 1614 1615config HAVE_ARCH_PFN_VALID 1616 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1617 1618config HAVE_GENERIC_RCU_GUP 1619 def_bool y 1620 depends on ARM_LPAE 1621 1622config HIGHMEM 1623 bool "High Memory Support" 1624 depends on MMU 1625 help 1626 The address space of ARM processors is only 4 Gigabytes large 1627 and it has to accommodate user address space, kernel address 1628 space as well as some memory mapped IO. That means that, if you 1629 have a large amount of physical memory and/or IO, not all of the 1630 memory can be "permanently mapped" by the kernel. The physical 1631 memory that is not permanently mapped is called "high memory". 1632 1633 Depending on the selected kernel/user memory split, minimum 1634 vmalloc space and actual amount of RAM, you may not need this 1635 option which should result in a slightly faster kernel. 1636 1637 If unsure, say n. 1638 1639config HIGHPTE 1640 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1641 depends on HIGHMEM 1642 default y 1643 help 1644 The VM uses one page of physical memory for each page table. 1645 For systems with a lot of processes, this can use a lot of 1646 precious low memory, eventually leading to low memory being 1647 consumed by page tables. Setting this option will allow 1648 user-space 2nd level page tables to reside in high memory. 1649 1650config CPU_SW_DOMAIN_PAN 1651 bool "Enable use of CPU domains to implement privileged no-access" 1652 depends on MMU && !ARM_LPAE 1653 default y 1654 help 1655 Increase kernel security by ensuring that normal kernel accesses 1656 are unable to access userspace addresses. This can help prevent 1657 use-after-free bugs becoming an exploitable privilege escalation 1658 by ensuring that magic values (such as LIST_POISON) will always 1659 fault when dereferenced. 1660 1661 CPUs with low-vector mappings use a best-efforts implementation. 1662 Their lower 1MB needs to remain accessible for the vectors, but 1663 the remainder of userspace will become appropriately inaccessible. 1664 1665config HW_PERF_EVENTS 1666 def_bool y 1667 depends on ARM_PMU 1668 1669config SYS_SUPPORTS_HUGETLBFS 1670 def_bool y 1671 depends on ARM_LPAE 1672 1673config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1674 def_bool y 1675 depends on ARM_LPAE 1676 1677config ARCH_WANT_GENERAL_HUGETLB 1678 def_bool y 1679 1680config ARM_MODULE_PLTS 1681 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1682 depends on MODULES 1683 help 1684 Allocate PLTs when loading modules so that jumps and calls whose 1685 targets are too far away for their relative offsets to be encoded 1686 in the instructions themselves can be bounced via veneers in the 1687 module's PLT. This allows modules to be allocated in the generic 1688 vmalloc area after the dedicated module memory area has been 1689 exhausted. The modules will use slightly more memory, but after 1690 rounding up to page size, the actual memory footprint is usually 1691 the same. 1692 1693 Say y if you are getting out of memory errors while loading modules 1694 1695source "mm/Kconfig" 1696 1697config FORCE_MAX_ZONEORDER 1698 int "Maximum zone order" 1699 default "12" if SOC_AM33XX 1700 default "9" if SA1111 || ARCH_EFM32 1701 default "11" 1702 help 1703 The kernel memory allocator divides physically contiguous memory 1704 blocks into "zones", where each zone is a power of two number of 1705 pages. This option selects the largest power of two that the kernel 1706 keeps in the memory allocator. If you need to allocate very large 1707 blocks of physically contiguous memory, then you may need to 1708 increase this value. 1709 1710 This config option is actually maximum order plus one. For example, 1711 a value of 11 means that the largest free memory block is 2^10 pages. 1712 1713config ALIGNMENT_TRAP 1714 bool 1715 depends on CPU_CP15_MMU 1716 default y if !ARCH_EBSA110 1717 select HAVE_PROC_CPU if PROC_FS 1718 help 1719 ARM processors cannot fetch/store information which is not 1720 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1721 address divisible by 4. On 32-bit ARM processors, these non-aligned 1722 fetch/store instructions will be emulated in software if you say 1723 here, which has a severe performance impact. This is necessary for 1724 correct operation of some network protocols. With an IP-only 1725 configuration it is safe to say N, otherwise say Y. 1726 1727config UACCESS_WITH_MEMCPY 1728 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1729 depends on MMU 1730 default y if CPU_FEROCEON 1731 help 1732 Implement faster copy_to_user and clear_user methods for CPU 1733 cores where a 8-word STM instruction give significantly higher 1734 memory write throughput than a sequence of individual 32bit stores. 1735 1736 A possible side effect is a slight increase in scheduling latency 1737 between threads sharing the same address space if they invoke 1738 such copy operations with large buffers. 1739 1740 However, if the CPU data cache is using a write-allocate mode, 1741 this option is unlikely to provide any performance gain. 1742 1743config SECCOMP 1744 bool 1745 prompt "Enable seccomp to safely compute untrusted bytecode" 1746 ---help--- 1747 This kernel feature is useful for number crunching applications 1748 that may need to compute untrusted bytecode during their 1749 execution. By using pipes or other transports made available to 1750 the process as file descriptors supporting the read/write 1751 syscalls, it's possible to isolate those applications in 1752 their own address space using seccomp. Once seccomp is 1753 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1754 and the task is only allowed to execute a few safe syscalls 1755 defined by each seccomp mode. 1756 1757config SWIOTLB 1758 def_bool y 1759 1760config IOMMU_HELPER 1761 def_bool SWIOTLB 1762 1763config PARAVIRT 1764 bool "Enable paravirtualization code" 1765 help 1766 This changes the kernel so it can modify itself when it is run 1767 under a hypervisor, potentially improving performance significantly 1768 over full virtualization. 1769 1770config PARAVIRT_TIME_ACCOUNTING 1771 bool "Paravirtual steal time accounting" 1772 select PARAVIRT 1773 default n 1774 help 1775 Select this option to enable fine granularity task steal time 1776 accounting. Time spent executing other tasks in parallel with 1777 the current vCPU is discounted from the vCPU power. To account for 1778 that, there can be a small performance impact. 1779 1780 If in doubt, say N here. 1781 1782config XEN_DOM0 1783 def_bool y 1784 depends on XEN 1785 1786config XEN 1787 bool "Xen guest support on ARM" 1788 depends on ARM && AEABI && OF 1789 depends on CPU_V7 && !CPU_V6 1790 depends on !GENERIC_ATOMIC64 1791 depends on MMU 1792 select ARCH_DMA_ADDR_T_64BIT 1793 select ARM_PSCI 1794 select SWIOTLB_XEN 1795 select PARAVIRT 1796 help 1797 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1798 1799endmenu 1800 1801menu "Boot options" 1802 1803config USE_OF 1804 bool "Flattened Device Tree support" 1805 select IRQ_DOMAIN 1806 select OF 1807 help 1808 Include support for flattened device tree machine descriptions. 1809 1810config ATAGS 1811 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1812 default y 1813 help 1814 This is the traditional way of passing data to the kernel at boot 1815 time. If you are solely relying on the flattened device tree (or 1816 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1817 to remove ATAGS support from your kernel binary. If unsure, 1818 leave this to y. 1819 1820config DEPRECATED_PARAM_STRUCT 1821 bool "Provide old way to pass kernel parameters" 1822 depends on ATAGS 1823 help 1824 This was deprecated in 2001 and announced to live on for 5 years. 1825 Some old boot loaders still use this way. 1826 1827# Compressed boot loader in ROM. Yes, we really want to ask about 1828# TEXT and BSS so we preserve their values in the config files. 1829config ZBOOT_ROM_TEXT 1830 hex "Compressed ROM boot loader base address" 1831 default "0" 1832 help 1833 The physical address at which the ROM-able zImage is to be 1834 placed in the target. Platforms which normally make use of 1835 ROM-able zImage formats normally set this to a suitable 1836 value in their defconfig file. 1837 1838 If ZBOOT_ROM is not enabled, this has no effect. 1839 1840config ZBOOT_ROM_BSS 1841 hex "Compressed ROM boot loader BSS address" 1842 default "0" 1843 help 1844 The base address of an area of read/write memory in the target 1845 for the ROM-able zImage which must be available while the 1846 decompressor is running. It must be large enough to hold the 1847 entire decompressed kernel plus an additional 128 KiB. 1848 Platforms which normally make use of ROM-able zImage formats 1849 normally set this to a suitable value in their defconfig file. 1850 1851 If ZBOOT_ROM is not enabled, this has no effect. 1852 1853config ZBOOT_ROM 1854 bool "Compressed boot loader in ROM/flash" 1855 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1856 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1857 help 1858 Say Y here if you intend to execute your compressed kernel image 1859 (zImage) directly from ROM or flash. If unsure, say N. 1860 1861config ARM_APPENDED_DTB 1862 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1863 depends on OF 1864 help 1865 With this option, the boot code will look for a device tree binary 1866 (DTB) appended to zImage 1867 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1868 1869 This is meant as a backward compatibility convenience for those 1870 systems with a bootloader that can't be upgraded to accommodate 1871 the documented boot protocol using a device tree. 1872 1873 Beware that there is very little in terms of protection against 1874 this option being confused by leftover garbage in memory that might 1875 look like a DTB header after a reboot if no actual DTB is appended 1876 to zImage. Do not leave this option active in a production kernel 1877 if you don't intend to always append a DTB. Proper passing of the 1878 location into r2 of a bootloader provided DTB is always preferable 1879 to this option. 1880 1881config ARM_ATAG_DTB_COMPAT 1882 bool "Supplement the appended DTB with traditional ATAG information" 1883 depends on ARM_APPENDED_DTB 1884 help 1885 Some old bootloaders can't be updated to a DTB capable one, yet 1886 they provide ATAGs with memory configuration, the ramdisk address, 1887 the kernel cmdline string, etc. Such information is dynamically 1888 provided by the bootloader and can't always be stored in a static 1889 DTB. To allow a device tree enabled kernel to be used with such 1890 bootloaders, this option allows zImage to extract the information 1891 from the ATAG list and store it at run time into the appended DTB. 1892 1893choice 1894 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1895 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1896 1897config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1898 bool "Use bootloader kernel arguments if available" 1899 help 1900 Uses the command-line options passed by the boot loader instead of 1901 the device tree bootargs property. If the boot loader doesn't provide 1902 any, the device tree bootargs property will be used. 1903 1904config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1905 bool "Extend with bootloader kernel arguments" 1906 help 1907 The command-line arguments provided by the boot loader will be 1908 appended to the the device tree bootargs property. 1909 1910endchoice 1911 1912config CMDLINE 1913 string "Default kernel command string" 1914 default "" 1915 help 1916 On some architectures (EBSA110 and CATS), there is currently no way 1917 for the boot loader to pass arguments to the kernel. For these 1918 architectures, you should supply some command-line options at build 1919 time by entering them here. As a minimum, you should specify the 1920 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1921 1922choice 1923 prompt "Kernel command line type" if CMDLINE != "" 1924 default CMDLINE_FROM_BOOTLOADER 1925 depends on ATAGS 1926 1927config CMDLINE_FROM_BOOTLOADER 1928 bool "Use bootloader kernel arguments if available" 1929 help 1930 Uses the command-line options passed by the boot loader. If 1931 the boot loader doesn't provide any, the default kernel command 1932 string provided in CMDLINE will be used. 1933 1934config CMDLINE_EXTEND 1935 bool "Extend bootloader kernel arguments" 1936 help 1937 The command-line arguments provided by the boot loader will be 1938 appended to the default kernel command string. 1939 1940config CMDLINE_FORCE 1941 bool "Always use the default kernel command string" 1942 help 1943 Always use the default kernel command string, even if the boot 1944 loader passes other arguments to the kernel. 1945 This is useful if you cannot or don't want to change the 1946 command-line options your boot loader passes to the kernel. 1947endchoice 1948 1949config XIP_KERNEL 1950 bool "Kernel Execute-In-Place from ROM" 1951 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1952 help 1953 Execute-In-Place allows the kernel to run from non-volatile storage 1954 directly addressable by the CPU, such as NOR flash. This saves RAM 1955 space since the text section of the kernel is not loaded from flash 1956 to RAM. Read-write sections, such as the data section and stack, 1957 are still copied to RAM. The XIP kernel is not compressed since 1958 it has to run directly from flash, so it will take more space to 1959 store it. The flash address used to link the kernel object files, 1960 and for storing it, is configuration dependent. Therefore, if you 1961 say Y here, you must know the proper physical address where to 1962 store the kernel image depending on your own flash memory usage. 1963 1964 Also note that the make target becomes "make xipImage" rather than 1965 "make zImage" or "make Image". The final kernel binary to put in 1966 ROM memory will be arch/arm/boot/xipImage. 1967 1968 If unsure, say N. 1969 1970config XIP_PHYS_ADDR 1971 hex "XIP Kernel Physical Location" 1972 depends on XIP_KERNEL 1973 default "0x00080000" 1974 help 1975 This is the physical address in your flash memory the kernel will 1976 be linked for and stored to. This address is dependent on your 1977 own flash usage. 1978 1979config KEXEC 1980 bool "Kexec system call (EXPERIMENTAL)" 1981 depends on (!SMP || PM_SLEEP_SMP) 1982 depends on !CPU_V7M 1983 select KEXEC_CORE 1984 help 1985 kexec is a system call that implements the ability to shutdown your 1986 current kernel, and to start another kernel. It is like a reboot 1987 but it is independent of the system firmware. And like a reboot 1988 you can start any kernel with it, not just Linux. 1989 1990 It is an ongoing process to be certain the hardware in a machine 1991 is properly shutdown, so do not be surprised if this code does not 1992 initially work for you. 1993 1994config ATAGS_PROC 1995 bool "Export atags in procfs" 1996 depends on ATAGS && KEXEC 1997 default y 1998 help 1999 Should the atags used to boot the kernel be exported in an "atags" 2000 file in procfs. Useful with kexec. 2001 2002config CRASH_DUMP 2003 bool "Build kdump crash kernel (EXPERIMENTAL)" 2004 help 2005 Generate crash dump after being started by kexec. This should 2006 be normally only set in special crash dump kernels which are 2007 loaded in the main kernel with kexec-tools into a specially 2008 reserved region and then later executed after a crash by 2009 kdump/kexec. The crash dump kernel must be compiled to a 2010 memory address not used by the main kernel 2011 2012 For more details see Documentation/kdump/kdump.txt 2013 2014config AUTO_ZRELADDR 2015 bool "Auto calculation of the decompressed kernel image address" 2016 help 2017 ZRELADDR is the physical address where the decompressed kernel 2018 image will be placed. If AUTO_ZRELADDR is selected, the address 2019 will be determined at run-time by masking the current IP with 2020 0xf8000000. This assumes the zImage being placed in the first 128MB 2021 from start of memory. 2022 2023config EFI_STUB 2024 bool 2025 2026config EFI 2027 bool "UEFI runtime support" 2028 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2029 select UCS2_STRING 2030 select EFI_PARAMS_FROM_FDT 2031 select EFI_STUB 2032 select EFI_ARMSTUB 2033 select EFI_RUNTIME_WRAPPERS 2034 ---help--- 2035 This option provides support for runtime services provided 2036 by UEFI firmware (such as non-volatile variables, realtime 2037 clock, and platform reset). A UEFI stub is also provided to 2038 allow the kernel to be booted as an EFI application. This 2039 is only useful for kernels that may run on systems that have 2040 UEFI firmware. 2041 2042endmenu 2043 2044menu "CPU Power Management" 2045 2046source "drivers/cpufreq/Kconfig" 2047 2048source "drivers/cpuidle/Kconfig" 2049 2050endmenu 2051 2052menu "Floating point emulation" 2053 2054comment "At least one emulation must be selected" 2055 2056config FPE_NWFPE 2057 bool "NWFPE math emulation" 2058 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2059 ---help--- 2060 Say Y to include the NWFPE floating point emulator in the kernel. 2061 This is necessary to run most binaries. Linux does not currently 2062 support floating point hardware so you need to say Y here even if 2063 your machine has an FPA or floating point co-processor podule. 2064 2065 You may say N here if you are going to load the Acorn FPEmulator 2066 early in the bootup. 2067 2068config FPE_NWFPE_XP 2069 bool "Support extended precision" 2070 depends on FPE_NWFPE 2071 help 2072 Say Y to include 80-bit support in the kernel floating-point 2073 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2074 Note that gcc does not generate 80-bit operations by default, 2075 so in most cases this option only enlarges the size of the 2076 floating point emulator without any good reason. 2077 2078 You almost surely want to say N here. 2079 2080config FPE_FASTFPE 2081 bool "FastFPE math emulation (EXPERIMENTAL)" 2082 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2083 ---help--- 2084 Say Y here to include the FAST floating point emulator in the kernel. 2085 This is an experimental much faster emulator which now also has full 2086 precision for the mantissa. It does not support any exceptions. 2087 It is very simple, and approximately 3-6 times faster than NWFPE. 2088 2089 It should be sufficient for most programs. It may be not suitable 2090 for scientific calculations, but you have to check this for yourself. 2091 If you do not feel you need a faster FP emulation you should better 2092 choose NWFPE. 2093 2094config VFP 2095 bool "VFP-format floating point maths" 2096 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2097 help 2098 Say Y to include VFP support code in the kernel. This is needed 2099 if your hardware includes a VFP unit. 2100 2101 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2102 release notes and additional status information. 2103 2104 Say N if your target does not have VFP hardware. 2105 2106config VFPv3 2107 bool 2108 depends on VFP 2109 default y if CPU_V7 2110 2111config NEON 2112 bool "Advanced SIMD (NEON) Extension support" 2113 depends on VFPv3 && CPU_V7 2114 help 2115 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2116 Extension. 2117 2118config KERNEL_MODE_NEON 2119 bool "Support for NEON in kernel mode" 2120 depends on NEON && AEABI 2121 help 2122 Say Y to include support for NEON in kernel mode. 2123 2124endmenu 2125 2126menu "Userspace binary formats" 2127 2128source "fs/Kconfig.binfmt" 2129 2130endmenu 2131 2132menu "Power management options" 2133 2134source "kernel/power/Kconfig" 2135 2136config ARCH_SUSPEND_POSSIBLE 2137 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2138 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2139 def_bool y 2140 2141config ARM_CPU_SUSPEND 2142 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2143 depends on ARCH_SUSPEND_POSSIBLE 2144 2145config ARCH_HIBERNATION_POSSIBLE 2146 bool 2147 depends on MMU 2148 default y if ARCH_SUSPEND_POSSIBLE 2149 2150endmenu 2151 2152source "net/Kconfig" 2153 2154source "drivers/Kconfig" 2155 2156source "drivers/firmware/Kconfig" 2157 2158source "fs/Kconfig" 2159 2160source "arch/arm/Kconfig.debug" 2161 2162source "security/Kconfig" 2163 2164source "crypto/Kconfig" 2165if CRYPTO 2166source "arch/arm/crypto/Kconfig" 2167endif 2168 2169source "lib/Kconfig" 2170 2171source "arch/arm/kvm/Kconfig" 2172