1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CURRENT_STACK_POINTER 12 select ARCH_HAS_DEBUG_VIRTUAL if MMU 13 select ARCH_HAS_DMA_ALLOC if MMU 14 select ARCH_HAS_DMA_OPS 15 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 16 select ARCH_HAS_ELF_RANDOMIZE 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_KEEPINITRD 19 select ARCH_HAS_KCOV 20 select ARCH_HAS_MEMBARRIER_SYNC_CORE 21 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 22 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 23 select ARCH_HAS_SETUP_DMA_OPS 24 select ARCH_HAS_SET_MEMORY 25 select ARCH_STACKWALK 26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 27 select ARCH_HAS_STRICT_MODULE_RWX if MMU 28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 29 select ARCH_HAS_SYNC_DMA_FOR_CPU 30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 32 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_KEEP_MEMBLOCK 35 select ARCH_HAS_UBSAN 36 select ARCH_MIGHT_HAVE_PC_PARPORT 37 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 38 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 39 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 40 select ARCH_SUPPORTS_ATOMIC_RMW 41 select ARCH_SUPPORTS_CFI 42 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 43 select ARCH_SUPPORTS_PER_VMA_LOCK 44 select ARCH_USE_BUILTIN_BSWAP 45 select ARCH_USE_CMPXCHG_LOCKREF 46 select ARCH_USE_MEMTEST 47 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 48 select ARCH_WANT_GENERAL_HUGETLB 49 select ARCH_WANT_IPC_PARSE_VERSION 50 select ARCH_WANT_LD_ORPHAN_WARN 51 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 52 select BUILDTIME_TABLE_SORT if MMU 53 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 54 select CLONE_BACKWARDS 55 select CPU_PM if SUSPEND || CPU_IDLE 56 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 57 select DMA_DECLARE_COHERENT 58 select DMA_GLOBAL_POOL if !MMU 59 select DMA_NONCOHERENT_MMAP if MMU 60 select EDAC_SUPPORT 61 select EDAC_ATOMIC_SCRUB 62 select GENERIC_ALLOCATOR 63 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 64 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 65 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 66 select GENERIC_IRQ_IPI if SMP 67 select GENERIC_CPU_AUTOPROBE 68 select GENERIC_CPU_DEVICES 69 select GENERIC_EARLY_IOREMAP 70 select GENERIC_IDLE_POLL_SETUP 71 select GENERIC_IRQ_MULTI_HANDLER 72 select GENERIC_IRQ_PROBE 73 select GENERIC_IRQ_SHOW 74 select GENERIC_IRQ_SHOW_LEVEL 75 select GENERIC_LIB_DEVMEM_IS_ALLOWED 76 select GENERIC_PCI_IOMAP 77 select GENERIC_SCHED_CLOCK 78 select GENERIC_SMP_IDLE_THREAD 79 select HARDIRQS_SW_RESEND 80 select HAS_IOPORT 81 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 83 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 88 select HAVE_ARCH_KSTACK_ERASE 89 select HAVE_ARCH_MMAP_RND_BITS if MMU 90 select HAVE_ARCH_PFN_VALID 91 select HAVE_ARCH_SECCOMP 92 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 93 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 94 select HAVE_ARCH_TRACEHOOK 95 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 96 select HAVE_ARM_SMCCC if CPU_V7 97 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 98 select HAVE_CONTEXT_TRACKING_USER 99 select HAVE_C_RECORDMCOUNT 100 select HAVE_BUILDTIME_MCOUNT_SORT 101 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 102 select HAVE_DMA_CONTIGUOUS if MMU 103 select HAVE_EXTRA_IPI_TRACEPOINTS 104 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 105 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 106 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 107 select HAVE_EXIT_THREAD 108 select HAVE_GUP_FAST if ARM_LPAE 109 select HAVE_FUNCTION_ERROR_INJECTION 110 select HAVE_FUNCTION_GRAPH_TRACER 111 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 112 select HAVE_GCC_PLUGINS 113 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 114 select HAVE_IRQ_TIME_ACCOUNTING 115 select HAVE_KERNEL_GZIP 116 select HAVE_KERNEL_LZ4 117 select HAVE_KERNEL_LZMA 118 select HAVE_KERNEL_LZO 119 select HAVE_KERNEL_XZ 120 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 121 select HAVE_KRETPROBES if HAVE_KPROBES 122 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 123 select HAVE_MOD_ARCH_SPECIFIC 124 select HAVE_NMI 125 select HAVE_OPTPROBES if !THUMB2_KERNEL 126 select HAVE_PAGE_SIZE_4KB 127 select HAVE_PCI if MMU 128 select HAVE_PERF_EVENTS 129 select HAVE_PERF_REGS 130 select HAVE_PERF_USER_STACK_DUMP 131 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 132 select HAVE_REGS_AND_STACK_ACCESS_API 133 select HAVE_RSEQ 134 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 135 select HAVE_STACKPROTECTOR 136 select HAVE_SYSCALL_TRACEPOINTS 137 select HAVE_UID16 138 select HAVE_VIRT_CPU_ACCOUNTING_GEN 139 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 140 select IRQ_FORCED_THREADING 141 select LOCK_MM_AND_FIND_VMA 142 select MODULES_USE_ELF_REL 143 select NEED_DMA_MAP_STATE 144 select OF_EARLY_FLATTREE if OF 145 select OLD_SIGACTION 146 select OLD_SIGSUSPEND3 147 select PCI_DOMAINS_GENERIC if PCI 148 select PCI_SYSCALL if PCI 149 select PERF_USE_VMALLOC 150 select RTC_LIB 151 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 152 select SYS_SUPPORTS_APM_EMULATION 153 select THREAD_INFO_IN_TASK 154 select TIMER_OF if OF 155 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 156 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 157 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 158 # Above selects are sorted alphabetically; please add new ones 159 # according to that. Thanks. 160 help 161 The ARM series is a line of low-power-consumption RISC chip designs 162 licensed by ARM Ltd and targeted at embedded applications and 163 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 164 manufactured, but legacy ARM-based PC hardware remains popular in 165 Europe. There is an ARM Linux project with a web page at 166 <http://www.arm.linux.org.uk/>. 167 168config ARM_HAS_GROUP_RELOCS 169 def_bool !COMPILE_TEST 170 help 171 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 172 relocations. The combined range is -/+ 256 MiB, which is usually 173 sufficient, but not for allyesconfig, so we disable this feature 174 when doing compile testing. 175 176config ARM_DMA_USE_IOMMU 177 bool 178 select NEED_SG_DMA_LENGTH 179 180if ARM_DMA_USE_IOMMU 181 182config ARM_DMA_IOMMU_ALIGNMENT 183 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 184 range 4 9 185 default 8 186 help 187 DMA mapping framework by default aligns all buffers to the smallest 188 PAGE_SIZE order which is greater than or equal to the requested buffer 189 size. This works well for buffers up to a few hundreds kilobytes, but 190 for larger buffers it just a waste of address space. Drivers which has 191 relatively small addressing window (like 64Mib) might run out of 192 virtual space with just a few allocations. 193 194 With this parameter you can specify the maximum PAGE_SIZE order for 195 DMA IOMMU buffers. Larger buffers will be aligned only to this 196 specified order. The order is expressed as a power of two multiplied 197 by the PAGE_SIZE. 198 199endif 200 201config SYS_SUPPORTS_APM_EMULATION 202 bool 203 204config HAVE_TCM 205 bool 206 select GENERIC_ALLOCATOR 207 208config HAVE_PROC_CPU 209 bool 210 211config NO_IOPORT_MAP 212 bool 213 214config SBUS 215 bool 216 217config STACKTRACE_SUPPORT 218 bool 219 default y 220 221config LOCKDEP_SUPPORT 222 bool 223 default y 224 225config ARCH_HAS_ILOG2_U32 226 bool 227 228config ARCH_HAS_ILOG2_U64 229 bool 230 231config ARCH_HAS_BANDGAP 232 bool 233 234config FIX_EARLYCON_MEM 235 def_bool y if MMU 236 237config GENERIC_HWEIGHT 238 bool 239 default y 240 241config GENERIC_CALIBRATE_DELAY 242 bool 243 default y 244 245config ARCH_MAY_HAVE_PC_FDC 246 bool 247 248config ARCH_SUPPORTS_UPROBES 249 def_bool y 250 251config GENERIC_ISA_DMA 252 bool 253 254config FIQ 255 bool 256 257config ARCH_MTD_XIP 258 bool 259 260config ARM_PATCH_PHYS_VIRT 261 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 262 default y 263 depends on MMU 264 help 265 Patch phys-to-virt and virt-to-phys translation functions at 266 boot and module load time according to the position of the 267 kernel in system memory. 268 269 This can only be used with non-XIP MMU kernels where the base 270 of physical memory is at a 2 MiB boundary. 271 272 Only disable this option if you know that you do not require 273 this feature (eg, building a kernel for a single machine) and 274 you need to shrink the kernel to the minimal size. 275 276config NEED_MACH_IO_H 277 bool 278 help 279 Select this when mach/io.h is required to provide special 280 definitions for this platform. The need for mach/io.h should 281 be avoided when possible. 282 283config NEED_MACH_MEMORY_H 284 bool 285 help 286 Select this when mach/memory.h is required to provide special 287 definitions for this platform. The need for mach/memory.h should 288 be avoided when possible. 289 290config PHYS_OFFSET 291 hex "Physical address of main memory" if MMU 292 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 293 default DRAM_BASE if !MMU 294 default 0x00000000 if ARCH_FOOTBRIDGE 295 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 296 default 0xa0000000 if ARCH_PXA 297 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 298 default 0 299 help 300 Please provide the physical address corresponding to the 301 location of main memory in your system. 302 303config GENERIC_BUG 304 def_bool y 305 depends on BUG 306 307config PGTABLE_LEVELS 308 int 309 default 3 if ARM_LPAE 310 default 2 311 312menu "System Type" 313 314config MMU 315 bool "MMU-based Paged Memory Management Support" 316 default y 317 help 318 Select if you want MMU-based virtualised addressing space 319 support by paged memory management. If unsure, say 'Y'. 320 321config ARM_SINGLE_ARMV7M 322 def_bool !MMU 323 select ARM_NVIC 324 select CPU_V7M 325 select NO_IOPORT_MAP 326 327config ARCH_MMAP_RND_BITS_MIN 328 default 8 329 330config ARCH_MMAP_RND_BITS_MAX 331 default 14 if PAGE_OFFSET=0x40000000 332 default 15 if PAGE_OFFSET=0x80000000 333 default 16 334 335config ARCH_MULTIPLATFORM 336 bool "Require kernel to be portable to multiple machines" if EXPERT 337 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 338 default y 339 help 340 In general, all Arm machines can be supported in a single 341 kernel image, covering either Armv4/v5 or Armv6/v7. 342 343 However, some configuration options require hardcoding machine 344 specific physical addresses or enable errata workarounds that may 345 break other machines. 346 347 Selecting N here allows using those options, including 348 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 349 350source "arch/arm/Kconfig.platforms" 351 352# 353# This is sorted alphabetically by mach-* pathname. However, plat-* 354# Kconfigs may be included either alphabetically (according to the 355# plat- suffix) or along side the corresponding mach-* source. 356# 357source "arch/arm/mach-actions/Kconfig" 358 359source "arch/arm/mach-alpine/Kconfig" 360 361source "arch/arm/mach-artpec/Kconfig" 362 363source "arch/arm/mach-aspeed/Kconfig" 364 365source "arch/arm/mach-at91/Kconfig" 366 367source "arch/arm/mach-axxia/Kconfig" 368 369source "arch/arm/mach-bcm/Kconfig" 370 371source "arch/arm/mach-berlin/Kconfig" 372 373source "arch/arm/mach-clps711x/Kconfig" 374 375source "arch/arm/mach-davinci/Kconfig" 376 377source "arch/arm/mach-digicolor/Kconfig" 378 379source "arch/arm/mach-dove/Kconfig" 380 381source "arch/arm/mach-ep93xx/Kconfig" 382 383source "arch/arm/mach-exynos/Kconfig" 384 385source "arch/arm/mach-footbridge/Kconfig" 386 387source "arch/arm/mach-gemini/Kconfig" 388 389source "arch/arm/mach-highbank/Kconfig" 390 391source "arch/arm/mach-hisi/Kconfig" 392 393source "arch/arm/mach-imx/Kconfig" 394 395source "arch/arm/mach-ixp4xx/Kconfig" 396 397source "arch/arm/mach-keystone/Kconfig" 398 399source "arch/arm/mach-lpc32xx/Kconfig" 400 401source "arch/arm/mach-mediatek/Kconfig" 402 403source "arch/arm/mach-meson/Kconfig" 404 405source "arch/arm/mach-milbeaut/Kconfig" 406 407source "arch/arm/mach-mmp/Kconfig" 408 409source "arch/arm/mach-mstar/Kconfig" 410 411source "arch/arm/mach-mv78xx0/Kconfig" 412 413source "arch/arm/mach-mvebu/Kconfig" 414 415source "arch/arm/mach-mxs/Kconfig" 416 417source "arch/arm/mach-nomadik/Kconfig" 418 419source "arch/arm/mach-npcm/Kconfig" 420 421source "arch/arm/mach-omap1/Kconfig" 422 423source "arch/arm/mach-omap2/Kconfig" 424 425source "arch/arm/mach-orion5x/Kconfig" 426 427source "arch/arm/mach-pxa/Kconfig" 428 429source "arch/arm/mach-qcom/Kconfig" 430 431source "arch/arm/mach-realtek/Kconfig" 432 433source "arch/arm/mach-rpc/Kconfig" 434 435source "arch/arm/mach-rockchip/Kconfig" 436 437source "arch/arm/mach-s3c/Kconfig" 438 439source "arch/arm/mach-s5pv210/Kconfig" 440 441source "arch/arm/mach-sa1100/Kconfig" 442 443source "arch/arm/mach-shmobile/Kconfig" 444 445source "arch/arm/mach-socfpga/Kconfig" 446 447source "arch/arm/mach-spear/Kconfig" 448 449source "arch/arm/mach-sti/Kconfig" 450 451source "arch/arm/mach-stm32/Kconfig" 452 453source "arch/arm/mach-sunxi/Kconfig" 454 455source "arch/arm/mach-tegra/Kconfig" 456 457source "arch/arm/mach-ux500/Kconfig" 458 459source "arch/arm/mach-versatile/Kconfig" 460 461source "arch/arm/mach-vt8500/Kconfig" 462 463source "arch/arm/mach-zynq/Kconfig" 464 465# ARMv7-M architecture 466config ARCH_LPC18XX 467 bool "NXP LPC18xx/LPC43xx" 468 depends on ARM_SINGLE_ARMV7M 469 select ARCH_HAS_RESET_CONTROLLER 470 select ARM_AMBA 471 select CLKSRC_LPC32XX 472 select PINCTRL 473 help 474 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 475 high performance microcontrollers. 476 477config ARCH_MPS2 478 bool "ARM MPS2 platform" 479 depends on ARM_SINGLE_ARMV7M 480 select ARM_AMBA 481 select CLKSRC_MPS2 482 help 483 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 484 with a range of available cores like Cortex-M3/M4/M7. 485 486 Please, note that depends which Application Note is used memory map 487 for the platform may vary, so adjustment of RAM base might be needed. 488 489# Definitions to make life easier 490config ARCH_ACORN 491 bool 492 493config PLAT_ORION 494 bool 495 select CLKSRC_MMIO 496 select GENERIC_IRQ_CHIP 497 select IRQ_DOMAIN 498 499config PLAT_ORION_LEGACY 500 bool 501 select PLAT_ORION 502 503config PLAT_VERSATILE 504 bool 505 506source "arch/arm/mm/Kconfig" 507 508config IWMMXT 509 bool "Enable iWMMXt support" 510 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 511 default y if PXA27x || PXA3xx || ARCH_MMP 512 help 513 Enable support for iWMMXt context switching at run time if 514 running on a CPU that supports it. 515 516if !MMU 517source "arch/arm/Kconfig-nommu" 518endif 519 520config PJ4B_ERRATA_4742 521 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 522 depends on CPU_PJ4B && MACH_ARMADA_370 523 default y 524 help 525 When coming out of either a Wait for Interrupt (WFI) or a Wait for 526 Event (WFE) IDLE states, a specific timing sensitivity exists between 527 the retiring WFI/WFE instructions and the newly issued subsequent 528 instructions. This sensitivity can result in a CPU hang scenario. 529 Workaround: 530 The software must insert either a Data Synchronization Barrier (DSB) 531 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 532 instruction 533 534config ARM_ERRATA_326103 535 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 536 depends on CPU_V6 537 help 538 Executing a SWP instruction to read-only memory does not set bit 11 539 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 540 treat the access as a read, preventing a COW from occurring and 541 causing the faulting task to livelock. 542 543config ARM_ERRATA_411920 544 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 545 depends on CPU_V6 || CPU_V6K 546 help 547 Invalidation of the Instruction Cache operation can 548 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 549 It does not affect the MPCore. This option enables the ARM Ltd. 550 recommended workaround. 551 552config ARM_ERRATA_430973 553 bool "ARM errata: Stale prediction on replaced interworking branch" 554 depends on CPU_V7 555 help 556 This option enables the workaround for the 430973 Cortex-A8 557 r1p* erratum. If a code sequence containing an ARM/Thumb 558 interworking branch is replaced with another code sequence at the 559 same virtual address, whether due to self-modifying code or virtual 560 to physical address re-mapping, Cortex-A8 does not recover from the 561 stale interworking branch prediction. This results in Cortex-A8 562 executing the new code sequence in the incorrect ARM or Thumb state. 563 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 564 and also flushes the branch target cache at every context switch. 565 Note that setting specific bits in the ACTLR register may not be 566 available in non-secure mode. 567 568config ARM_ERRATA_458693 569 bool "ARM errata: Processor deadlock when a false hazard is created" 570 depends on CPU_V7 571 depends on !ARCH_MULTIPLATFORM 572 help 573 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 574 erratum. For very specific sequences of memory operations, it is 575 possible for a hazard condition intended for a cache line to instead 576 be incorrectly associated with a different cache line. This false 577 hazard might then cause a processor deadlock. The workaround enables 578 the L1 caching of the NEON accesses and disables the PLD instruction 579 in the ACTLR register. Note that setting specific bits in the ACTLR 580 register may not be available in non-secure mode and thus is not 581 available on a multiplatform kernel. This should be applied by the 582 bootloader instead. 583 584config ARM_ERRATA_460075 585 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 586 depends on CPU_V7 587 depends on !ARCH_MULTIPLATFORM 588 help 589 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 590 erratum. Any asynchronous access to the L2 cache may encounter a 591 situation in which recent store transactions to the L2 cache are lost 592 and overwritten with stale memory contents from external memory. The 593 workaround disables the write-allocate mode for the L2 cache via the 594 ACTLR register. Note that setting specific bits in the ACTLR register 595 may not be available in non-secure mode and thus is not available on 596 a multiplatform kernel. This should be applied by the bootloader 597 instead. 598 599config ARM_ERRATA_742230 600 bool "ARM errata: DMB operation may be faulty" 601 depends on CPU_V7 && SMP 602 depends on !ARCH_MULTIPLATFORM 603 help 604 This option enables the workaround for the 742230 Cortex-A9 605 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 606 between two write operations may not ensure the correct visibility 607 ordering of the two writes. This workaround sets a specific bit in 608 the diagnostic register of the Cortex-A9 which causes the DMB 609 instruction to behave as a DSB, ensuring the correct behaviour of 610 the two writes. Note that setting specific bits in the diagnostics 611 register may not be available in non-secure mode and thus is not 612 available on a multiplatform kernel. This should be applied by the 613 bootloader instead. 614 615config ARM_ERRATA_742231 616 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 617 depends on CPU_V7 && SMP 618 depends on !ARCH_MULTIPLATFORM 619 help 620 This option enables the workaround for the 742231 Cortex-A9 621 (r2p0..r2p2) erratum. Under certain conditions, specific to the 622 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 623 accessing some data located in the same cache line, may get corrupted 624 data due to bad handling of the address hazard when the line gets 625 replaced from one of the CPUs at the same time as another CPU is 626 accessing it. This workaround sets specific bits in the diagnostic 627 register of the Cortex-A9 which reduces the linefill issuing 628 capabilities of the processor. Note that setting specific bits in the 629 diagnostics register may not be available in non-secure mode and thus 630 is not available on a multiplatform kernel. This should be applied by 631 the bootloader instead. 632 633config ARM_ERRATA_643719 634 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 635 depends on CPU_V7 && SMP 636 default y 637 help 638 This option enables the workaround for the 643719 Cortex-A9 (prior to 639 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 640 register returns zero when it should return one. The workaround 641 corrects this value, ensuring cache maintenance operations which use 642 it behave as intended and avoiding data corruption. 643 644config ARM_ERRATA_720789 645 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 646 depends on CPU_V7 647 help 648 This option enables the workaround for the 720789 Cortex-A9 (prior to 649 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 650 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 651 As a consequence of this erratum, some TLB entries which should be 652 invalidated are not, resulting in an incoherency in the system page 653 tables. The workaround changes the TLB flushing routines to invalidate 654 entries regardless of the ASID. 655 656config ARM_ERRATA_743622 657 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 658 depends on CPU_V7 659 depends on !ARCH_MULTIPLATFORM 660 help 661 This option enables the workaround for the 743622 Cortex-A9 662 (r2p*) erratum. Under very rare conditions, a faulty 663 optimisation in the Cortex-A9 Store Buffer may lead to data 664 corruption. This workaround sets a specific bit in the diagnostic 665 register of the Cortex-A9 which disables the Store Buffer 666 optimisation, preventing the defect from occurring. This has no 667 visible impact on the overall performance or power consumption of the 668 processor. Note that setting specific bits in the diagnostics register 669 may not be available in non-secure mode and thus is not available on a 670 multiplatform kernel. This should be applied by the bootloader instead. 671 672config ARM_ERRATA_751472 673 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 674 depends on CPU_V7 675 depends on !ARCH_MULTIPLATFORM 676 help 677 This option enables the workaround for the 751472 Cortex-A9 (prior 678 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 679 completion of a following broadcasted operation if the second 680 operation is received by a CPU before the ICIALLUIS has completed, 681 potentially leading to corrupted entries in the cache or TLB. 682 Note that setting specific bits in the diagnostics register may 683 not be available in non-secure mode and thus is not available on 684 a multiplatform kernel. This should be applied by the bootloader 685 instead. 686 687config ARM_ERRATA_754322 688 bool "ARM errata: possible faulty MMU translations following an ASID switch" 689 depends on CPU_V7 690 help 691 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 692 r3p*) erratum. A speculative memory access may cause a page table walk 693 which starts prior to an ASID switch but completes afterwards. This 694 can populate the micro-TLB with a stale entry which may be hit with 695 the new ASID. This workaround places two dsb instructions in the mm 696 switching code so that no page table walks can cross the ASID switch. 697 698config ARM_ERRATA_754327 699 bool "ARM errata: no automatic Store Buffer drain" 700 depends on CPU_V7 && SMP 701 help 702 This option enables the workaround for the 754327 Cortex-A9 (prior to 703 r2p0) erratum. The Store Buffer does not have any automatic draining 704 mechanism and therefore a livelock may occur if an external agent 705 continuously polls a memory location waiting to observe an update. 706 This workaround defines cpu_relax() as smp_mb(), preventing correctly 707 written polling loops from denying visibility of updates to memory. 708 709config ARM_ERRATA_364296 710 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 711 depends on CPU_V6 712 help 713 This options enables the workaround for the 364296 ARM1136 714 r0p2 erratum (possible cache data corruption with 715 hit-under-miss enabled). It sets the undocumented bit 31 in 716 the auxiliary control register and the FI bit in the control 717 register, thus disabling hit-under-miss without putting the 718 processor into full low interrupt latency mode. ARM11MPCore 719 is not affected. 720 721config ARM_ERRATA_764369 722 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 723 depends on CPU_V7 && SMP 724 help 725 This option enables the workaround for erratum 764369 726 affecting Cortex-A9 MPCore with two or more processors (all 727 current revisions). Under certain timing circumstances, a data 728 cache line maintenance operation by MVA targeting an Inner 729 Shareable memory region may fail to proceed up to either the 730 Point of Coherency or to the Point of Unification of the 731 system. This workaround adds a DSB instruction before the 732 relevant cache maintenance functions and sets a specific bit 733 in the diagnostic control register of the SCU. 734 735config ARM_ERRATA_764319 736 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 737 depends on CPU_V7 738 help 739 This option enables the workaround for the 764319 Cortex-A9 erratum. 740 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 741 unexpected Undefined Instruction exception when the DBGSWENABLE 742 external pin is set to 0, even when the CP14 accesses are performed 743 from a privileged mode. This work around catches the exception in a 744 way the kernel does not stop execution. 745 746config ARM_ERRATA_775420 747 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 748 depends on CPU_V7 749 help 750 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 751 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 752 operation aborts with MMU exception, it might cause the processor 753 to deadlock. This workaround puts DSB before executing ISB if 754 an abort may occur on cache maintenance. 755 756config ARM_ERRATA_798181 757 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 758 depends on CPU_V7 && SMP 759 help 760 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 761 adequately shooting down all use of the old entries. This 762 option enables the Linux kernel workaround for this erratum 763 which sends an IPI to the CPUs that are running the same ASID 764 as the one being invalidated. 765 766config ARM_ERRATA_773022 767 bool "ARM errata: incorrect instructions may be executed from loop buffer" 768 depends on CPU_V7 769 help 770 This option enables the workaround for the 773022 Cortex-A15 771 (up to r0p4) erratum. In certain rare sequences of code, the 772 loop buffer may deliver incorrect instructions. This 773 workaround disables the loop buffer to avoid the erratum. 774 775config ARM_ERRATA_818325_852422 776 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 777 depends on CPU_V7 778 help 779 This option enables the workaround for: 780 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 781 instruction might deadlock. Fixed in r0p1. 782 - Cortex-A12 852422: Execution of a sequence of instructions might 783 lead to either a data corruption or a CPU deadlock. Not fixed in 784 any Cortex-A12 cores yet. 785 This workaround for all both errata involves setting bit[12] of the 786 Feature Register. This bit disables an optimisation applied to a 787 sequence of 2 instructions that use opposing condition codes. 788 789config ARM_ERRATA_821420 790 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 791 depends on CPU_V7 792 help 793 This option enables the workaround for the 821420 Cortex-A12 794 (all revs) erratum. In very rare timing conditions, a sequence 795 of VMOV to Core registers instructions, for which the second 796 one is in the shadow of a branch or abort, can lead to a 797 deadlock when the VMOV instructions are issued out-of-order. 798 799config ARM_ERRATA_825619 800 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 801 depends on CPU_V7 802 help 803 This option enables the workaround for the 825619 Cortex-A12 804 (all revs) erratum. Within rare timing constraints, executing a 805 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 806 and Device/Strongly-Ordered loads and stores might cause deadlock 807 808config ARM_ERRATA_857271 809 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 857271 Cortex-A12 813 (all revs) erratum. Under very rare timing conditions, the CPU might 814 hang. The workaround is expected to have a < 1% performance impact. 815 816config ARM_ERRATA_852421 817 bool "ARM errata: A17: DMB ST might fail to create order between stores" 818 depends on CPU_V7 819 help 820 This option enables the workaround for the 852421 Cortex-A17 821 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 822 execution of a DMB ST instruction might fail to properly order 823 stores from GroupA and stores from GroupB. 824 825config ARM_ERRATA_852423 826 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 827 depends on CPU_V7 828 help 829 This option enables the workaround for: 830 - Cortex-A17 852423: Execution of a sequence of instructions might 831 lead to either a data corruption or a CPU deadlock. Not fixed in 832 any Cortex-A17 cores yet. 833 This is identical to Cortex-A12 erratum 852422. It is a separate 834 config option from the A12 erratum due to the way errata are checked 835 for and handled. 836 837config ARM_ERRATA_857272 838 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 839 depends on CPU_V7 840 help 841 This option enables the workaround for the 857272 Cortex-A17 erratum. 842 This erratum is not known to be fixed in any A17 revision. 843 This is identical to Cortex-A12 erratum 857271. It is a separate 844 config option from the A12 erratum due to the way errata are checked 845 for and handled. 846 847endmenu 848 849source "arch/arm/common/Kconfig" 850 851menu "Bus support" 852 853config ISA 854 bool 855 help 856 Find out whether you have ISA slots on your motherboard. ISA is the 857 name of a bus system, i.e. the way the CPU talks to the other stuff 858 inside your box. Other bus systems are PCI, EISA, MicroChannel 859 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 860 newer boards don't support it. If you have ISA, say Y, otherwise N. 861 862# Select ISA DMA interface 863config ISA_DMA_API 864 bool 865 866config ARM_ERRATA_814220 867 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 868 depends on CPU_V7 869 help 870 The v7 ARM states that all cache and branch predictor maintenance 871 operations that do not specify an address execute, relative to 872 each other, in program order. 873 However, because of this erratum, an L2 set/way cache maintenance 874 operation can overtake an L1 set/way cache maintenance operation. 875 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 876 r0p4, r0p5. 877 878endmenu 879 880menu "Kernel Features" 881 882config HAVE_SMP 883 bool 884 help 885 This option should be selected by machines which have an SMP- 886 capable CPU. 887 888 The only effect of this option is to make the SMP-related 889 options available to the user for configuration. 890 891config SMP 892 bool "Symmetric Multi-Processing" 893 depends on CPU_V6K || CPU_V7 894 depends on HAVE_SMP 895 depends on MMU || ARM_MPU 896 select IRQ_WORK 897 help 898 This enables support for systems with more than one CPU. If you have 899 a system with only one CPU, say N. If you have a system with more 900 than one CPU, say Y. 901 902 If you say N here, the kernel will run on uni- and multiprocessor 903 machines, but will use only one CPU of a multiprocessor machine. If 904 you say Y here, the kernel will run on many, but not all, 905 uniprocessor machines. On a uniprocessor machine, the kernel 906 will run faster if you say N here. 907 908 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 909 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 910 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 911 912 If you don't know what to do here, say N. 913 914config SMP_ON_UP 915 bool "Allow booting SMP kernel on uniprocessor systems" 916 depends on SMP && MMU 917 default y 918 help 919 SMP kernels contain instructions which fail on non-SMP processors. 920 Enabling this option allows the kernel to modify itself to make 921 these instructions safe. Disabling it allows about 1K of space 922 savings. 923 924 If you don't know what to do here, say Y. 925 926 927config CURRENT_POINTER_IN_TPIDRURO 928 def_bool y 929 depends on CPU_32v6K && !CPU_V6 930 931config IRQSTACKS 932 def_bool y 933 select HAVE_IRQ_EXIT_ON_IRQ_STACK 934 select HAVE_SOFTIRQ_ON_OWN_STACK 935 936config ARM_CPU_TOPOLOGY 937 bool "Support cpu topology definition" 938 depends on SMP && CPU_V7 939 select ARCH_SUPPORTS_SCHED_MC 940 select ARCH_SUPPORTS_SCHED_SMT 941 default y 942 help 943 Support ARM cpu topology definition. The MPIDR register defines 944 affinity between processors which is then used to describe the cpu 945 topology of an ARM System. 946 947config HAVE_ARM_SCU 948 bool 949 help 950 This option enables support for the ARM snoop control unit 951 952config HAVE_ARM_ARCH_TIMER 953 bool "Architected timer support" 954 depends on CPU_V7 955 select ARM_ARCH_TIMER 956 help 957 This option enables support for the ARM architected timer 958 959config HAVE_ARM_TWD 960 bool 961 help 962 This options enables support for the ARM timer and watchdog unit 963 964config MCPM 965 bool "Multi-Cluster Power Management" 966 depends on CPU_V7 && SMP 967 help 968 This option provides the common power management infrastructure 969 for (multi-)cluster based systems, such as big.LITTLE based 970 systems. 971 972config MCPM_QUAD_CLUSTER 973 bool 974 depends on MCPM 975 help 976 To avoid wasting resources unnecessarily, MCPM only supports up 977 to 2 clusters by default. 978 Platforms with 3 or 4 clusters that use MCPM must select this 979 option to allow the additional clusters to be managed. 980 981config BIG_LITTLE 982 bool "big.LITTLE support (Experimental)" 983 depends on CPU_V7 && SMP 984 select MCPM 985 help 986 This option enables support selections for the big.LITTLE 987 system architecture. 988 989config BL_SWITCHER 990 bool "big.LITTLE switcher support" 991 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 992 select CPU_PM 993 help 994 The big.LITTLE "switcher" provides the core functionality to 995 transparently handle transition between a cluster of A15's 996 and a cluster of A7's in a big.LITTLE system. 997 998config BL_SWITCHER_DUMMY_IF 999 tristate "Simple big.LITTLE switcher user interface" 1000 depends on BL_SWITCHER && DEBUG_KERNEL 1001 help 1002 This is a simple and dummy char dev interface to control 1003 the big.LITTLE switcher core code. It is meant for 1004 debugging purposes only. 1005 1006choice 1007 prompt "Memory split" 1008 depends on MMU 1009 default VMSPLIT_3G 1010 help 1011 Select the desired split between kernel and user memory. 1012 1013 If you are not absolutely sure what you are doing, leave this 1014 option alone! 1015 1016 config VMSPLIT_3G 1017 bool "3G/1G user/kernel split" 1018 config VMSPLIT_3G_OPT 1019 depends on !ARM_LPAE 1020 bool "3G/1G user/kernel split (for full 1G low memory)" 1021 config VMSPLIT_2G 1022 bool "2G/2G user/kernel split" 1023 config VMSPLIT_1G 1024 bool "1G/3G user/kernel split" 1025endchoice 1026 1027config PAGE_OFFSET 1028 hex 1029 default PHYS_OFFSET if !MMU 1030 default 0x40000000 if VMSPLIT_1G 1031 default 0x80000000 if VMSPLIT_2G 1032 default 0xB0000000 if VMSPLIT_3G_OPT 1033 default 0xC0000000 1034 1035config KASAN_SHADOW_OFFSET 1036 hex 1037 depends on KASAN 1038 default 0x1f000000 if PAGE_OFFSET=0x40000000 1039 default 0x5f000000 if PAGE_OFFSET=0x80000000 1040 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1041 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1042 default 0xffffffff 1043 1044config NR_CPUS 1045 int "Maximum number of CPUs (2-32)" 1046 range 2 16 if DEBUG_KMAP_LOCAL 1047 range 2 32 if !DEBUG_KMAP_LOCAL 1048 depends on SMP 1049 default "4" 1050 help 1051 The maximum number of CPUs that the kernel can support. 1052 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1053 debugging is enabled, which uses half of the per-CPU fixmap 1054 slots as guard regions. 1055 1056config HOTPLUG_CPU 1057 bool "Support for hot-pluggable CPUs" 1058 depends on SMP 1059 select GENERIC_IRQ_MIGRATION 1060 help 1061 Say Y here to experiment with turning CPUs off and on. CPUs 1062 can be controlled through /sys/devices/system/cpu. 1063 1064config ARM_PSCI 1065 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1066 depends on HAVE_ARM_SMCCC 1067 select ARM_PSCI_FW 1068 help 1069 Say Y here if you want Linux to communicate with system firmware 1070 implementing the PSCI specification for CPU-centric power 1071 management operations described in ARM document number ARM DEN 1072 0022A ("Power State Coordination Interface System Software on 1073 ARM processors"). 1074 1075config HZ_FIXED 1076 int 1077 default 128 if SOC_AT91RM9200 1078 default 0 1079 1080choice 1081 depends on HZ_FIXED = 0 1082 prompt "Timer frequency" 1083 1084config HZ_100 1085 bool "100 Hz" 1086 1087config HZ_200 1088 bool "200 Hz" 1089 1090config HZ_250 1091 bool "250 Hz" 1092 1093config HZ_300 1094 bool "300 Hz" 1095 1096config HZ_500 1097 bool "500 Hz" 1098 1099config HZ_1000 1100 bool "1000 Hz" 1101 1102endchoice 1103 1104config HZ 1105 int 1106 default HZ_FIXED if HZ_FIXED != 0 1107 default 100 if HZ_100 1108 default 200 if HZ_200 1109 default 250 if HZ_250 1110 default 300 if HZ_300 1111 default 500 if HZ_500 1112 default 1000 1113 1114config SCHED_HRTICK 1115 def_bool HIGH_RES_TIMERS 1116 1117config THUMB2_KERNEL 1118 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1119 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1120 default y if CPU_THUMBONLY 1121 select ARM_UNWIND 1122 help 1123 By enabling this option, the kernel will be compiled in 1124 Thumb-2 mode. 1125 1126 If unsure, say N. 1127 1128config ARM_PATCH_IDIV 1129 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1130 depends on CPU_32v7 1131 default y 1132 help 1133 The ARM compiler inserts calls to __aeabi_idiv() and 1134 __aeabi_uidiv() when it needs to perform division on signed 1135 and unsigned integers. Some v7 CPUs have support for the sdiv 1136 and udiv instructions that can be used to implement those 1137 functions. 1138 1139 Enabling this option allows the kernel to modify itself to 1140 replace the first two instructions of these library functions 1141 with the sdiv or udiv plus "bx lr" instructions when the CPU 1142 it is running on supports them. Typically this will be faster 1143 and less power intensive than running the original library 1144 code to do integer division. 1145 1146config AEABI 1147 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1148 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1149 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1150 help 1151 This option allows for the kernel to be compiled using the latest 1152 ARM ABI (aka EABI). This is only useful if you are using a user 1153 space environment that is also compiled with EABI. 1154 1155 Since there are major incompatibilities between the legacy ABI and 1156 EABI, especially with regard to structure member alignment, this 1157 option also changes the kernel syscall calling convention to 1158 disambiguate both ABIs and allow for backward compatibility support 1159 (selected with CONFIG_OABI_COMPAT). 1160 1161 To use this you need GCC version 4.0.0 or later. 1162 1163config OABI_COMPAT 1164 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1165 depends on AEABI && !THUMB2_KERNEL 1166 help 1167 This option preserves the old syscall interface along with the 1168 new (ARM EABI) one. It also provides a compatibility layer to 1169 intercept syscalls that have structure arguments which layout 1170 in memory differs between the legacy ABI and the new ARM EABI 1171 (only for non "thumb" binaries). This option adds a tiny 1172 overhead to all syscalls and produces a slightly larger kernel. 1173 1174 The seccomp filter system will not be available when this is 1175 selected, since there is no way yet to sensibly distinguish 1176 between calling conventions during filtering. 1177 1178 If you know you'll be using only pure EABI user space then you 1179 can say N here. If this option is not selected and you attempt 1180 to execute a legacy ABI binary then the result will be 1181 UNPREDICTABLE (in fact it can be predicted that it won't work 1182 at all). If in doubt say N. 1183 1184config ARCH_SELECT_MEMORY_MODEL 1185 def_bool y 1186 1187config ARCH_FLATMEM_ENABLE 1188 def_bool !(ARCH_RPC || ARCH_SA1100) 1189 1190config ARCH_SPARSEMEM_ENABLE 1191 def_bool !ARCH_FOOTBRIDGE 1192 select SPARSEMEM_STATIC if SPARSEMEM 1193 1194config HIGHMEM 1195 bool "High Memory Support" 1196 depends on MMU 1197 select KMAP_LOCAL 1198 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1199 help 1200 The address space of ARM processors is only 4 Gigabytes large 1201 and it has to accommodate user address space, kernel address 1202 space as well as some memory mapped IO. That means that, if you 1203 have a large amount of physical memory and/or IO, not all of the 1204 memory can be "permanently mapped" by the kernel. The physical 1205 memory that is not permanently mapped is called "high memory". 1206 1207 Depending on the selected kernel/user memory split, minimum 1208 vmalloc space and actual amount of RAM, you may not need this 1209 option which should result in a slightly faster kernel. 1210 1211 If unsure, say n. 1212 1213config HIGHPTE 1214 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1215 depends on HIGHMEM 1216 default y 1217 help 1218 The VM uses one page of physical memory for each page table. 1219 For systems with a lot of processes, this can use a lot of 1220 precious low memory, eventually leading to low memory being 1221 consumed by page tables. Setting this option will allow 1222 user-space 2nd level page tables to reside in high memory. 1223 1224config ARM_PAN 1225 bool "Enable privileged no-access" 1226 depends on MMU 1227 default y 1228 help 1229 Increase kernel security by ensuring that normal kernel accesses 1230 are unable to access userspace addresses. This can help prevent 1231 use-after-free bugs becoming an exploitable privilege escalation 1232 by ensuring that magic values (such as LIST_POISON) will always 1233 fault when dereferenced. 1234 1235 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1236 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1237 1238config CPU_SW_DOMAIN_PAN 1239 def_bool y 1240 depends on ARM_PAN && !ARM_LPAE 1241 help 1242 Enable use of CPU domains to implement privileged no-access. 1243 1244 CPUs with low-vector mappings use a best-efforts implementation. 1245 Their lower 1MB needs to remain accessible for the vectors, but 1246 the remainder of userspace will become appropriately inaccessible. 1247 1248config CPU_TTBR0_PAN 1249 def_bool y 1250 depends on ARM_PAN && ARM_LPAE 1251 help 1252 Enable privileged no-access by disabling TTBR0 page table walks when 1253 running in kernel mode. 1254 1255config HW_PERF_EVENTS 1256 def_bool y 1257 depends on ARM_PMU 1258 1259config ARM_MODULE_PLTS 1260 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1261 depends on MODULES 1262 select KASAN_VMALLOC if KASAN 1263 default y 1264 help 1265 Allocate PLTs when loading modules so that jumps and calls whose 1266 targets are too far away for their relative offsets to be encoded 1267 in the instructions themselves can be bounced via veneers in the 1268 module's PLT. This allows modules to be allocated in the generic 1269 vmalloc area after the dedicated module memory area has been 1270 exhausted. The modules will use slightly more memory, but after 1271 rounding up to page size, the actual memory footprint is usually 1272 the same. 1273 1274 Disabling this is usually safe for small single-platform 1275 configurations. If unsure, say y. 1276 1277config ARCH_FORCE_MAX_ORDER 1278 int "Order of maximal physically contiguous allocations" 1279 default "11" if SOC_AM33XX 1280 default "8" if SA1111 1281 default "10" 1282 help 1283 The kernel page allocator limits the size of maximal physically 1284 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1285 defines the maximal power of two of number of pages that can be 1286 allocated as a single contiguous block. This option allows 1287 overriding the default setting when ability to allocate very 1288 large blocks of physically contiguous memory is required. 1289 1290 Don't change if unsure. 1291 1292config ALIGNMENT_TRAP 1293 def_bool CPU_CP15_MMU 1294 select HAVE_PROC_CPU if PROC_FS 1295 help 1296 ARM processors cannot fetch/store information which is not 1297 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1298 address divisible by 4. On 32-bit ARM processors, these non-aligned 1299 fetch/store instructions will be emulated in software if you say 1300 here, which has a severe performance impact. This is necessary for 1301 correct operation of some network protocols. With an IP-only 1302 configuration it is safe to say N, otherwise say Y. 1303 1304config UACCESS_WITH_MEMCPY 1305 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1306 depends on MMU 1307 default y if CPU_FEROCEON 1308 help 1309 Implement faster copy_to_user and clear_user methods for CPU 1310 cores where a 8-word STM instruction give significantly higher 1311 memory write throughput than a sequence of individual 32bit stores. 1312 1313 A possible side effect is a slight increase in scheduling latency 1314 between threads sharing the same address space if they invoke 1315 such copy operations with large buffers. 1316 1317 However, if the CPU data cache is using a write-allocate mode, 1318 this option is unlikely to provide any performance gain. 1319 1320config PARAVIRT 1321 bool "Enable paravirtualization code" 1322 help 1323 This changes the kernel so it can modify itself when it is run 1324 under a hypervisor, potentially improving performance significantly 1325 over full virtualization. 1326 1327config PARAVIRT_TIME_ACCOUNTING 1328 bool "Paravirtual steal time accounting" 1329 select PARAVIRT 1330 help 1331 Select this option to enable fine granularity task steal time 1332 accounting. Time spent executing other tasks in parallel with 1333 the current vCPU is discounted from the vCPU power. To account for 1334 that, there can be a small performance impact. 1335 1336 If in doubt, say N here. 1337 1338config XEN_DOM0 1339 def_bool y 1340 depends on XEN 1341 1342config XEN 1343 bool "Xen guest support on ARM" 1344 depends on ARM && AEABI && OF 1345 depends on CPU_V7 && !CPU_V6 1346 depends on !GENERIC_ATOMIC64 1347 depends on MMU 1348 select ARCH_DMA_ADDR_T_64BIT 1349 select ARM_PSCI 1350 select SWIOTLB 1351 select SWIOTLB_XEN 1352 select PARAVIRT 1353 help 1354 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1355 1356config CC_HAVE_STACKPROTECTOR_TLS 1357 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1358 1359config STACKPROTECTOR_PER_TASK 1360 bool "Use a unique stack canary value for each task" 1361 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1362 depends on CC_HAVE_STACKPROTECTOR_TLS 1363 default y 1364 help 1365 Due to the fact that GCC uses an ordinary symbol reference from 1366 which to load the value of the stack canary, this value can only 1367 change at reboot time on SMP systems, and all tasks running in the 1368 kernel's address space are forced to use the same canary value for 1369 the entire duration that the system is up. 1370 1371 Enable this option to switch to a different method that uses a 1372 different canary value for each task. 1373 1374endmenu 1375 1376menu "Boot options" 1377 1378config USE_OF 1379 bool "Flattened Device Tree support" 1380 select IRQ_DOMAIN 1381 select OF 1382 help 1383 Include support for flattened device tree machine descriptions. 1384 1385config ARCH_WANT_FLAT_DTB_INSTALL 1386 def_bool y 1387 1388config ATAGS 1389 bool "Support for the traditional ATAGS boot data passing" 1390 default y 1391 help 1392 This is the traditional way of passing data to the kernel at boot 1393 time. If you are solely relying on the flattened device tree (or 1394 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1395 to remove ATAGS support from your kernel binary. 1396 1397config DEPRECATED_PARAM_STRUCT 1398 bool "Provide old way to pass kernel parameters" 1399 depends on ATAGS 1400 help 1401 This was deprecated in 2001 and announced to live on for 5 years. 1402 Some old boot loaders still use this way. 1403 1404# Compressed boot loader in ROM. Yes, we really want to ask about 1405# TEXT and BSS so we preserve their values in the config files. 1406config ZBOOT_ROM_TEXT 1407 hex "Compressed ROM boot loader base address" 1408 default 0x0 1409 help 1410 The physical address at which the ROM-able zImage is to be 1411 placed in the target. Platforms which normally make use of 1412 ROM-able zImage formats normally set this to a suitable 1413 value in their defconfig file. 1414 1415 If ZBOOT_ROM is not enabled, this has no effect. 1416 1417config ZBOOT_ROM_BSS 1418 hex "Compressed ROM boot loader BSS address" 1419 default 0x0 1420 help 1421 The base address of an area of read/write memory in the target 1422 for the ROM-able zImage which must be available while the 1423 decompressor is running. It must be large enough to hold the 1424 entire decompressed kernel plus an additional 128 KiB. 1425 Platforms which normally make use of ROM-able zImage formats 1426 normally set this to a suitable value in their defconfig file. 1427 1428 If ZBOOT_ROM is not enabled, this has no effect. 1429 1430config ZBOOT_ROM 1431 bool "Compressed boot loader in ROM/flash" 1432 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1433 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1434 help 1435 Say Y here if you intend to execute your compressed kernel image 1436 (zImage) directly from ROM or flash. If unsure, say N. 1437 1438config ARM_APPENDED_DTB 1439 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1440 depends on OF 1441 help 1442 With this option, the boot code will look for a device tree binary 1443 (DTB) appended to zImage 1444 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1445 1446 This is meant as a backward compatibility convenience for those 1447 systems with a bootloader that can't be upgraded to accommodate 1448 the documented boot protocol using a device tree. 1449 1450 Beware that there is very little in terms of protection against 1451 this option being confused by leftover garbage in memory that might 1452 look like a DTB header after a reboot if no actual DTB is appended 1453 to zImage. Do not leave this option active in a production kernel 1454 if you don't intend to always append a DTB. Proper passing of the 1455 location into r2 of a bootloader provided DTB is always preferable 1456 to this option. 1457 1458config ARM_ATAG_DTB_COMPAT 1459 bool "Supplement the appended DTB with traditional ATAG information" 1460 depends on ARM_APPENDED_DTB 1461 help 1462 Some old bootloaders can't be updated to a DTB capable one, yet 1463 they provide ATAGs with memory configuration, the ramdisk address, 1464 the kernel cmdline string, etc. Such information is dynamically 1465 provided by the bootloader and can't always be stored in a static 1466 DTB. To allow a device tree enabled kernel to be used with such 1467 bootloaders, this option allows zImage to extract the information 1468 from the ATAG list and store it at run time into the appended DTB. 1469 1470choice 1471 prompt "Kernel command line type" 1472 depends on ARM_ATAG_DTB_COMPAT 1473 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1474 1475config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1476 bool "Use bootloader kernel arguments if available" 1477 help 1478 Uses the command-line options passed by the boot loader instead of 1479 the device tree bootargs property. If the boot loader doesn't provide 1480 any, the device tree bootargs property will be used. 1481 1482config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1483 bool "Extend with bootloader kernel arguments" 1484 help 1485 The command-line arguments provided by the boot loader will be 1486 appended to the the device tree bootargs property. 1487 1488endchoice 1489 1490config CMDLINE 1491 string "Default kernel command string" 1492 default "" 1493 help 1494 On some architectures (e.g. CATS), there is currently no way 1495 for the boot loader to pass arguments to the kernel. For these 1496 architectures, you should supply some command-line options at build 1497 time by entering them here. As a minimum, you should specify the 1498 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1499 1500choice 1501 prompt "Kernel command line type" 1502 depends on CMDLINE != "" 1503 default CMDLINE_FROM_BOOTLOADER 1504 1505config CMDLINE_FROM_BOOTLOADER 1506 bool "Use bootloader kernel arguments if available" 1507 help 1508 Uses the command-line options passed by the boot loader. If 1509 the boot loader doesn't provide any, the default kernel command 1510 string provided in CMDLINE will be used. 1511 1512config CMDLINE_EXTEND 1513 bool "Extend bootloader kernel arguments" 1514 help 1515 The command-line arguments provided by the boot loader will be 1516 appended to the default kernel command string. 1517 1518config CMDLINE_FORCE 1519 bool "Always use the default kernel command string" 1520 help 1521 Always use the default kernel command string, even if the boot 1522 loader passes other arguments to the kernel. 1523 This is useful if you cannot or don't want to change the 1524 command-line options your boot loader passes to the kernel. 1525endchoice 1526 1527config XIP_KERNEL 1528 bool "Kernel Execute-In-Place from ROM" 1529 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1530 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1531 help 1532 Execute-In-Place allows the kernel to run from non-volatile storage 1533 directly addressable by the CPU, such as NOR flash. This saves RAM 1534 space since the text section of the kernel is not loaded from flash 1535 to RAM. Read-write sections, such as the data section and stack, 1536 are still copied to RAM. The XIP kernel is not compressed since 1537 it has to run directly from flash, so it will take more space to 1538 store it. The flash address used to link the kernel object files, 1539 and for storing it, is configuration dependent. Therefore, if you 1540 say Y here, you must know the proper physical address where to 1541 store the kernel image depending on your own flash memory usage. 1542 1543 Also note that the make target becomes "make xipImage" rather than 1544 "make zImage" or "make Image". The final kernel binary to put in 1545 ROM memory will be arch/arm/boot/xipImage. 1546 1547 If unsure, say N. 1548 1549config XIP_PHYS_ADDR 1550 hex "XIP Kernel Physical Location" 1551 depends on XIP_KERNEL 1552 default "0x00080000" 1553 help 1554 This is the physical address in your flash memory the kernel will 1555 be linked for and stored to. This address is dependent on your 1556 own flash usage. 1557 1558config XIP_DEFLATED_DATA 1559 bool "Store kernel .data section compressed in ROM" 1560 depends on XIP_KERNEL 1561 select ZLIB_INFLATE 1562 help 1563 Before the kernel is actually executed, its .data section has to be 1564 copied to RAM from ROM. This option allows for storing that data 1565 in compressed form and decompressed to RAM rather than merely being 1566 copied, saving some precious ROM space. A possible drawback is a 1567 slightly longer boot delay. 1568 1569config ARCH_SUPPORTS_KEXEC 1570 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1571 1572config ATAGS_PROC 1573 bool "Export atags in procfs" 1574 depends on ATAGS && KEXEC 1575 default y 1576 help 1577 Should the atags used to boot the kernel be exported in an "atags" 1578 file in procfs. Useful with kexec. 1579 1580config ARCH_SUPPORTS_CRASH_DUMP 1581 def_bool y 1582 1583config ARCH_DEFAULT_CRASH_DUMP 1584 def_bool y 1585 1586config AUTO_ZRELADDR 1587 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1588 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1589 help 1590 ZRELADDR is the physical address where the decompressed kernel 1591 image will be placed. If AUTO_ZRELADDR is selected, the address 1592 will be determined at run-time, either by masking the current IP 1593 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1594 This assumes the zImage being placed in the first 128MB from 1595 start of memory. 1596 1597config EFI_STUB 1598 bool 1599 1600config EFI 1601 bool "UEFI runtime support" 1602 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1603 select UCS2_STRING 1604 select EFI_PARAMS_FROM_FDT 1605 select EFI_STUB 1606 select EFI_GENERIC_STUB 1607 select EFI_RUNTIME_WRAPPERS 1608 help 1609 This option provides support for runtime services provided 1610 by UEFI firmware (such as non-volatile variables, realtime 1611 clock, and platform reset). A UEFI stub is also provided to 1612 allow the kernel to be booted as an EFI application. This 1613 is only useful for kernels that may run on systems that have 1614 UEFI firmware. 1615 1616config DMI 1617 bool "Enable support for SMBIOS (DMI) tables" 1618 depends on EFI 1619 default y 1620 help 1621 This enables SMBIOS/DMI feature for systems. 1622 1623 This option is only useful on systems that have UEFI firmware. 1624 However, even with this option, the resultant kernel should 1625 continue to boot on existing non-UEFI platforms. 1626 1627 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1628 i.e., the the practice of identifying the platform via DMI to 1629 decide whether certain workarounds for buggy hardware and/or 1630 firmware need to be enabled. This would require the DMI subsystem 1631 to be enabled much earlier than we do on ARM, which is non-trivial. 1632 1633endmenu 1634 1635menu "CPU Power Management" 1636 1637source "drivers/cpufreq/Kconfig" 1638 1639source "drivers/cpuidle/Kconfig" 1640 1641endmenu 1642 1643menu "Floating point emulation" 1644 1645comment "At least one emulation must be selected" 1646 1647config FPE_NWFPE 1648 bool "NWFPE math emulation" 1649 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1650 help 1651 Say Y to include the NWFPE floating point emulator in the kernel. 1652 This is necessary to run most binaries. Linux does not currently 1653 support floating point hardware so you need to say Y here even if 1654 your machine has an FPA or floating point co-processor podule. 1655 1656 You may say N here if you are going to load the Acorn FPEmulator 1657 early in the bootup. 1658 1659config FPE_NWFPE_XP 1660 bool "Support extended precision" 1661 depends on FPE_NWFPE 1662 help 1663 Say Y to include 80-bit support in the kernel floating-point 1664 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1665 Note that gcc does not generate 80-bit operations by default, 1666 so in most cases this option only enlarges the size of the 1667 floating point emulator without any good reason. 1668 1669 You almost surely want to say N here. 1670 1671config FPE_FASTFPE 1672 bool "FastFPE math emulation (EXPERIMENTAL)" 1673 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1674 help 1675 Say Y here to include the FAST floating point emulator in the kernel. 1676 This is an experimental much faster emulator which now also has full 1677 precision for the mantissa. It does not support any exceptions. 1678 It is very simple, and approximately 3-6 times faster than NWFPE. 1679 1680 It should be sufficient for most programs. It may be not suitable 1681 for scientific calculations, but you have to check this for yourself. 1682 If you do not feel you need a faster FP emulation you should better 1683 choose NWFPE. 1684 1685config VFP 1686 bool "VFP-format floating point maths" 1687 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1688 help 1689 Say Y to include VFP support code in the kernel. This is needed 1690 if your hardware includes a VFP unit. 1691 1692 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1693 release notes and additional status information. 1694 1695 Say N if your target does not have VFP hardware. 1696 1697config VFPv3 1698 bool 1699 depends on VFP 1700 default y if CPU_V7 1701 1702config NEON 1703 bool "Advanced SIMD (NEON) Extension support" 1704 depends on VFPv3 && CPU_V7 1705 help 1706 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1707 Extension. 1708 1709config KERNEL_MODE_NEON 1710 bool "Support for NEON in kernel mode" 1711 depends on NEON && AEABI 1712 help 1713 Say Y to include support for NEON in kernel mode. 1714 1715endmenu 1716 1717menu "Power management options" 1718 1719source "kernel/power/Kconfig" 1720 1721config ARCH_SUSPEND_POSSIBLE 1722 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1723 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1724 def_bool y 1725 1726config ARM_CPU_SUSPEND 1727 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1728 depends on ARCH_SUSPEND_POSSIBLE 1729 1730config ARCH_HIBERNATION_POSSIBLE 1731 bool 1732 depends on MMU 1733 default y if ARCH_SUSPEND_POSSIBLE 1734 1735endmenu 1736