1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_CPU_AUTOPROBE 53 select GENERIC_EARLY_IOREMAP 54 select GENERIC_IDLE_POLL_SETUP 55 select GENERIC_IRQ_PROBE 56 select GENERIC_IRQ_SHOW 57 select GENERIC_IRQ_SHOW_LEVEL 58 select GENERIC_PCI_IOMAP 59 select GENERIC_SCHED_CLOCK 60 select GENERIC_SMP_IDLE_THREAD 61 select GENERIC_STRNCPY_FROM_USER 62 select GENERIC_STRNLEN_USER 63 select HANDLE_DOMAIN_IRQ 64 select HARDIRQS_SW_RESEND 65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_MMAP_RND_BITS if MMU 70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 72 select HAVE_ARCH_TRACEHOOK 73 select HAVE_ARM_SMCCC if CPU_V7 74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 75 select HAVE_CONTEXT_TRACKING 76 select HAVE_C_RECORDMCOUNT 77 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 78 select HAVE_DMA_CONTIGUOUS if MMU 79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 82 select HAVE_EXIT_THREAD 83 select HAVE_FAST_GUP if ARM_LPAE 84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 87 select HAVE_GCC_PLUGINS 88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 89 select HAVE_IDE if PCI || ISA || PCMCIA 90 select HAVE_IRQ_TIME_ACCOUNTING 91 select HAVE_KERNEL_GZIP 92 select HAVE_KERNEL_LZ4 93 select HAVE_KERNEL_LZMA 94 select HAVE_KERNEL_LZO 95 select HAVE_KERNEL_XZ 96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 97 select HAVE_KRETPROBES if HAVE_KPROBES 98 select HAVE_MOD_ARCH_SPECIFIC 99 select HAVE_NMI 100 select HAVE_OPROFILE if HAVE_PERF_EVENTS 101 select HAVE_OPTPROBES if !THUMB2_KERNEL 102 select HAVE_PERF_EVENTS 103 select HAVE_PERF_REGS 104 select HAVE_PERF_USER_STACK_DUMP 105 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 106 select HAVE_REGS_AND_STACK_ACCESS_API 107 select HAVE_RSEQ 108 select HAVE_STACKPROTECTOR 109 select HAVE_SYSCALL_TRACEPOINTS 110 select HAVE_UID16 111 select HAVE_VIRT_CPU_ACCOUNTING_GEN 112 select IRQ_FORCED_THREADING 113 select MODULES_USE_ELF_REL 114 select NEED_DMA_MAP_STATE 115 select OF_EARLY_FLATTREE if OF 116 select OLD_SIGACTION 117 select OLD_SIGSUSPEND3 118 select PCI_SYSCALL if PCI 119 select PERF_USE_VMALLOC 120 select RTC_LIB 121 select SYS_SUPPORTS_APM_EMULATION 122 # Above selects are sorted alphabetically; please add new ones 123 # according to that. Thanks. 124 help 125 The ARM series is a line of low-power-consumption RISC chip designs 126 licensed by ARM Ltd and targeted at embedded applications and 127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 128 manufactured, but legacy ARM-based PC hardware remains popular in 129 Europe. There is an ARM Linux project with a web page at 130 <http://www.arm.linux.org.uk/>. 131 132config ARM_HAS_SG_CHAIN 133 bool 134 135config ARM_DMA_USE_IOMMU 136 bool 137 select ARM_HAS_SG_CHAIN 138 select NEED_SG_DMA_LENGTH 139 140if ARM_DMA_USE_IOMMU 141 142config ARM_DMA_IOMMU_ALIGNMENT 143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 144 range 4 9 145 default 8 146 help 147 DMA mapping framework by default aligns all buffers to the smallest 148 PAGE_SIZE order which is greater than or equal to the requested buffer 149 size. This works well for buffers up to a few hundreds kilobytes, but 150 for larger buffers it just a waste of address space. Drivers which has 151 relatively small addressing window (like 64Mib) might run out of 152 virtual space with just a few allocations. 153 154 With this parameter you can specify the maximum PAGE_SIZE order for 155 DMA IOMMU buffers. Larger buffers will be aligned only to this 156 specified order. The order is expressed as a power of two multiplied 157 by the PAGE_SIZE. 158 159endif 160 161config SYS_SUPPORTS_APM_EMULATION 162 bool 163 164config HAVE_TCM 165 bool 166 select GENERIC_ALLOCATOR 167 168config HAVE_PROC_CPU 169 bool 170 171config NO_IOPORT_MAP 172 bool 173 174config SBUS 175 bool 176 177config STACKTRACE_SUPPORT 178 bool 179 default y 180 181config LOCKDEP_SUPPORT 182 bool 183 default y 184 185config TRACE_IRQFLAGS_SUPPORT 186 bool 187 default !CPU_V7M 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 16MB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_EBSA110 || \ 268 ARCH_FOOTBRIDGE 269 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 270 default 0x20000000 if ARCH_S5PV210 271 default 0xc0000000 if ARCH_SA1100 272 help 273 Please provide the physical address corresponding to the 274 location of main memory in your system. 275 276config GENERIC_BUG 277 def_bool y 278 depends on BUG 279 280config PGTABLE_LEVELS 281 int 282 default 3 if ARM_LPAE 283 default 2 284 285menu "System Type" 286 287config MMU 288 bool "MMU-based Paged Memory Management Support" 289 default y 290 help 291 Select if you want MMU-based virtualised addressing space 292 support by paged memory management. If unsure, say 'Y'. 293 294config ARCH_MMAP_RND_BITS_MIN 295 default 8 296 297config ARCH_MMAP_RND_BITS_MAX 298 default 14 if PAGE_OFFSET=0x40000000 299 default 15 if PAGE_OFFSET=0x80000000 300 default 16 301 302# 303# The "ARM system type" choice list is ordered alphabetically by option 304# text. Please add new entries in the option alphabetic order. 305# 306choice 307 prompt "ARM system type" 308 default ARM_SINGLE_ARMV7M if !MMU 309 default ARCH_MULTIPLATFORM if MMU 310 311config ARCH_MULTIPLATFORM 312 bool "Allow multiple platforms to be selected" 313 depends on MMU 314 select ARCH_FLATMEM_ENABLE 315 select ARCH_SPARSEMEM_ENABLE 316 select ARCH_SELECT_MEMORY_MODEL 317 select ARM_HAS_SG_CHAIN 318 select ARM_PATCH_PHYS_VIRT 319 select AUTO_ZRELADDR 320 select TIMER_OF 321 select COMMON_CLK 322 select GENERIC_CLOCKEVENTS 323 select GENERIC_IRQ_MULTI_HANDLER 324 select HAVE_PCI 325 select PCI_DOMAINS_GENERIC if PCI 326 select SPARSE_IRQ 327 select USE_OF 328 329config ARM_SINGLE_ARMV7M 330 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 331 depends on !MMU 332 select ARM_NVIC 333 select AUTO_ZRELADDR 334 select TIMER_OF 335 select COMMON_CLK 336 select CPU_V7M 337 select GENERIC_CLOCKEVENTS 338 select NO_IOPORT_MAP 339 select SPARSE_IRQ 340 select USE_OF 341 342config ARCH_EBSA110 343 bool "EBSA-110" 344 select ARCH_USES_GETTIMEOFFSET 345 select CPU_SA110 346 select ISA 347 select NEED_MACH_IO_H 348 select NEED_MACH_MEMORY_H 349 select NO_IOPORT_MAP 350 help 351 This is an evaluation board for the StrongARM processor available 352 from Digital. It has limited hardware on-board, including an 353 Ethernet interface, two PCMCIA sockets, two serial ports and a 354 parallel port. 355 356config ARCH_EP93XX 357 bool "EP93xx-based" 358 select ARCH_SPARSEMEM_ENABLE 359 select ARM_AMBA 360 imply ARM_PATCH_PHYS_VIRT 361 select ARM_VIC 362 select AUTO_ZRELADDR 363 select CLKDEV_LOOKUP 364 select CLKSRC_MMIO 365 select CPU_ARM920T 366 select GENERIC_CLOCKEVENTS 367 select GPIOLIB 368 select HAVE_LEGACY_CLK 369 help 370 This enables support for the Cirrus EP93xx series of CPUs. 371 372config ARCH_FOOTBRIDGE 373 bool "FootBridge" 374 select CPU_SA110 375 select FOOTBRIDGE 376 select GENERIC_CLOCKEVENTS 377 select HAVE_IDE 378 select NEED_MACH_IO_H if !MMU 379 select NEED_MACH_MEMORY_H 380 help 381 Support for systems based on the DC21285 companion chip 382 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 383 384config ARCH_IOP32X 385 bool "IOP32x-based" 386 depends on MMU 387 select CPU_XSCALE 388 select GPIO_IOP 389 select GPIOLIB 390 select NEED_RET_TO_USER 391 select FORCE_PCI 392 select PLAT_IOP 393 help 394 Support for Intel's 80219 and IOP32X (XScale) family of 395 processors. 396 397config ARCH_IXP4XX 398 bool "IXP4xx-based" 399 depends on MMU 400 select ARCH_HAS_DMA_SET_COHERENT_MASK 401 select ARCH_SUPPORTS_BIG_ENDIAN 402 select CPU_XSCALE 403 select DMABOUNCE if PCI 404 select GENERIC_CLOCKEVENTS 405 select GENERIC_IRQ_MULTI_HANDLER 406 select GPIO_IXP4XX 407 select GPIOLIB 408 select HAVE_PCI 409 select IXP4XX_IRQ 410 select IXP4XX_TIMER 411 select NEED_MACH_IO_H 412 select USB_EHCI_BIG_ENDIAN_DESC 413 select USB_EHCI_BIG_ENDIAN_MMIO 414 help 415 Support for Intel's IXP4XX (XScale) family of processors. 416 417config ARCH_DOVE 418 bool "Marvell Dove" 419 select CPU_PJ4 420 select GENERIC_CLOCKEVENTS 421 select GENERIC_IRQ_MULTI_HANDLER 422 select GPIOLIB 423 select HAVE_PCI 424 select MVEBU_MBUS 425 select PINCTRL 426 select PINCTRL_DOVE 427 select PLAT_ORION_LEGACY 428 select SPARSE_IRQ 429 select PM_GENERIC_DOMAINS if PM 430 help 431 Support for the Marvell Dove SoC 88AP510 432 433config ARCH_PXA 434 bool "PXA2xx/PXA3xx-based" 435 depends on MMU 436 select ARCH_MTD_XIP 437 select ARM_CPU_SUSPEND if PM 438 select AUTO_ZRELADDR 439 select COMMON_CLK 440 select CLKSRC_PXA 441 select CLKSRC_MMIO 442 select TIMER_OF 443 select CPU_XSCALE if !CPU_XSC3 444 select GENERIC_CLOCKEVENTS 445 select GENERIC_IRQ_MULTI_HANDLER 446 select GPIO_PXA 447 select GPIOLIB 448 select HAVE_IDE 449 select IRQ_DOMAIN 450 select PLAT_PXA 451 select SPARSE_IRQ 452 help 453 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 454 455config ARCH_RPC 456 bool "RiscPC" 457 depends on MMU 458 select ARCH_ACORN 459 select ARCH_MAY_HAVE_PC_FDC 460 select ARCH_SPARSEMEM_ENABLE 461 select ARM_HAS_SG_CHAIN 462 select CPU_SA110 463 select FIQ 464 select HAVE_IDE 465 select HAVE_PATA_PLATFORM 466 select ISA_DMA_API 467 select NEED_MACH_IO_H 468 select NEED_MACH_MEMORY_H 469 select NO_IOPORT_MAP 470 help 471 On the Acorn Risc-PC, Linux can support the internal IDE disk and 472 CD-ROM interface, serial and parallel port, and the floppy drive. 473 474config ARCH_SA1100 475 bool "SA1100-based" 476 select ARCH_MTD_XIP 477 select ARCH_SPARSEMEM_ENABLE 478 select CLKSRC_MMIO 479 select CLKSRC_PXA 480 select TIMER_OF if OF 481 select COMMON_CLK 482 select CPU_FREQ 483 select CPU_SA1100 484 select GENERIC_CLOCKEVENTS 485 select GENERIC_IRQ_MULTI_HANDLER 486 select GPIOLIB 487 select HAVE_IDE 488 select IRQ_DOMAIN 489 select ISA 490 select NEED_MACH_MEMORY_H 491 select SPARSE_IRQ 492 help 493 Support for StrongARM 11x0 based boards. 494 495config ARCH_S3C24XX 496 bool "Samsung S3C24XX SoCs" 497 select ATAGS 498 select CLKSRC_SAMSUNG_PWM 499 select GENERIC_CLOCKEVENTS 500 select GPIO_SAMSUNG 501 select GPIOLIB 502 select GENERIC_IRQ_MULTI_HANDLER 503 select HAVE_S3C2410_I2C if I2C 504 select HAVE_S3C_RTC if RTC_CLASS 505 select NEED_MACH_IO_H 506 select S3C2410_WATCHDOG 507 select SAMSUNG_ATAGS 508 select USE_OF 509 select WATCHDOG 510 help 511 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 512 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 513 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 514 Samsung SMDK2410 development board (and derivatives). 515 516config ARCH_OMAP1 517 bool "TI OMAP1" 518 depends on MMU 519 select ARCH_HAS_HOLES_MEMORYMODEL 520 select ARCH_OMAP 521 select CLKDEV_LOOKUP 522 select CLKSRC_MMIO 523 select GENERIC_CLOCKEVENTS 524 select GENERIC_IRQ_CHIP 525 select GENERIC_IRQ_MULTI_HANDLER 526 select GPIOLIB 527 select HAVE_IDE 528 select HAVE_LEGACY_CLK 529 select IRQ_DOMAIN 530 select NEED_MACH_IO_H if PCCARD 531 select NEED_MACH_MEMORY_H 532 select SPARSE_IRQ 533 help 534 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 535 536endchoice 537 538menu "Multiple platform selection" 539 depends on ARCH_MULTIPLATFORM 540 541comment "CPU Core family selection" 542 543config ARCH_MULTI_V4 544 bool "ARMv4 based platforms (FA526)" 545 depends on !ARCH_MULTI_V6_V7 546 select ARCH_MULTI_V4_V5 547 select CPU_FA526 548 549config ARCH_MULTI_V4T 550 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 551 depends on !ARCH_MULTI_V6_V7 552 select ARCH_MULTI_V4_V5 553 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 554 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 555 CPU_ARM925T || CPU_ARM940T) 556 557config ARCH_MULTI_V5 558 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 559 depends on !ARCH_MULTI_V6_V7 560 select ARCH_MULTI_V4_V5 561 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 562 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 563 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 564 565config ARCH_MULTI_V4_V5 566 bool 567 568config ARCH_MULTI_V6 569 bool "ARMv6 based platforms (ARM11)" 570 select ARCH_MULTI_V6_V7 571 select CPU_V6K 572 573config ARCH_MULTI_V7 574 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 575 default y 576 select ARCH_MULTI_V6_V7 577 select CPU_V7 578 select HAVE_SMP 579 580config ARCH_MULTI_V6_V7 581 bool 582 select MIGHT_HAVE_CACHE_L2X0 583 584config ARCH_MULTI_CPU_AUTO 585 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 586 select ARCH_MULTI_V5 587 588endmenu 589 590config ARCH_VIRT 591 bool "Dummy Virtual Machine" 592 depends on ARCH_MULTI_V7 593 select ARM_AMBA 594 select ARM_GIC 595 select ARM_GIC_V2M if PCI 596 select ARM_GIC_V3 597 select ARM_GIC_V3_ITS if PCI 598 select ARM_PSCI 599 select HAVE_ARM_ARCH_TIMER 600 select ARCH_SUPPORTS_BIG_ENDIAN 601 602# 603# This is sorted alphabetically by mach-* pathname. However, plat-* 604# Kconfigs may be included either alphabetically (according to the 605# plat- suffix) or along side the corresponding mach-* source. 606# 607source "arch/arm/mach-actions/Kconfig" 608 609source "arch/arm/mach-alpine/Kconfig" 610 611source "arch/arm/mach-artpec/Kconfig" 612 613source "arch/arm/mach-asm9260/Kconfig" 614 615source "arch/arm/mach-aspeed/Kconfig" 616 617source "arch/arm/mach-at91/Kconfig" 618 619source "arch/arm/mach-axxia/Kconfig" 620 621source "arch/arm/mach-bcm/Kconfig" 622 623source "arch/arm/mach-berlin/Kconfig" 624 625source "arch/arm/mach-clps711x/Kconfig" 626 627source "arch/arm/mach-cns3xxx/Kconfig" 628 629source "arch/arm/mach-davinci/Kconfig" 630 631source "arch/arm/mach-digicolor/Kconfig" 632 633source "arch/arm/mach-dove/Kconfig" 634 635source "arch/arm/mach-ep93xx/Kconfig" 636 637source "arch/arm/mach-exynos/Kconfig" 638 639source "arch/arm/mach-footbridge/Kconfig" 640 641source "arch/arm/mach-gemini/Kconfig" 642 643source "arch/arm/mach-highbank/Kconfig" 644 645source "arch/arm/mach-hisi/Kconfig" 646 647source "arch/arm/mach-imx/Kconfig" 648 649source "arch/arm/mach-integrator/Kconfig" 650 651source "arch/arm/mach-iop32x/Kconfig" 652 653source "arch/arm/mach-ixp4xx/Kconfig" 654 655source "arch/arm/mach-keystone/Kconfig" 656 657source "arch/arm/mach-lpc32xx/Kconfig" 658 659source "arch/arm/mach-mediatek/Kconfig" 660 661source "arch/arm/mach-meson/Kconfig" 662 663source "arch/arm/mach-milbeaut/Kconfig" 664 665source "arch/arm/mach-mmp/Kconfig" 666 667source "arch/arm/mach-moxart/Kconfig" 668 669source "arch/arm/mach-mstar/Kconfig" 670 671source "arch/arm/mach-mv78xx0/Kconfig" 672 673source "arch/arm/mach-mvebu/Kconfig" 674 675source "arch/arm/mach-mxs/Kconfig" 676 677source "arch/arm/mach-nomadik/Kconfig" 678 679source "arch/arm/mach-npcm/Kconfig" 680 681source "arch/arm/mach-nspire/Kconfig" 682 683source "arch/arm/plat-omap/Kconfig" 684 685source "arch/arm/mach-omap1/Kconfig" 686 687source "arch/arm/mach-omap2/Kconfig" 688 689source "arch/arm/mach-orion5x/Kconfig" 690 691source "arch/arm/mach-oxnas/Kconfig" 692 693source "arch/arm/mach-picoxcell/Kconfig" 694 695source "arch/arm/mach-prima2/Kconfig" 696 697source "arch/arm/mach-pxa/Kconfig" 698source "arch/arm/plat-pxa/Kconfig" 699 700source "arch/arm/mach-qcom/Kconfig" 701 702source "arch/arm/mach-rda/Kconfig" 703 704source "arch/arm/mach-realtek/Kconfig" 705 706source "arch/arm/mach-realview/Kconfig" 707 708source "arch/arm/mach-rockchip/Kconfig" 709 710source "arch/arm/mach-s3c/Kconfig" 711 712source "arch/arm/mach-s5pv210/Kconfig" 713 714source "arch/arm/mach-sa1100/Kconfig" 715 716source "arch/arm/mach-shmobile/Kconfig" 717 718source "arch/arm/mach-socfpga/Kconfig" 719 720source "arch/arm/mach-spear/Kconfig" 721 722source "arch/arm/mach-sti/Kconfig" 723 724source "arch/arm/mach-stm32/Kconfig" 725 726source "arch/arm/mach-sunxi/Kconfig" 727 728source "arch/arm/mach-tango/Kconfig" 729 730source "arch/arm/mach-tegra/Kconfig" 731 732source "arch/arm/mach-u300/Kconfig" 733 734source "arch/arm/mach-uniphier/Kconfig" 735 736source "arch/arm/mach-ux500/Kconfig" 737 738source "arch/arm/mach-versatile/Kconfig" 739 740source "arch/arm/mach-vexpress/Kconfig" 741 742source "arch/arm/mach-vt8500/Kconfig" 743 744source "arch/arm/mach-zx/Kconfig" 745 746source "arch/arm/mach-zynq/Kconfig" 747 748# ARMv7-M architecture 749config ARCH_EFM32 750 bool "Energy Micro efm32" 751 depends on ARM_SINGLE_ARMV7M 752 select GPIOLIB 753 help 754 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 755 processors. 756 757config ARCH_LPC18XX 758 bool "NXP LPC18xx/LPC43xx" 759 depends on ARM_SINGLE_ARMV7M 760 select ARCH_HAS_RESET_CONTROLLER 761 select ARM_AMBA 762 select CLKSRC_LPC32XX 763 select PINCTRL 764 help 765 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 766 high performance microcontrollers. 767 768config ARCH_MPS2 769 bool "ARM MPS2 platform" 770 depends on ARM_SINGLE_ARMV7M 771 select ARM_AMBA 772 select CLKSRC_MPS2 773 help 774 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 775 with a range of available cores like Cortex-M3/M4/M7. 776 777 Please, note that depends which Application Note is used memory map 778 for the platform may vary, so adjustment of RAM base might be needed. 779 780# Definitions to make life easier 781config ARCH_ACORN 782 bool 783 784config PLAT_IOP 785 bool 786 select GENERIC_CLOCKEVENTS 787 788config PLAT_ORION 789 bool 790 select CLKSRC_MMIO 791 select COMMON_CLK 792 select GENERIC_IRQ_CHIP 793 select IRQ_DOMAIN 794 795config PLAT_ORION_LEGACY 796 bool 797 select PLAT_ORION 798 799config PLAT_PXA 800 bool 801 802config PLAT_VERSATILE 803 bool 804 805source "arch/arm/mm/Kconfig" 806 807config IWMMXT 808 bool "Enable iWMMXt support" 809 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 810 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 811 help 812 Enable support for iWMMXt context switching at run time if 813 running on a CPU that supports it. 814 815if !MMU 816source "arch/arm/Kconfig-nommu" 817endif 818 819config PJ4B_ERRATA_4742 820 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 821 depends on CPU_PJ4B && MACH_ARMADA_370 822 default y 823 help 824 When coming out of either a Wait for Interrupt (WFI) or a Wait for 825 Event (WFE) IDLE states, a specific timing sensitivity exists between 826 the retiring WFI/WFE instructions and the newly issued subsequent 827 instructions. This sensitivity can result in a CPU hang scenario. 828 Workaround: 829 The software must insert either a Data Synchronization Barrier (DSB) 830 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 831 instruction 832 833config ARM_ERRATA_326103 834 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 835 depends on CPU_V6 836 help 837 Executing a SWP instruction to read-only memory does not set bit 11 838 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 839 treat the access as a read, preventing a COW from occurring and 840 causing the faulting task to livelock. 841 842config ARM_ERRATA_411920 843 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 844 depends on CPU_V6 || CPU_V6K 845 help 846 Invalidation of the Instruction Cache operation can 847 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 848 It does not affect the MPCore. This option enables the ARM Ltd. 849 recommended workaround. 850 851config ARM_ERRATA_430973 852 bool "ARM errata: Stale prediction on replaced interworking branch" 853 depends on CPU_V7 854 help 855 This option enables the workaround for the 430973 Cortex-A8 856 r1p* erratum. If a code sequence containing an ARM/Thumb 857 interworking branch is replaced with another code sequence at the 858 same virtual address, whether due to self-modifying code or virtual 859 to physical address re-mapping, Cortex-A8 does not recover from the 860 stale interworking branch prediction. This results in Cortex-A8 861 executing the new code sequence in the incorrect ARM or Thumb state. 862 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 863 and also flushes the branch target cache at every context switch. 864 Note that setting specific bits in the ACTLR register may not be 865 available in non-secure mode. 866 867config ARM_ERRATA_458693 868 bool "ARM errata: Processor deadlock when a false hazard is created" 869 depends on CPU_V7 870 depends on !ARCH_MULTIPLATFORM 871 help 872 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 873 erratum. For very specific sequences of memory operations, it is 874 possible for a hazard condition intended for a cache line to instead 875 be incorrectly associated with a different cache line. This false 876 hazard might then cause a processor deadlock. The workaround enables 877 the L1 caching of the NEON accesses and disables the PLD instruction 878 in the ACTLR register. Note that setting specific bits in the ACTLR 879 register may not be available in non-secure mode. 880 881config ARM_ERRATA_460075 882 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 883 depends on CPU_V7 884 depends on !ARCH_MULTIPLATFORM 885 help 886 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 887 erratum. Any asynchronous access to the L2 cache may encounter a 888 situation in which recent store transactions to the L2 cache are lost 889 and overwritten with stale memory contents from external memory. The 890 workaround disables the write-allocate mode for the L2 cache via the 891 ACTLR register. Note that setting specific bits in the ACTLR register 892 may not be available in non-secure mode. 893 894config ARM_ERRATA_742230 895 bool "ARM errata: DMB operation may be faulty" 896 depends on CPU_V7 && SMP 897 depends on !ARCH_MULTIPLATFORM 898 help 899 This option enables the workaround for the 742230 Cortex-A9 900 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 901 between two write operations may not ensure the correct visibility 902 ordering of the two writes. This workaround sets a specific bit in 903 the diagnostic register of the Cortex-A9 which causes the DMB 904 instruction to behave as a DSB, ensuring the correct behaviour of 905 the two writes. 906 907config ARM_ERRATA_742231 908 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 909 depends on CPU_V7 && SMP 910 depends on !ARCH_MULTIPLATFORM 911 help 912 This option enables the workaround for the 742231 Cortex-A9 913 (r2p0..r2p2) erratum. Under certain conditions, specific to the 914 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 915 accessing some data located in the same cache line, may get corrupted 916 data due to bad handling of the address hazard when the line gets 917 replaced from one of the CPUs at the same time as another CPU is 918 accessing it. This workaround sets specific bits in the diagnostic 919 register of the Cortex-A9 which reduces the linefill issuing 920 capabilities of the processor. 921 922config ARM_ERRATA_643719 923 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 924 depends on CPU_V7 && SMP 925 default y 926 help 927 This option enables the workaround for the 643719 Cortex-A9 (prior to 928 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 929 register returns zero when it should return one. The workaround 930 corrects this value, ensuring cache maintenance operations which use 931 it behave as intended and avoiding data corruption. 932 933config ARM_ERRATA_720789 934 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 935 depends on CPU_V7 936 help 937 This option enables the workaround for the 720789 Cortex-A9 (prior to 938 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 939 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 940 As a consequence of this erratum, some TLB entries which should be 941 invalidated are not, resulting in an incoherency in the system page 942 tables. The workaround changes the TLB flushing routines to invalidate 943 entries regardless of the ASID. 944 945config ARM_ERRATA_743622 946 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 947 depends on CPU_V7 948 depends on !ARCH_MULTIPLATFORM 949 help 950 This option enables the workaround for the 743622 Cortex-A9 951 (r2p*) erratum. Under very rare conditions, a faulty 952 optimisation in the Cortex-A9 Store Buffer may lead to data 953 corruption. This workaround sets a specific bit in the diagnostic 954 register of the Cortex-A9 which disables the Store Buffer 955 optimisation, preventing the defect from occurring. This has no 956 visible impact on the overall performance or power consumption of the 957 processor. 958 959config ARM_ERRATA_751472 960 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 961 depends on CPU_V7 962 depends on !ARCH_MULTIPLATFORM 963 help 964 This option enables the workaround for the 751472 Cortex-A9 (prior 965 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 966 completion of a following broadcasted operation if the second 967 operation is received by a CPU before the ICIALLUIS has completed, 968 potentially leading to corrupted entries in the cache or TLB. 969 970config ARM_ERRATA_754322 971 bool "ARM errata: possible faulty MMU translations following an ASID switch" 972 depends on CPU_V7 973 help 974 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 975 r3p*) erratum. A speculative memory access may cause a page table walk 976 which starts prior to an ASID switch but completes afterwards. This 977 can populate the micro-TLB with a stale entry which may be hit with 978 the new ASID. This workaround places two dsb instructions in the mm 979 switching code so that no page table walks can cross the ASID switch. 980 981config ARM_ERRATA_754327 982 bool "ARM errata: no automatic Store Buffer drain" 983 depends on CPU_V7 && SMP 984 help 985 This option enables the workaround for the 754327 Cortex-A9 (prior to 986 r2p0) erratum. The Store Buffer does not have any automatic draining 987 mechanism and therefore a livelock may occur if an external agent 988 continuously polls a memory location waiting to observe an update. 989 This workaround defines cpu_relax() as smp_mb(), preventing correctly 990 written polling loops from denying visibility of updates to memory. 991 992config ARM_ERRATA_364296 993 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 994 depends on CPU_V6 995 help 996 This options enables the workaround for the 364296 ARM1136 997 r0p2 erratum (possible cache data corruption with 998 hit-under-miss enabled). It sets the undocumented bit 31 in 999 the auxiliary control register and the FI bit in the control 1000 register, thus disabling hit-under-miss without putting the 1001 processor into full low interrupt latency mode. ARM11MPCore 1002 is not affected. 1003 1004config ARM_ERRATA_764369 1005 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1006 depends on CPU_V7 && SMP 1007 help 1008 This option enables the workaround for erratum 764369 1009 affecting Cortex-A9 MPCore with two or more processors (all 1010 current revisions). Under certain timing circumstances, a data 1011 cache line maintenance operation by MVA targeting an Inner 1012 Shareable memory region may fail to proceed up to either the 1013 Point of Coherency or to the Point of Unification of the 1014 system. This workaround adds a DSB instruction before the 1015 relevant cache maintenance functions and sets a specific bit 1016 in the diagnostic control register of the SCU. 1017 1018config ARM_ERRATA_775420 1019 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1020 depends on CPU_V7 1021 help 1022 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1023 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1024 operation aborts with MMU exception, it might cause the processor 1025 to deadlock. This workaround puts DSB before executing ISB if 1026 an abort may occur on cache maintenance. 1027 1028config ARM_ERRATA_798181 1029 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1030 depends on CPU_V7 && SMP 1031 help 1032 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1033 adequately shooting down all use of the old entries. This 1034 option enables the Linux kernel workaround for this erratum 1035 which sends an IPI to the CPUs that are running the same ASID 1036 as the one being invalidated. 1037 1038config ARM_ERRATA_773022 1039 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1040 depends on CPU_V7 1041 help 1042 This option enables the workaround for the 773022 Cortex-A15 1043 (up to r0p4) erratum. In certain rare sequences of code, the 1044 loop buffer may deliver incorrect instructions. This 1045 workaround disables the loop buffer to avoid the erratum. 1046 1047config ARM_ERRATA_818325_852422 1048 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1049 depends on CPU_V7 1050 help 1051 This option enables the workaround for: 1052 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1053 instruction might deadlock. Fixed in r0p1. 1054 - Cortex-A12 852422: Execution of a sequence of instructions might 1055 lead to either a data corruption or a CPU deadlock. Not fixed in 1056 any Cortex-A12 cores yet. 1057 This workaround for all both errata involves setting bit[12] of the 1058 Feature Register. This bit disables an optimisation applied to a 1059 sequence of 2 instructions that use opposing condition codes. 1060 1061config ARM_ERRATA_821420 1062 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1063 depends on CPU_V7 1064 help 1065 This option enables the workaround for the 821420 Cortex-A12 1066 (all revs) erratum. In very rare timing conditions, a sequence 1067 of VMOV to Core registers instructions, for which the second 1068 one is in the shadow of a branch or abort, can lead to a 1069 deadlock when the VMOV instructions are issued out-of-order. 1070 1071config ARM_ERRATA_825619 1072 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1073 depends on CPU_V7 1074 help 1075 This option enables the workaround for the 825619 Cortex-A12 1076 (all revs) erratum. Within rare timing constraints, executing a 1077 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1078 and Device/Strongly-Ordered loads and stores might cause deadlock 1079 1080config ARM_ERRATA_857271 1081 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1082 depends on CPU_V7 1083 help 1084 This option enables the workaround for the 857271 Cortex-A12 1085 (all revs) erratum. Under very rare timing conditions, the CPU might 1086 hang. The workaround is expected to have a < 1% performance impact. 1087 1088config ARM_ERRATA_852421 1089 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1090 depends on CPU_V7 1091 help 1092 This option enables the workaround for the 852421 Cortex-A17 1093 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1094 execution of a DMB ST instruction might fail to properly order 1095 stores from GroupA and stores from GroupB. 1096 1097config ARM_ERRATA_852423 1098 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1099 depends on CPU_V7 1100 help 1101 This option enables the workaround for: 1102 - Cortex-A17 852423: Execution of a sequence of instructions might 1103 lead to either a data corruption or a CPU deadlock. Not fixed in 1104 any Cortex-A17 cores yet. 1105 This is identical to Cortex-A12 erratum 852422. It is a separate 1106 config option from the A12 erratum due to the way errata are checked 1107 for and handled. 1108 1109config ARM_ERRATA_857272 1110 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1111 depends on CPU_V7 1112 help 1113 This option enables the workaround for the 857272 Cortex-A17 erratum. 1114 This erratum is not known to be fixed in any A17 revision. 1115 This is identical to Cortex-A12 erratum 857271. It is a separate 1116 config option from the A12 erratum due to the way errata are checked 1117 for and handled. 1118 1119endmenu 1120 1121source "arch/arm/common/Kconfig" 1122 1123menu "Bus support" 1124 1125config ISA 1126 bool 1127 help 1128 Find out whether you have ISA slots on your motherboard. ISA is the 1129 name of a bus system, i.e. the way the CPU talks to the other stuff 1130 inside your box. Other bus systems are PCI, EISA, MicroChannel 1131 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1132 newer boards don't support it. If you have ISA, say Y, otherwise N. 1133 1134# Select ISA DMA controller support 1135config ISA_DMA 1136 bool 1137 select ISA_DMA_API 1138 1139# Select ISA DMA interface 1140config ISA_DMA_API 1141 bool 1142 1143config PCI_NANOENGINE 1144 bool "BSE nanoEngine PCI support" 1145 depends on SA1100_NANOENGINE 1146 help 1147 Enable PCI on the BSE nanoEngine board. 1148 1149config ARM_ERRATA_814220 1150 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1151 depends on CPU_V7 1152 help 1153 The v7 ARM states that all cache and branch predictor maintenance 1154 operations that do not specify an address execute, relative to 1155 each other, in program order. 1156 However, because of this erratum, an L2 set/way cache maintenance 1157 operation can overtake an L1 set/way cache maintenance operation. 1158 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1159 r0p4, r0p5. 1160 1161endmenu 1162 1163menu "Kernel Features" 1164 1165config HAVE_SMP 1166 bool 1167 help 1168 This option should be selected by machines which have an SMP- 1169 capable CPU. 1170 1171 The only effect of this option is to make the SMP-related 1172 options available to the user for configuration. 1173 1174config SMP 1175 bool "Symmetric Multi-Processing" 1176 depends on CPU_V6K || CPU_V7 1177 depends on GENERIC_CLOCKEVENTS 1178 depends on HAVE_SMP 1179 depends on MMU || ARM_MPU 1180 select IRQ_WORK 1181 help 1182 This enables support for systems with more than one CPU. If you have 1183 a system with only one CPU, say N. If you have a system with more 1184 than one CPU, say Y. 1185 1186 If you say N here, the kernel will run on uni- and multiprocessor 1187 machines, but will use only one CPU of a multiprocessor machine. If 1188 you say Y here, the kernel will run on many, but not all, 1189 uniprocessor machines. On a uniprocessor machine, the kernel 1190 will run faster if you say N here. 1191 1192 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1193 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1194 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1195 1196 If you don't know what to do here, say N. 1197 1198config SMP_ON_UP 1199 bool "Allow booting SMP kernel on uniprocessor systems" 1200 depends on SMP && !XIP_KERNEL && MMU 1201 default y 1202 help 1203 SMP kernels contain instructions which fail on non-SMP processors. 1204 Enabling this option allows the kernel to modify itself to make 1205 these instructions safe. Disabling it allows about 1K of space 1206 savings. 1207 1208 If you don't know what to do here, say Y. 1209 1210config ARM_CPU_TOPOLOGY 1211 bool "Support cpu topology definition" 1212 depends on SMP && CPU_V7 1213 default y 1214 help 1215 Support ARM cpu topology definition. The MPIDR register defines 1216 affinity between processors which is then used to describe the cpu 1217 topology of an ARM System. 1218 1219config SCHED_MC 1220 bool "Multi-core scheduler support" 1221 depends on ARM_CPU_TOPOLOGY 1222 help 1223 Multi-core scheduler support improves the CPU scheduler's decision 1224 making when dealing with multi-core CPU chips at a cost of slightly 1225 increased overhead in some places. If unsure say N here. 1226 1227config SCHED_SMT 1228 bool "SMT scheduler support" 1229 depends on ARM_CPU_TOPOLOGY 1230 help 1231 Improves the CPU scheduler's decision making when dealing with 1232 MultiThreading at a cost of slightly increased overhead in some 1233 places. If unsure say N here. 1234 1235config HAVE_ARM_SCU 1236 bool 1237 help 1238 This option enables support for the ARM snoop control unit 1239 1240config HAVE_ARM_ARCH_TIMER 1241 bool "Architected timer support" 1242 depends on CPU_V7 1243 select ARM_ARCH_TIMER 1244 help 1245 This option enables support for the ARM architected timer 1246 1247config HAVE_ARM_TWD 1248 bool 1249 help 1250 This options enables support for the ARM timer and watchdog unit 1251 1252config MCPM 1253 bool "Multi-Cluster Power Management" 1254 depends on CPU_V7 && SMP 1255 help 1256 This option provides the common power management infrastructure 1257 for (multi-)cluster based systems, such as big.LITTLE based 1258 systems. 1259 1260config MCPM_QUAD_CLUSTER 1261 bool 1262 depends on MCPM 1263 help 1264 To avoid wasting resources unnecessarily, MCPM only supports up 1265 to 2 clusters by default. 1266 Platforms with 3 or 4 clusters that use MCPM must select this 1267 option to allow the additional clusters to be managed. 1268 1269config BIG_LITTLE 1270 bool "big.LITTLE support (Experimental)" 1271 depends on CPU_V7 && SMP 1272 select MCPM 1273 help 1274 This option enables support selections for the big.LITTLE 1275 system architecture. 1276 1277config BL_SWITCHER 1278 bool "big.LITTLE switcher support" 1279 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1280 select CPU_PM 1281 help 1282 The big.LITTLE "switcher" provides the core functionality to 1283 transparently handle transition between a cluster of A15's 1284 and a cluster of A7's in a big.LITTLE system. 1285 1286config BL_SWITCHER_DUMMY_IF 1287 tristate "Simple big.LITTLE switcher user interface" 1288 depends on BL_SWITCHER && DEBUG_KERNEL 1289 help 1290 This is a simple and dummy char dev interface to control 1291 the big.LITTLE switcher core code. It is meant for 1292 debugging purposes only. 1293 1294choice 1295 prompt "Memory split" 1296 depends on MMU 1297 default VMSPLIT_3G 1298 help 1299 Select the desired split between kernel and user memory. 1300 1301 If you are not absolutely sure what you are doing, leave this 1302 option alone! 1303 1304 config VMSPLIT_3G 1305 bool "3G/1G user/kernel split" 1306 config VMSPLIT_3G_OPT 1307 depends on !ARM_LPAE 1308 bool "3G/1G user/kernel split (for full 1G low memory)" 1309 config VMSPLIT_2G 1310 bool "2G/2G user/kernel split" 1311 config VMSPLIT_1G 1312 bool "1G/3G user/kernel split" 1313endchoice 1314 1315config PAGE_OFFSET 1316 hex 1317 default PHYS_OFFSET if !MMU 1318 default 0x40000000 if VMSPLIT_1G 1319 default 0x80000000 if VMSPLIT_2G 1320 default 0xB0000000 if VMSPLIT_3G_OPT 1321 default 0xC0000000 1322 1323config NR_CPUS 1324 int "Maximum number of CPUs (2-32)" 1325 range 2 32 1326 depends on SMP 1327 default "4" 1328 1329config HOTPLUG_CPU 1330 bool "Support for hot-pluggable CPUs" 1331 depends on SMP 1332 select GENERIC_IRQ_MIGRATION 1333 help 1334 Say Y here to experiment with turning CPUs off and on. CPUs 1335 can be controlled through /sys/devices/system/cpu. 1336 1337config ARM_PSCI 1338 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1339 depends on HAVE_ARM_SMCCC 1340 select ARM_PSCI_FW 1341 help 1342 Say Y here if you want Linux to communicate with system firmware 1343 implementing the PSCI specification for CPU-centric power 1344 management operations described in ARM document number ARM DEN 1345 0022A ("Power State Coordination Interface System Software on 1346 ARM processors"). 1347 1348# The GPIO number here must be sorted by descending number. In case of 1349# a multiplatform kernel, we just want the highest value required by the 1350# selected platforms. 1351config ARCH_NR_GPIO 1352 int 1353 default 2048 if ARCH_SOCFPGA 1354 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1355 ARCH_ZYNQ || ARCH_ASPEED 1356 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1357 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1358 default 416 if ARCH_SUNXI 1359 default 392 if ARCH_U8500 1360 default 352 if ARCH_VT8500 1361 default 288 if ARCH_ROCKCHIP 1362 default 264 if MACH_H4700 1363 default 0 1364 help 1365 Maximum number of GPIOs in the system. 1366 1367 If unsure, leave the default value. 1368 1369config HZ_FIXED 1370 int 1371 default 200 if ARCH_EBSA110 1372 default 128 if SOC_AT91RM9200 1373 default 0 1374 1375choice 1376 depends on HZ_FIXED = 0 1377 prompt "Timer frequency" 1378 1379config HZ_100 1380 bool "100 Hz" 1381 1382config HZ_200 1383 bool "200 Hz" 1384 1385config HZ_250 1386 bool "250 Hz" 1387 1388config HZ_300 1389 bool "300 Hz" 1390 1391config HZ_500 1392 bool "500 Hz" 1393 1394config HZ_1000 1395 bool "1000 Hz" 1396 1397endchoice 1398 1399config HZ 1400 int 1401 default HZ_FIXED if HZ_FIXED != 0 1402 default 100 if HZ_100 1403 default 200 if HZ_200 1404 default 250 if HZ_250 1405 default 300 if HZ_300 1406 default 500 if HZ_500 1407 default 1000 1408 1409config SCHED_HRTICK 1410 def_bool HIGH_RES_TIMERS 1411 1412config THUMB2_KERNEL 1413 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1414 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1415 default y if CPU_THUMBONLY 1416 select ARM_UNWIND 1417 help 1418 By enabling this option, the kernel will be compiled in 1419 Thumb-2 mode. 1420 1421 If unsure, say N. 1422 1423config ARM_PATCH_IDIV 1424 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1425 depends on CPU_32v7 && !XIP_KERNEL 1426 default y 1427 help 1428 The ARM compiler inserts calls to __aeabi_idiv() and 1429 __aeabi_uidiv() when it needs to perform division on signed 1430 and unsigned integers. Some v7 CPUs have support for the sdiv 1431 and udiv instructions that can be used to implement those 1432 functions. 1433 1434 Enabling this option allows the kernel to modify itself to 1435 replace the first two instructions of these library functions 1436 with the sdiv or udiv plus "bx lr" instructions when the CPU 1437 it is running on supports them. Typically this will be faster 1438 and less power intensive than running the original library 1439 code to do integer division. 1440 1441config AEABI 1442 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1443 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1444 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1445 help 1446 This option allows for the kernel to be compiled using the latest 1447 ARM ABI (aka EABI). This is only useful if you are using a user 1448 space environment that is also compiled with EABI. 1449 1450 Since there are major incompatibilities between the legacy ABI and 1451 EABI, especially with regard to structure member alignment, this 1452 option also changes the kernel syscall calling convention to 1453 disambiguate both ABIs and allow for backward compatibility support 1454 (selected with CONFIG_OABI_COMPAT). 1455 1456 To use this you need GCC version 4.0.0 or later. 1457 1458config OABI_COMPAT 1459 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1460 depends on AEABI && !THUMB2_KERNEL 1461 help 1462 This option preserves the old syscall interface along with the 1463 new (ARM EABI) one. It also provides a compatibility layer to 1464 intercept syscalls that have structure arguments which layout 1465 in memory differs between the legacy ABI and the new ARM EABI 1466 (only for non "thumb" binaries). This option adds a tiny 1467 overhead to all syscalls and produces a slightly larger kernel. 1468 1469 The seccomp filter system will not be available when this is 1470 selected, since there is no way yet to sensibly distinguish 1471 between calling conventions during filtering. 1472 1473 If you know you'll be using only pure EABI user space then you 1474 can say N here. If this option is not selected and you attempt 1475 to execute a legacy ABI binary then the result will be 1476 UNPREDICTABLE (in fact it can be predicted that it won't work 1477 at all). If in doubt say N. 1478 1479config ARCH_HAS_HOLES_MEMORYMODEL 1480 bool 1481 1482config ARCH_SELECT_MEMORY_MODEL 1483 bool 1484 1485config ARCH_FLATMEM_ENABLE 1486 bool 1487 1488config ARCH_SPARSEMEM_ENABLE 1489 bool 1490 select SPARSEMEM_STATIC if SPARSEMEM 1491 1492config HAVE_ARCH_PFN_VALID 1493 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1494 1495config HIGHMEM 1496 bool "High Memory Support" 1497 depends on MMU 1498 help 1499 The address space of ARM processors is only 4 Gigabytes large 1500 and it has to accommodate user address space, kernel address 1501 space as well as some memory mapped IO. That means that, if you 1502 have a large amount of physical memory and/or IO, not all of the 1503 memory can be "permanently mapped" by the kernel. The physical 1504 memory that is not permanently mapped is called "high memory". 1505 1506 Depending on the selected kernel/user memory split, minimum 1507 vmalloc space and actual amount of RAM, you may not need this 1508 option which should result in a slightly faster kernel. 1509 1510 If unsure, say n. 1511 1512config HIGHPTE 1513 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1514 depends on HIGHMEM 1515 default y 1516 help 1517 The VM uses one page of physical memory for each page table. 1518 For systems with a lot of processes, this can use a lot of 1519 precious low memory, eventually leading to low memory being 1520 consumed by page tables. Setting this option will allow 1521 user-space 2nd level page tables to reside in high memory. 1522 1523config CPU_SW_DOMAIN_PAN 1524 bool "Enable use of CPU domains to implement privileged no-access" 1525 depends on MMU && !ARM_LPAE 1526 default y 1527 help 1528 Increase kernel security by ensuring that normal kernel accesses 1529 are unable to access userspace addresses. This can help prevent 1530 use-after-free bugs becoming an exploitable privilege escalation 1531 by ensuring that magic values (such as LIST_POISON) will always 1532 fault when dereferenced. 1533 1534 CPUs with low-vector mappings use a best-efforts implementation. 1535 Their lower 1MB needs to remain accessible for the vectors, but 1536 the remainder of userspace will become appropriately inaccessible. 1537 1538config HW_PERF_EVENTS 1539 def_bool y 1540 depends on ARM_PMU 1541 1542config SYS_SUPPORTS_HUGETLBFS 1543 def_bool y 1544 depends on ARM_LPAE 1545 1546config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1547 def_bool y 1548 depends on ARM_LPAE 1549 1550config ARCH_WANT_GENERAL_HUGETLB 1551 def_bool y 1552 1553config ARM_MODULE_PLTS 1554 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1555 depends on MODULES 1556 default y 1557 help 1558 Allocate PLTs when loading modules so that jumps and calls whose 1559 targets are too far away for their relative offsets to be encoded 1560 in the instructions themselves can be bounced via veneers in the 1561 module's PLT. This allows modules to be allocated in the generic 1562 vmalloc area after the dedicated module memory area has been 1563 exhausted. The modules will use slightly more memory, but after 1564 rounding up to page size, the actual memory footprint is usually 1565 the same. 1566 1567 Disabling this is usually safe for small single-platform 1568 configurations. If unsure, say y. 1569 1570config FORCE_MAX_ZONEORDER 1571 int "Maximum zone order" 1572 default "12" if SOC_AM33XX 1573 default "9" if SA1111 || ARCH_EFM32 1574 default "11" 1575 help 1576 The kernel memory allocator divides physically contiguous memory 1577 blocks into "zones", where each zone is a power of two number of 1578 pages. This option selects the largest power of two that the kernel 1579 keeps in the memory allocator. If you need to allocate very large 1580 blocks of physically contiguous memory, then you may need to 1581 increase this value. 1582 1583 This config option is actually maximum order plus one. For example, 1584 a value of 11 means that the largest free memory block is 2^10 pages. 1585 1586config ALIGNMENT_TRAP 1587 bool 1588 depends on CPU_CP15_MMU 1589 default y if !ARCH_EBSA110 1590 select HAVE_PROC_CPU if PROC_FS 1591 help 1592 ARM processors cannot fetch/store information which is not 1593 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1594 address divisible by 4. On 32-bit ARM processors, these non-aligned 1595 fetch/store instructions will be emulated in software if you say 1596 here, which has a severe performance impact. This is necessary for 1597 correct operation of some network protocols. With an IP-only 1598 configuration it is safe to say N, otherwise say Y. 1599 1600config UACCESS_WITH_MEMCPY 1601 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1602 depends on MMU 1603 default y if CPU_FEROCEON 1604 help 1605 Implement faster copy_to_user and clear_user methods for CPU 1606 cores where a 8-word STM instruction give significantly higher 1607 memory write throughput than a sequence of individual 32bit stores. 1608 1609 A possible side effect is a slight increase in scheduling latency 1610 between threads sharing the same address space if they invoke 1611 such copy operations with large buffers. 1612 1613 However, if the CPU data cache is using a write-allocate mode, 1614 this option is unlikely to provide any performance gain. 1615 1616config SECCOMP 1617 bool 1618 prompt "Enable seccomp to safely compute untrusted bytecode" 1619 help 1620 This kernel feature is useful for number crunching applications 1621 that may need to compute untrusted bytecode during their 1622 execution. By using pipes or other transports made available to 1623 the process as file descriptors supporting the read/write 1624 syscalls, it's possible to isolate those applications in 1625 their own address space using seccomp. Once seccomp is 1626 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1627 and the task is only allowed to execute a few safe syscalls 1628 defined by each seccomp mode. 1629 1630config PARAVIRT 1631 bool "Enable paravirtualization code" 1632 help 1633 This changes the kernel so it can modify itself when it is run 1634 under a hypervisor, potentially improving performance significantly 1635 over full virtualization. 1636 1637config PARAVIRT_TIME_ACCOUNTING 1638 bool "Paravirtual steal time accounting" 1639 select PARAVIRT 1640 help 1641 Select this option to enable fine granularity task steal time 1642 accounting. Time spent executing other tasks in parallel with 1643 the current vCPU is discounted from the vCPU power. To account for 1644 that, there can be a small performance impact. 1645 1646 If in doubt, say N here. 1647 1648config XEN_DOM0 1649 def_bool y 1650 depends on XEN 1651 1652config XEN 1653 bool "Xen guest support on ARM" 1654 depends on ARM && AEABI && OF 1655 depends on CPU_V7 && !CPU_V6 1656 depends on !GENERIC_ATOMIC64 1657 depends on MMU 1658 select ARCH_DMA_ADDR_T_64BIT 1659 select ARM_PSCI 1660 select SWIOTLB 1661 select SWIOTLB_XEN 1662 select PARAVIRT 1663 help 1664 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1665 1666config STACKPROTECTOR_PER_TASK 1667 bool "Use a unique stack canary value for each task" 1668 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1669 select GCC_PLUGIN_ARM_SSP_PER_TASK 1670 default y 1671 help 1672 Due to the fact that GCC uses an ordinary symbol reference from 1673 which to load the value of the stack canary, this value can only 1674 change at reboot time on SMP systems, and all tasks running in the 1675 kernel's address space are forced to use the same canary value for 1676 the entire duration that the system is up. 1677 1678 Enable this option to switch to a different method that uses a 1679 different canary value for each task. 1680 1681endmenu 1682 1683menu "Boot options" 1684 1685config USE_OF 1686 bool "Flattened Device Tree support" 1687 select IRQ_DOMAIN 1688 select OF 1689 help 1690 Include support for flattened device tree machine descriptions. 1691 1692config ATAGS 1693 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1694 default y 1695 help 1696 This is the traditional way of passing data to the kernel at boot 1697 time. If you are solely relying on the flattened device tree (or 1698 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1699 to remove ATAGS support from your kernel binary. If unsure, 1700 leave this to y. 1701 1702config DEPRECATED_PARAM_STRUCT 1703 bool "Provide old way to pass kernel parameters" 1704 depends on ATAGS 1705 help 1706 This was deprecated in 2001 and announced to live on for 5 years. 1707 Some old boot loaders still use this way. 1708 1709# Compressed boot loader in ROM. Yes, we really want to ask about 1710# TEXT and BSS so we preserve their values in the config files. 1711config ZBOOT_ROM_TEXT 1712 hex "Compressed ROM boot loader base address" 1713 default 0x0 1714 help 1715 The physical address at which the ROM-able zImage is to be 1716 placed in the target. Platforms which normally make use of 1717 ROM-able zImage formats normally set this to a suitable 1718 value in their defconfig file. 1719 1720 If ZBOOT_ROM is not enabled, this has no effect. 1721 1722config ZBOOT_ROM_BSS 1723 hex "Compressed ROM boot loader BSS address" 1724 default 0x0 1725 help 1726 The base address of an area of read/write memory in the target 1727 for the ROM-able zImage which must be available while the 1728 decompressor is running. It must be large enough to hold the 1729 entire decompressed kernel plus an additional 128 KiB. 1730 Platforms which normally make use of ROM-able zImage formats 1731 normally set this to a suitable value in their defconfig file. 1732 1733 If ZBOOT_ROM is not enabled, this has no effect. 1734 1735config ZBOOT_ROM 1736 bool "Compressed boot loader in ROM/flash" 1737 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1738 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1739 help 1740 Say Y here if you intend to execute your compressed kernel image 1741 (zImage) directly from ROM or flash. If unsure, say N. 1742 1743config ARM_APPENDED_DTB 1744 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1745 depends on OF 1746 help 1747 With this option, the boot code will look for a device tree binary 1748 (DTB) appended to zImage 1749 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1750 1751 This is meant as a backward compatibility convenience for those 1752 systems with a bootloader that can't be upgraded to accommodate 1753 the documented boot protocol using a device tree. 1754 1755 Beware that there is very little in terms of protection against 1756 this option being confused by leftover garbage in memory that might 1757 look like a DTB header after a reboot if no actual DTB is appended 1758 to zImage. Do not leave this option active in a production kernel 1759 if you don't intend to always append a DTB. Proper passing of the 1760 location into r2 of a bootloader provided DTB is always preferable 1761 to this option. 1762 1763config ARM_ATAG_DTB_COMPAT 1764 bool "Supplement the appended DTB with traditional ATAG information" 1765 depends on ARM_APPENDED_DTB 1766 help 1767 Some old bootloaders can't be updated to a DTB capable one, yet 1768 they provide ATAGs with memory configuration, the ramdisk address, 1769 the kernel cmdline string, etc. Such information is dynamically 1770 provided by the bootloader and can't always be stored in a static 1771 DTB. To allow a device tree enabled kernel to be used with such 1772 bootloaders, this option allows zImage to extract the information 1773 from the ATAG list and store it at run time into the appended DTB. 1774 1775choice 1776 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1777 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1778 1779config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1780 bool "Use bootloader kernel arguments if available" 1781 help 1782 Uses the command-line options passed by the boot loader instead of 1783 the device tree bootargs property. If the boot loader doesn't provide 1784 any, the device tree bootargs property will be used. 1785 1786config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1787 bool "Extend with bootloader kernel arguments" 1788 help 1789 The command-line arguments provided by the boot loader will be 1790 appended to the the device tree bootargs property. 1791 1792endchoice 1793 1794config CMDLINE 1795 string "Default kernel command string" 1796 default "" 1797 help 1798 On some architectures (EBSA110 and CATS), there is currently no way 1799 for the boot loader to pass arguments to the kernel. For these 1800 architectures, you should supply some command-line options at build 1801 time by entering them here. As a minimum, you should specify the 1802 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1803 1804choice 1805 prompt "Kernel command line type" if CMDLINE != "" 1806 default CMDLINE_FROM_BOOTLOADER 1807 depends on ATAGS 1808 1809config CMDLINE_FROM_BOOTLOADER 1810 bool "Use bootloader kernel arguments if available" 1811 help 1812 Uses the command-line options passed by the boot loader. If 1813 the boot loader doesn't provide any, the default kernel command 1814 string provided in CMDLINE will be used. 1815 1816config CMDLINE_EXTEND 1817 bool "Extend bootloader kernel arguments" 1818 help 1819 The command-line arguments provided by the boot loader will be 1820 appended to the default kernel command string. 1821 1822config CMDLINE_FORCE 1823 bool "Always use the default kernel command string" 1824 help 1825 Always use the default kernel command string, even if the boot 1826 loader passes other arguments to the kernel. 1827 This is useful if you cannot or don't want to change the 1828 command-line options your boot loader passes to the kernel. 1829endchoice 1830 1831config XIP_KERNEL 1832 bool "Kernel Execute-In-Place from ROM" 1833 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1834 help 1835 Execute-In-Place allows the kernel to run from non-volatile storage 1836 directly addressable by the CPU, such as NOR flash. This saves RAM 1837 space since the text section of the kernel is not loaded from flash 1838 to RAM. Read-write sections, such as the data section and stack, 1839 are still copied to RAM. The XIP kernel is not compressed since 1840 it has to run directly from flash, so it will take more space to 1841 store it. The flash address used to link the kernel object files, 1842 and for storing it, is configuration dependent. Therefore, if you 1843 say Y here, you must know the proper physical address where to 1844 store the kernel image depending on your own flash memory usage. 1845 1846 Also note that the make target becomes "make xipImage" rather than 1847 "make zImage" or "make Image". The final kernel binary to put in 1848 ROM memory will be arch/arm/boot/xipImage. 1849 1850 If unsure, say N. 1851 1852config XIP_PHYS_ADDR 1853 hex "XIP Kernel Physical Location" 1854 depends on XIP_KERNEL 1855 default "0x00080000" 1856 help 1857 This is the physical address in your flash memory the kernel will 1858 be linked for and stored to. This address is dependent on your 1859 own flash usage. 1860 1861config XIP_DEFLATED_DATA 1862 bool "Store kernel .data section compressed in ROM" 1863 depends on XIP_KERNEL 1864 select ZLIB_INFLATE 1865 help 1866 Before the kernel is actually executed, its .data section has to be 1867 copied to RAM from ROM. This option allows for storing that data 1868 in compressed form and decompressed to RAM rather than merely being 1869 copied, saving some precious ROM space. A possible drawback is a 1870 slightly longer boot delay. 1871 1872config KEXEC 1873 bool "Kexec system call (EXPERIMENTAL)" 1874 depends on (!SMP || PM_SLEEP_SMP) 1875 depends on MMU 1876 select KEXEC_CORE 1877 help 1878 kexec is a system call that implements the ability to shutdown your 1879 current kernel, and to start another kernel. It is like a reboot 1880 but it is independent of the system firmware. And like a reboot 1881 you can start any kernel with it, not just Linux. 1882 1883 It is an ongoing process to be certain the hardware in a machine 1884 is properly shutdown, so do not be surprised if this code does not 1885 initially work for you. 1886 1887config ATAGS_PROC 1888 bool "Export atags in procfs" 1889 depends on ATAGS && KEXEC 1890 default y 1891 help 1892 Should the atags used to boot the kernel be exported in an "atags" 1893 file in procfs. Useful with kexec. 1894 1895config CRASH_DUMP 1896 bool "Build kdump crash kernel (EXPERIMENTAL)" 1897 help 1898 Generate crash dump after being started by kexec. This should 1899 be normally only set in special crash dump kernels which are 1900 loaded in the main kernel with kexec-tools into a specially 1901 reserved region and then later executed after a crash by 1902 kdump/kexec. The crash dump kernel must be compiled to a 1903 memory address not used by the main kernel 1904 1905 For more details see Documentation/admin-guide/kdump/kdump.rst 1906 1907config AUTO_ZRELADDR 1908 bool "Auto calculation of the decompressed kernel image address" 1909 help 1910 ZRELADDR is the physical address where the decompressed kernel 1911 image will be placed. If AUTO_ZRELADDR is selected, the address 1912 will be determined at run-time by masking the current IP with 1913 0xf8000000. This assumes the zImage being placed in the first 128MB 1914 from start of memory. 1915 1916config EFI_STUB 1917 bool 1918 1919config EFI 1920 bool "UEFI runtime support" 1921 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1922 select UCS2_STRING 1923 select EFI_PARAMS_FROM_FDT 1924 select EFI_STUB 1925 select EFI_GENERIC_STUB 1926 select EFI_RUNTIME_WRAPPERS 1927 help 1928 This option provides support for runtime services provided 1929 by UEFI firmware (such as non-volatile variables, realtime 1930 clock, and platform reset). A UEFI stub is also provided to 1931 allow the kernel to be booted as an EFI application. This 1932 is only useful for kernels that may run on systems that have 1933 UEFI firmware. 1934 1935config DMI 1936 bool "Enable support for SMBIOS (DMI) tables" 1937 depends on EFI 1938 default y 1939 help 1940 This enables SMBIOS/DMI feature for systems. 1941 1942 This option is only useful on systems that have UEFI firmware. 1943 However, even with this option, the resultant kernel should 1944 continue to boot on existing non-UEFI platforms. 1945 1946 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1947 i.e., the the practice of identifying the platform via DMI to 1948 decide whether certain workarounds for buggy hardware and/or 1949 firmware need to be enabled. This would require the DMI subsystem 1950 to be enabled much earlier than we do on ARM, which is non-trivial. 1951 1952endmenu 1953 1954menu "CPU Power Management" 1955 1956source "drivers/cpufreq/Kconfig" 1957 1958source "drivers/cpuidle/Kconfig" 1959 1960endmenu 1961 1962menu "Floating point emulation" 1963 1964comment "At least one emulation must be selected" 1965 1966config FPE_NWFPE 1967 bool "NWFPE math emulation" 1968 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1969 help 1970 Say Y to include the NWFPE floating point emulator in the kernel. 1971 This is necessary to run most binaries. Linux does not currently 1972 support floating point hardware so you need to say Y here even if 1973 your machine has an FPA or floating point co-processor podule. 1974 1975 You may say N here if you are going to load the Acorn FPEmulator 1976 early in the bootup. 1977 1978config FPE_NWFPE_XP 1979 bool "Support extended precision" 1980 depends on FPE_NWFPE 1981 help 1982 Say Y to include 80-bit support in the kernel floating-point 1983 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1984 Note that gcc does not generate 80-bit operations by default, 1985 so in most cases this option only enlarges the size of the 1986 floating point emulator without any good reason. 1987 1988 You almost surely want to say N here. 1989 1990config FPE_FASTFPE 1991 bool "FastFPE math emulation (EXPERIMENTAL)" 1992 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1993 help 1994 Say Y here to include the FAST floating point emulator in the kernel. 1995 This is an experimental much faster emulator which now also has full 1996 precision for the mantissa. It does not support any exceptions. 1997 It is very simple, and approximately 3-6 times faster than NWFPE. 1998 1999 It should be sufficient for most programs. It may be not suitable 2000 for scientific calculations, but you have to check this for yourself. 2001 If you do not feel you need a faster FP emulation you should better 2002 choose NWFPE. 2003 2004config VFP 2005 bool "VFP-format floating point maths" 2006 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2007 help 2008 Say Y to include VFP support code in the kernel. This is needed 2009 if your hardware includes a VFP unit. 2010 2011 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2012 release notes and additional status information. 2013 2014 Say N if your target does not have VFP hardware. 2015 2016config VFPv3 2017 bool 2018 depends on VFP 2019 default y if CPU_V7 2020 2021config NEON 2022 bool "Advanced SIMD (NEON) Extension support" 2023 depends on VFPv3 && CPU_V7 2024 help 2025 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2026 Extension. 2027 2028config KERNEL_MODE_NEON 2029 bool "Support for NEON in kernel mode" 2030 depends on NEON && AEABI 2031 help 2032 Say Y to include support for NEON in kernel mode. 2033 2034endmenu 2035 2036menu "Power management options" 2037 2038source "kernel/power/Kconfig" 2039 2040config ARCH_SUSPEND_POSSIBLE 2041 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2042 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2043 def_bool y 2044 2045config ARM_CPU_SUSPEND 2046 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2047 depends on ARCH_SUSPEND_POSSIBLE 2048 2049config ARCH_HIBERNATION_POSSIBLE 2050 bool 2051 depends on MMU 2052 default y if ARCH_SUSPEND_POSSIBLE 2053 2054endmenu 2055 2056source "drivers/firmware/Kconfig" 2057 2058if CRYPTO 2059source "arch/arm/crypto/Kconfig" 2060endif 2061 2062source "arch/arm/Kconfig.assembler" 2063