1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CURRENT_STACK_POINTER 12 select ARCH_HAS_DEBUG_VIRTUAL if MMU 13 select ARCH_HAS_DMA_ALLOC if MMU 14 select ARCH_HAS_DMA_OPS 15 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 16 select ARCH_HAS_ELF_RANDOMIZE 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_KEEPINITRD 19 select ARCH_HAS_KCOV 20 select ARCH_HAS_MEMBARRIER_SYNC_CORE 21 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 22 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 23 select ARCH_HAS_SETUP_DMA_OPS 24 select ARCH_HAS_SET_MEMORY 25 select ARCH_STACKWALK 26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 27 select ARCH_HAS_STRICT_MODULE_RWX if MMU 28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 29 select ARCH_HAS_SYNC_DMA_FOR_CPU 30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 32 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_KEEP_MEMBLOCK 35 select ARCH_HAS_UBSAN 36 select ARCH_MIGHT_HAVE_PC_PARPORT 37 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 38 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 39 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 40 select ARCH_SUPPORTS_ATOMIC_RMW 41 select ARCH_SUPPORTS_CFI 42 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 43 select ARCH_SUPPORTS_PER_VMA_LOCK 44 select ARCH_USE_BUILTIN_BSWAP 45 select ARCH_USE_CMPXCHG_LOCKREF 46 select ARCH_USE_MEMTEST 47 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 48 select ARCH_WANT_GENERAL_HUGETLB 49 select ARCH_WANT_IPC_PARSE_VERSION 50 select ARCH_WANT_LD_ORPHAN_WARN 51 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 52 select BUILDTIME_TABLE_SORT if MMU 53 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 54 select CLONE_BACKWARDS 55 select CPU_PM if SUSPEND || CPU_IDLE 56 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 57 select DMA_DECLARE_COHERENT 58 select DMA_GLOBAL_POOL if !MMU 59 select DMA_NONCOHERENT_MMAP if MMU 60 select EDAC_SUPPORT 61 select EDAC_ATOMIC_SCRUB 62 select GENERIC_ALLOCATOR 63 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 64 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 65 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 66 select GENERIC_IRQ_IPI if SMP 67 select GENERIC_CPU_AUTOPROBE 68 select GENERIC_CPU_DEVICES 69 select GENERIC_EARLY_IOREMAP 70 select GENERIC_IDLE_POLL_SETUP 71 select GENERIC_IRQ_MULTI_HANDLER 72 select GENERIC_IRQ_PROBE 73 select GENERIC_IRQ_SHOW 74 select GENERIC_IRQ_SHOW_LEVEL 75 select GENERIC_LIB_DEVMEM_IS_ALLOWED 76 select GENERIC_PCI_IOMAP 77 select GENERIC_SCHED_CLOCK 78 select GENERIC_SMP_IDLE_THREAD 79 select HARDIRQS_SW_RESEND 80 select HAS_IOPORT 81 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 83 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 88 select HAVE_ARCH_KSTACK_ERASE 89 select HAVE_ARCH_MMAP_RND_BITS if MMU 90 select HAVE_ARCH_PFN_VALID 91 select HAVE_ARCH_SECCOMP 92 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 93 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 94 select HAVE_ARCH_TRACEHOOK 95 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 96 select HAVE_ARM_SMCCC if CPU_V7 97 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 98 select HAVE_CONTEXT_TRACKING_USER 99 select HAVE_C_RECORDMCOUNT 100 select HAVE_BUILDTIME_MCOUNT_SORT 101 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 102 select HAVE_DMA_CONTIGUOUS if MMU 103 select HAVE_EXTRA_IPI_TRACEPOINTS 104 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 105 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 106 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 107 select HAVE_EXIT_THREAD 108 select HAVE_GUP_FAST if ARM_LPAE 109 select HAVE_FUNCTION_ERROR_INJECTION 110 select HAVE_FUNCTION_GRAPH_TRACER 111 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 112 select HAVE_GCC_PLUGINS 113 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 114 select HAVE_IRQ_TIME_ACCOUNTING 115 select HAVE_KERNEL_GZIP 116 select HAVE_KERNEL_LZ4 117 select HAVE_KERNEL_LZMA 118 select HAVE_KERNEL_LZO 119 select HAVE_KERNEL_XZ 120 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 121 select HAVE_KRETPROBES if HAVE_KPROBES 122 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 123 select HAVE_MOD_ARCH_SPECIFIC 124 select HAVE_NMI 125 select HAVE_OPTPROBES if !THUMB2_KERNEL 126 select HAVE_PAGE_SIZE_4KB 127 select HAVE_PCI if MMU 128 select HAVE_PERF_EVENTS 129 select HAVE_PERF_REGS 130 select HAVE_PERF_USER_STACK_DUMP 131 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 132 select HAVE_REGS_AND_STACK_ACCESS_API 133 select HAVE_RSEQ 134 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 135 select HAVE_STACKPROTECTOR 136 select HAVE_SYSCALL_TRACEPOINTS 137 select HAVE_UID16 138 select HAVE_VIRT_CPU_ACCOUNTING_GEN 139 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 140 select IRQ_FORCED_THREADING 141 select LOCK_MM_AND_FIND_VMA 142 select MODULES_USE_ELF_REL 143 select NEED_DMA_MAP_STATE 144 select OF_EARLY_FLATTREE if OF 145 select OLD_SIGACTION 146 select OLD_SIGSUSPEND3 147 select PCI_DOMAINS_GENERIC if PCI 148 select PCI_SYSCALL if PCI 149 select PERF_USE_VMALLOC 150 select RTC_LIB 151 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 152 select SYS_SUPPORTS_APM_EMULATION 153 select THREAD_INFO_IN_TASK 154 select TIMER_OF if OF 155 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 156 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 157 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 158 # Above selects are sorted alphabetically; please add new ones 159 # according to that. Thanks. 160 help 161 The ARM series is a line of low-power-consumption RISC chip designs 162 licensed by ARM Ltd and targeted at embedded applications and 163 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 164 manufactured, but legacy ARM-based PC hardware remains popular in 165 Europe. There is an ARM Linux project with a web page at 166 <http://www.arm.linux.org.uk/>. 167 168config ARM_HAS_GROUP_RELOCS 169 def_bool y 170 depends on !LD_IS_LLD || LLD_VERSION >= 140000 171 depends on !COMPILE_TEST 172 help 173 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 174 relocations, which have been around for a long time, but were not 175 supported in LLD until version 14. The combined range is -/+ 256 MiB, 176 which is usually sufficient, but not for allyesconfig, so we disable 177 this feature when doing compile testing. 178 179config ARM_DMA_USE_IOMMU 180 bool 181 select NEED_SG_DMA_LENGTH 182 183if ARM_DMA_USE_IOMMU 184 185config ARM_DMA_IOMMU_ALIGNMENT 186 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 187 range 4 9 188 default 8 189 help 190 DMA mapping framework by default aligns all buffers to the smallest 191 PAGE_SIZE order which is greater than or equal to the requested buffer 192 size. This works well for buffers up to a few hundreds kilobytes, but 193 for larger buffers it just a waste of address space. Drivers which has 194 relatively small addressing window (like 64Mib) might run out of 195 virtual space with just a few allocations. 196 197 With this parameter you can specify the maximum PAGE_SIZE order for 198 DMA IOMMU buffers. Larger buffers will be aligned only to this 199 specified order. The order is expressed as a power of two multiplied 200 by the PAGE_SIZE. 201 202endif 203 204config SYS_SUPPORTS_APM_EMULATION 205 bool 206 207config HAVE_TCM 208 bool 209 select GENERIC_ALLOCATOR 210 211config HAVE_PROC_CPU 212 bool 213 214config NO_IOPORT_MAP 215 bool 216 217config SBUS 218 bool 219 220config STACKTRACE_SUPPORT 221 bool 222 default y 223 224config LOCKDEP_SUPPORT 225 bool 226 default y 227 228config ARCH_HAS_ILOG2_U32 229 bool 230 231config ARCH_HAS_ILOG2_U64 232 bool 233 234config ARCH_HAS_BANDGAP 235 bool 236 237config FIX_EARLYCON_MEM 238 def_bool y if MMU 239 240config GENERIC_HWEIGHT 241 bool 242 default y 243 244config GENERIC_CALIBRATE_DELAY 245 bool 246 default y 247 248config ARCH_MAY_HAVE_PC_FDC 249 bool 250 251config ARCH_SUPPORTS_UPROBES 252 def_bool y 253 254config GENERIC_ISA_DMA 255 bool 256 257config FIQ 258 bool 259 260config ARCH_MTD_XIP 261 bool 262 263config ARM_PATCH_PHYS_VIRT 264 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 265 default y 266 depends on MMU 267 help 268 Patch phys-to-virt and virt-to-phys translation functions at 269 boot and module load time according to the position of the 270 kernel in system memory. 271 272 This can only be used with non-XIP MMU kernels where the base 273 of physical memory is at a 2 MiB boundary. 274 275 Only disable this option if you know that you do not require 276 this feature (eg, building a kernel for a single machine) and 277 you need to shrink the kernel to the minimal size. 278 279config NEED_MACH_IO_H 280 bool 281 help 282 Select this when mach/io.h is required to provide special 283 definitions for this platform. The need for mach/io.h should 284 be avoided when possible. 285 286config NEED_MACH_MEMORY_H 287 bool 288 help 289 Select this when mach/memory.h is required to provide special 290 definitions for this platform. The need for mach/memory.h should 291 be avoided when possible. 292 293config PHYS_OFFSET 294 hex "Physical address of main memory" if MMU 295 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 296 default DRAM_BASE if !MMU 297 default 0x00000000 if ARCH_FOOTBRIDGE 298 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 299 default 0xa0000000 if ARCH_PXA 300 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 301 default 0 302 help 303 Please provide the physical address corresponding to the 304 location of main memory in your system. 305 306config GENERIC_BUG 307 def_bool y 308 depends on BUG 309 310config PGTABLE_LEVELS 311 int 312 default 3 if ARM_LPAE 313 default 2 314 315menu "System Type" 316 317config MMU 318 bool "MMU-based Paged Memory Management Support" 319 default y 320 help 321 Select if you want MMU-based virtualised addressing space 322 support by paged memory management. If unsure, say 'Y'. 323 324config ARM_SINGLE_ARMV7M 325 def_bool !MMU 326 select ARM_NVIC 327 select CPU_V7M 328 select NO_IOPORT_MAP 329 330config ARCH_MMAP_RND_BITS_MIN 331 default 8 332 333config ARCH_MMAP_RND_BITS_MAX 334 default 14 if PAGE_OFFSET=0x40000000 335 default 15 if PAGE_OFFSET=0x80000000 336 default 16 337 338config ARCH_MULTIPLATFORM 339 bool "Require kernel to be portable to multiple machines" if EXPERT 340 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 341 default y 342 help 343 In general, all Arm machines can be supported in a single 344 kernel image, covering either Armv4/v5 or Armv6/v7. 345 346 However, some configuration options require hardcoding machine 347 specific physical addresses or enable errata workarounds that may 348 break other machines. 349 350 Selecting N here allows using those options, including 351 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 352 353source "arch/arm/Kconfig.platforms" 354 355# 356# This is sorted alphabetically by mach-* pathname. However, plat-* 357# Kconfigs may be included either alphabetically (according to the 358# plat- suffix) or along side the corresponding mach-* source. 359# 360source "arch/arm/mach-actions/Kconfig" 361 362source "arch/arm/mach-alpine/Kconfig" 363 364source "arch/arm/mach-artpec/Kconfig" 365 366source "arch/arm/mach-aspeed/Kconfig" 367 368source "arch/arm/mach-at91/Kconfig" 369 370source "arch/arm/mach-axxia/Kconfig" 371 372source "arch/arm/mach-bcm/Kconfig" 373 374source "arch/arm/mach-berlin/Kconfig" 375 376source "arch/arm/mach-clps711x/Kconfig" 377 378source "arch/arm/mach-davinci/Kconfig" 379 380source "arch/arm/mach-digicolor/Kconfig" 381 382source "arch/arm/mach-dove/Kconfig" 383 384source "arch/arm/mach-ep93xx/Kconfig" 385 386source "arch/arm/mach-exynos/Kconfig" 387 388source "arch/arm/mach-footbridge/Kconfig" 389 390source "arch/arm/mach-gemini/Kconfig" 391 392source "arch/arm/mach-highbank/Kconfig" 393 394source "arch/arm/mach-hisi/Kconfig" 395 396source "arch/arm/mach-hpe/Kconfig" 397 398source "arch/arm/mach-imx/Kconfig" 399 400source "arch/arm/mach-ixp4xx/Kconfig" 401 402source "arch/arm/mach-keystone/Kconfig" 403 404source "arch/arm/mach-lpc32xx/Kconfig" 405 406source "arch/arm/mach-mediatek/Kconfig" 407 408source "arch/arm/mach-meson/Kconfig" 409 410source "arch/arm/mach-milbeaut/Kconfig" 411 412source "arch/arm/mach-mmp/Kconfig" 413 414source "arch/arm/mach-mstar/Kconfig" 415 416source "arch/arm/mach-mv78xx0/Kconfig" 417 418source "arch/arm/mach-mvebu/Kconfig" 419 420source "arch/arm/mach-mxs/Kconfig" 421 422source "arch/arm/mach-nomadik/Kconfig" 423 424source "arch/arm/mach-npcm/Kconfig" 425 426source "arch/arm/mach-omap1/Kconfig" 427 428source "arch/arm/mach-omap2/Kconfig" 429 430source "arch/arm/mach-orion5x/Kconfig" 431 432source "arch/arm/mach-pxa/Kconfig" 433 434source "arch/arm/mach-qcom/Kconfig" 435 436source "arch/arm/mach-realtek/Kconfig" 437 438source "arch/arm/mach-rpc/Kconfig" 439 440source "arch/arm/mach-rockchip/Kconfig" 441 442source "arch/arm/mach-s3c/Kconfig" 443 444source "arch/arm/mach-s5pv210/Kconfig" 445 446source "arch/arm/mach-sa1100/Kconfig" 447 448source "arch/arm/mach-shmobile/Kconfig" 449 450source "arch/arm/mach-socfpga/Kconfig" 451 452source "arch/arm/mach-spear/Kconfig" 453 454source "arch/arm/mach-sti/Kconfig" 455 456source "arch/arm/mach-stm32/Kconfig" 457 458source "arch/arm/mach-sunxi/Kconfig" 459 460source "arch/arm/mach-tegra/Kconfig" 461 462source "arch/arm/mach-ux500/Kconfig" 463 464source "arch/arm/mach-versatile/Kconfig" 465 466source "arch/arm/mach-vt8500/Kconfig" 467 468source "arch/arm/mach-zynq/Kconfig" 469 470# ARMv7-M architecture 471config ARCH_LPC18XX 472 bool "NXP LPC18xx/LPC43xx" 473 depends on ARM_SINGLE_ARMV7M 474 select ARCH_HAS_RESET_CONTROLLER 475 select ARM_AMBA 476 select CLKSRC_LPC32XX 477 select PINCTRL 478 help 479 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 480 high performance microcontrollers. 481 482config ARCH_MPS2 483 bool "ARM MPS2 platform" 484 depends on ARM_SINGLE_ARMV7M 485 select ARM_AMBA 486 select CLKSRC_MPS2 487 help 488 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 489 with a range of available cores like Cortex-M3/M4/M7. 490 491 Please, note that depends which Application Note is used memory map 492 for the platform may vary, so adjustment of RAM base might be needed. 493 494# Definitions to make life easier 495config ARCH_ACORN 496 bool 497 498config PLAT_ORION 499 bool 500 select CLKSRC_MMIO 501 select GENERIC_IRQ_CHIP 502 select IRQ_DOMAIN 503 504config PLAT_ORION_LEGACY 505 bool 506 select PLAT_ORION 507 508config PLAT_VERSATILE 509 bool 510 511source "arch/arm/mm/Kconfig" 512 513config IWMMXT 514 bool "Enable iWMMXt support" 515 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 516 default y if PXA27x || PXA3xx || ARCH_MMP 517 help 518 Enable support for iWMMXt context switching at run time if 519 running on a CPU that supports it. 520 521if !MMU 522source "arch/arm/Kconfig-nommu" 523endif 524 525config PJ4B_ERRATA_4742 526 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 527 depends on CPU_PJ4B && MACH_ARMADA_370 528 default y 529 help 530 When coming out of either a Wait for Interrupt (WFI) or a Wait for 531 Event (WFE) IDLE states, a specific timing sensitivity exists between 532 the retiring WFI/WFE instructions and the newly issued subsequent 533 instructions. This sensitivity can result in a CPU hang scenario. 534 Workaround: 535 The software must insert either a Data Synchronization Barrier (DSB) 536 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 537 instruction 538 539config ARM_ERRATA_326103 540 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 541 depends on CPU_V6 542 help 543 Executing a SWP instruction to read-only memory does not set bit 11 544 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 545 treat the access as a read, preventing a COW from occurring and 546 causing the faulting task to livelock. 547 548config ARM_ERRATA_411920 549 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 550 depends on CPU_V6 || CPU_V6K 551 help 552 Invalidation of the Instruction Cache operation can 553 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 554 It does not affect the MPCore. This option enables the ARM Ltd. 555 recommended workaround. 556 557config ARM_ERRATA_430973 558 bool "ARM errata: Stale prediction on replaced interworking branch" 559 depends on CPU_V7 560 help 561 This option enables the workaround for the 430973 Cortex-A8 562 r1p* erratum. If a code sequence containing an ARM/Thumb 563 interworking branch is replaced with another code sequence at the 564 same virtual address, whether due to self-modifying code or virtual 565 to physical address re-mapping, Cortex-A8 does not recover from the 566 stale interworking branch prediction. This results in Cortex-A8 567 executing the new code sequence in the incorrect ARM or Thumb state. 568 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 569 and also flushes the branch target cache at every context switch. 570 Note that setting specific bits in the ACTLR register may not be 571 available in non-secure mode. 572 573config ARM_ERRATA_458693 574 bool "ARM errata: Processor deadlock when a false hazard is created" 575 depends on CPU_V7 576 depends on !ARCH_MULTIPLATFORM 577 help 578 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 579 erratum. For very specific sequences of memory operations, it is 580 possible for a hazard condition intended for a cache line to instead 581 be incorrectly associated with a different cache line. This false 582 hazard might then cause a processor deadlock. The workaround enables 583 the L1 caching of the NEON accesses and disables the PLD instruction 584 in the ACTLR register. Note that setting specific bits in the ACTLR 585 register may not be available in non-secure mode and thus is not 586 available on a multiplatform kernel. This should be applied by the 587 bootloader instead. 588 589config ARM_ERRATA_460075 590 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 591 depends on CPU_V7 592 depends on !ARCH_MULTIPLATFORM 593 help 594 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 595 erratum. Any asynchronous access to the L2 cache may encounter a 596 situation in which recent store transactions to the L2 cache are lost 597 and overwritten with stale memory contents from external memory. The 598 workaround disables the write-allocate mode for the L2 cache via the 599 ACTLR register. Note that setting specific bits in the ACTLR register 600 may not be available in non-secure mode and thus is not available on 601 a multiplatform kernel. This should be applied by the bootloader 602 instead. 603 604config ARM_ERRATA_742230 605 bool "ARM errata: DMB operation may be faulty" 606 depends on CPU_V7 && SMP 607 depends on !ARCH_MULTIPLATFORM 608 help 609 This option enables the workaround for the 742230 Cortex-A9 610 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 611 between two write operations may not ensure the correct visibility 612 ordering of the two writes. This workaround sets a specific bit in 613 the diagnostic register of the Cortex-A9 which causes the DMB 614 instruction to behave as a DSB, ensuring the correct behaviour of 615 the two writes. Note that setting specific bits in the diagnostics 616 register may not be available in non-secure mode and thus is not 617 available on a multiplatform kernel. This should be applied by the 618 bootloader instead. 619 620config ARM_ERRATA_742231 621 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 622 depends on CPU_V7 && SMP 623 depends on !ARCH_MULTIPLATFORM 624 help 625 This option enables the workaround for the 742231 Cortex-A9 626 (r2p0..r2p2) erratum. Under certain conditions, specific to the 627 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 628 accessing some data located in the same cache line, may get corrupted 629 data due to bad handling of the address hazard when the line gets 630 replaced from one of the CPUs at the same time as another CPU is 631 accessing it. This workaround sets specific bits in the diagnostic 632 register of the Cortex-A9 which reduces the linefill issuing 633 capabilities of the processor. Note that setting specific bits in the 634 diagnostics register may not be available in non-secure mode and thus 635 is not available on a multiplatform kernel. This should be applied by 636 the bootloader instead. 637 638config ARM_ERRATA_643719 639 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 640 depends on CPU_V7 && SMP 641 default y 642 help 643 This option enables the workaround for the 643719 Cortex-A9 (prior to 644 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 645 register returns zero when it should return one. The workaround 646 corrects this value, ensuring cache maintenance operations which use 647 it behave as intended and avoiding data corruption. 648 649config ARM_ERRATA_720789 650 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 651 depends on CPU_V7 652 help 653 This option enables the workaround for the 720789 Cortex-A9 (prior to 654 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 655 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 656 As a consequence of this erratum, some TLB entries which should be 657 invalidated are not, resulting in an incoherency in the system page 658 tables. The workaround changes the TLB flushing routines to invalidate 659 entries regardless of the ASID. 660 661config ARM_ERRATA_743622 662 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 663 depends on CPU_V7 664 depends on !ARCH_MULTIPLATFORM 665 help 666 This option enables the workaround for the 743622 Cortex-A9 667 (r2p*) erratum. Under very rare conditions, a faulty 668 optimisation in the Cortex-A9 Store Buffer may lead to data 669 corruption. This workaround sets a specific bit in the diagnostic 670 register of the Cortex-A9 which disables the Store Buffer 671 optimisation, preventing the defect from occurring. This has no 672 visible impact on the overall performance or power consumption of the 673 processor. Note that setting specific bits in the diagnostics register 674 may not be available in non-secure mode and thus is not available on a 675 multiplatform kernel. This should be applied by the bootloader instead. 676 677config ARM_ERRATA_751472 678 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 679 depends on CPU_V7 680 depends on !ARCH_MULTIPLATFORM 681 help 682 This option enables the workaround for the 751472 Cortex-A9 (prior 683 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 684 completion of a following broadcasted operation if the second 685 operation is received by a CPU before the ICIALLUIS has completed, 686 potentially leading to corrupted entries in the cache or TLB. 687 Note that setting specific bits in the diagnostics register may 688 not be available in non-secure mode and thus is not available on 689 a multiplatform kernel. This should be applied by the bootloader 690 instead. 691 692config ARM_ERRATA_754322 693 bool "ARM errata: possible faulty MMU translations following an ASID switch" 694 depends on CPU_V7 695 help 696 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 697 r3p*) erratum. A speculative memory access may cause a page table walk 698 which starts prior to an ASID switch but completes afterwards. This 699 can populate the micro-TLB with a stale entry which may be hit with 700 the new ASID. This workaround places two dsb instructions in the mm 701 switching code so that no page table walks can cross the ASID switch. 702 703config ARM_ERRATA_754327 704 bool "ARM errata: no automatic Store Buffer drain" 705 depends on CPU_V7 && SMP 706 help 707 This option enables the workaround for the 754327 Cortex-A9 (prior to 708 r2p0) erratum. The Store Buffer does not have any automatic draining 709 mechanism and therefore a livelock may occur if an external agent 710 continuously polls a memory location waiting to observe an update. 711 This workaround defines cpu_relax() as smp_mb(), preventing correctly 712 written polling loops from denying visibility of updates to memory. 713 714config ARM_ERRATA_364296 715 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 716 depends on CPU_V6 717 help 718 This options enables the workaround for the 364296 ARM1136 719 r0p2 erratum (possible cache data corruption with 720 hit-under-miss enabled). It sets the undocumented bit 31 in 721 the auxiliary control register and the FI bit in the control 722 register, thus disabling hit-under-miss without putting the 723 processor into full low interrupt latency mode. ARM11MPCore 724 is not affected. 725 726config ARM_ERRATA_764369 727 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 728 depends on CPU_V7 && SMP 729 help 730 This option enables the workaround for erratum 764369 731 affecting Cortex-A9 MPCore with two or more processors (all 732 current revisions). Under certain timing circumstances, a data 733 cache line maintenance operation by MVA targeting an Inner 734 Shareable memory region may fail to proceed up to either the 735 Point of Coherency or to the Point of Unification of the 736 system. This workaround adds a DSB instruction before the 737 relevant cache maintenance functions and sets a specific bit 738 in the diagnostic control register of the SCU. 739 740config ARM_ERRATA_764319 741 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 742 depends on CPU_V7 743 help 744 This option enables the workaround for the 764319 Cortex-A9 erratum. 745 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 746 unexpected Undefined Instruction exception when the DBGSWENABLE 747 external pin is set to 0, even when the CP14 accesses are performed 748 from a privileged mode. This work around catches the exception in a 749 way the kernel does not stop execution. 750 751config ARM_ERRATA_775420 752 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 753 depends on CPU_V7 754 help 755 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 756 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 757 operation aborts with MMU exception, it might cause the processor 758 to deadlock. This workaround puts DSB before executing ISB if 759 an abort may occur on cache maintenance. 760 761config ARM_ERRATA_798181 762 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 763 depends on CPU_V7 && SMP 764 help 765 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 766 adequately shooting down all use of the old entries. This 767 option enables the Linux kernel workaround for this erratum 768 which sends an IPI to the CPUs that are running the same ASID 769 as the one being invalidated. 770 771config ARM_ERRATA_773022 772 bool "ARM errata: incorrect instructions may be executed from loop buffer" 773 depends on CPU_V7 774 help 775 This option enables the workaround for the 773022 Cortex-A15 776 (up to r0p4) erratum. In certain rare sequences of code, the 777 loop buffer may deliver incorrect instructions. This 778 workaround disables the loop buffer to avoid the erratum. 779 780config ARM_ERRATA_818325_852422 781 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 782 depends on CPU_V7 783 help 784 This option enables the workaround for: 785 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 786 instruction might deadlock. Fixed in r0p1. 787 - Cortex-A12 852422: Execution of a sequence of instructions might 788 lead to either a data corruption or a CPU deadlock. Not fixed in 789 any Cortex-A12 cores yet. 790 This workaround for all both errata involves setting bit[12] of the 791 Feature Register. This bit disables an optimisation applied to a 792 sequence of 2 instructions that use opposing condition codes. 793 794config ARM_ERRATA_821420 795 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 796 depends on CPU_V7 797 help 798 This option enables the workaround for the 821420 Cortex-A12 799 (all revs) erratum. In very rare timing conditions, a sequence 800 of VMOV to Core registers instructions, for which the second 801 one is in the shadow of a branch or abort, can lead to a 802 deadlock when the VMOV instructions are issued out-of-order. 803 804config ARM_ERRATA_825619 805 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 806 depends on CPU_V7 807 help 808 This option enables the workaround for the 825619 Cortex-A12 809 (all revs) erratum. Within rare timing constraints, executing a 810 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 811 and Device/Strongly-Ordered loads and stores might cause deadlock 812 813config ARM_ERRATA_857271 814 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 815 depends on CPU_V7 816 help 817 This option enables the workaround for the 857271 Cortex-A12 818 (all revs) erratum. Under very rare timing conditions, the CPU might 819 hang. The workaround is expected to have a < 1% performance impact. 820 821config ARM_ERRATA_852421 822 bool "ARM errata: A17: DMB ST might fail to create order between stores" 823 depends on CPU_V7 824 help 825 This option enables the workaround for the 852421 Cortex-A17 826 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 827 execution of a DMB ST instruction might fail to properly order 828 stores from GroupA and stores from GroupB. 829 830config ARM_ERRATA_852423 831 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 832 depends on CPU_V7 833 help 834 This option enables the workaround for: 835 - Cortex-A17 852423: Execution of a sequence of instructions might 836 lead to either a data corruption or a CPU deadlock. Not fixed in 837 any Cortex-A17 cores yet. 838 This is identical to Cortex-A12 erratum 852422. It is a separate 839 config option from the A12 erratum due to the way errata are checked 840 for and handled. 841 842config ARM_ERRATA_857272 843 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 844 depends on CPU_V7 845 help 846 This option enables the workaround for the 857272 Cortex-A17 erratum. 847 This erratum is not known to be fixed in any A17 revision. 848 This is identical to Cortex-A12 erratum 857271. It is a separate 849 config option from the A12 erratum due to the way errata are checked 850 for and handled. 851 852endmenu 853 854source "arch/arm/common/Kconfig" 855 856menu "Bus support" 857 858config ISA 859 bool 860 help 861 Find out whether you have ISA slots on your motherboard. ISA is the 862 name of a bus system, i.e. the way the CPU talks to the other stuff 863 inside your box. Other bus systems are PCI, EISA, MicroChannel 864 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 865 newer boards don't support it. If you have ISA, say Y, otherwise N. 866 867# Select ISA DMA interface 868config ISA_DMA_API 869 bool 870 871config ARM_ERRATA_814220 872 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 873 depends on CPU_V7 874 help 875 The v7 ARM states that all cache and branch predictor maintenance 876 operations that do not specify an address execute, relative to 877 each other, in program order. 878 However, because of this erratum, an L2 set/way cache maintenance 879 operation can overtake an L1 set/way cache maintenance operation. 880 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 881 r0p4, r0p5. 882 883endmenu 884 885menu "Kernel Features" 886 887config HAVE_SMP 888 bool 889 help 890 This option should be selected by machines which have an SMP- 891 capable CPU. 892 893 The only effect of this option is to make the SMP-related 894 options available to the user for configuration. 895 896config SMP 897 bool "Symmetric Multi-Processing" 898 depends on CPU_V6K || CPU_V7 899 depends on HAVE_SMP 900 depends on MMU || ARM_MPU 901 select IRQ_WORK 902 help 903 This enables support for systems with more than one CPU. If you have 904 a system with only one CPU, say N. If you have a system with more 905 than one CPU, say Y. 906 907 If you say N here, the kernel will run on uni- and multiprocessor 908 machines, but will use only one CPU of a multiprocessor machine. If 909 you say Y here, the kernel will run on many, but not all, 910 uniprocessor machines. On a uniprocessor machine, the kernel 911 will run faster if you say N here. 912 913 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 914 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 915 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 916 917 If you don't know what to do here, say N. 918 919config SMP_ON_UP 920 bool "Allow booting SMP kernel on uniprocessor systems" 921 depends on SMP && MMU 922 default y 923 help 924 SMP kernels contain instructions which fail on non-SMP processors. 925 Enabling this option allows the kernel to modify itself to make 926 these instructions safe. Disabling it allows about 1K of space 927 savings. 928 929 If you don't know what to do here, say Y. 930 931 932config CURRENT_POINTER_IN_TPIDRURO 933 def_bool y 934 depends on CPU_32v6K && !CPU_V6 935 936config IRQSTACKS 937 def_bool y 938 select HAVE_IRQ_EXIT_ON_IRQ_STACK 939 select HAVE_SOFTIRQ_ON_OWN_STACK 940 941config ARM_CPU_TOPOLOGY 942 bool "Support cpu topology definition" 943 depends on SMP && CPU_V7 944 select ARCH_SUPPORTS_SCHED_MC 945 select ARCH_SUPPORTS_SCHED_SMT 946 default y 947 help 948 Support ARM cpu topology definition. The MPIDR register defines 949 affinity between processors which is then used to describe the cpu 950 topology of an ARM System. 951 952config HAVE_ARM_SCU 953 bool 954 help 955 This option enables support for the ARM snoop control unit 956 957config HAVE_ARM_ARCH_TIMER 958 bool "Architected timer support" 959 depends on CPU_V7 960 select ARM_ARCH_TIMER 961 help 962 This option enables support for the ARM architected timer 963 964config HAVE_ARM_TWD 965 bool 966 help 967 This options enables support for the ARM timer and watchdog unit 968 969config MCPM 970 bool "Multi-Cluster Power Management" 971 depends on CPU_V7 && SMP 972 help 973 This option provides the common power management infrastructure 974 for (multi-)cluster based systems, such as big.LITTLE based 975 systems. 976 977config MCPM_QUAD_CLUSTER 978 bool 979 depends on MCPM 980 help 981 To avoid wasting resources unnecessarily, MCPM only supports up 982 to 2 clusters by default. 983 Platforms with 3 or 4 clusters that use MCPM must select this 984 option to allow the additional clusters to be managed. 985 986config BIG_LITTLE 987 bool "big.LITTLE support (Experimental)" 988 depends on CPU_V7 && SMP 989 select MCPM 990 help 991 This option enables support selections for the big.LITTLE 992 system architecture. 993 994config BL_SWITCHER 995 bool "big.LITTLE switcher support" 996 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 997 select CPU_PM 998 help 999 The big.LITTLE "switcher" provides the core functionality to 1000 transparently handle transition between a cluster of A15's 1001 and a cluster of A7's in a big.LITTLE system. 1002 1003config BL_SWITCHER_DUMMY_IF 1004 tristate "Simple big.LITTLE switcher user interface" 1005 depends on BL_SWITCHER && DEBUG_KERNEL 1006 help 1007 This is a simple and dummy char dev interface to control 1008 the big.LITTLE switcher core code. It is meant for 1009 debugging purposes only. 1010 1011choice 1012 prompt "Memory split" 1013 depends on MMU 1014 default VMSPLIT_3G 1015 help 1016 Select the desired split between kernel and user memory. 1017 1018 If you are not absolutely sure what you are doing, leave this 1019 option alone! 1020 1021 config VMSPLIT_3G 1022 bool "3G/1G user/kernel split" 1023 config VMSPLIT_3G_OPT 1024 depends on !ARM_LPAE 1025 bool "3G/1G user/kernel split (for full 1G low memory)" 1026 config VMSPLIT_2G 1027 bool "2G/2G user/kernel split" 1028 config VMSPLIT_1G 1029 bool "1G/3G user/kernel split" 1030endchoice 1031 1032config PAGE_OFFSET 1033 hex 1034 default PHYS_OFFSET if !MMU 1035 default 0x40000000 if VMSPLIT_1G 1036 default 0x80000000 if VMSPLIT_2G 1037 default 0xB0000000 if VMSPLIT_3G_OPT 1038 default 0xC0000000 1039 1040config KASAN_SHADOW_OFFSET 1041 hex 1042 depends on KASAN 1043 default 0x1f000000 if PAGE_OFFSET=0x40000000 1044 default 0x5f000000 if PAGE_OFFSET=0x80000000 1045 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1046 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1047 default 0xffffffff 1048 1049config NR_CPUS 1050 int "Maximum number of CPUs (2-32)" 1051 range 2 16 if DEBUG_KMAP_LOCAL 1052 range 2 32 if !DEBUG_KMAP_LOCAL 1053 depends on SMP 1054 default "4" 1055 help 1056 The maximum number of CPUs that the kernel can support. 1057 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1058 debugging is enabled, which uses half of the per-CPU fixmap 1059 slots as guard regions. 1060 1061config HOTPLUG_CPU 1062 bool "Support for hot-pluggable CPUs" 1063 depends on SMP 1064 select GENERIC_IRQ_MIGRATION 1065 help 1066 Say Y here to experiment with turning CPUs off and on. CPUs 1067 can be controlled through /sys/devices/system/cpu. 1068 1069config ARM_PSCI 1070 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1071 depends on HAVE_ARM_SMCCC 1072 select ARM_PSCI_FW 1073 help 1074 Say Y here if you want Linux to communicate with system firmware 1075 implementing the PSCI specification for CPU-centric power 1076 management operations described in ARM document number ARM DEN 1077 0022A ("Power State Coordination Interface System Software on 1078 ARM processors"). 1079 1080config HZ_FIXED 1081 int 1082 default 128 if SOC_AT91RM9200 1083 default 0 1084 1085choice 1086 depends on HZ_FIXED = 0 1087 prompt "Timer frequency" 1088 1089config HZ_100 1090 bool "100 Hz" 1091 1092config HZ_200 1093 bool "200 Hz" 1094 1095config HZ_250 1096 bool "250 Hz" 1097 1098config HZ_300 1099 bool "300 Hz" 1100 1101config HZ_500 1102 bool "500 Hz" 1103 1104config HZ_1000 1105 bool "1000 Hz" 1106 1107endchoice 1108 1109config HZ 1110 int 1111 default HZ_FIXED if HZ_FIXED != 0 1112 default 100 if HZ_100 1113 default 200 if HZ_200 1114 default 250 if HZ_250 1115 default 300 if HZ_300 1116 default 500 if HZ_500 1117 default 1000 1118 1119config SCHED_HRTICK 1120 def_bool HIGH_RES_TIMERS 1121 1122config THUMB2_KERNEL 1123 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1124 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1125 default y if CPU_THUMBONLY 1126 select ARM_UNWIND 1127 help 1128 By enabling this option, the kernel will be compiled in 1129 Thumb-2 mode. 1130 1131 If unsure, say N. 1132 1133config ARM_PATCH_IDIV 1134 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1135 depends on CPU_32v7 1136 default y 1137 help 1138 The ARM compiler inserts calls to __aeabi_idiv() and 1139 __aeabi_uidiv() when it needs to perform division on signed 1140 and unsigned integers. Some v7 CPUs have support for the sdiv 1141 and udiv instructions that can be used to implement those 1142 functions. 1143 1144 Enabling this option allows the kernel to modify itself to 1145 replace the first two instructions of these library functions 1146 with the sdiv or udiv plus "bx lr" instructions when the CPU 1147 it is running on supports them. Typically this will be faster 1148 and less power intensive than running the original library 1149 code to do integer division. 1150 1151config AEABI 1152 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1153 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1154 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1155 help 1156 This option allows for the kernel to be compiled using the latest 1157 ARM ABI (aka EABI). This is only useful if you are using a user 1158 space environment that is also compiled with EABI. 1159 1160 Since there are major incompatibilities between the legacy ABI and 1161 EABI, especially with regard to structure member alignment, this 1162 option also changes the kernel syscall calling convention to 1163 disambiguate both ABIs and allow for backward compatibility support 1164 (selected with CONFIG_OABI_COMPAT). 1165 1166 To use this you need GCC version 4.0.0 or later. 1167 1168config OABI_COMPAT 1169 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1170 depends on AEABI && !THUMB2_KERNEL 1171 help 1172 This option preserves the old syscall interface along with the 1173 new (ARM EABI) one. It also provides a compatibility layer to 1174 intercept syscalls that have structure arguments which layout 1175 in memory differs between the legacy ABI and the new ARM EABI 1176 (only for non "thumb" binaries). This option adds a tiny 1177 overhead to all syscalls and produces a slightly larger kernel. 1178 1179 The seccomp filter system will not be available when this is 1180 selected, since there is no way yet to sensibly distinguish 1181 between calling conventions during filtering. 1182 1183 If you know you'll be using only pure EABI user space then you 1184 can say N here. If this option is not selected and you attempt 1185 to execute a legacy ABI binary then the result will be 1186 UNPREDICTABLE (in fact it can be predicted that it won't work 1187 at all). If in doubt say N. 1188 1189config ARCH_SELECT_MEMORY_MODEL 1190 def_bool y 1191 1192config ARCH_FLATMEM_ENABLE 1193 def_bool !(ARCH_RPC || ARCH_SA1100) 1194 1195config ARCH_SPARSEMEM_ENABLE 1196 def_bool !ARCH_FOOTBRIDGE 1197 select SPARSEMEM_STATIC if SPARSEMEM 1198 1199config HIGHMEM 1200 bool "High Memory Support" 1201 depends on MMU 1202 select KMAP_LOCAL 1203 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1204 help 1205 The address space of ARM processors is only 4 Gigabytes large 1206 and it has to accommodate user address space, kernel address 1207 space as well as some memory mapped IO. That means that, if you 1208 have a large amount of physical memory and/or IO, not all of the 1209 memory can be "permanently mapped" by the kernel. The physical 1210 memory that is not permanently mapped is called "high memory". 1211 1212 Depending on the selected kernel/user memory split, minimum 1213 vmalloc space and actual amount of RAM, you may not need this 1214 option which should result in a slightly faster kernel. 1215 1216 If unsure, say n. 1217 1218config HIGHPTE 1219 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1220 depends on HIGHMEM 1221 default y 1222 help 1223 The VM uses one page of physical memory for each page table. 1224 For systems with a lot of processes, this can use a lot of 1225 precious low memory, eventually leading to low memory being 1226 consumed by page tables. Setting this option will allow 1227 user-space 2nd level page tables to reside in high memory. 1228 1229config ARM_PAN 1230 bool "Enable privileged no-access" 1231 depends on MMU 1232 default y 1233 help 1234 Increase kernel security by ensuring that normal kernel accesses 1235 are unable to access userspace addresses. This can help prevent 1236 use-after-free bugs becoming an exploitable privilege escalation 1237 by ensuring that magic values (such as LIST_POISON) will always 1238 fault when dereferenced. 1239 1240 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1241 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1242 1243config CPU_SW_DOMAIN_PAN 1244 def_bool y 1245 depends on ARM_PAN && !ARM_LPAE 1246 help 1247 Enable use of CPU domains to implement privileged no-access. 1248 1249 CPUs with low-vector mappings use a best-efforts implementation. 1250 Their lower 1MB needs to remain accessible for the vectors, but 1251 the remainder of userspace will become appropriately inaccessible. 1252 1253config CPU_TTBR0_PAN 1254 def_bool y 1255 depends on ARM_PAN && ARM_LPAE 1256 help 1257 Enable privileged no-access by disabling TTBR0 page table walks when 1258 running in kernel mode. 1259 1260config HW_PERF_EVENTS 1261 def_bool y 1262 depends on ARM_PMU 1263 1264config ARM_MODULE_PLTS 1265 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1266 depends on MODULES 1267 select KASAN_VMALLOC if KASAN 1268 default y 1269 help 1270 Allocate PLTs when loading modules so that jumps and calls whose 1271 targets are too far away for their relative offsets to be encoded 1272 in the instructions themselves can be bounced via veneers in the 1273 module's PLT. This allows modules to be allocated in the generic 1274 vmalloc area after the dedicated module memory area has been 1275 exhausted. The modules will use slightly more memory, but after 1276 rounding up to page size, the actual memory footprint is usually 1277 the same. 1278 1279 Disabling this is usually safe for small single-platform 1280 configurations. If unsure, say y. 1281 1282config ARCH_FORCE_MAX_ORDER 1283 int "Order of maximal physically contiguous allocations" 1284 default "11" if SOC_AM33XX 1285 default "8" if SA1111 1286 default "10" 1287 help 1288 The kernel page allocator limits the size of maximal physically 1289 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1290 defines the maximal power of two of number of pages that can be 1291 allocated as a single contiguous block. This option allows 1292 overriding the default setting when ability to allocate very 1293 large blocks of physically contiguous memory is required. 1294 1295 Don't change if unsure. 1296 1297config ALIGNMENT_TRAP 1298 def_bool CPU_CP15_MMU 1299 select HAVE_PROC_CPU if PROC_FS 1300 help 1301 ARM processors cannot fetch/store information which is not 1302 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1303 address divisible by 4. On 32-bit ARM processors, these non-aligned 1304 fetch/store instructions will be emulated in software if you say 1305 here, which has a severe performance impact. This is necessary for 1306 correct operation of some network protocols. With an IP-only 1307 configuration it is safe to say N, otherwise say Y. 1308 1309config UACCESS_WITH_MEMCPY 1310 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1311 depends on MMU 1312 default y if CPU_FEROCEON 1313 help 1314 Implement faster copy_to_user and clear_user methods for CPU 1315 cores where a 8-word STM instruction give significantly higher 1316 memory write throughput than a sequence of individual 32bit stores. 1317 1318 A possible side effect is a slight increase in scheduling latency 1319 between threads sharing the same address space if they invoke 1320 such copy operations with large buffers. 1321 1322 However, if the CPU data cache is using a write-allocate mode, 1323 this option is unlikely to provide any performance gain. 1324 1325config PARAVIRT 1326 bool "Enable paravirtualization code" 1327 help 1328 This changes the kernel so it can modify itself when it is run 1329 under a hypervisor, potentially improving performance significantly 1330 over full virtualization. 1331 1332config PARAVIRT_TIME_ACCOUNTING 1333 bool "Paravirtual steal time accounting" 1334 select PARAVIRT 1335 help 1336 Select this option to enable fine granularity task steal time 1337 accounting. Time spent executing other tasks in parallel with 1338 the current vCPU is discounted from the vCPU power. To account for 1339 that, there can be a small performance impact. 1340 1341 If in doubt, say N here. 1342 1343config XEN_DOM0 1344 def_bool y 1345 depends on XEN 1346 1347config XEN 1348 bool "Xen guest support on ARM" 1349 depends on ARM && AEABI && OF 1350 depends on CPU_V7 && !CPU_V6 1351 depends on !GENERIC_ATOMIC64 1352 depends on MMU 1353 select ARCH_DMA_ADDR_T_64BIT 1354 select ARM_PSCI 1355 select SWIOTLB 1356 select SWIOTLB_XEN 1357 select PARAVIRT 1358 help 1359 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1360 1361config CC_HAVE_STACKPROTECTOR_TLS 1362 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1363 1364config STACKPROTECTOR_PER_TASK 1365 bool "Use a unique stack canary value for each task" 1366 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1367 depends on CC_HAVE_STACKPROTECTOR_TLS 1368 default y 1369 help 1370 Due to the fact that GCC uses an ordinary symbol reference from 1371 which to load the value of the stack canary, this value can only 1372 change at reboot time on SMP systems, and all tasks running in the 1373 kernel's address space are forced to use the same canary value for 1374 the entire duration that the system is up. 1375 1376 Enable this option to switch to a different method that uses a 1377 different canary value for each task. 1378 1379endmenu 1380 1381menu "Boot options" 1382 1383config USE_OF 1384 bool "Flattened Device Tree support" 1385 select IRQ_DOMAIN 1386 select OF 1387 help 1388 Include support for flattened device tree machine descriptions. 1389 1390config ARCH_WANT_FLAT_DTB_INSTALL 1391 def_bool y 1392 1393config ATAGS 1394 bool "Support for the traditional ATAGS boot data passing" 1395 default y 1396 help 1397 This is the traditional way of passing data to the kernel at boot 1398 time. If you are solely relying on the flattened device tree (or 1399 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1400 to remove ATAGS support from your kernel binary. 1401 1402config DEPRECATED_PARAM_STRUCT 1403 bool "Provide old way to pass kernel parameters" 1404 depends on ATAGS 1405 help 1406 This was deprecated in 2001 and announced to live on for 5 years. 1407 Some old boot loaders still use this way. 1408 1409# Compressed boot loader in ROM. Yes, we really want to ask about 1410# TEXT and BSS so we preserve their values in the config files. 1411config ZBOOT_ROM_TEXT 1412 hex "Compressed ROM boot loader base address" 1413 default 0x0 1414 help 1415 The physical address at which the ROM-able zImage is to be 1416 placed in the target. Platforms which normally make use of 1417 ROM-able zImage formats normally set this to a suitable 1418 value in their defconfig file. 1419 1420 If ZBOOT_ROM is not enabled, this has no effect. 1421 1422config ZBOOT_ROM_BSS 1423 hex "Compressed ROM boot loader BSS address" 1424 default 0x0 1425 help 1426 The base address of an area of read/write memory in the target 1427 for the ROM-able zImage which must be available while the 1428 decompressor is running. It must be large enough to hold the 1429 entire decompressed kernel plus an additional 128 KiB. 1430 Platforms which normally make use of ROM-able zImage formats 1431 normally set this to a suitable value in their defconfig file. 1432 1433 If ZBOOT_ROM is not enabled, this has no effect. 1434 1435config ZBOOT_ROM 1436 bool "Compressed boot loader in ROM/flash" 1437 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1438 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1439 help 1440 Say Y here if you intend to execute your compressed kernel image 1441 (zImage) directly from ROM or flash. If unsure, say N. 1442 1443config ARM_APPENDED_DTB 1444 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1445 depends on OF 1446 help 1447 With this option, the boot code will look for a device tree binary 1448 (DTB) appended to zImage 1449 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1450 1451 This is meant as a backward compatibility convenience for those 1452 systems with a bootloader that can't be upgraded to accommodate 1453 the documented boot protocol using a device tree. 1454 1455 Beware that there is very little in terms of protection against 1456 this option being confused by leftover garbage in memory that might 1457 look like a DTB header after a reboot if no actual DTB is appended 1458 to zImage. Do not leave this option active in a production kernel 1459 if you don't intend to always append a DTB. Proper passing of the 1460 location into r2 of a bootloader provided DTB is always preferable 1461 to this option. 1462 1463config ARM_ATAG_DTB_COMPAT 1464 bool "Supplement the appended DTB with traditional ATAG information" 1465 depends on ARM_APPENDED_DTB 1466 help 1467 Some old bootloaders can't be updated to a DTB capable one, yet 1468 they provide ATAGs with memory configuration, the ramdisk address, 1469 the kernel cmdline string, etc. Such information is dynamically 1470 provided by the bootloader and can't always be stored in a static 1471 DTB. To allow a device tree enabled kernel to be used with such 1472 bootloaders, this option allows zImage to extract the information 1473 from the ATAG list and store it at run time into the appended DTB. 1474 1475choice 1476 prompt "Kernel command line type" 1477 depends on ARM_ATAG_DTB_COMPAT 1478 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1479 1480config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1481 bool "Use bootloader kernel arguments if available" 1482 help 1483 Uses the command-line options passed by the boot loader instead of 1484 the device tree bootargs property. If the boot loader doesn't provide 1485 any, the device tree bootargs property will be used. 1486 1487config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1488 bool "Extend with bootloader kernel arguments" 1489 help 1490 The command-line arguments provided by the boot loader will be 1491 appended to the the device tree bootargs property. 1492 1493endchoice 1494 1495config CMDLINE 1496 string "Default kernel command string" 1497 default "" 1498 help 1499 On some architectures (e.g. CATS), there is currently no way 1500 for the boot loader to pass arguments to the kernel. For these 1501 architectures, you should supply some command-line options at build 1502 time by entering them here. As a minimum, you should specify the 1503 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1504 1505choice 1506 prompt "Kernel command line type" 1507 depends on CMDLINE != "" 1508 default CMDLINE_FROM_BOOTLOADER 1509 1510config CMDLINE_FROM_BOOTLOADER 1511 bool "Use bootloader kernel arguments if available" 1512 help 1513 Uses the command-line options passed by the boot loader. If 1514 the boot loader doesn't provide any, the default kernel command 1515 string provided in CMDLINE will be used. 1516 1517config CMDLINE_EXTEND 1518 bool "Extend bootloader kernel arguments" 1519 help 1520 The command-line arguments provided by the boot loader will be 1521 appended to the default kernel command string. 1522 1523config CMDLINE_FORCE 1524 bool "Always use the default kernel command string" 1525 help 1526 Always use the default kernel command string, even if the boot 1527 loader passes other arguments to the kernel. 1528 This is useful if you cannot or don't want to change the 1529 command-line options your boot loader passes to the kernel. 1530endchoice 1531 1532config XIP_KERNEL 1533 bool "Kernel Execute-In-Place from ROM" 1534 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1535 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1536 help 1537 Execute-In-Place allows the kernel to run from non-volatile storage 1538 directly addressable by the CPU, such as NOR flash. This saves RAM 1539 space since the text section of the kernel is not loaded from flash 1540 to RAM. Read-write sections, such as the data section and stack, 1541 are still copied to RAM. The XIP kernel is not compressed since 1542 it has to run directly from flash, so it will take more space to 1543 store it. The flash address used to link the kernel object files, 1544 and for storing it, is configuration dependent. Therefore, if you 1545 say Y here, you must know the proper physical address where to 1546 store the kernel image depending on your own flash memory usage. 1547 1548 Also note that the make target becomes "make xipImage" rather than 1549 "make zImage" or "make Image". The final kernel binary to put in 1550 ROM memory will be arch/arm/boot/xipImage. 1551 1552 If unsure, say N. 1553 1554config XIP_PHYS_ADDR 1555 hex "XIP Kernel Physical Location" 1556 depends on XIP_KERNEL 1557 default "0x00080000" 1558 help 1559 This is the physical address in your flash memory the kernel will 1560 be linked for and stored to. This address is dependent on your 1561 own flash usage. 1562 1563config XIP_DEFLATED_DATA 1564 bool "Store kernel .data section compressed in ROM" 1565 depends on XIP_KERNEL 1566 select ZLIB_INFLATE 1567 help 1568 Before the kernel is actually executed, its .data section has to be 1569 copied to RAM from ROM. This option allows for storing that data 1570 in compressed form and decompressed to RAM rather than merely being 1571 copied, saving some precious ROM space. A possible drawback is a 1572 slightly longer boot delay. 1573 1574config ARCH_SUPPORTS_KEXEC 1575 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1576 1577config ATAGS_PROC 1578 bool "Export atags in procfs" 1579 depends on ATAGS && KEXEC 1580 default y 1581 help 1582 Should the atags used to boot the kernel be exported in an "atags" 1583 file in procfs. Useful with kexec. 1584 1585config ARCH_SUPPORTS_CRASH_DUMP 1586 def_bool y 1587 1588config ARCH_DEFAULT_CRASH_DUMP 1589 def_bool y 1590 1591config AUTO_ZRELADDR 1592 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1593 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1594 help 1595 ZRELADDR is the physical address where the decompressed kernel 1596 image will be placed. If AUTO_ZRELADDR is selected, the address 1597 will be determined at run-time, either by masking the current IP 1598 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1599 This assumes the zImage being placed in the first 128MB from 1600 start of memory. 1601 1602config EFI_STUB 1603 bool 1604 1605config EFI 1606 bool "UEFI runtime support" 1607 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1608 select UCS2_STRING 1609 select EFI_PARAMS_FROM_FDT 1610 select EFI_STUB 1611 select EFI_GENERIC_STUB 1612 select EFI_RUNTIME_WRAPPERS 1613 help 1614 This option provides support for runtime services provided 1615 by UEFI firmware (such as non-volatile variables, realtime 1616 clock, and platform reset). A UEFI stub is also provided to 1617 allow the kernel to be booted as an EFI application. This 1618 is only useful for kernels that may run on systems that have 1619 UEFI firmware. 1620 1621config DMI 1622 bool "Enable support for SMBIOS (DMI) tables" 1623 depends on EFI 1624 default y 1625 help 1626 This enables SMBIOS/DMI feature for systems. 1627 1628 This option is only useful on systems that have UEFI firmware. 1629 However, even with this option, the resultant kernel should 1630 continue to boot on existing non-UEFI platforms. 1631 1632 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1633 i.e., the the practice of identifying the platform via DMI to 1634 decide whether certain workarounds for buggy hardware and/or 1635 firmware need to be enabled. This would require the DMI subsystem 1636 to be enabled much earlier than we do on ARM, which is non-trivial. 1637 1638endmenu 1639 1640menu "CPU Power Management" 1641 1642source "drivers/cpufreq/Kconfig" 1643 1644source "drivers/cpuidle/Kconfig" 1645 1646endmenu 1647 1648menu "Floating point emulation" 1649 1650comment "At least one emulation must be selected" 1651 1652config FPE_NWFPE 1653 bool "NWFPE math emulation" 1654 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1655 help 1656 Say Y to include the NWFPE floating point emulator in the kernel. 1657 This is necessary to run most binaries. Linux does not currently 1658 support floating point hardware so you need to say Y here even if 1659 your machine has an FPA or floating point co-processor podule. 1660 1661 You may say N here if you are going to load the Acorn FPEmulator 1662 early in the bootup. 1663 1664config FPE_NWFPE_XP 1665 bool "Support extended precision" 1666 depends on FPE_NWFPE 1667 help 1668 Say Y to include 80-bit support in the kernel floating-point 1669 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1670 Note that gcc does not generate 80-bit operations by default, 1671 so in most cases this option only enlarges the size of the 1672 floating point emulator without any good reason. 1673 1674 You almost surely want to say N here. 1675 1676config FPE_FASTFPE 1677 bool "FastFPE math emulation (EXPERIMENTAL)" 1678 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1679 help 1680 Say Y here to include the FAST floating point emulator in the kernel. 1681 This is an experimental much faster emulator which now also has full 1682 precision for the mantissa. It does not support any exceptions. 1683 It is very simple, and approximately 3-6 times faster than NWFPE. 1684 1685 It should be sufficient for most programs. It may be not suitable 1686 for scientific calculations, but you have to check this for yourself. 1687 If you do not feel you need a faster FP emulation you should better 1688 choose NWFPE. 1689 1690config VFP 1691 bool "VFP-format floating point maths" 1692 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1693 help 1694 Say Y to include VFP support code in the kernel. This is needed 1695 if your hardware includes a VFP unit. 1696 1697 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1698 release notes and additional status information. 1699 1700 Say N if your target does not have VFP hardware. 1701 1702config VFPv3 1703 bool 1704 depends on VFP 1705 default y if CPU_V7 1706 1707config NEON 1708 bool "Advanced SIMD (NEON) Extension support" 1709 depends on VFPv3 && CPU_V7 1710 help 1711 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1712 Extension. 1713 1714config KERNEL_MODE_NEON 1715 bool "Support for NEON in kernel mode" 1716 depends on NEON && AEABI 1717 help 1718 Say Y to include support for NEON in kernel mode. 1719 1720endmenu 1721 1722menu "Power management options" 1723 1724source "kernel/power/Kconfig" 1725 1726config ARCH_SUSPEND_POSSIBLE 1727 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1728 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1729 def_bool y 1730 1731config ARM_CPU_SUSPEND 1732 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1733 depends on ARCH_SUSPEND_POSSIBLE 1734 1735config ARCH_HIBERNATION_POSSIBLE 1736 bool 1737 depends on MMU 1738 default y if ARCH_SUSPEND_POSSIBLE 1739 1740endmenu 1741