1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CC_CAN_LINK 10 select ARCH_HAS_CPU_CACHE_ALIASING 11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_HAS_DEBUG_VIRTUAL if MMU 14 select ARCH_HAS_DMA_ALLOC if MMU 15 select ARCH_HAS_DMA_OPS 16 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 17 select ARCH_HAS_ELF_RANDOMIZE 18 select ARCH_HAS_FORTIFY_SOURCE 19 select ARCH_HAS_KEEPINITRD 20 select ARCH_HAS_KCOV 21 select ARCH_HAS_MEMBARRIER_SYNC_CORE 22 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 23 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 24 select ARCH_HAS_SETUP_DMA_OPS 25 select ARCH_HAS_SET_MEMORY 26 select ARCH_STACKWALK 27 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 28 select ARCH_HAS_STRICT_MODULE_RWX if MMU 29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 30 select ARCH_HAS_SYNC_DMA_FOR_CPU 31 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 33 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_KEEP_MEMBLOCK 36 select ARCH_HAS_UBSAN 37 select ARCH_MIGHT_HAVE_PC_PARPORT 38 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 39 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 40 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 41 select ARCH_SUPPORTS_ATOMIC_RMW 42 select ARCH_SUPPORTS_CFI 43 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 44 select ARCH_SUPPORTS_PER_VMA_LOCK 45 select ARCH_SUPPORTS_RT 46 select ARCH_USE_BUILTIN_BSWAP 47 select ARCH_USE_CMPXCHG_LOCKREF 48 select ARCH_USE_MEMTEST 49 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 50 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 51 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 52 select ARCH_WANT_GENERAL_HUGETLB 53 select ARCH_WANT_IPC_PARSE_VERSION 54 select ARCH_WANT_LD_ORPHAN_WARN 55 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 56 select BUILDTIME_TABLE_SORT if MMU 57 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 58 select CLONE_BACKWARDS 59 select CPU_PM if SUSPEND || CPU_IDLE 60 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 61 select DMA_DECLARE_COHERENT 62 select DMA_GLOBAL_POOL if !MMU 63 select DMA_NONCOHERENT_MMAP if MMU 64 select EDAC_SUPPORT 65 select EDAC_ATOMIC_SCRUB 66 select GENERIC_ALLOCATOR 67 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 68 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 69 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 70 select GENERIC_IRQ_IPI if SMP 71 select GENERIC_CPU_AUTOPROBE 72 select GENERIC_CPU_DEVICES 73 select GENERIC_EARLY_IOREMAP 74 select GENERIC_IDLE_POLL_SETUP 75 select GENERIC_IRQ_MULTI_HANDLER 76 select GENERIC_IRQ_PROBE 77 select GENERIC_IRQ_SHOW 78 select GENERIC_IRQ_SHOW_LEVEL 79 select GENERIC_LIB_DEVMEM_IS_ALLOWED 80 select GENERIC_PCI_IOMAP 81 select GENERIC_SCHED_CLOCK 82 select GENERIC_SMP_IDLE_THREAD 83 select HARDIRQS_SW_RESEND 84 select HAS_IOPORT 85 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 86 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 && BITREVERSE 87 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP) 88 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 89 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 90 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 91 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 92 select HAVE_ARCH_KSTACK_ERASE 93 select HAVE_ARCH_MMAP_RND_BITS if MMU 94 select HAVE_ARCH_PFN_VALID 95 select HAVE_ARCH_SECCOMP 96 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 97 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 98 select HAVE_ARCH_TRACEHOOK 99 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 100 select HAVE_ARM_SMCCC if CPU_V7 101 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 102 select HAVE_CONTEXT_TRACKING_USER 103 select HAVE_C_RECORDMCOUNT 104 select HAVE_BUILDTIME_MCOUNT_SORT 105 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 106 select HAVE_DMA_CONTIGUOUS if MMU 107 select HAVE_EXTRA_IPI_TRACEPOINTS 108 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 109 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 110 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 111 select HAVE_EXIT_THREAD 112 select HAVE_GUP_FAST if ARM_LPAE 113 select HAVE_FUNCTION_ERROR_INJECTION 114 select HAVE_FUNCTION_GRAPH_TRACER 115 select HAVE_FUNCTION_GRAPH_FREGS 116 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 117 select HAVE_GCC_PLUGINS 118 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 119 select HAVE_IRQ_TIME_ACCOUNTING 120 select HAVE_KERNEL_GZIP 121 select HAVE_KERNEL_LZ4 122 select HAVE_KERNEL_LZMA 123 select HAVE_KERNEL_LZO 124 select HAVE_KERNEL_XZ 125 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 126 select HAVE_KRETPROBES if HAVE_KPROBES 127 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 128 select HAVE_MOD_ARCH_SPECIFIC 129 select HAVE_NMI 130 select HAVE_OPTPROBES if !THUMB2_KERNEL 131 select HAVE_PAGE_SIZE_4KB 132 select HAVE_PCI if MMU 133 select HAVE_PERF_EVENTS 134 select HAVE_PERF_REGS 135 select HAVE_PERF_USER_STACK_DUMP 136 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 137 select HAVE_REGS_AND_STACK_ACCESS_API 138 select HAVE_RSEQ 139 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN 140 select HAVE_STACKPROTECTOR 141 select HAVE_SYSCALL_TRACEPOINTS 142 select HAVE_UID16 143 select HAVE_VIRT_CPU_ACCOUNTING_GEN 144 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 145 select IRQ_FORCED_THREADING 146 select LOCK_MM_AND_FIND_VMA 147 select MODULES_USE_ELF_REL 148 select NEED_DMA_MAP_STATE 149 select OF_EARLY_FLATTREE if OF 150 select OLD_SIGACTION 151 select OLD_SIGSUSPEND3 152 select PCI_DOMAINS_GENERIC if PCI 153 select PCI_SYSCALL if PCI 154 select PERF_USE_VMALLOC 155 select RTC_LIB 156 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 157 select SYS_SUPPORTS_APM_EMULATION 158 select THREAD_INFO_IN_TASK 159 select TIMER_OF if OF 160 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 161 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 162 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 163 # Above selects are sorted alphabetically; please add new ones 164 # according to that. Thanks. 165 help 166 The ARM series is a line of low-power-consumption RISC chip designs 167 licensed by ARM Ltd and targeted at embedded applications and 168 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 169 manufactured, but legacy ARM-based PC hardware remains popular in 170 Europe. There is an ARM Linux project with a web page at 171 <http://www.arm.linux.org.uk/>. 172 173config ARM_HAS_GROUP_RELOCS 174 def_bool !COMPILE_TEST 175 help 176 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 177 relocations. The combined range is -/+ 256 MiB, which is usually 178 sufficient, but not for allyesconfig, so we disable this feature 179 when doing compile testing. 180 181config ARM_DMA_USE_IOMMU 182 bool 183 select NEED_SG_DMA_LENGTH 184 185if ARM_DMA_USE_IOMMU 186 187config ARM_DMA_IOMMU_ALIGNMENT 188 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 189 range 4 9 190 default 8 191 help 192 DMA mapping framework by default aligns all buffers to the smallest 193 PAGE_SIZE order which is greater than or equal to the requested buffer 194 size. This works well for buffers up to a few hundreds kilobytes, but 195 for larger buffers it just a waste of address space. Drivers which has 196 relatively small addressing window (like 64Mib) might run out of 197 virtual space with just a few allocations. 198 199 With this parameter you can specify the maximum PAGE_SIZE order for 200 DMA IOMMU buffers. Larger buffers will be aligned only to this 201 specified order. The order is expressed as a power of two multiplied 202 by the PAGE_SIZE. 203 204endif 205 206config SYS_SUPPORTS_APM_EMULATION 207 bool 208 209config HAVE_TCM 210 bool 211 select GENERIC_ALLOCATOR 212 213config HAVE_PROC_CPU 214 bool 215 216config NO_IOPORT_MAP 217 bool 218 219config SBUS 220 bool 221 222config STACKTRACE_SUPPORT 223 bool 224 default y 225 226config LOCKDEP_SUPPORT 227 bool 228 default y 229 230config ARCH_HAS_ILOG2_U32 231 bool 232 233config ARCH_HAS_ILOG2_U64 234 bool 235 236config ARCH_HAS_BANDGAP 237 bool 238 239config FIX_EARLYCON_MEM 240 def_bool y if MMU 241 242config GENERIC_HWEIGHT 243 bool 244 default y 245 246config GENERIC_CALIBRATE_DELAY 247 bool 248 default y 249 250config ARCH_MAY_HAVE_PC_FDC 251 bool 252 253config ARCH_SUPPORTS_UPROBES 254 def_bool y 255 256config GENERIC_ISA_DMA 257 bool 258 259config FIQ 260 bool 261 262config ARCH_MTD_XIP 263 bool 264 265config ARM_PATCH_PHYS_VIRT 266 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 267 default y 268 depends on MMU 269 help 270 Patch phys-to-virt and virt-to-phys translation functions at 271 boot and module load time according to the position of the 272 kernel in system memory. 273 274 This can only be used with non-XIP MMU kernels where the base 275 of physical memory is at a 2 MiB boundary. 276 277 Only disable this option if you know that you do not require 278 this feature (eg, building a kernel for a single machine) and 279 you need to shrink the kernel to the minimal size. 280 281config NEED_MACH_IO_H 282 bool 283 help 284 Select this when mach/io.h is required to provide special 285 definitions for this platform. The need for mach/io.h should 286 be avoided when possible. 287 288config NEED_MACH_MEMORY_H 289 bool 290 help 291 Select this when mach/memory.h is required to provide special 292 definitions for this platform. The need for mach/memory.h should 293 be avoided when possible. 294 295config PHYS_OFFSET 296 hex "Physical address of main memory" if MMU 297 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 298 default DRAM_BASE if !MMU 299 default 0x00000000 if ARCH_FOOTBRIDGE 300 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 301 default 0xa0000000 if ARCH_PXA 302 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 303 default 0 304 help 305 Please provide the physical address corresponding to the 306 location of main memory in your system. 307 308config GENERIC_BUG 309 def_bool y 310 depends on BUG 311 312config PGTABLE_LEVELS 313 int 314 default 3 if ARM_LPAE 315 default 2 316 317menu "System Type" 318 319config MMU 320 bool "MMU-based Paged Memory Management Support" 321 default y 322 help 323 Select if you want MMU-based virtualised addressing space 324 support by paged memory management. If unsure, say 'Y'. 325 326config ARM_SINGLE_ARMV7M 327 def_bool !MMU 328 select ARM_NVIC 329 select CPU_V7M 330 select NO_IOPORT_MAP 331 332config ARCH_MMAP_RND_BITS_MIN 333 default 8 334 335config ARCH_MMAP_RND_BITS_MAX 336 default 14 if PAGE_OFFSET=0x40000000 337 default 15 if PAGE_OFFSET=0x80000000 338 default 16 339 340config ARCH_MULTIPLATFORM 341 bool "Require kernel to be portable to multiple machines" if EXPERT 342 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 343 default y 344 help 345 In general, all Arm machines can be supported in a single 346 kernel image, covering either Armv4/v5 or Armv6/v7. 347 348 However, some configuration options require hardcoding machine 349 specific physical addresses or enable errata workarounds that may 350 break other machines. 351 352 Selecting N here allows using those options, including 353 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 354 355source "arch/arm/Kconfig.platforms" 356 357# 358# This is sorted alphabetically by mach-* pathname. However, plat-* 359# Kconfigs may be included either alphabetically (according to the 360# plat- suffix) or along side the corresponding mach-* source. 361# 362source "arch/arm/mach-actions/Kconfig" 363 364source "arch/arm/mach-alpine/Kconfig" 365 366source "arch/arm/mach-artpec/Kconfig" 367 368source "arch/arm/mach-aspeed/Kconfig" 369 370source "arch/arm/mach-at91/Kconfig" 371 372source "arch/arm/mach-axxia/Kconfig" 373 374source "arch/arm/mach-bcm/Kconfig" 375 376source "arch/arm/mach-berlin/Kconfig" 377 378source "arch/arm/mach-clps711x/Kconfig" 379 380source "arch/arm/mach-davinci/Kconfig" 381 382source "arch/arm/mach-digicolor/Kconfig" 383 384source "arch/arm/mach-dove/Kconfig" 385 386source "arch/arm/mach-ep93xx/Kconfig" 387 388source "arch/arm/mach-exynos/Kconfig" 389 390source "arch/arm/mach-footbridge/Kconfig" 391 392source "arch/arm/mach-gemini/Kconfig" 393 394source "arch/arm/mach-highbank/Kconfig" 395 396source "arch/arm/mach-hisi/Kconfig" 397 398source "arch/arm/mach-imx/Kconfig" 399 400source "arch/arm/mach-ixp4xx/Kconfig" 401 402source "arch/arm/mach-keystone/Kconfig" 403 404source "arch/arm/mach-lpc32xx/Kconfig" 405 406source "arch/arm/mach-mediatek/Kconfig" 407 408source "arch/arm/mach-meson/Kconfig" 409 410source "arch/arm/mach-milbeaut/Kconfig" 411 412source "arch/arm/mach-mmp/Kconfig" 413 414source "arch/arm/mach-mstar/Kconfig" 415 416source "arch/arm/mach-mv78xx0/Kconfig" 417 418source "arch/arm/mach-mvebu/Kconfig" 419 420source "arch/arm/mach-mxs/Kconfig" 421 422source "arch/arm/mach-nomadik/Kconfig" 423 424source "arch/arm/mach-npcm/Kconfig" 425 426source "arch/arm/mach-omap1/Kconfig" 427 428source "arch/arm/mach-omap2/Kconfig" 429 430source "arch/arm/mach-orion5x/Kconfig" 431 432source "arch/arm/mach-pxa/Kconfig" 433 434source "arch/arm/mach-qcom/Kconfig" 435 436source "arch/arm/mach-realtek/Kconfig" 437 438source "arch/arm/mach-rpc/Kconfig" 439 440source "arch/arm/mach-rockchip/Kconfig" 441 442source "arch/arm/mach-s3c/Kconfig" 443 444source "arch/arm/mach-s5pv210/Kconfig" 445 446source "arch/arm/mach-sa1100/Kconfig" 447 448source "arch/arm/mach-shmobile/Kconfig" 449 450source "arch/arm/mach-socfpga/Kconfig" 451 452source "arch/arm/mach-spear/Kconfig" 453 454source "arch/arm/mach-sti/Kconfig" 455 456source "arch/arm/mach-stm32/Kconfig" 457 458source "arch/arm/mach-sunxi/Kconfig" 459 460source "arch/arm/mach-tegra/Kconfig" 461 462source "arch/arm/mach-ux500/Kconfig" 463 464source "arch/arm/mach-versatile/Kconfig" 465 466source "arch/arm/mach-vt8500/Kconfig" 467 468source "arch/arm/mach-zte/Kconfig" 469 470source "arch/arm/mach-zynq/Kconfig" 471 472# ARMv7-M architecture 473config ARCH_LPC18XX 474 bool "NXP LPC18xx/LPC43xx" 475 depends on ARM_SINGLE_ARMV7M 476 select ARCH_HAS_RESET_CONTROLLER 477 select ARM_AMBA 478 select CLKSRC_LPC32XX 479 select PINCTRL 480 help 481 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 482 high performance microcontrollers. 483 484config ARCH_MPS2 485 bool "ARM MPS2 platform" 486 depends on ARM_SINGLE_ARMV7M 487 select ARM_AMBA 488 select CLKSRC_MPS2 489 help 490 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 491 with a range of available cores like Cortex-M3/M4/M7. 492 493 Please, note that depends which Application Note is used memory map 494 for the platform may vary, so adjustment of RAM base might be needed. 495 496# Definitions to make life easier 497config ARCH_ACORN 498 bool 499 500config PLAT_ORION 501 bool 502 select CLKSRC_MMIO 503 select GENERIC_IRQ_CHIP 504 select IRQ_DOMAIN 505 506config PLAT_ORION_LEGACY 507 bool 508 select PLAT_ORION 509 510config PLAT_VERSATILE 511 bool 512 513source "arch/arm/mm/Kconfig" 514 515config IWMMXT 516 bool "Enable iWMMXt support (DEPRECATED)" 517 depends on PXA27x || PXA3xx || ARCH_MMP 518 help 519 Enable support for iWMMXt context switching at run time if 520 running on a CPU that supports it. 521 522 Machines that actually support this feature are very rare, 523 and support is deprecated in new gcc-14. While there were a 524 few applications that used this in the past, none are known 525 to still do so. 526 527 If you use this, please send a patch to remove the 528 deprecation, otherwise this will be removed in early 529 2027. 530 531if !MMU 532source "arch/arm/Kconfig-nommu" 533endif 534 535config PJ4B_ERRATA_4742 536 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 537 depends on CPU_PJ4B && MACH_ARMADA_370 538 default y 539 help 540 When coming out of either a Wait for Interrupt (WFI) or a Wait for 541 Event (WFE) IDLE states, a specific timing sensitivity exists between 542 the retiring WFI/WFE instructions and the newly issued subsequent 543 instructions. This sensitivity can result in a CPU hang scenario. 544 Workaround: 545 The software must insert either a Data Synchronization Barrier (DSB) 546 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 547 instruction 548 549config ARM_ERRATA_326103 550 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 551 depends on CPU_V6 552 help 553 Executing a SWP instruction to read-only memory does not set bit 11 554 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 555 treat the access as a read, preventing a COW from occurring and 556 causing the faulting task to livelock. 557 558config ARM_ERRATA_411920 559 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 560 depends on CPU_V6 || CPU_V6K 561 help 562 Invalidation of the Instruction Cache operation can 563 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 564 It does not affect the MPCore. This option enables the ARM Ltd. 565 recommended workaround. 566 567config ARM_ERRATA_430973 568 bool "ARM errata: Stale prediction on replaced interworking branch" 569 depends on CPU_V7 570 help 571 This option enables the workaround for the 430973 Cortex-A8 572 r1p* erratum. If a code sequence containing an ARM/Thumb 573 interworking branch is replaced with another code sequence at the 574 same virtual address, whether due to self-modifying code or virtual 575 to physical address re-mapping, Cortex-A8 does not recover from the 576 stale interworking branch prediction. This results in Cortex-A8 577 executing the new code sequence in the incorrect ARM or Thumb state. 578 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 579 and also flushes the branch target cache at every context switch. 580 Note that setting specific bits in the ACTLR register may not be 581 available in non-secure mode. 582 583config ARM_ERRATA_458693 584 bool "ARM errata: Processor deadlock when a false hazard is created" 585 depends on CPU_V7 586 depends on !ARCH_MULTIPLATFORM 587 help 588 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 589 erratum. For very specific sequences of memory operations, it is 590 possible for a hazard condition intended for a cache line to instead 591 be incorrectly associated with a different cache line. This false 592 hazard might then cause a processor deadlock. The workaround enables 593 the L1 caching of the NEON accesses and disables the PLD instruction 594 in the ACTLR register. Note that setting specific bits in the ACTLR 595 register may not be available in non-secure mode and thus is not 596 available on a multiplatform kernel. This should be applied by the 597 bootloader instead. 598 599config ARM_ERRATA_460075 600 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 601 depends on CPU_V7 602 depends on !ARCH_MULTIPLATFORM 603 help 604 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 605 erratum. Any asynchronous access to the L2 cache may encounter a 606 situation in which recent store transactions to the L2 cache are lost 607 and overwritten with stale memory contents from external memory. The 608 workaround disables the write-allocate mode for the L2 cache via the 609 ACTLR register. Note that setting specific bits in the ACTLR register 610 may not be available in non-secure mode and thus is not available on 611 a multiplatform kernel. This should be applied by the bootloader 612 instead. 613 614config ARM_ERRATA_742230 615 bool "ARM errata: DMB operation may be faulty" 616 depends on CPU_V7 && SMP 617 depends on !ARCH_MULTIPLATFORM 618 help 619 This option enables the workaround for the 742230 Cortex-A9 620 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 621 between two write operations may not ensure the correct visibility 622 ordering of the two writes. This workaround sets a specific bit in 623 the diagnostic register of the Cortex-A9 which causes the DMB 624 instruction to behave as a DSB, ensuring the correct behaviour of 625 the two writes. Note that setting specific bits in the diagnostics 626 register may not be available in non-secure mode and thus is not 627 available on a multiplatform kernel. This should be applied by the 628 bootloader instead. 629 630config ARM_ERRATA_742231 631 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 632 depends on CPU_V7 && SMP 633 depends on !ARCH_MULTIPLATFORM 634 help 635 This option enables the workaround for the 742231 Cortex-A9 636 (r2p0..r2p2) erratum. Under certain conditions, specific to the 637 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 638 accessing some data located in the same cache line, may get corrupted 639 data due to bad handling of the address hazard when the line gets 640 replaced from one of the CPUs at the same time as another CPU is 641 accessing it. This workaround sets specific bits in the diagnostic 642 register of the Cortex-A9 which reduces the linefill issuing 643 capabilities of the processor. Note that setting specific bits in the 644 diagnostics register may not be available in non-secure mode and thus 645 is not available on a multiplatform kernel. This should be applied by 646 the bootloader instead. 647 648config ARM_ERRATA_643719 649 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 650 depends on CPU_V7 && SMP 651 default y 652 help 653 This option enables the workaround for the 643719 Cortex-A9 (prior to 654 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 655 register returns zero when it should return one. The workaround 656 corrects this value, ensuring cache maintenance operations which use 657 it behave as intended and avoiding data corruption. 658 659config ARM_ERRATA_720789 660 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 661 depends on CPU_V7 662 help 663 This option enables the workaround for the 720789 Cortex-A9 (prior to 664 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 665 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 666 As a consequence of this erratum, some TLB entries which should be 667 invalidated are not, resulting in an incoherency in the system page 668 tables. The workaround changes the TLB flushing routines to invalidate 669 entries regardless of the ASID. 670 671config ARM_ERRATA_743622 672 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 673 depends on CPU_V7 674 depends on !ARCH_MULTIPLATFORM 675 help 676 This option enables the workaround for the 743622 Cortex-A9 677 (r2p*) erratum. Under very rare conditions, a faulty 678 optimisation in the Cortex-A9 Store Buffer may lead to data 679 corruption. This workaround sets a specific bit in the diagnostic 680 register of the Cortex-A9 which disables the Store Buffer 681 optimisation, preventing the defect from occurring. This has no 682 visible impact on the overall performance or power consumption of the 683 processor. Note that setting specific bits in the diagnostics register 684 may not be available in non-secure mode and thus is not available on a 685 multiplatform kernel. This should be applied by the bootloader instead. 686 687config ARM_ERRATA_751472 688 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 689 depends on CPU_V7 690 depends on !ARCH_MULTIPLATFORM 691 help 692 This option enables the workaround for the 751472 Cortex-A9 (prior 693 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 694 completion of a following broadcasted operation if the second 695 operation is received by a CPU before the ICIALLUIS has completed, 696 potentially leading to corrupted entries in the cache or TLB. 697 Note that setting specific bits in the diagnostics register may 698 not be available in non-secure mode and thus is not available on 699 a multiplatform kernel. This should be applied by the bootloader 700 instead. 701 702config ARM_ERRATA_754322 703 bool "ARM errata: possible faulty MMU translations following an ASID switch" 704 depends on CPU_V7 705 help 706 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 707 r3p*) erratum. A speculative memory access may cause a page table walk 708 which starts prior to an ASID switch but completes afterwards. This 709 can populate the micro-TLB with a stale entry which may be hit with 710 the new ASID. This workaround places two dsb instructions in the mm 711 switching code so that no page table walks can cross the ASID switch. 712 713config ARM_ERRATA_754327 714 bool "ARM errata: no automatic Store Buffer drain" 715 depends on CPU_V7 && SMP 716 help 717 This option enables the workaround for the 754327 Cortex-A9 (prior to 718 r2p0) erratum. The Store Buffer does not have any automatic draining 719 mechanism and therefore a livelock may occur if an external agent 720 continuously polls a memory location waiting to observe an update. 721 This workaround defines cpu_relax() as smp_mb(), preventing correctly 722 written polling loops from denying visibility of updates to memory. 723 724config ARM_ERRATA_364296 725 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 726 depends on CPU_V6 727 help 728 This options enables the workaround for the 364296 ARM1136 729 r0p2 erratum (possible cache data corruption with 730 hit-under-miss enabled). It sets the undocumented bit 31 in 731 the auxiliary control register and the FI bit in the control 732 register, thus disabling hit-under-miss without putting the 733 processor into full low interrupt latency mode. ARM11MPCore 734 is not affected. 735 736config ARM_ERRATA_764369 737 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 738 depends on CPU_V7 && SMP 739 help 740 This option enables the workaround for erratum 764369 741 affecting Cortex-A9 MPCore with two or more processors (all 742 current revisions). Under certain timing circumstances, a data 743 cache line maintenance operation by MVA targeting an Inner 744 Shareable memory region may fail to proceed up to either the 745 Point of Coherency or to the Point of Unification of the 746 system. This workaround adds a DSB instruction before the 747 relevant cache maintenance functions and sets a specific bit 748 in the diagnostic control register of the SCU. 749 750config ARM_ERRATA_764319 751 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 752 depends on CPU_V7 753 help 754 This option enables the workaround for the 764319 Cortex-A9 erratum. 755 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 756 unexpected Undefined Instruction exception when the DBGSWENABLE 757 external pin is set to 0, even when the CP14 accesses are performed 758 from a privileged mode. This work around catches the exception in a 759 way the kernel does not stop execution. 760 761config ARM_ERRATA_775420 762 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 763 depends on CPU_V7 764 help 765 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 766 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 767 operation aborts with MMU exception, it might cause the processor 768 to deadlock. This workaround puts DSB before executing ISB if 769 an abort may occur on cache maintenance. 770 771config ARM_ERRATA_798181 772 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 773 depends on CPU_V7 && SMP 774 help 775 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 776 adequately shooting down all use of the old entries. This 777 option enables the Linux kernel workaround for this erratum 778 which sends an IPI to the CPUs that are running the same ASID 779 as the one being invalidated. 780 781config ARM_ERRATA_773022 782 bool "ARM errata: incorrect instructions may be executed from loop buffer" 783 depends on CPU_V7 784 help 785 This option enables the workaround for the 773022 Cortex-A15 786 (up to r0p4) erratum. In certain rare sequences of code, the 787 loop buffer may deliver incorrect instructions. This 788 workaround disables the loop buffer to avoid the erratum. 789 790config ARM_ERRATA_818325_852422 791 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 792 depends on CPU_V7 793 help 794 This option enables the workaround for: 795 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 796 instruction might deadlock. Fixed in r0p1. 797 - Cortex-A12 852422: Execution of a sequence of instructions might 798 lead to either a data corruption or a CPU deadlock. Not fixed in 799 any Cortex-A12 cores yet. 800 This workaround for all both errata involves setting bit[12] of the 801 Feature Register. This bit disables an optimisation applied to a 802 sequence of 2 instructions that use opposing condition codes. 803 804config ARM_ERRATA_821420 805 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 806 depends on CPU_V7 807 help 808 This option enables the workaround for the 821420 Cortex-A12 809 (all revs) erratum. In very rare timing conditions, a sequence 810 of VMOV to Core registers instructions, for which the second 811 one is in the shadow of a branch or abort, can lead to a 812 deadlock when the VMOV instructions are issued out-of-order. 813 814config ARM_ERRATA_825619 815 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 816 depends on CPU_V7 817 help 818 This option enables the workaround for the 825619 Cortex-A12 819 (all revs) erratum. Within rare timing constraints, executing a 820 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 821 and Device/Strongly-Ordered loads and stores might cause deadlock 822 823config ARM_ERRATA_857271 824 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 825 depends on CPU_V7 826 help 827 This option enables the workaround for the 857271 Cortex-A12 828 (all revs) erratum. Under very rare timing conditions, the CPU might 829 hang. The workaround is expected to have a < 1% performance impact. 830 831config ARM_ERRATA_852421 832 bool "ARM errata: A17: DMB ST might fail to create order between stores" 833 depends on CPU_V7 834 help 835 This option enables the workaround for the 852421 Cortex-A17 836 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 837 execution of a DMB ST instruction might fail to properly order 838 stores from GroupA and stores from GroupB. 839 840config ARM_ERRATA_852423 841 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 842 depends on CPU_V7 843 help 844 This option enables the workaround for: 845 - Cortex-A17 852423: Execution of a sequence of instructions might 846 lead to either a data corruption or a CPU deadlock. Not fixed in 847 any Cortex-A17 cores yet. 848 This is identical to Cortex-A12 erratum 852422. It is a separate 849 config option from the A12 erratum due to the way errata are checked 850 for and handled. 851 852config ARM_ERRATA_857272 853 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 854 depends on CPU_V7 855 help 856 This option enables the workaround for the 857272 Cortex-A17 erratum. 857 This erratum is not known to be fixed in any A17 revision. 858 This is identical to Cortex-A12 erratum 857271. It is a separate 859 config option from the A12 erratum due to the way errata are checked 860 for and handled. 861 862endmenu 863 864source "arch/arm/common/Kconfig" 865 866menu "Bus support" 867 868config ISA 869 bool 870 help 871 Find out whether you have ISA slots on your motherboard. ISA is the 872 name of a bus system, i.e. the way the CPU talks to the other stuff 873 inside your box. Other bus systems are PCI, EISA, MicroChannel 874 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 875 newer boards don't support it. If you have ISA, say Y, otherwise N. 876 877# Select ISA DMA interface 878config ISA_DMA_API 879 bool 880 881config ARM_ERRATA_814220 882 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 883 depends on CPU_V7 884 help 885 The v7 ARM states that all cache and branch predictor maintenance 886 operations that do not specify an address execute, relative to 887 each other, in program order. 888 However, because of this erratum, an L2 set/way cache maintenance 889 operation can overtake an L1 set/way cache maintenance operation. 890 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 891 r0p4, r0p5. 892 893endmenu 894 895menu "Kernel Features" 896 897config HAVE_SMP 898 bool 899 help 900 This option should be selected by machines which have an SMP- 901 capable CPU. 902 903 The only effect of this option is to make the SMP-related 904 options available to the user for configuration. 905 906config SMP 907 bool "Symmetric Multi-Processing" 908 depends on CPU_V6K || CPU_V7 909 depends on HAVE_SMP 910 depends on MMU || ARM_MPU 911 select IRQ_WORK 912 help 913 This enables support for systems with more than one CPU. If you have 914 a system with only one CPU, say N. If you have a system with more 915 than one CPU, say Y. 916 917 If you say N here, the kernel will run on uni- and multiprocessor 918 machines, but will use only one CPU of a multiprocessor machine. If 919 you say Y here, the kernel will run on many, but not all, 920 uniprocessor machines. On a uniprocessor machine, the kernel 921 will run faster if you say N here. 922 923 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 924 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 925 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 926 927 If you don't know what to do here, say N. 928 929config SMP_ON_UP 930 bool "Allow booting SMP kernel on uniprocessor systems" 931 depends on SMP && MMU 932 default y 933 help 934 SMP kernels contain instructions which fail on non-SMP processors. 935 Enabling this option allows the kernel to modify itself to make 936 these instructions safe. Disabling it allows about 1K of space 937 savings. 938 939 If you don't know what to do here, say Y. 940 941 942config CURRENT_POINTER_IN_TPIDRURO 943 def_bool y 944 depends on CPU_32v6K && !CPU_V6 945 946config IRQSTACKS 947 def_bool y 948 select HAVE_IRQ_EXIT_ON_IRQ_STACK 949 select HAVE_SOFTIRQ_ON_OWN_STACK 950 951config ARM_CPU_TOPOLOGY 952 bool "Support cpu topology definition" 953 depends on SMP && CPU_V7 954 select ARCH_SUPPORTS_SCHED_MC 955 select ARCH_SUPPORTS_SCHED_SMT 956 default y 957 help 958 Support ARM cpu topology definition. The MPIDR register defines 959 affinity between processors which is then used to describe the cpu 960 topology of an ARM System. 961 962config HAVE_ARM_SCU 963 bool 964 help 965 This option enables support for the ARM snoop control unit 966 967config HAVE_ARM_ARCH_TIMER 968 bool "Architected timer support" 969 depends on CPU_V7 970 select ARM_ARCH_TIMER 971 help 972 This option enables support for the ARM architected timer 973 974config HAVE_ARM_TWD 975 bool 976 help 977 This options enables support for the ARM timer and watchdog unit 978 979config MCPM 980 bool "Multi-Cluster Power Management" 981 depends on CPU_V7 && SMP 982 help 983 This option provides the common power management infrastructure 984 for (multi-)cluster based systems, such as big.LITTLE based 985 systems. 986 987config MCPM_QUAD_CLUSTER 988 bool 989 depends on MCPM 990 help 991 To avoid wasting resources unnecessarily, MCPM only supports up 992 to 2 clusters by default. 993 Platforms with 3 or 4 clusters that use MCPM must select this 994 option to allow the additional clusters to be managed. 995 996config BIG_LITTLE 997 bool "big.LITTLE support (Experimental)" 998 depends on CPU_V7 && SMP 999 select MCPM 1000 help 1001 This option enables support selections for the big.LITTLE 1002 system architecture. 1003 1004config BL_SWITCHER 1005 bool "big.LITTLE switcher support" 1006 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1007 select CPU_PM 1008 help 1009 The big.LITTLE "switcher" provides the core functionality to 1010 transparently handle transition between a cluster of A15's 1011 and a cluster of A7's in a big.LITTLE system. 1012 1013config BL_SWITCHER_DUMMY_IF 1014 tristate "Simple big.LITTLE switcher user interface" 1015 depends on BL_SWITCHER && DEBUG_KERNEL 1016 help 1017 This is a simple and dummy char dev interface to control 1018 the big.LITTLE switcher core code. It is meant for 1019 debugging purposes only. 1020 1021choice 1022 prompt "Memory split" 1023 depends on MMU 1024 default VMSPLIT_3G 1025 help 1026 Select the desired split between kernel and user memory. 1027 1028 If you are not absolutely sure what you are doing, leave this 1029 option alone! 1030 1031 config VMSPLIT_3G 1032 bool "3G/1G user/kernel split" 1033 config VMSPLIT_3G_OPT 1034 depends on !ARM_LPAE 1035 bool "3G/1G user/kernel split (for full 1G low memory)" 1036 config VMSPLIT_2G 1037 bool "2G/2G user/kernel split" 1038 config VMSPLIT_1G 1039 bool "1G/3G user/kernel split" 1040endchoice 1041 1042config PAGE_OFFSET 1043 hex 1044 default PHYS_OFFSET if !MMU 1045 default 0x40000000 if VMSPLIT_1G 1046 default 0x80000000 if VMSPLIT_2G 1047 default 0xB0000000 if VMSPLIT_3G_OPT 1048 default 0xC0000000 1049 1050config KASAN_SHADOW_OFFSET 1051 hex 1052 depends on KASAN 1053 default 0x1f000000 if PAGE_OFFSET=0x40000000 1054 default 0x5f000000 if PAGE_OFFSET=0x80000000 1055 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1056 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1057 default 0xffffffff 1058 1059config NR_CPUS 1060 int "Maximum number of CPUs (2-32)" 1061 range 2 16 if DEBUG_KMAP_LOCAL 1062 range 2 32 if !DEBUG_KMAP_LOCAL 1063 depends on SMP 1064 default "4" 1065 help 1066 The maximum number of CPUs that the kernel can support. 1067 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1068 debugging is enabled, which uses half of the per-CPU fixmap 1069 slots as guard regions. 1070 1071config HOTPLUG_CPU 1072 bool "Support for hot-pluggable CPUs" 1073 depends on SMP 1074 select GENERIC_IRQ_MIGRATION 1075 help 1076 Say Y here to experiment with turning CPUs off and on. CPUs 1077 can be controlled through /sys/devices/system/cpu. 1078 1079config ARM_PSCI 1080 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1081 depends on HAVE_ARM_SMCCC 1082 select ARM_PSCI_FW 1083 help 1084 Say Y here if you want Linux to communicate with system firmware 1085 implementing the PSCI specification for CPU-centric power 1086 management operations described in ARM document number ARM DEN 1087 0022A ("Power State Coordination Interface System Software on 1088 ARM processors"). 1089 1090config HZ_FIXED 1091 int 1092 default 128 if SOC_AT91RM9200 1093 default 0 1094 1095choice 1096 depends on HZ_FIXED = 0 1097 prompt "Timer frequency" 1098 1099config HZ_100 1100 bool "100 Hz" 1101 1102config HZ_200 1103 bool "200 Hz" 1104 1105config HZ_250 1106 bool "250 Hz" 1107 1108config HZ_300 1109 bool "300 Hz" 1110 1111config HZ_500 1112 bool "500 Hz" 1113 1114config HZ_1000 1115 bool "1000 Hz" 1116 1117endchoice 1118 1119config HZ 1120 int 1121 default HZ_FIXED if HZ_FIXED != 0 1122 default 100 if HZ_100 1123 default 200 if HZ_200 1124 default 250 if HZ_250 1125 default 300 if HZ_300 1126 default 500 if HZ_500 1127 default 1000 1128 1129config SCHED_HRTICK 1130 def_bool HIGH_RES_TIMERS 1131 1132config THUMB2_KERNEL 1133 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1134 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1135 default y if CPU_THUMBONLY 1136 select ARM_UNWIND 1137 help 1138 By enabling this option, the kernel will be compiled in 1139 Thumb-2 mode. 1140 1141 If unsure, say N. 1142 1143config ARM_PATCH_IDIV 1144 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1145 depends on CPU_32v7 1146 default y 1147 help 1148 The ARM compiler inserts calls to __aeabi_idiv() and 1149 __aeabi_uidiv() when it needs to perform division on signed 1150 and unsigned integers. Some v7 CPUs have support for the sdiv 1151 and udiv instructions that can be used to implement those 1152 functions. 1153 1154 Enabling this option allows the kernel to modify itself to 1155 replace the first two instructions of these library functions 1156 with the sdiv or udiv plus "bx lr" instructions when the CPU 1157 it is running on supports them. Typically this will be faster 1158 and less power intensive than running the original library 1159 code to do integer division. 1160 1161config AEABI 1162 bool "Use the ARM EABI to compile the kernel" if CPU_SA110 || CPU_SA1100 1163 default y 1164 help 1165 The Arm EABI is the default ABI on all modern Linux 1166 distributions, replacing the obsolete and "OABI" that was 1167 commonly used on ARMv4 distributions before ca. 2013. 1168 1169 Everyone should enable this, as support for OABI user space 1170 was dropped in gcc-4.8 and most distributions after ca. 2013. 1171 1172 Support for OABI mode will be removed from the kernel 1173 once Intel StrongARM CPUs are phased out. 1174 1175config OABI_COMPAT 1176 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1177 depends on AEABI && !THUMB2_KERNEL 1178 depends on CPU_SA110 || CPU_SA1100 1179 help 1180 This option preserves the old syscall interface along with the 1181 new (ARM EABI) one. It also provides a compatibility layer to 1182 intercept syscalls that have structure arguments which layout 1183 in memory differs between the legacy ABI and the new ARM EABI 1184 (only for non "thumb" binaries). This option adds a tiny 1185 overhead to all syscalls and produces a slightly larger kernel. 1186 1187 The seccomp filter system will not be available when this is 1188 selected, since there is no way yet to sensibly distinguish 1189 between calling conventions during filtering. 1190 1191 Support for OABI_COMPAT will be removed from the kernel 1192 once Intel StrongARM CPUs are phased out. 1193 1194config ARCH_SELECT_MEMORY_MODEL 1195 def_bool y 1196 1197config ARCH_FLATMEM_ENABLE 1198 def_bool !(ARCH_RPC || ARCH_SA1100) 1199 1200config ARCH_SPARSEMEM_ENABLE 1201 def_bool !ARCH_FOOTBRIDGE 1202 select SPARSEMEM_STATIC if SPARSEMEM 1203 1204config HIGHMEM 1205 bool "High Memory Support" 1206 depends on MMU 1207 select KMAP_LOCAL 1208 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1209 help 1210 The address space of ARM processors is only 4 Gigabytes large 1211 and it has to accommodate user address space, kernel address 1212 space as well as some memory mapped IO. That means that, if you 1213 have a large amount of physical memory and/or IO, not all of the 1214 memory can be "permanently mapped" by the kernel. The physical 1215 memory that is not permanently mapped is called "high memory". 1216 1217 Depending on the selected kernel/user memory split, minimum 1218 vmalloc space and actual amount of RAM, you may not need this 1219 option which should result in a slightly faster kernel. 1220 1221 If unsure, say n. 1222 1223config HIGHPTE 1224 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1225 depends on HIGHMEM && !PREEMPT_RT 1226 default y 1227 help 1228 The VM uses one page of physical memory for each page table. 1229 For systems with a lot of processes, this can use a lot of 1230 precious low memory, eventually leading to low memory being 1231 consumed by page tables. Setting this option will allow 1232 user-space 2nd level page tables to reside in high memory. 1233 1234config ARM_PAN 1235 bool "Enable privileged no-access" 1236 depends on MMU 1237 default y 1238 help 1239 Increase kernel security by ensuring that normal kernel accesses 1240 are unable to access userspace addresses. This can help prevent 1241 use-after-free bugs becoming an exploitable privilege escalation 1242 by ensuring that magic values (such as LIST_POISON) will always 1243 fault when dereferenced. 1244 1245 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1246 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1247 1248config CPU_SW_DOMAIN_PAN 1249 def_bool y 1250 depends on ARM_PAN && !ARM_LPAE 1251 help 1252 Enable use of CPU domains to implement privileged no-access. 1253 1254 CPUs with low-vector mappings use a best-efforts implementation. 1255 Their lower 1MB needs to remain accessible for the vectors, but 1256 the remainder of userspace will become appropriately inaccessible. 1257 1258config CPU_TTBR0_PAN 1259 def_bool y 1260 depends on ARM_PAN && ARM_LPAE 1261 help 1262 Enable privileged no-access by disabling TTBR0 page table walks when 1263 running in kernel mode. 1264 1265config HW_PERF_EVENTS 1266 def_bool y 1267 depends on ARM_PMU 1268 1269config ARM_MODULE_PLTS 1270 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1271 depends on MODULES 1272 select KASAN_VMALLOC if KASAN 1273 default y 1274 help 1275 Allocate PLTs when loading modules so that jumps and calls whose 1276 targets are too far away for their relative offsets to be encoded 1277 in the instructions themselves can be bounced via veneers in the 1278 module's PLT. This allows modules to be allocated in the generic 1279 vmalloc area after the dedicated module memory area has been 1280 exhausted. The modules will use slightly more memory, but after 1281 rounding up to page size, the actual memory footprint is usually 1282 the same. 1283 1284 Disabling this is usually safe for small single-platform 1285 configurations. If unsure, say y. 1286 1287config ARCH_FORCE_MAX_ORDER 1288 int "Order of maximal physically contiguous allocations" 1289 default "11" if SOC_AM33XX 1290 default "8" if SA1111 1291 default "10" 1292 help 1293 The kernel page allocator limits the size of maximal physically 1294 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1295 defines the maximal power of two of number of pages that can be 1296 allocated as a single contiguous block. This option allows 1297 overriding the default setting when ability to allocate very 1298 large blocks of physically contiguous memory is required. 1299 1300 Don't change if unsure. 1301 1302config ALIGNMENT_TRAP 1303 def_bool CPU_CP15_MMU 1304 select HAVE_PROC_CPU if PROC_FS 1305 help 1306 ARM processors cannot fetch/store information which is not 1307 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1308 address divisible by 4. On 32-bit ARM processors, these non-aligned 1309 fetch/store instructions will be emulated in software if you say 1310 here, which has a severe performance impact. This is necessary for 1311 correct operation of some network protocols. With an IP-only 1312 configuration it is safe to say N, otherwise say Y. 1313 1314config UACCESS_WITH_MEMCPY 1315 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1316 depends on MMU 1317 default y if CPU_FEROCEON 1318 help 1319 Implement faster copy_to_user and clear_user methods for CPU 1320 cores where a 8-word STM instruction give significantly higher 1321 memory write throughput than a sequence of individual 32bit stores. 1322 1323 A possible side effect is a slight increase in scheduling latency 1324 between threads sharing the same address space if they invoke 1325 such copy operations with large buffers. 1326 1327 However, if the CPU data cache is using a write-allocate mode, 1328 this option is unlikely to provide any performance gain. 1329 1330config PARAVIRT 1331 bool "Enable paravirtualization code" 1332 select HAVE_PV_STEAL_CLOCK_GEN 1333 help 1334 This changes the kernel so it can modify itself when it is run 1335 under a hypervisor, potentially improving performance significantly 1336 over full virtualization. 1337 1338config PARAVIRT_TIME_ACCOUNTING 1339 bool "Paravirtual steal time accounting" 1340 select PARAVIRT 1341 help 1342 Select this option to enable fine granularity task steal time 1343 accounting. Time spent executing other tasks in parallel with 1344 the current vCPU is discounted from the vCPU power. To account for 1345 that, there can be a small performance impact. 1346 1347 If in doubt, say N here. 1348 1349config XEN_DOM0 1350 def_bool y 1351 depends on XEN 1352 1353config XEN 1354 bool "Xen guest support on ARM" 1355 depends on ARM && AEABI && OF 1356 depends on CPU_V7 && !CPU_V6 1357 depends on !GENERIC_ATOMIC64 1358 depends on MMU 1359 select ARCH_DMA_ADDR_T_64BIT 1360 select ARM_PSCI 1361 select SWIOTLB 1362 select SWIOTLB_XEN 1363 select PARAVIRT 1364 help 1365 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1366 1367config CC_HAVE_STACKPROTECTOR_TLS 1368 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1369 1370config STACKPROTECTOR_PER_TASK 1371 bool "Use a unique stack canary value for each task" 1372 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1373 depends on CC_HAVE_STACKPROTECTOR_TLS 1374 default y 1375 help 1376 Due to the fact that GCC uses an ordinary symbol reference from 1377 which to load the value of the stack canary, this value can only 1378 change at reboot time on SMP systems, and all tasks running in the 1379 kernel's address space are forced to use the same canary value for 1380 the entire duration that the system is up. 1381 1382 Enable this option to switch to a different method that uses a 1383 different canary value for each task. 1384 1385endmenu 1386 1387menu "Boot options" 1388 1389config USE_OF 1390 bool "Flattened Device Tree support" 1391 select IRQ_DOMAIN 1392 select OF 1393 help 1394 Include support for flattened device tree machine descriptions. 1395 1396config ARCH_WANT_FLAT_DTB_INSTALL 1397 def_bool y 1398 1399config ATAGS 1400 bool "Support for the traditional ATAGS boot data passing" 1401 depends on EXPERT 1402 help 1403 This is the traditional way of passing data to the kernel at 1404 boot but is now only used by a few of the oldest ARMv4 and 1405 ARMv5 machines. Users that still rely on ATAGS should plan 1406 on migrating to devicetree based booting. 1407 1408 Support for ATAGS will be removed when the last machine using 1409 it is either converted to DT or removed. 1410 1411config DEPRECATED_PARAM_STRUCT 1412 bool "Provide old way to pass kernel parameters (DEPRECATED)" 1413 depends on ATAGS 1414 help 1415 This was deprecated in 2001 and announced to live on for 5 years. 1416 It is now scheduled for removal in early 2027. 1417 1418# Compressed boot loader in ROM. Yes, we really want to ask about 1419# TEXT and BSS so we preserve their values in the config files. 1420config ZBOOT_ROM_TEXT 1421 hex "Compressed ROM boot loader base address" 1422 default 0x0 1423 help 1424 The physical address at which the ROM-able zImage is to be 1425 placed in the target. Platforms which normally make use of 1426 ROM-able zImage formats normally set this to a suitable 1427 value in their defconfig file. 1428 1429 If ZBOOT_ROM is not enabled, this has no effect. 1430 1431config ZBOOT_ROM_BSS 1432 hex "Compressed ROM boot loader BSS address" 1433 default 0x0 1434 help 1435 The base address of an area of read/write memory in the target 1436 for the ROM-able zImage which must be available while the 1437 decompressor is running. It must be large enough to hold the 1438 entire decompressed kernel plus an additional 128 KiB. 1439 Platforms which normally make use of ROM-able zImage formats 1440 normally set this to a suitable value in their defconfig file. 1441 1442 If ZBOOT_ROM is not enabled, this has no effect. 1443 1444config ZBOOT_ROM 1445 bool "Compressed boot loader in ROM/flash" 1446 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1447 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1448 help 1449 Say Y here if you intend to execute your compressed kernel image 1450 (zImage) directly from ROM or flash. If unsure, say N. 1451 1452config ARM_APPENDED_DTB 1453 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1454 depends on OF 1455 help 1456 With this option, the boot code will look for a device tree binary 1457 (DTB) appended to zImage 1458 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1459 1460 This is meant as a backward compatibility convenience for those 1461 systems with a bootloader that can't be upgraded to accommodate 1462 the documented boot protocol using a device tree. 1463 1464 Beware that there is very little in terms of protection against 1465 this option being confused by leftover garbage in memory that might 1466 look like a DTB header after a reboot if no actual DTB is appended 1467 to zImage. Do not leave this option active in a production kernel 1468 if you don't intend to always append a DTB. Proper passing of the 1469 location into r2 of a bootloader provided DTB is always preferable 1470 to this option. 1471 1472config ARM_ATAG_DTB_COMPAT 1473 bool "Supplement the appended DTB with traditional ATAG information" 1474 depends on ARM_APPENDED_DTB 1475 help 1476 Some old bootloaders can't be updated to a DTB capable one, yet 1477 they provide ATAGs with memory configuration, the ramdisk address, 1478 the kernel cmdline string, etc. Such information is dynamically 1479 provided by the bootloader and can't always be stored in a static 1480 DTB. To allow a device tree enabled kernel to be used with such 1481 bootloaders, this option allows zImage to extract the information 1482 from the ATAG list and store it at run time into the appended DTB. 1483 1484choice 1485 prompt "Kernel command line type" 1486 depends on ARM_ATAG_DTB_COMPAT 1487 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1488 1489config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1490 bool "Use bootloader kernel arguments if available" 1491 help 1492 Uses the command-line options passed by the boot loader instead of 1493 the device tree bootargs property. If the boot loader doesn't provide 1494 any, the device tree bootargs property will be used. 1495 1496config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1497 bool "Extend with bootloader kernel arguments" 1498 help 1499 The command-line arguments provided by the boot loader will be 1500 appended to the the device tree bootargs property. 1501 1502endchoice 1503 1504config CMDLINE 1505 string "Default kernel command string" 1506 default "" 1507 help 1508 On some architectures (e.g. CATS), there is currently no way 1509 for the boot loader to pass arguments to the kernel. For these 1510 architectures, you should supply some command-line options at build 1511 time by entering them here. As a minimum, you should specify the 1512 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1513 1514choice 1515 prompt "Kernel command line type" 1516 depends on CMDLINE != "" 1517 default CMDLINE_FROM_BOOTLOADER 1518 1519config CMDLINE_FROM_BOOTLOADER 1520 bool "Use bootloader kernel arguments if available" 1521 help 1522 Uses the command-line options passed by the boot loader. If 1523 the boot loader doesn't provide any, the default kernel command 1524 string provided in CMDLINE will be used. 1525 1526config CMDLINE_EXTEND 1527 bool "Extend bootloader kernel arguments" 1528 help 1529 The command-line arguments provided by the boot loader will be 1530 appended to the default kernel command string. 1531 1532config CMDLINE_FORCE 1533 bool "Always use the default kernel command string" 1534 help 1535 Always use the default kernel command string, even if the boot 1536 loader passes other arguments to the kernel. 1537 This is useful if you cannot or don't want to change the 1538 command-line options your boot loader passes to the kernel. 1539endchoice 1540 1541config XIP_KERNEL 1542 bool "Kernel Execute-In-Place from ROM" 1543 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1544 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1545 help 1546 Execute-In-Place allows the kernel to run from non-volatile storage 1547 directly addressable by the CPU, such as NOR flash. This saves RAM 1548 space since the text section of the kernel is not loaded from flash 1549 to RAM. Read-write sections, such as the data section and stack, 1550 are still copied to RAM. The XIP kernel is not compressed since 1551 it has to run directly from flash, so it will take more space to 1552 store it. The flash address used to link the kernel object files, 1553 and for storing it, is configuration dependent. Therefore, if you 1554 say Y here, you must know the proper physical address where to 1555 store the kernel image depending on your own flash memory usage. 1556 1557 Also note that the make target becomes "make xipImage" rather than 1558 "make zImage" or "make Image". The final kernel binary to put in 1559 ROM memory will be arch/arm/boot/xipImage. 1560 1561 If unsure, say N. 1562 1563config XIP_PHYS_ADDR 1564 hex "XIP Kernel Physical Location" 1565 depends on XIP_KERNEL 1566 default "0x00080000" 1567 help 1568 This is the physical address in your flash memory the kernel will 1569 be linked for and stored to. This address is dependent on your 1570 own flash usage. 1571 1572config XIP_DEFLATED_DATA 1573 bool "Store kernel .data section compressed in ROM" 1574 depends on XIP_KERNEL 1575 select ZLIB_INFLATE 1576 help 1577 Before the kernel is actually executed, its .data section has to be 1578 copied to RAM from ROM. This option allows for storing that data 1579 in compressed form and decompressed to RAM rather than merely being 1580 copied, saving some precious ROM space. A possible drawback is a 1581 slightly longer boot delay. 1582 1583config ARCH_SUPPORTS_KEXEC 1584 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1585 1586config ATAGS_PROC 1587 bool "Export atags in procfs" 1588 depends on ATAGS && KEXEC 1589 default y 1590 help 1591 Should the atags used to boot the kernel be exported in an "atags" 1592 file in procfs. Useful with kexec. 1593 1594config ARCH_SUPPORTS_CRASH_DUMP 1595 def_bool y 1596 1597config ARCH_DEFAULT_CRASH_DUMP 1598 def_bool y 1599 1600config AUTO_ZRELADDR 1601 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1602 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1603 help 1604 ZRELADDR is the physical address where the decompressed kernel 1605 image will be placed. If AUTO_ZRELADDR is selected, the address 1606 will be determined at run-time, either by masking the current IP 1607 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1608 This assumes the zImage being placed in the first 128MB from 1609 start of memory. 1610 1611config EFI_STUB 1612 bool 1613 1614config EFI 1615 bool "UEFI runtime support" 1616 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1617 select UCS2_STRING 1618 select EFI_PARAMS_FROM_FDT 1619 select EFI_STUB 1620 select EFI_GENERIC_STUB 1621 select EFI_RUNTIME_WRAPPERS 1622 help 1623 This option provides support for runtime services provided 1624 by UEFI firmware (such as non-volatile variables, realtime 1625 clock, and platform reset). A UEFI stub is also provided to 1626 allow the kernel to be booted as an EFI application. This 1627 is only useful for kernels that may run on systems that have 1628 UEFI firmware. 1629 1630config DMI 1631 bool "Enable support for SMBIOS (DMI) tables" 1632 depends on EFI 1633 default y 1634 help 1635 This enables SMBIOS/DMI feature for systems. 1636 1637 This option is only useful on systems that have UEFI firmware. 1638 However, even with this option, the resultant kernel should 1639 continue to boot on existing non-UEFI platforms. 1640 1641 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1642 i.e., the the practice of identifying the platform via DMI to 1643 decide whether certain workarounds for buggy hardware and/or 1644 firmware need to be enabled. This would require the DMI subsystem 1645 to be enabled much earlier than we do on ARM, which is non-trivial. 1646 1647endmenu 1648 1649menu "CPU Power Management" 1650 1651source "drivers/cpufreq/Kconfig" 1652 1653source "drivers/cpuidle/Kconfig" 1654 1655endmenu 1656 1657menu "Floating point emulation" 1658 1659comment "At least one emulation must be selected" 1660 1661config FPE_NWFPE 1662 bool "NWFPE math emulation (DEPRECATED)" 1663 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1664 help 1665 Say Y to include the NWFPE floating point emulator in the kernel. 1666 1667 This is only used on OABI userspace binaries, either using a 1668 pure OABI (!CONFIG_AEABI) kernel, or the OABI emulation. 1669 1670 Support for NWFPE will be removed in the future when OABI 1671 support is removed. 1672 1673config FPE_NWFPE_XP 1674 bool "Support extended precision" 1675 depends on FPE_NWFPE 1676 help 1677 Say Y to include 80-bit support in the kernel floating-point 1678 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1679 Note that gcc does not generate 80-bit operations by default, 1680 so in most cases this option only enlarges the size of the 1681 floating point emulator without any good reason. 1682 1683 You almost surely want to say N here. 1684 1685config FPE_FASTFPE 1686 bool "FastFPE math emulation (EXPERIMENTAL)" 1687 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1688 help 1689 Say Y here to include the FAST floating point emulator in the kernel. 1690 This is an experimental much faster emulator which now also has full 1691 precision for the mantissa. It does not support any exceptions. 1692 It is very simple, and approximately 3-6 times faster than NWFPE. 1693 1694 It should be sufficient for most programs. It may be not suitable 1695 for scientific calculations, but you have to check this for yourself. 1696 If you do not feel you need a faster FP emulation you should better 1697 choose NWFPE. 1698 1699config VFP 1700 bool "VFP-format floating point maths" 1701 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1702 help 1703 Say Y to include VFP support code in the kernel. This is needed 1704 if your hardware includes a VFP unit. 1705 1706 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1707 release notes and additional status information. 1708 1709 Say N if your target does not have VFP hardware. 1710 1711config VFPv3 1712 bool 1713 depends on VFP 1714 default y if CPU_V7 1715 1716config NEON 1717 bool "Advanced SIMD (NEON) Extension support" 1718 depends on VFPv3 && CPU_V7 1719 help 1720 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1721 Extension. 1722 1723config KERNEL_MODE_NEON 1724 bool "Support for NEON in kernel mode" 1725 depends on NEON && AEABI 1726 help 1727 Say Y to include support for NEON in kernel mode. 1728 1729endmenu 1730 1731config ARCH_CC_CAN_LINK 1732 bool 1733 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN 1734 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8 1735 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32 1736 1737config ARCH_USERFLAGS 1738 string 1739 default "-mlittle-endian" if CPU_LITTLE_ENDIAN 1740 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8 1741 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32 1742 1743menu "Power management options" 1744 1745source "kernel/power/Kconfig" 1746 1747config ARCH_SUSPEND_POSSIBLE 1748 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1749 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1750 def_bool y 1751 1752config ARM_CPU_SUSPEND 1753 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1754 depends on ARCH_SUSPEND_POSSIBLE 1755 1756config ARCH_HIBERNATION_POSSIBLE 1757 bool 1758 depends on MMU 1759 default y if ARCH_SUSPEND_POSSIBLE 1760 1761endmenu 1762