1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_CACHE_ALIASING 9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 10 select ARCH_HAS_CURRENT_STACK_POINTER 11 select ARCH_HAS_DEBUG_VIRTUAL if MMU 12 select ARCH_HAS_DMA_ALLOC if MMU 13 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 14 select ARCH_HAS_ELF_RANDOMIZE 15 select ARCH_HAS_FORTIFY_SOURCE 16 select ARCH_HAS_KEEPINITRD 17 select ARCH_HAS_KCOV 18 select ARCH_HAS_MEMBARRIER_SYNC_CORE 19 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 20 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 21 select ARCH_HAS_SETUP_DMA_OPS 22 select ARCH_HAS_SET_MEMORY 23 select ARCH_STACKWALK 24 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 25 select ARCH_HAS_STRICT_MODULE_RWX if MMU 26 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 27 select ARCH_HAS_SYNC_DMA_FOR_CPU 28 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 29 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 30 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 31 select ARCH_HAS_GCOV_PROFILE_ALL 32 select ARCH_KEEP_MEMBLOCK 33 select ARCH_HAS_UBSAN 34 select ARCH_MIGHT_HAVE_PC_PARPORT 35 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 36 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 37 select ARCH_SUPPORTS_ATOMIC_RMW 38 select ARCH_SUPPORTS_CFI_CLANG 39 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 40 select ARCH_SUPPORTS_PER_VMA_LOCK 41 select ARCH_USE_BUILTIN_BSWAP 42 select ARCH_USE_CMPXCHG_LOCKREF 43 select ARCH_USE_MEMTEST 44 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 45 select ARCH_WANT_GENERAL_HUGETLB 46 select ARCH_WANT_IPC_PARSE_VERSION 47 select ARCH_WANT_LD_ORPHAN_WARN 48 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 49 select BUILDTIME_TABLE_SORT if MMU 50 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 51 select CLONE_BACKWARDS 52 select CPU_PM if SUSPEND || CPU_IDLE 53 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 54 select DMA_DECLARE_COHERENT 55 select DMA_GLOBAL_POOL if !MMU 56 select DMA_OPS 57 select DMA_NONCOHERENT_MMAP if MMU 58 select EDAC_SUPPORT 59 select EDAC_ATOMIC_SCRUB 60 select GENERIC_ALLOCATOR 61 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 62 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 63 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 64 select GENERIC_IRQ_IPI if SMP 65 select GENERIC_CPU_AUTOPROBE 66 select GENERIC_EARLY_IOREMAP 67 select GENERIC_IDLE_POLL_SETUP 68 select GENERIC_IRQ_MULTI_HANDLER 69 select GENERIC_IRQ_PROBE 70 select GENERIC_IRQ_SHOW 71 select GENERIC_IRQ_SHOW_LEVEL 72 select GENERIC_LIB_DEVMEM_IS_ALLOWED 73 select GENERIC_PCI_IOMAP 74 select GENERIC_SCHED_CLOCK 75 select GENERIC_SMP_IDLE_THREAD 76 select HARDIRQS_SW_RESEND 77 select HAS_IOPORT 78 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 80 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 81 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 82 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 83 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 84 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 85 select HAVE_ARCH_MMAP_RND_BITS if MMU 86 select HAVE_ARCH_PFN_VALID 87 select HAVE_ARCH_SECCOMP 88 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 89 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 90 select HAVE_ARCH_TRACEHOOK 91 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 92 select HAVE_ARM_SMCCC if CPU_V7 93 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 94 select HAVE_CONTEXT_TRACKING_USER 95 select HAVE_C_RECORDMCOUNT 96 select HAVE_BUILDTIME_MCOUNT_SORT 97 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 98 select HAVE_DMA_CONTIGUOUS if MMU 99 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 100 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 101 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 102 select HAVE_EXIT_THREAD 103 select HAVE_GUP_FAST if ARM_LPAE 104 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 105 select HAVE_FUNCTION_ERROR_INJECTION 106 select HAVE_FUNCTION_GRAPH_TRACER 107 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 108 select HAVE_GCC_PLUGINS 109 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 110 select HAVE_IRQ_TIME_ACCOUNTING 111 select HAVE_KERNEL_GZIP 112 select HAVE_KERNEL_LZ4 113 select HAVE_KERNEL_LZMA 114 select HAVE_KERNEL_LZO 115 select HAVE_KERNEL_XZ 116 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 117 select HAVE_KRETPROBES if HAVE_KPROBES 118 select HAVE_MOD_ARCH_SPECIFIC 119 select HAVE_NMI 120 select HAVE_OPTPROBES if !THUMB2_KERNEL 121 select HAVE_PAGE_SIZE_4KB 122 select HAVE_PCI if MMU 123 select HAVE_PERF_EVENTS 124 select HAVE_PERF_REGS 125 select HAVE_PERF_USER_STACK_DUMP 126 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 127 select HAVE_REGS_AND_STACK_ACCESS_API 128 select HAVE_RSEQ 129 select HAVE_STACKPROTECTOR 130 select HAVE_SYSCALL_TRACEPOINTS 131 select HAVE_UID16 132 select HAVE_VIRT_CPU_ACCOUNTING_GEN 133 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 134 select IRQ_FORCED_THREADING 135 select LOCK_MM_AND_FIND_VMA 136 select MODULES_USE_ELF_REL 137 select NEED_DMA_MAP_STATE 138 select OF_EARLY_FLATTREE if OF 139 select OLD_SIGACTION 140 select OLD_SIGSUSPEND3 141 select PCI_DOMAINS_GENERIC if PCI 142 select PCI_SYSCALL if PCI 143 select PERF_USE_VMALLOC 144 select RTC_LIB 145 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 146 select SYS_SUPPORTS_APM_EMULATION 147 select THREAD_INFO_IN_TASK 148 select TIMER_OF if OF 149 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 150 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 151 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 152 # Above selects are sorted alphabetically; please add new ones 153 # according to that. Thanks. 154 help 155 The ARM series is a line of low-power-consumption RISC chip designs 156 licensed by ARM Ltd and targeted at embedded applications and 157 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 158 manufactured, but legacy ARM-based PC hardware remains popular in 159 Europe. There is an ARM Linux project with a web page at 160 <http://www.arm.linux.org.uk/>. 161 162config ARM_HAS_GROUP_RELOCS 163 def_bool y 164 depends on !LD_IS_LLD || LLD_VERSION >= 140000 165 depends on !COMPILE_TEST 166 help 167 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 168 relocations, which have been around for a long time, but were not 169 supported in LLD until version 14. The combined range is -/+ 256 MiB, 170 which is usually sufficient, but not for allyesconfig, so we disable 171 this feature when doing compile testing. 172 173config ARM_DMA_USE_IOMMU 174 bool 175 select NEED_SG_DMA_LENGTH 176 177if ARM_DMA_USE_IOMMU 178 179config ARM_DMA_IOMMU_ALIGNMENT 180 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 181 range 4 9 182 default 8 183 help 184 DMA mapping framework by default aligns all buffers to the smallest 185 PAGE_SIZE order which is greater than or equal to the requested buffer 186 size. This works well for buffers up to a few hundreds kilobytes, but 187 for larger buffers it just a waste of address space. Drivers which has 188 relatively small addressing window (like 64Mib) might run out of 189 virtual space with just a few allocations. 190 191 With this parameter you can specify the maximum PAGE_SIZE order for 192 DMA IOMMU buffers. Larger buffers will be aligned only to this 193 specified order. The order is expressed as a power of two multiplied 194 by the PAGE_SIZE. 195 196endif 197 198config SYS_SUPPORTS_APM_EMULATION 199 bool 200 201config HAVE_TCM 202 bool 203 select GENERIC_ALLOCATOR 204 205config HAVE_PROC_CPU 206 bool 207 208config NO_IOPORT_MAP 209 bool 210 211config SBUS 212 bool 213 214config STACKTRACE_SUPPORT 215 bool 216 default y 217 218config LOCKDEP_SUPPORT 219 bool 220 default y 221 222config ARCH_HAS_ILOG2_U32 223 bool 224 225config ARCH_HAS_ILOG2_U64 226 bool 227 228config ARCH_HAS_BANDGAP 229 bool 230 231config FIX_EARLYCON_MEM 232 def_bool y if MMU 233 234config GENERIC_HWEIGHT 235 bool 236 default y 237 238config GENERIC_CALIBRATE_DELAY 239 bool 240 default y 241 242config ARCH_MAY_HAVE_PC_FDC 243 bool 244 245config ARCH_SUPPORTS_UPROBES 246 def_bool y 247 248config GENERIC_ISA_DMA 249 bool 250 251config FIQ 252 bool 253 254config ARCH_MTD_XIP 255 bool 256 257config ARM_PATCH_PHYS_VIRT 258 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 259 default y 260 depends on MMU 261 help 262 Patch phys-to-virt and virt-to-phys translation functions at 263 boot and module load time according to the position of the 264 kernel in system memory. 265 266 This can only be used with non-XIP MMU kernels where the base 267 of physical memory is at a 2 MiB boundary. 268 269 Only disable this option if you know that you do not require 270 this feature (eg, building a kernel for a single machine) and 271 you need to shrink the kernel to the minimal size. 272 273config NEED_MACH_IO_H 274 bool 275 help 276 Select this when mach/io.h is required to provide special 277 definitions for this platform. The need for mach/io.h should 278 be avoided when possible. 279 280config NEED_MACH_MEMORY_H 281 bool 282 help 283 Select this when mach/memory.h is required to provide special 284 definitions for this platform. The need for mach/memory.h should 285 be avoided when possible. 286 287config PHYS_OFFSET 288 hex "Physical address of main memory" if MMU 289 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 290 default DRAM_BASE if !MMU 291 default 0x00000000 if ARCH_FOOTBRIDGE 292 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 293 default 0xa0000000 if ARCH_PXA 294 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 295 default 0 296 help 297 Please provide the physical address corresponding to the 298 location of main memory in your system. 299 300config GENERIC_BUG 301 def_bool y 302 depends on BUG 303 304config PGTABLE_LEVELS 305 int 306 default 3 if ARM_LPAE 307 default 2 308 309menu "System Type" 310 311config MMU 312 bool "MMU-based Paged Memory Management Support" 313 default y 314 help 315 Select if you want MMU-based virtualised addressing space 316 support by paged memory management. If unsure, say 'Y'. 317 318config ARM_SINGLE_ARMV7M 319 def_bool !MMU 320 select ARM_NVIC 321 select CPU_V7M 322 select NO_IOPORT_MAP 323 324config ARCH_MMAP_RND_BITS_MIN 325 default 8 326 327config ARCH_MMAP_RND_BITS_MAX 328 default 14 if PAGE_OFFSET=0x40000000 329 default 15 if PAGE_OFFSET=0x80000000 330 default 16 331 332config ARCH_MULTIPLATFORM 333 bool "Require kernel to be portable to multiple machines" if EXPERT 334 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 335 default y 336 help 337 In general, all Arm machines can be supported in a single 338 kernel image, covering either Armv4/v5 or Armv6/v7. 339 340 However, some configuration options require hardcoding machine 341 specific physical addresses or enable errata workarounds that may 342 break other machines. 343 344 Selecting N here allows using those options, including 345 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 346 347source "arch/arm/Kconfig.platforms" 348 349# 350# This is sorted alphabetically by mach-* pathname. However, plat-* 351# Kconfigs may be included either alphabetically (according to the 352# plat- suffix) or along side the corresponding mach-* source. 353# 354source "arch/arm/mach-actions/Kconfig" 355 356source "arch/arm/mach-alpine/Kconfig" 357 358source "arch/arm/mach-artpec/Kconfig" 359 360source "arch/arm/mach-aspeed/Kconfig" 361 362source "arch/arm/mach-at91/Kconfig" 363 364source "arch/arm/mach-axxia/Kconfig" 365 366source "arch/arm/mach-bcm/Kconfig" 367 368source "arch/arm/mach-berlin/Kconfig" 369 370source "arch/arm/mach-clps711x/Kconfig" 371 372source "arch/arm/mach-davinci/Kconfig" 373 374source "arch/arm/mach-digicolor/Kconfig" 375 376source "arch/arm/mach-dove/Kconfig" 377 378source "arch/arm/mach-ep93xx/Kconfig" 379 380source "arch/arm/mach-exynos/Kconfig" 381 382source "arch/arm/mach-footbridge/Kconfig" 383 384source "arch/arm/mach-gemini/Kconfig" 385 386source "arch/arm/mach-highbank/Kconfig" 387 388source "arch/arm/mach-hisi/Kconfig" 389 390source "arch/arm/mach-hpe/Kconfig" 391 392source "arch/arm/mach-imx/Kconfig" 393 394source "arch/arm/mach-ixp4xx/Kconfig" 395 396source "arch/arm/mach-keystone/Kconfig" 397 398source "arch/arm/mach-lpc32xx/Kconfig" 399 400source "arch/arm/mach-mediatek/Kconfig" 401 402source "arch/arm/mach-meson/Kconfig" 403 404source "arch/arm/mach-milbeaut/Kconfig" 405 406source "arch/arm/mach-mmp/Kconfig" 407 408source "arch/arm/mach-mstar/Kconfig" 409 410source "arch/arm/mach-mv78xx0/Kconfig" 411 412source "arch/arm/mach-mvebu/Kconfig" 413 414source "arch/arm/mach-mxs/Kconfig" 415 416source "arch/arm/mach-nomadik/Kconfig" 417 418source "arch/arm/mach-npcm/Kconfig" 419 420source "arch/arm/mach-omap1/Kconfig" 421 422source "arch/arm/mach-omap2/Kconfig" 423 424source "arch/arm/mach-orion5x/Kconfig" 425 426source "arch/arm/mach-pxa/Kconfig" 427 428source "arch/arm/mach-qcom/Kconfig" 429 430source "arch/arm/mach-realtek/Kconfig" 431 432source "arch/arm/mach-rpc/Kconfig" 433 434source "arch/arm/mach-rockchip/Kconfig" 435 436source "arch/arm/mach-s3c/Kconfig" 437 438source "arch/arm/mach-s5pv210/Kconfig" 439 440source "arch/arm/mach-sa1100/Kconfig" 441 442source "arch/arm/mach-shmobile/Kconfig" 443 444source "arch/arm/mach-socfpga/Kconfig" 445 446source "arch/arm/mach-spear/Kconfig" 447 448source "arch/arm/mach-sti/Kconfig" 449 450source "arch/arm/mach-stm32/Kconfig" 451 452source "arch/arm/mach-sunxi/Kconfig" 453 454source "arch/arm/mach-tegra/Kconfig" 455 456source "arch/arm/mach-ux500/Kconfig" 457 458source "arch/arm/mach-versatile/Kconfig" 459 460source "arch/arm/mach-vt8500/Kconfig" 461 462source "arch/arm/mach-zynq/Kconfig" 463 464# ARMv7-M architecture 465config ARCH_LPC18XX 466 bool "NXP LPC18xx/LPC43xx" 467 depends on ARM_SINGLE_ARMV7M 468 select ARCH_HAS_RESET_CONTROLLER 469 select ARM_AMBA 470 select CLKSRC_LPC32XX 471 select PINCTRL 472 help 473 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 474 high performance microcontrollers. 475 476config ARCH_MPS2 477 bool "ARM MPS2 platform" 478 depends on ARM_SINGLE_ARMV7M 479 select ARM_AMBA 480 select CLKSRC_MPS2 481 help 482 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 483 with a range of available cores like Cortex-M3/M4/M7. 484 485 Please, note that depends which Application Note is used memory map 486 for the platform may vary, so adjustment of RAM base might be needed. 487 488# Definitions to make life easier 489config ARCH_ACORN 490 bool 491 492config PLAT_ORION 493 bool 494 select CLKSRC_MMIO 495 select GENERIC_IRQ_CHIP 496 select IRQ_DOMAIN 497 498config PLAT_ORION_LEGACY 499 bool 500 select PLAT_ORION 501 502config PLAT_VERSATILE 503 bool 504 505source "arch/arm/mm/Kconfig" 506 507config IWMMXT 508 bool "Enable iWMMXt support" 509 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 510 default y if PXA27x || PXA3xx || ARCH_MMP 511 help 512 Enable support for iWMMXt context switching at run time if 513 running on a CPU that supports it. 514 515if !MMU 516source "arch/arm/Kconfig-nommu" 517endif 518 519config PJ4B_ERRATA_4742 520 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 521 depends on CPU_PJ4B && MACH_ARMADA_370 522 default y 523 help 524 When coming out of either a Wait for Interrupt (WFI) or a Wait for 525 Event (WFE) IDLE states, a specific timing sensitivity exists between 526 the retiring WFI/WFE instructions and the newly issued subsequent 527 instructions. This sensitivity can result in a CPU hang scenario. 528 Workaround: 529 The software must insert either a Data Synchronization Barrier (DSB) 530 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 531 instruction 532 533config ARM_ERRATA_326103 534 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 535 depends on CPU_V6 536 help 537 Executing a SWP instruction to read-only memory does not set bit 11 538 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 539 treat the access as a read, preventing a COW from occurring and 540 causing the faulting task to livelock. 541 542config ARM_ERRATA_411920 543 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 544 depends on CPU_V6 || CPU_V6K 545 help 546 Invalidation of the Instruction Cache operation can 547 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 548 It does not affect the MPCore. This option enables the ARM Ltd. 549 recommended workaround. 550 551config ARM_ERRATA_430973 552 bool "ARM errata: Stale prediction on replaced interworking branch" 553 depends on CPU_V7 554 help 555 This option enables the workaround for the 430973 Cortex-A8 556 r1p* erratum. If a code sequence containing an ARM/Thumb 557 interworking branch is replaced with another code sequence at the 558 same virtual address, whether due to self-modifying code or virtual 559 to physical address re-mapping, Cortex-A8 does not recover from the 560 stale interworking branch prediction. This results in Cortex-A8 561 executing the new code sequence in the incorrect ARM or Thumb state. 562 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 563 and also flushes the branch target cache at every context switch. 564 Note that setting specific bits in the ACTLR register may not be 565 available in non-secure mode. 566 567config ARM_ERRATA_458693 568 bool "ARM errata: Processor deadlock when a false hazard is created" 569 depends on CPU_V7 570 depends on !ARCH_MULTIPLATFORM 571 help 572 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 573 erratum. For very specific sequences of memory operations, it is 574 possible for a hazard condition intended for a cache line to instead 575 be incorrectly associated with a different cache line. This false 576 hazard might then cause a processor deadlock. The workaround enables 577 the L1 caching of the NEON accesses and disables the PLD instruction 578 in the ACTLR register. Note that setting specific bits in the ACTLR 579 register may not be available in non-secure mode and thus is not 580 available on a multiplatform kernel. This should be applied by the 581 bootloader instead. 582 583config ARM_ERRATA_460075 584 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 585 depends on CPU_V7 586 depends on !ARCH_MULTIPLATFORM 587 help 588 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 589 erratum. Any asynchronous access to the L2 cache may encounter a 590 situation in which recent store transactions to the L2 cache are lost 591 and overwritten with stale memory contents from external memory. The 592 workaround disables the write-allocate mode for the L2 cache via the 593 ACTLR register. Note that setting specific bits in the ACTLR register 594 may not be available in non-secure mode and thus is not available on 595 a multiplatform kernel. This should be applied by the bootloader 596 instead. 597 598config ARM_ERRATA_742230 599 bool "ARM errata: DMB operation may be faulty" 600 depends on CPU_V7 && SMP 601 depends on !ARCH_MULTIPLATFORM 602 help 603 This option enables the workaround for the 742230 Cortex-A9 604 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 605 between two write operations may not ensure the correct visibility 606 ordering of the two writes. This workaround sets a specific bit in 607 the diagnostic register of the Cortex-A9 which causes the DMB 608 instruction to behave as a DSB, ensuring the correct behaviour of 609 the two writes. Note that setting specific bits in the diagnostics 610 register may not be available in non-secure mode and thus is not 611 available on a multiplatform kernel. This should be applied by the 612 bootloader instead. 613 614config ARM_ERRATA_742231 615 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 616 depends on CPU_V7 && SMP 617 depends on !ARCH_MULTIPLATFORM 618 help 619 This option enables the workaround for the 742231 Cortex-A9 620 (r2p0..r2p2) erratum. Under certain conditions, specific to the 621 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 622 accessing some data located in the same cache line, may get corrupted 623 data due to bad handling of the address hazard when the line gets 624 replaced from one of the CPUs at the same time as another CPU is 625 accessing it. This workaround sets specific bits in the diagnostic 626 register of the Cortex-A9 which reduces the linefill issuing 627 capabilities of the processor. Note that setting specific bits in the 628 diagnostics register may not be available in non-secure mode and thus 629 is not available on a multiplatform kernel. This should be applied by 630 the bootloader instead. 631 632config ARM_ERRATA_643719 633 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 634 depends on CPU_V7 && SMP 635 default y 636 help 637 This option enables the workaround for the 643719 Cortex-A9 (prior to 638 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 639 register returns zero when it should return one. The workaround 640 corrects this value, ensuring cache maintenance operations which use 641 it behave as intended and avoiding data corruption. 642 643config ARM_ERRATA_720789 644 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 645 depends on CPU_V7 646 help 647 This option enables the workaround for the 720789 Cortex-A9 (prior to 648 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 649 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 650 As a consequence of this erratum, some TLB entries which should be 651 invalidated are not, resulting in an incoherency in the system page 652 tables. The workaround changes the TLB flushing routines to invalidate 653 entries regardless of the ASID. 654 655config ARM_ERRATA_743622 656 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 657 depends on CPU_V7 658 depends on !ARCH_MULTIPLATFORM 659 help 660 This option enables the workaround for the 743622 Cortex-A9 661 (r2p*) erratum. Under very rare conditions, a faulty 662 optimisation in the Cortex-A9 Store Buffer may lead to data 663 corruption. This workaround sets a specific bit in the diagnostic 664 register of the Cortex-A9 which disables the Store Buffer 665 optimisation, preventing the defect from occurring. This has no 666 visible impact on the overall performance or power consumption of the 667 processor. Note that setting specific bits in the diagnostics register 668 may not be available in non-secure mode and thus is not available on a 669 multiplatform kernel. This should be applied by the bootloader instead. 670 671config ARM_ERRATA_751472 672 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 673 depends on CPU_V7 674 depends on !ARCH_MULTIPLATFORM 675 help 676 This option enables the workaround for the 751472 Cortex-A9 (prior 677 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 678 completion of a following broadcasted operation if the second 679 operation is received by a CPU before the ICIALLUIS has completed, 680 potentially leading to corrupted entries in the cache or TLB. 681 Note that setting specific bits in the diagnostics register may 682 not be available in non-secure mode and thus is not available on 683 a multiplatform kernel. This should be applied by the bootloader 684 instead. 685 686config ARM_ERRATA_754322 687 bool "ARM errata: possible faulty MMU translations following an ASID switch" 688 depends on CPU_V7 689 help 690 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 691 r3p*) erratum. A speculative memory access may cause a page table walk 692 which starts prior to an ASID switch but completes afterwards. This 693 can populate the micro-TLB with a stale entry which may be hit with 694 the new ASID. This workaround places two dsb instructions in the mm 695 switching code so that no page table walks can cross the ASID switch. 696 697config ARM_ERRATA_754327 698 bool "ARM errata: no automatic Store Buffer drain" 699 depends on CPU_V7 && SMP 700 help 701 This option enables the workaround for the 754327 Cortex-A9 (prior to 702 r2p0) erratum. The Store Buffer does not have any automatic draining 703 mechanism and therefore a livelock may occur if an external agent 704 continuously polls a memory location waiting to observe an update. 705 This workaround defines cpu_relax() as smp_mb(), preventing correctly 706 written polling loops from denying visibility of updates to memory. 707 708config ARM_ERRATA_364296 709 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 710 depends on CPU_V6 711 help 712 This options enables the workaround for the 364296 ARM1136 713 r0p2 erratum (possible cache data corruption with 714 hit-under-miss enabled). It sets the undocumented bit 31 in 715 the auxiliary control register and the FI bit in the control 716 register, thus disabling hit-under-miss without putting the 717 processor into full low interrupt latency mode. ARM11MPCore 718 is not affected. 719 720config ARM_ERRATA_764369 721 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 722 depends on CPU_V7 && SMP 723 help 724 This option enables the workaround for erratum 764369 725 affecting Cortex-A9 MPCore with two or more processors (all 726 current revisions). Under certain timing circumstances, a data 727 cache line maintenance operation by MVA targeting an Inner 728 Shareable memory region may fail to proceed up to either the 729 Point of Coherency or to the Point of Unification of the 730 system. This workaround adds a DSB instruction before the 731 relevant cache maintenance functions and sets a specific bit 732 in the diagnostic control register of the SCU. 733 734config ARM_ERRATA_764319 735 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 736 depends on CPU_V7 737 help 738 This option enables the workaround for the 764319 Cortex A-9 erratum. 739 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 740 unexpected Undefined Instruction exception when the DBGSWENABLE 741 external pin is set to 0, even when the CP14 accesses are performed 742 from a privileged mode. This work around catches the exception in a 743 way the kernel does not stop execution. 744 745config ARM_ERRATA_775420 746 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 747 depends on CPU_V7 748 help 749 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 750 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 751 operation aborts with MMU exception, it might cause the processor 752 to deadlock. This workaround puts DSB before executing ISB if 753 an abort may occur on cache maintenance. 754 755config ARM_ERRATA_798181 756 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 757 depends on CPU_V7 && SMP 758 help 759 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 760 adequately shooting down all use of the old entries. This 761 option enables the Linux kernel workaround for this erratum 762 which sends an IPI to the CPUs that are running the same ASID 763 as the one being invalidated. 764 765config ARM_ERRATA_773022 766 bool "ARM errata: incorrect instructions may be executed from loop buffer" 767 depends on CPU_V7 768 help 769 This option enables the workaround for the 773022 Cortex-A15 770 (up to r0p4) erratum. In certain rare sequences of code, the 771 loop buffer may deliver incorrect instructions. This 772 workaround disables the loop buffer to avoid the erratum. 773 774config ARM_ERRATA_818325_852422 775 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 776 depends on CPU_V7 777 help 778 This option enables the workaround for: 779 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 780 instruction might deadlock. Fixed in r0p1. 781 - Cortex-A12 852422: Execution of a sequence of instructions might 782 lead to either a data corruption or a CPU deadlock. Not fixed in 783 any Cortex-A12 cores yet. 784 This workaround for all both errata involves setting bit[12] of the 785 Feature Register. This bit disables an optimisation applied to a 786 sequence of 2 instructions that use opposing condition codes. 787 788config ARM_ERRATA_821420 789 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 790 depends on CPU_V7 791 help 792 This option enables the workaround for the 821420 Cortex-A12 793 (all revs) erratum. In very rare timing conditions, a sequence 794 of VMOV to Core registers instructions, for which the second 795 one is in the shadow of a branch or abort, can lead to a 796 deadlock when the VMOV instructions are issued out-of-order. 797 798config ARM_ERRATA_825619 799 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 800 depends on CPU_V7 801 help 802 This option enables the workaround for the 825619 Cortex-A12 803 (all revs) erratum. Within rare timing constraints, executing a 804 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 805 and Device/Strongly-Ordered loads and stores might cause deadlock 806 807config ARM_ERRATA_857271 808 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 809 depends on CPU_V7 810 help 811 This option enables the workaround for the 857271 Cortex-A12 812 (all revs) erratum. Under very rare timing conditions, the CPU might 813 hang. The workaround is expected to have a < 1% performance impact. 814 815config ARM_ERRATA_852421 816 bool "ARM errata: A17: DMB ST might fail to create order between stores" 817 depends on CPU_V7 818 help 819 This option enables the workaround for the 852421 Cortex-A17 820 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 821 execution of a DMB ST instruction might fail to properly order 822 stores from GroupA and stores from GroupB. 823 824config ARM_ERRATA_852423 825 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 826 depends on CPU_V7 827 help 828 This option enables the workaround for: 829 - Cortex-A17 852423: Execution of a sequence of instructions might 830 lead to either a data corruption or a CPU deadlock. Not fixed in 831 any Cortex-A17 cores yet. 832 This is identical to Cortex-A12 erratum 852422. It is a separate 833 config option from the A12 erratum due to the way errata are checked 834 for and handled. 835 836config ARM_ERRATA_857272 837 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 838 depends on CPU_V7 839 help 840 This option enables the workaround for the 857272 Cortex-A17 erratum. 841 This erratum is not known to be fixed in any A17 revision. 842 This is identical to Cortex-A12 erratum 857271. It is a separate 843 config option from the A12 erratum due to the way errata are checked 844 for and handled. 845 846endmenu 847 848source "arch/arm/common/Kconfig" 849 850menu "Bus support" 851 852config ISA 853 bool 854 help 855 Find out whether you have ISA slots on your motherboard. ISA is the 856 name of a bus system, i.e. the way the CPU talks to the other stuff 857 inside your box. Other bus systems are PCI, EISA, MicroChannel 858 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 859 newer boards don't support it. If you have ISA, say Y, otherwise N. 860 861# Select ISA DMA interface 862config ISA_DMA_API 863 bool 864 865config ARM_ERRATA_814220 866 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 867 depends on CPU_V7 868 help 869 The v7 ARM states that all cache and branch predictor maintenance 870 operations that do not specify an address execute, relative to 871 each other, in program order. 872 However, because of this erratum, an L2 set/way cache maintenance 873 operation can overtake an L1 set/way cache maintenance operation. 874 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 875 r0p4, r0p5. 876 877endmenu 878 879menu "Kernel Features" 880 881config HAVE_SMP 882 bool 883 help 884 This option should be selected by machines which have an SMP- 885 capable CPU. 886 887 The only effect of this option is to make the SMP-related 888 options available to the user for configuration. 889 890config SMP 891 bool "Symmetric Multi-Processing" 892 depends on CPU_V6K || CPU_V7 893 depends on HAVE_SMP 894 depends on MMU || ARM_MPU 895 select IRQ_WORK 896 help 897 This enables support for systems with more than one CPU. If you have 898 a system with only one CPU, say N. If you have a system with more 899 than one CPU, say Y. 900 901 If you say N here, the kernel will run on uni- and multiprocessor 902 machines, but will use only one CPU of a multiprocessor machine. If 903 you say Y here, the kernel will run on many, but not all, 904 uniprocessor machines. On a uniprocessor machine, the kernel 905 will run faster if you say N here. 906 907 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 908 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 909 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 910 911 If you don't know what to do here, say N. 912 913config SMP_ON_UP 914 bool "Allow booting SMP kernel on uniprocessor systems" 915 depends on SMP && MMU 916 default y 917 help 918 SMP kernels contain instructions which fail on non-SMP processors. 919 Enabling this option allows the kernel to modify itself to make 920 these instructions safe. Disabling it allows about 1K of space 921 savings. 922 923 If you don't know what to do here, say Y. 924 925 926config CURRENT_POINTER_IN_TPIDRURO 927 def_bool y 928 depends on CPU_32v6K && !CPU_V6 929 930config IRQSTACKS 931 def_bool y 932 select HAVE_IRQ_EXIT_ON_IRQ_STACK 933 select HAVE_SOFTIRQ_ON_OWN_STACK 934 935config ARM_CPU_TOPOLOGY 936 bool "Support cpu topology definition" 937 depends on SMP && CPU_V7 938 default y 939 help 940 Support ARM cpu topology definition. The MPIDR register defines 941 affinity between processors which is then used to describe the cpu 942 topology of an ARM System. 943 944config SCHED_MC 945 bool "Multi-core scheduler support" 946 depends on ARM_CPU_TOPOLOGY 947 help 948 Multi-core scheduler support improves the CPU scheduler's decision 949 making when dealing with multi-core CPU chips at a cost of slightly 950 increased overhead in some places. If unsure say N here. 951 952config SCHED_SMT 953 bool "SMT scheduler support" 954 depends on ARM_CPU_TOPOLOGY 955 help 956 Improves the CPU scheduler's decision making when dealing with 957 MultiThreading at a cost of slightly increased overhead in some 958 places. If unsure say N here. 959 960config HAVE_ARM_SCU 961 bool 962 help 963 This option enables support for the ARM snoop control unit 964 965config HAVE_ARM_ARCH_TIMER 966 bool "Architected timer support" 967 depends on CPU_V7 968 select ARM_ARCH_TIMER 969 help 970 This option enables support for the ARM architected timer 971 972config HAVE_ARM_TWD 973 bool 974 help 975 This options enables support for the ARM timer and watchdog unit 976 977config MCPM 978 bool "Multi-Cluster Power Management" 979 depends on CPU_V7 && SMP 980 help 981 This option provides the common power management infrastructure 982 for (multi-)cluster based systems, such as big.LITTLE based 983 systems. 984 985config MCPM_QUAD_CLUSTER 986 bool 987 depends on MCPM 988 help 989 To avoid wasting resources unnecessarily, MCPM only supports up 990 to 2 clusters by default. 991 Platforms with 3 or 4 clusters that use MCPM must select this 992 option to allow the additional clusters to be managed. 993 994config BIG_LITTLE 995 bool "big.LITTLE support (Experimental)" 996 depends on CPU_V7 && SMP 997 select MCPM 998 help 999 This option enables support selections for the big.LITTLE 1000 system architecture. 1001 1002config BL_SWITCHER 1003 bool "big.LITTLE switcher support" 1004 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1005 select CPU_PM 1006 help 1007 The big.LITTLE "switcher" provides the core functionality to 1008 transparently handle transition between a cluster of A15's 1009 and a cluster of A7's in a big.LITTLE system. 1010 1011config BL_SWITCHER_DUMMY_IF 1012 tristate "Simple big.LITTLE switcher user interface" 1013 depends on BL_SWITCHER && DEBUG_KERNEL 1014 help 1015 This is a simple and dummy char dev interface to control 1016 the big.LITTLE switcher core code. It is meant for 1017 debugging purposes only. 1018 1019choice 1020 prompt "Memory split" 1021 depends on MMU 1022 default VMSPLIT_3G 1023 help 1024 Select the desired split between kernel and user memory. 1025 1026 If you are not absolutely sure what you are doing, leave this 1027 option alone! 1028 1029 config VMSPLIT_3G 1030 bool "3G/1G user/kernel split" 1031 config VMSPLIT_3G_OPT 1032 depends on !ARM_LPAE 1033 bool "3G/1G user/kernel split (for full 1G low memory)" 1034 config VMSPLIT_2G 1035 bool "2G/2G user/kernel split" 1036 config VMSPLIT_1G 1037 bool "1G/3G user/kernel split" 1038endchoice 1039 1040config PAGE_OFFSET 1041 hex 1042 default PHYS_OFFSET if !MMU 1043 default 0x40000000 if VMSPLIT_1G 1044 default 0x80000000 if VMSPLIT_2G 1045 default 0xB0000000 if VMSPLIT_3G_OPT 1046 default 0xC0000000 1047 1048config KASAN_SHADOW_OFFSET 1049 hex 1050 depends on KASAN 1051 default 0x1f000000 if PAGE_OFFSET=0x40000000 1052 default 0x5f000000 if PAGE_OFFSET=0x80000000 1053 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1054 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1055 default 0xffffffff 1056 1057config NR_CPUS 1058 int "Maximum number of CPUs (2-32)" 1059 range 2 16 if DEBUG_KMAP_LOCAL 1060 range 2 32 if !DEBUG_KMAP_LOCAL 1061 depends on SMP 1062 default "4" 1063 help 1064 The maximum number of CPUs that the kernel can support. 1065 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1066 debugging is enabled, which uses half of the per-CPU fixmap 1067 slots as guard regions. 1068 1069config HOTPLUG_CPU 1070 bool "Support for hot-pluggable CPUs" 1071 depends on SMP 1072 select GENERIC_IRQ_MIGRATION 1073 help 1074 Say Y here to experiment with turning CPUs off and on. CPUs 1075 can be controlled through /sys/devices/system/cpu. 1076 1077config ARM_PSCI 1078 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1079 depends on HAVE_ARM_SMCCC 1080 select ARM_PSCI_FW 1081 help 1082 Say Y here if you want Linux to communicate with system firmware 1083 implementing the PSCI specification for CPU-centric power 1084 management operations described in ARM document number ARM DEN 1085 0022A ("Power State Coordination Interface System Software on 1086 ARM processors"). 1087 1088config HZ_FIXED 1089 int 1090 default 128 if SOC_AT91RM9200 1091 default 0 1092 1093choice 1094 depends on HZ_FIXED = 0 1095 prompt "Timer frequency" 1096 1097config HZ_100 1098 bool "100 Hz" 1099 1100config HZ_200 1101 bool "200 Hz" 1102 1103config HZ_250 1104 bool "250 Hz" 1105 1106config HZ_300 1107 bool "300 Hz" 1108 1109config HZ_500 1110 bool "500 Hz" 1111 1112config HZ_1000 1113 bool "1000 Hz" 1114 1115endchoice 1116 1117config HZ 1118 int 1119 default HZ_FIXED if HZ_FIXED != 0 1120 default 100 if HZ_100 1121 default 200 if HZ_200 1122 default 250 if HZ_250 1123 default 300 if HZ_300 1124 default 500 if HZ_500 1125 default 1000 1126 1127config SCHED_HRTICK 1128 def_bool HIGH_RES_TIMERS 1129 1130config THUMB2_KERNEL 1131 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1132 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1133 default y if CPU_THUMBONLY 1134 select ARM_UNWIND 1135 help 1136 By enabling this option, the kernel will be compiled in 1137 Thumb-2 mode. 1138 1139 If unsure, say N. 1140 1141config ARM_PATCH_IDIV 1142 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1143 depends on CPU_32v7 1144 default y 1145 help 1146 The ARM compiler inserts calls to __aeabi_idiv() and 1147 __aeabi_uidiv() when it needs to perform division on signed 1148 and unsigned integers. Some v7 CPUs have support for the sdiv 1149 and udiv instructions that can be used to implement those 1150 functions. 1151 1152 Enabling this option allows the kernel to modify itself to 1153 replace the first two instructions of these library functions 1154 with the sdiv or udiv plus "bx lr" instructions when the CPU 1155 it is running on supports them. Typically this will be faster 1156 and less power intensive than running the original library 1157 code to do integer division. 1158 1159config AEABI 1160 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1161 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1162 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1163 help 1164 This option allows for the kernel to be compiled using the latest 1165 ARM ABI (aka EABI). This is only useful if you are using a user 1166 space environment that is also compiled with EABI. 1167 1168 Since there are major incompatibilities between the legacy ABI and 1169 EABI, especially with regard to structure member alignment, this 1170 option also changes the kernel syscall calling convention to 1171 disambiguate both ABIs and allow for backward compatibility support 1172 (selected with CONFIG_OABI_COMPAT). 1173 1174 To use this you need GCC version 4.0.0 or later. 1175 1176config OABI_COMPAT 1177 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1178 depends on AEABI && !THUMB2_KERNEL 1179 help 1180 This option preserves the old syscall interface along with the 1181 new (ARM EABI) one. It also provides a compatibility layer to 1182 intercept syscalls that have structure arguments which layout 1183 in memory differs between the legacy ABI and the new ARM EABI 1184 (only for non "thumb" binaries). This option adds a tiny 1185 overhead to all syscalls and produces a slightly larger kernel. 1186 1187 The seccomp filter system will not be available when this is 1188 selected, since there is no way yet to sensibly distinguish 1189 between calling conventions during filtering. 1190 1191 If you know you'll be using only pure EABI user space then you 1192 can say N here. If this option is not selected and you attempt 1193 to execute a legacy ABI binary then the result will be 1194 UNPREDICTABLE (in fact it can be predicted that it won't work 1195 at all). If in doubt say N. 1196 1197config ARCH_SELECT_MEMORY_MODEL 1198 def_bool y 1199 1200config ARCH_FLATMEM_ENABLE 1201 def_bool !(ARCH_RPC || ARCH_SA1100) 1202 1203config ARCH_SPARSEMEM_ENABLE 1204 def_bool !ARCH_FOOTBRIDGE 1205 select SPARSEMEM_STATIC if SPARSEMEM 1206 1207config HIGHMEM 1208 bool "High Memory Support" 1209 depends on MMU 1210 select KMAP_LOCAL 1211 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1212 help 1213 The address space of ARM processors is only 4 Gigabytes large 1214 and it has to accommodate user address space, kernel address 1215 space as well as some memory mapped IO. That means that, if you 1216 have a large amount of physical memory and/or IO, not all of the 1217 memory can be "permanently mapped" by the kernel. The physical 1218 memory that is not permanently mapped is called "high memory". 1219 1220 Depending on the selected kernel/user memory split, minimum 1221 vmalloc space and actual amount of RAM, you may not need this 1222 option which should result in a slightly faster kernel. 1223 1224 If unsure, say n. 1225 1226config HIGHPTE 1227 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1228 depends on HIGHMEM 1229 default y 1230 help 1231 The VM uses one page of physical memory for each page table. 1232 For systems with a lot of processes, this can use a lot of 1233 precious low memory, eventually leading to low memory being 1234 consumed by page tables. Setting this option will allow 1235 user-space 2nd level page tables to reside in high memory. 1236 1237config ARM_PAN 1238 bool "Enable privileged no-access" 1239 depends on MMU 1240 default y 1241 help 1242 Increase kernel security by ensuring that normal kernel accesses 1243 are unable to access userspace addresses. This can help prevent 1244 use-after-free bugs becoming an exploitable privilege escalation 1245 by ensuring that magic values (such as LIST_POISON) will always 1246 fault when dereferenced. 1247 1248 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1249 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1250 1251config CPU_SW_DOMAIN_PAN 1252 def_bool y 1253 depends on ARM_PAN && !ARM_LPAE 1254 help 1255 Enable use of CPU domains to implement privileged no-access. 1256 1257 CPUs with low-vector mappings use a best-efforts implementation. 1258 Their lower 1MB needs to remain accessible for the vectors, but 1259 the remainder of userspace will become appropriately inaccessible. 1260 1261config CPU_TTBR0_PAN 1262 def_bool y 1263 depends on ARM_PAN && ARM_LPAE 1264 help 1265 Enable privileged no-access by disabling TTBR0 page table walks when 1266 running in kernel mode. 1267 1268config HW_PERF_EVENTS 1269 def_bool y 1270 depends on ARM_PMU 1271 1272config ARM_MODULE_PLTS 1273 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1274 depends on MODULES 1275 select KASAN_VMALLOC if KASAN 1276 default y 1277 help 1278 Allocate PLTs when loading modules so that jumps and calls whose 1279 targets are too far away for their relative offsets to be encoded 1280 in the instructions themselves can be bounced via veneers in the 1281 module's PLT. This allows modules to be allocated in the generic 1282 vmalloc area after the dedicated module memory area has been 1283 exhausted. The modules will use slightly more memory, but after 1284 rounding up to page size, the actual memory footprint is usually 1285 the same. 1286 1287 Disabling this is usually safe for small single-platform 1288 configurations. If unsure, say y. 1289 1290config ARCH_FORCE_MAX_ORDER 1291 int "Order of maximal physically contiguous allocations" 1292 default "11" if SOC_AM33XX 1293 default "8" if SA1111 1294 default "10" 1295 help 1296 The kernel page allocator limits the size of maximal physically 1297 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1298 defines the maximal power of two of number of pages that can be 1299 allocated as a single contiguous block. This option allows 1300 overriding the default setting when ability to allocate very 1301 large blocks of physically contiguous memory is required. 1302 1303 Don't change if unsure. 1304 1305config ALIGNMENT_TRAP 1306 def_bool CPU_CP15_MMU 1307 select HAVE_PROC_CPU if PROC_FS 1308 help 1309 ARM processors cannot fetch/store information which is not 1310 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1311 address divisible by 4. On 32-bit ARM processors, these non-aligned 1312 fetch/store instructions will be emulated in software if you say 1313 here, which has a severe performance impact. This is necessary for 1314 correct operation of some network protocols. With an IP-only 1315 configuration it is safe to say N, otherwise say Y. 1316 1317config UACCESS_WITH_MEMCPY 1318 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1319 depends on MMU 1320 default y if CPU_FEROCEON 1321 help 1322 Implement faster copy_to_user and clear_user methods for CPU 1323 cores where a 8-word STM instruction give significantly higher 1324 memory write throughput than a sequence of individual 32bit stores. 1325 1326 A possible side effect is a slight increase in scheduling latency 1327 between threads sharing the same address space if they invoke 1328 such copy operations with large buffers. 1329 1330 However, if the CPU data cache is using a write-allocate mode, 1331 this option is unlikely to provide any performance gain. 1332 1333config PARAVIRT 1334 bool "Enable paravirtualization code" 1335 help 1336 This changes the kernel so it can modify itself when it is run 1337 under a hypervisor, potentially improving performance significantly 1338 over full virtualization. 1339 1340config PARAVIRT_TIME_ACCOUNTING 1341 bool "Paravirtual steal time accounting" 1342 select PARAVIRT 1343 help 1344 Select this option to enable fine granularity task steal time 1345 accounting. Time spent executing other tasks in parallel with 1346 the current vCPU is discounted from the vCPU power. To account for 1347 that, there can be a small performance impact. 1348 1349 If in doubt, say N here. 1350 1351config XEN_DOM0 1352 def_bool y 1353 depends on XEN 1354 1355config XEN 1356 bool "Xen guest support on ARM" 1357 depends on ARM && AEABI && OF 1358 depends on CPU_V7 && !CPU_V6 1359 depends on !GENERIC_ATOMIC64 1360 depends on MMU 1361 select ARCH_DMA_ADDR_T_64BIT 1362 select ARM_PSCI 1363 select SWIOTLB 1364 select SWIOTLB_XEN 1365 select PARAVIRT 1366 help 1367 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1368 1369config CC_HAVE_STACKPROTECTOR_TLS 1370 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1371 1372config STACKPROTECTOR_PER_TASK 1373 bool "Use a unique stack canary value for each task" 1374 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1375 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1376 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1377 default y 1378 help 1379 Due to the fact that GCC uses an ordinary symbol reference from 1380 which to load the value of the stack canary, this value can only 1381 change at reboot time on SMP systems, and all tasks running in the 1382 kernel's address space are forced to use the same canary value for 1383 the entire duration that the system is up. 1384 1385 Enable this option to switch to a different method that uses a 1386 different canary value for each task. 1387 1388endmenu 1389 1390menu "Boot options" 1391 1392config USE_OF 1393 bool "Flattened Device Tree support" 1394 select IRQ_DOMAIN 1395 select OF 1396 help 1397 Include support for flattened device tree machine descriptions. 1398 1399config ARCH_WANT_FLAT_DTB_INSTALL 1400 def_bool y 1401 1402config ATAGS 1403 bool "Support for the traditional ATAGS boot data passing" 1404 default y 1405 help 1406 This is the traditional way of passing data to the kernel at boot 1407 time. If you are solely relying on the flattened device tree (or 1408 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1409 to remove ATAGS support from your kernel binary. 1410 1411config DEPRECATED_PARAM_STRUCT 1412 bool "Provide old way to pass kernel parameters" 1413 depends on ATAGS 1414 help 1415 This was deprecated in 2001 and announced to live on for 5 years. 1416 Some old boot loaders still use this way. 1417 1418# Compressed boot loader in ROM. Yes, we really want to ask about 1419# TEXT and BSS so we preserve their values in the config files. 1420config ZBOOT_ROM_TEXT 1421 hex "Compressed ROM boot loader base address" 1422 default 0x0 1423 help 1424 The physical address at which the ROM-able zImage is to be 1425 placed in the target. Platforms which normally make use of 1426 ROM-able zImage formats normally set this to a suitable 1427 value in their defconfig file. 1428 1429 If ZBOOT_ROM is not enabled, this has no effect. 1430 1431config ZBOOT_ROM_BSS 1432 hex "Compressed ROM boot loader BSS address" 1433 default 0x0 1434 help 1435 The base address of an area of read/write memory in the target 1436 for the ROM-able zImage which must be available while the 1437 decompressor is running. It must be large enough to hold the 1438 entire decompressed kernel plus an additional 128 KiB. 1439 Platforms which normally make use of ROM-able zImage formats 1440 normally set this to a suitable value in their defconfig file. 1441 1442 If ZBOOT_ROM is not enabled, this has no effect. 1443 1444config ZBOOT_ROM 1445 bool "Compressed boot loader in ROM/flash" 1446 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1447 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1448 help 1449 Say Y here if you intend to execute your compressed kernel image 1450 (zImage) directly from ROM or flash. If unsure, say N. 1451 1452config ARM_APPENDED_DTB 1453 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1454 depends on OF 1455 help 1456 With this option, the boot code will look for a device tree binary 1457 (DTB) appended to zImage 1458 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1459 1460 This is meant as a backward compatibility convenience for those 1461 systems with a bootloader that can't be upgraded to accommodate 1462 the documented boot protocol using a device tree. 1463 1464 Beware that there is very little in terms of protection against 1465 this option being confused by leftover garbage in memory that might 1466 look like a DTB header after a reboot if no actual DTB is appended 1467 to zImage. Do not leave this option active in a production kernel 1468 if you don't intend to always append a DTB. Proper passing of the 1469 location into r2 of a bootloader provided DTB is always preferable 1470 to this option. 1471 1472config ARM_ATAG_DTB_COMPAT 1473 bool "Supplement the appended DTB with traditional ATAG information" 1474 depends on ARM_APPENDED_DTB 1475 help 1476 Some old bootloaders can't be updated to a DTB capable one, yet 1477 they provide ATAGs with memory configuration, the ramdisk address, 1478 the kernel cmdline string, etc. Such information is dynamically 1479 provided by the bootloader and can't always be stored in a static 1480 DTB. To allow a device tree enabled kernel to be used with such 1481 bootloaders, this option allows zImage to extract the information 1482 from the ATAG list and store it at run time into the appended DTB. 1483 1484choice 1485 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1486 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1487 1488config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1489 bool "Use bootloader kernel arguments if available" 1490 help 1491 Uses the command-line options passed by the boot loader instead of 1492 the device tree bootargs property. If the boot loader doesn't provide 1493 any, the device tree bootargs property will be used. 1494 1495config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1496 bool "Extend with bootloader kernel arguments" 1497 help 1498 The command-line arguments provided by the boot loader will be 1499 appended to the the device tree bootargs property. 1500 1501endchoice 1502 1503config CMDLINE 1504 string "Default kernel command string" 1505 default "" 1506 help 1507 On some architectures (e.g. CATS), there is currently no way 1508 for the boot loader to pass arguments to the kernel. For these 1509 architectures, you should supply some command-line options at build 1510 time by entering them here. As a minimum, you should specify the 1511 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1512 1513choice 1514 prompt "Kernel command line type" if CMDLINE != "" 1515 default CMDLINE_FROM_BOOTLOADER 1516 1517config CMDLINE_FROM_BOOTLOADER 1518 bool "Use bootloader kernel arguments if available" 1519 help 1520 Uses the command-line options passed by the boot loader. If 1521 the boot loader doesn't provide any, the default kernel command 1522 string provided in CMDLINE will be used. 1523 1524config CMDLINE_EXTEND 1525 bool "Extend bootloader kernel arguments" 1526 help 1527 The command-line arguments provided by the boot loader will be 1528 appended to the default kernel command string. 1529 1530config CMDLINE_FORCE 1531 bool "Always use the default kernel command string" 1532 help 1533 Always use the default kernel command string, even if the boot 1534 loader passes other arguments to the kernel. 1535 This is useful if you cannot or don't want to change the 1536 command-line options your boot loader passes to the kernel. 1537endchoice 1538 1539config XIP_KERNEL 1540 bool "Kernel Execute-In-Place from ROM" 1541 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1542 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1543 help 1544 Execute-In-Place allows the kernel to run from non-volatile storage 1545 directly addressable by the CPU, such as NOR flash. This saves RAM 1546 space since the text section of the kernel is not loaded from flash 1547 to RAM. Read-write sections, such as the data section and stack, 1548 are still copied to RAM. The XIP kernel is not compressed since 1549 it has to run directly from flash, so it will take more space to 1550 store it. The flash address used to link the kernel object files, 1551 and for storing it, is configuration dependent. Therefore, if you 1552 say Y here, you must know the proper physical address where to 1553 store the kernel image depending on your own flash memory usage. 1554 1555 Also note that the make target becomes "make xipImage" rather than 1556 "make zImage" or "make Image". The final kernel binary to put in 1557 ROM memory will be arch/arm/boot/xipImage. 1558 1559 If unsure, say N. 1560 1561config XIP_PHYS_ADDR 1562 hex "XIP Kernel Physical Location" 1563 depends on XIP_KERNEL 1564 default "0x00080000" 1565 help 1566 This is the physical address in your flash memory the kernel will 1567 be linked for and stored to. This address is dependent on your 1568 own flash usage. 1569 1570config XIP_DEFLATED_DATA 1571 bool "Store kernel .data section compressed in ROM" 1572 depends on XIP_KERNEL 1573 select ZLIB_INFLATE 1574 help 1575 Before the kernel is actually executed, its .data section has to be 1576 copied to RAM from ROM. This option allows for storing that data 1577 in compressed form and decompressed to RAM rather than merely being 1578 copied, saving some precious ROM space. A possible drawback is a 1579 slightly longer boot delay. 1580 1581config ARCH_SUPPORTS_KEXEC 1582 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1583 1584config ATAGS_PROC 1585 bool "Export atags in procfs" 1586 depends on ATAGS && KEXEC 1587 default y 1588 help 1589 Should the atags used to boot the kernel be exported in an "atags" 1590 file in procfs. Useful with kexec. 1591 1592config ARCH_SUPPORTS_CRASH_DUMP 1593 def_bool y 1594 1595config AUTO_ZRELADDR 1596 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1597 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1598 help 1599 ZRELADDR is the physical address where the decompressed kernel 1600 image will be placed. If AUTO_ZRELADDR is selected, the address 1601 will be determined at run-time, either by masking the current IP 1602 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1603 This assumes the zImage being placed in the first 128MB from 1604 start of memory. 1605 1606config EFI_STUB 1607 bool 1608 1609config EFI 1610 bool "UEFI runtime support" 1611 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1612 select UCS2_STRING 1613 select EFI_PARAMS_FROM_FDT 1614 select EFI_STUB 1615 select EFI_GENERIC_STUB 1616 select EFI_RUNTIME_WRAPPERS 1617 help 1618 This option provides support for runtime services provided 1619 by UEFI firmware (such as non-volatile variables, realtime 1620 clock, and platform reset). A UEFI stub is also provided to 1621 allow the kernel to be booted as an EFI application. This 1622 is only useful for kernels that may run on systems that have 1623 UEFI firmware. 1624 1625config DMI 1626 bool "Enable support for SMBIOS (DMI) tables" 1627 depends on EFI 1628 default y 1629 help 1630 This enables SMBIOS/DMI feature for systems. 1631 1632 This option is only useful on systems that have UEFI firmware. 1633 However, even with this option, the resultant kernel should 1634 continue to boot on existing non-UEFI platforms. 1635 1636 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1637 i.e., the the practice of identifying the platform via DMI to 1638 decide whether certain workarounds for buggy hardware and/or 1639 firmware need to be enabled. This would require the DMI subsystem 1640 to be enabled much earlier than we do on ARM, which is non-trivial. 1641 1642endmenu 1643 1644menu "CPU Power Management" 1645 1646source "drivers/cpufreq/Kconfig" 1647 1648source "drivers/cpuidle/Kconfig" 1649 1650endmenu 1651 1652menu "Floating point emulation" 1653 1654comment "At least one emulation must be selected" 1655 1656config FPE_NWFPE 1657 bool "NWFPE math emulation" 1658 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1659 help 1660 Say Y to include the NWFPE floating point emulator in the kernel. 1661 This is necessary to run most binaries. Linux does not currently 1662 support floating point hardware so you need to say Y here even if 1663 your machine has an FPA or floating point co-processor podule. 1664 1665 You may say N here if you are going to load the Acorn FPEmulator 1666 early in the bootup. 1667 1668config FPE_NWFPE_XP 1669 bool "Support extended precision" 1670 depends on FPE_NWFPE 1671 help 1672 Say Y to include 80-bit support in the kernel floating-point 1673 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1674 Note that gcc does not generate 80-bit operations by default, 1675 so in most cases this option only enlarges the size of the 1676 floating point emulator without any good reason. 1677 1678 You almost surely want to say N here. 1679 1680config FPE_FASTFPE 1681 bool "FastFPE math emulation (EXPERIMENTAL)" 1682 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1683 help 1684 Say Y here to include the FAST floating point emulator in the kernel. 1685 This is an experimental much faster emulator which now also has full 1686 precision for the mantissa. It does not support any exceptions. 1687 It is very simple, and approximately 3-6 times faster than NWFPE. 1688 1689 It should be sufficient for most programs. It may be not suitable 1690 for scientific calculations, but you have to check this for yourself. 1691 If you do not feel you need a faster FP emulation you should better 1692 choose NWFPE. 1693 1694config VFP 1695 bool "VFP-format floating point maths" 1696 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1697 help 1698 Say Y to include VFP support code in the kernel. This is needed 1699 if your hardware includes a VFP unit. 1700 1701 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1702 release notes and additional status information. 1703 1704 Say N if your target does not have VFP hardware. 1705 1706config VFPv3 1707 bool 1708 depends on VFP 1709 default y if CPU_V7 1710 1711config NEON 1712 bool "Advanced SIMD (NEON) Extension support" 1713 depends on VFPv3 && CPU_V7 1714 help 1715 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1716 Extension. 1717 1718config KERNEL_MODE_NEON 1719 bool "Support for NEON in kernel mode" 1720 depends on NEON && AEABI 1721 help 1722 Say Y to include support for NEON in kernel mode. 1723 1724endmenu 1725 1726menu "Power management options" 1727 1728source "kernel/power/Kconfig" 1729 1730config ARCH_SUSPEND_POSSIBLE 1731 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1732 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1733 def_bool y 1734 1735config ARM_CPU_SUSPEND 1736 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1737 depends on ARCH_SUSPEND_POSSIBLE 1738 1739config ARCH_HIBERNATION_POSSIBLE 1740 bool 1741 depends on MMU 1742 default y if ARCH_SUSPEND_POSSIBLE 1743 1744endmenu 1745 1746source "arch/arm/Kconfig.assembler" 1747