1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_USE_MEMTEST 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_IPC_PARSE_VERSION 40 select ARCH_WANT_LD_ORPHAN_WARN 41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 42 select BUILDTIME_TABLE_SORT if MMU 43 select CLONE_BACKWARDS 44 select CPU_PM if SUSPEND || CPU_IDLE 45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 46 select DMA_DECLARE_COHERENT 47 select DMA_OPS 48 select DMA_REMAP if MMU 49 select EDAC_SUPPORT 50 select EDAC_ATOMIC_SCRUB 51 select GENERIC_ALLOCATOR 52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 55 select GENERIC_IRQ_IPI if SMP 56 select GENERIC_CPU_AUTOPROBE 57 select GENERIC_EARLY_IOREMAP 58 select GENERIC_IDLE_POLL_SETUP 59 select GENERIC_IRQ_PROBE 60 select GENERIC_IRQ_SHOW 61 select GENERIC_IRQ_SHOW_LEVEL 62 select GENERIC_LIB_DEVMEM_IS_ALLOWED 63 select GENERIC_PCI_IOMAP 64 select GENERIC_SCHED_CLOCK 65 select GENERIC_SMP_IDLE_THREAD 66 select GENERIC_STRNCPY_FROM_USER 67 select GENERIC_STRNLEN_USER 68 select HANDLE_DOMAIN_IRQ 69 select HARDIRQS_SW_RESEND 70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 87 select HAVE_DMA_CONTIGUOUS if MMU 88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 91 select HAVE_EXIT_THREAD 92 select HAVE_FAST_GUP if ARM_LPAE 93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IDE if PCI || ISA || PCMCIA 99 select HAVE_IRQ_TIME_ACCOUNTING 100 select HAVE_KERNEL_GZIP 101 select HAVE_KERNEL_LZ4 102 select HAVE_KERNEL_LZMA 103 select HAVE_KERNEL_LZO 104 select HAVE_KERNEL_XZ 105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 106 select HAVE_KRETPROBES if HAVE_KPROBES 107 select HAVE_MOD_ARCH_SPECIFIC 108 select HAVE_NMI 109 select HAVE_OPTPROBES if !THUMB2_KERNEL 110 select HAVE_PERF_EVENTS 111 select HAVE_PERF_REGS 112 select HAVE_PERF_USER_STACK_DUMP 113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 114 select HAVE_REGS_AND_STACK_ACCESS_API 115 select HAVE_RSEQ 116 select HAVE_STACKPROTECTOR 117 select HAVE_SYSCALL_TRACEPOINTS 118 select HAVE_UID16 119 select HAVE_VIRT_CPU_ACCOUNTING_GEN 120 select IRQ_FORCED_THREADING 121 select MODULES_USE_ELF_REL 122 select NEED_DMA_MAP_STATE 123 select OF_EARLY_FLATTREE if OF 124 select OLD_SIGACTION 125 select OLD_SIGSUSPEND3 126 select PCI_SYSCALL if PCI 127 select PERF_USE_VMALLOC 128 select RTC_LIB 129 select SET_FS 130 select SYS_SUPPORTS_APM_EMULATION 131 # Above selects are sorted alphabetically; please add new ones 132 # according to that. Thanks. 133 help 134 The ARM series is a line of low-power-consumption RISC chip designs 135 licensed by ARM Ltd and targeted at embedded applications and 136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 137 manufactured, but legacy ARM-based PC hardware remains popular in 138 Europe. There is an ARM Linux project with a web page at 139 <http://www.arm.linux.org.uk/>. 140 141config ARM_HAS_SG_CHAIN 142 bool 143 144config ARM_DMA_USE_IOMMU 145 bool 146 select ARM_HAS_SG_CHAIN 147 select NEED_SG_DMA_LENGTH 148 149if ARM_DMA_USE_IOMMU 150 151config ARM_DMA_IOMMU_ALIGNMENT 152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 153 range 4 9 154 default 8 155 help 156 DMA mapping framework by default aligns all buffers to the smallest 157 PAGE_SIZE order which is greater than or equal to the requested buffer 158 size. This works well for buffers up to a few hundreds kilobytes, but 159 for larger buffers it just a waste of address space. Drivers which has 160 relatively small addressing window (like 64Mib) might run out of 161 virtual space with just a few allocations. 162 163 With this parameter you can specify the maximum PAGE_SIZE order for 164 DMA IOMMU buffers. Larger buffers will be aligned only to this 165 specified order. The order is expressed as a power of two multiplied 166 by the PAGE_SIZE. 167 168endif 169 170config SYS_SUPPORTS_APM_EMULATION 171 bool 172 173config HAVE_TCM 174 bool 175 select GENERIC_ALLOCATOR 176 177config HAVE_PROC_CPU 178 bool 179 180config NO_IOPORT_MAP 181 bool 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config ARCH_HAS_ILOG2_U32 199 bool 200 201config ARCH_HAS_ILOG2_U64 202 bool 203 204config ARCH_HAS_BANDGAP 205 bool 206 207config FIX_EARLYCON_MEM 208 def_bool y if MMU 209 210config GENERIC_HWEIGHT 211 bool 212 default y 213 214config GENERIC_CALIBRATE_DELAY 215 bool 216 default y 217 218config ARCH_MAY_HAVE_PC_FDC 219 bool 220 221config ARCH_SUPPORTS_UPROBES 222 def_bool y 223 224config ARCH_HAS_DMA_SET_COHERENT_MASK 225 bool 226 227config GENERIC_ISA_DMA 228 bool 229 230config FIQ 231 bool 232 233config NEED_RET_TO_USER 234 bool 235 236config ARCH_MTD_XIP 237 bool 238 239config ARM_PATCH_PHYS_VIRT 240 bool "Patch physical to virtual translations at runtime" if EMBEDDED 241 default y 242 depends on !XIP_KERNEL && MMU 243 help 244 Patch phys-to-virt and virt-to-phys translation functions at 245 boot and module load time according to the position of the 246 kernel in system memory. 247 248 This can only be used with non-XIP MMU kernels where the base 249 of physical memory is at a 2 MiB boundary. 250 251 Only disable this option if you know that you do not require 252 this feature (eg, building a kernel for a single machine) and 253 you need to shrink the kernel to the minimal size. 254 255config NEED_MACH_IO_H 256 bool 257 help 258 Select this when mach/io.h is required to provide special 259 definitions for this platform. The need for mach/io.h should 260 be avoided when possible. 261 262config NEED_MACH_MEMORY_H 263 bool 264 help 265 Select this when mach/memory.h is required to provide special 266 definitions for this platform. The need for mach/memory.h should 267 be avoided when possible. 268 269config PHYS_OFFSET 270 hex "Physical address of main memory" if MMU 271 depends on !ARM_PATCH_PHYS_VIRT 272 default DRAM_BASE if !MMU 273 default 0x00000000 if ARCH_FOOTBRIDGE 274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 275 default 0x20000000 if ARCH_S5PV210 276 default 0xc0000000 if ARCH_SA1100 277 help 278 Please provide the physical address corresponding to the 279 location of main memory in your system. 280 281config GENERIC_BUG 282 def_bool y 283 depends on BUG 284 285config PGTABLE_LEVELS 286 int 287 default 3 if ARM_LPAE 288 default 2 289 290menu "System Type" 291 292config MMU 293 bool "MMU-based Paged Memory Management Support" 294 default y 295 help 296 Select if you want MMU-based virtualised addressing space 297 support by paged memory management. If unsure, say 'Y'. 298 299config ARCH_MMAP_RND_BITS_MIN 300 default 8 301 302config ARCH_MMAP_RND_BITS_MAX 303 default 14 if PAGE_OFFSET=0x40000000 304 default 15 if PAGE_OFFSET=0x80000000 305 default 16 306 307# 308# The "ARM system type" choice list is ordered alphabetically by option 309# text. Please add new entries in the option alphabetic order. 310# 311choice 312 prompt "ARM system type" 313 default ARM_SINGLE_ARMV7M if !MMU 314 default ARCH_MULTIPLATFORM if MMU 315 316config ARCH_MULTIPLATFORM 317 bool "Allow multiple platforms to be selected" 318 depends on MMU 319 select ARCH_FLATMEM_ENABLE 320 select ARCH_SPARSEMEM_ENABLE 321 select ARCH_SELECT_MEMORY_MODEL 322 select ARM_HAS_SG_CHAIN 323 select ARM_PATCH_PHYS_VIRT 324 select AUTO_ZRELADDR 325 select TIMER_OF 326 select COMMON_CLK 327 select GENERIC_IRQ_MULTI_HANDLER 328 select HAVE_PCI 329 select PCI_DOMAINS_GENERIC if PCI 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARM_NVIC 337 select AUTO_ZRELADDR 338 select TIMER_OF 339 select COMMON_CLK 340 select CPU_V7M 341 select NO_IOPORT_MAP 342 select SPARSE_IRQ 343 select USE_OF 344 345config ARCH_EP93XX 346 bool "EP93xx-based" 347 select ARCH_SPARSEMEM_ENABLE 348 select ARM_AMBA 349 imply ARM_PATCH_PHYS_VIRT 350 select ARM_VIC 351 select GENERIC_IRQ_MULTI_HANDLER 352 select AUTO_ZRELADDR 353 select CLKSRC_MMIO 354 select CPU_ARM920T 355 select GPIOLIB 356 select HAVE_LEGACY_CLK 357 help 358 This enables support for the Cirrus EP93xx series of CPUs. 359 360config ARCH_FOOTBRIDGE 361 bool "FootBridge" 362 select CPU_SA110 363 select FOOTBRIDGE 364 select HAVE_IDE 365 select NEED_MACH_IO_H if !MMU 366 select NEED_MACH_MEMORY_H 367 help 368 Support for systems based on the DC21285 companion chip 369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 370 371config ARCH_IOP32X 372 bool "IOP32x-based" 373 depends on MMU 374 select CPU_XSCALE 375 select GPIO_IOP 376 select GPIOLIB 377 select NEED_RET_TO_USER 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 depends on MMU 387 select ARCH_HAS_DMA_SET_COHERENT_MASK 388 select ARCH_SUPPORTS_BIG_ENDIAN 389 select CPU_XSCALE 390 select DMABOUNCE if PCI 391 select GENERIC_IRQ_MULTI_HANDLER 392 select GPIO_IXP4XX 393 select GPIOLIB 394 select HAVE_PCI 395 select IXP4XX_IRQ 396 select IXP4XX_TIMER 397 select NEED_MACH_IO_H 398 select USB_EHCI_BIG_ENDIAN_DESC 399 select USB_EHCI_BIG_ENDIAN_MMIO 400 help 401 Support for Intel's IXP4XX (XScale) family of processors. 402 403config ARCH_DOVE 404 bool "Marvell Dove" 405 select CPU_PJ4 406 select GENERIC_IRQ_MULTI_HANDLER 407 select GPIOLIB 408 select HAVE_PCI 409 select MVEBU_MBUS 410 select PINCTRL 411 select PINCTRL_DOVE 412 select PLAT_ORION_LEGACY 413 select SPARSE_IRQ 414 select PM_GENERIC_DOMAINS if PM 415 help 416 Support for the Marvell Dove SoC 88AP510 417 418config ARCH_PXA 419 bool "PXA2xx/PXA3xx-based" 420 depends on MMU 421 select ARCH_MTD_XIP 422 select ARM_CPU_SUSPEND if PM 423 select AUTO_ZRELADDR 424 select COMMON_CLK 425 select CLKSRC_PXA 426 select CLKSRC_MMIO 427 select TIMER_OF 428 select CPU_XSCALE if !CPU_XSC3 429 select GENERIC_IRQ_MULTI_HANDLER 430 select GPIO_PXA 431 select GPIOLIB 432 select HAVE_IDE 433 select IRQ_DOMAIN 434 select PLAT_PXA 435 select SPARSE_IRQ 436 help 437 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 438 439config ARCH_RPC 440 bool "RiscPC" 441 depends on MMU 442 select ARCH_ACORN 443 select ARCH_MAY_HAVE_PC_FDC 444 select ARCH_SPARSEMEM_ENABLE 445 select ARM_HAS_SG_CHAIN 446 select CPU_SA110 447 select FIQ 448 select HAVE_IDE 449 select HAVE_PATA_PLATFORM 450 select ISA_DMA_API 451 select LEGACY_TIMER_TICK 452 select NEED_MACH_IO_H 453 select NEED_MACH_MEMORY_H 454 select NO_IOPORT_MAP 455 help 456 On the Acorn Risc-PC, Linux can support the internal IDE disk and 457 CD-ROM interface, serial and parallel port, and the floppy drive. 458 459config ARCH_SA1100 460 bool "SA1100-based" 461 select ARCH_MTD_XIP 462 select ARCH_SPARSEMEM_ENABLE 463 select CLKSRC_MMIO 464 select CLKSRC_PXA 465 select TIMER_OF if OF 466 select COMMON_CLK 467 select CPU_FREQ 468 select CPU_SA1100 469 select GENERIC_IRQ_MULTI_HANDLER 470 select GPIOLIB 471 select HAVE_IDE 472 select IRQ_DOMAIN 473 select ISA 474 select NEED_MACH_MEMORY_H 475 select SPARSE_IRQ 476 help 477 Support for StrongARM 11x0 based boards. 478 479config ARCH_S3C24XX 480 bool "Samsung S3C24XX SoCs" 481 select ATAGS 482 select CLKSRC_SAMSUNG_PWM 483 select GPIO_SAMSUNG 484 select GPIOLIB 485 select GENERIC_IRQ_MULTI_HANDLER 486 select HAVE_S3C2410_I2C if I2C 487 select HAVE_S3C_RTC if RTC_CLASS 488 select NEED_MACH_IO_H 489 select S3C2410_WATCHDOG 490 select SAMSUNG_ATAGS 491 select USE_OF 492 select WATCHDOG 493 help 494 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 495 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 496 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 497 Samsung SMDK2410 development board (and derivatives). 498 499config ARCH_OMAP1 500 bool "TI OMAP1" 501 depends on MMU 502 select ARCH_OMAP 503 select CLKSRC_MMIO 504 select GENERIC_IRQ_CHIP 505 select GENERIC_IRQ_MULTI_HANDLER 506 select GPIOLIB 507 select HAVE_IDE 508 select HAVE_LEGACY_CLK 509 select IRQ_DOMAIN 510 select NEED_MACH_IO_H if PCCARD 511 select NEED_MACH_MEMORY_H 512 select SPARSE_IRQ 513 help 514 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 515 516endchoice 517 518menu "Multiple platform selection" 519 depends on ARCH_MULTIPLATFORM 520 521comment "CPU Core family selection" 522 523config ARCH_MULTI_V4 524 bool "ARMv4 based platforms (FA526)" 525 depends on !ARCH_MULTI_V6_V7 526 select ARCH_MULTI_V4_V5 527 select CPU_FA526 528 529config ARCH_MULTI_V4T 530 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 531 depends on !ARCH_MULTI_V6_V7 532 select ARCH_MULTI_V4_V5 533 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 534 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 535 CPU_ARM925T || CPU_ARM940T) 536 537config ARCH_MULTI_V5 538 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 539 depends on !ARCH_MULTI_V6_V7 540 select ARCH_MULTI_V4_V5 541 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 542 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 543 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 544 545config ARCH_MULTI_V4_V5 546 bool 547 548config ARCH_MULTI_V6 549 bool "ARMv6 based platforms (ARM11)" 550 select ARCH_MULTI_V6_V7 551 select CPU_V6K 552 553config ARCH_MULTI_V7 554 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 555 default y 556 select ARCH_MULTI_V6_V7 557 select CPU_V7 558 select HAVE_SMP 559 560config ARCH_MULTI_V6_V7 561 bool 562 select MIGHT_HAVE_CACHE_L2X0 563 564config ARCH_MULTI_CPU_AUTO 565 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 566 select ARCH_MULTI_V5 567 568endmenu 569 570config ARCH_VIRT 571 bool "Dummy Virtual Machine" 572 depends on ARCH_MULTI_V7 573 select ARM_AMBA 574 select ARM_GIC 575 select ARM_GIC_V2M if PCI 576 select ARM_GIC_V3 577 select ARM_GIC_V3_ITS if PCI 578 select ARM_PSCI 579 select HAVE_ARM_ARCH_TIMER 580 select ARCH_SUPPORTS_BIG_ENDIAN 581 582# 583# This is sorted alphabetically by mach-* pathname. However, plat-* 584# Kconfigs may be included either alphabetically (according to the 585# plat- suffix) or along side the corresponding mach-* source. 586# 587source "arch/arm/mach-actions/Kconfig" 588 589source "arch/arm/mach-alpine/Kconfig" 590 591source "arch/arm/mach-artpec/Kconfig" 592 593source "arch/arm/mach-asm9260/Kconfig" 594 595source "arch/arm/mach-aspeed/Kconfig" 596 597source "arch/arm/mach-at91/Kconfig" 598 599source "arch/arm/mach-axxia/Kconfig" 600 601source "arch/arm/mach-bcm/Kconfig" 602 603source "arch/arm/mach-berlin/Kconfig" 604 605source "arch/arm/mach-clps711x/Kconfig" 606 607source "arch/arm/mach-cns3xxx/Kconfig" 608 609source "arch/arm/mach-davinci/Kconfig" 610 611source "arch/arm/mach-digicolor/Kconfig" 612 613source "arch/arm/mach-dove/Kconfig" 614 615source "arch/arm/mach-ep93xx/Kconfig" 616 617source "arch/arm/mach-exynos/Kconfig" 618 619source "arch/arm/mach-footbridge/Kconfig" 620 621source "arch/arm/mach-gemini/Kconfig" 622 623source "arch/arm/mach-highbank/Kconfig" 624 625source "arch/arm/mach-hisi/Kconfig" 626 627source "arch/arm/mach-imx/Kconfig" 628 629source "arch/arm/mach-integrator/Kconfig" 630 631source "arch/arm/mach-iop32x/Kconfig" 632 633source "arch/arm/mach-ixp4xx/Kconfig" 634 635source "arch/arm/mach-keystone/Kconfig" 636 637source "arch/arm/mach-lpc32xx/Kconfig" 638 639source "arch/arm/mach-mediatek/Kconfig" 640 641source "arch/arm/mach-meson/Kconfig" 642 643source "arch/arm/mach-milbeaut/Kconfig" 644 645source "arch/arm/mach-mmp/Kconfig" 646 647source "arch/arm/mach-moxart/Kconfig" 648 649source "arch/arm/mach-mstar/Kconfig" 650 651source "arch/arm/mach-mv78xx0/Kconfig" 652 653source "arch/arm/mach-mvebu/Kconfig" 654 655source "arch/arm/mach-mxs/Kconfig" 656 657source "arch/arm/mach-nomadik/Kconfig" 658 659source "arch/arm/mach-npcm/Kconfig" 660 661source "arch/arm/mach-nspire/Kconfig" 662 663source "arch/arm/plat-omap/Kconfig" 664 665source "arch/arm/mach-omap1/Kconfig" 666 667source "arch/arm/mach-omap2/Kconfig" 668 669source "arch/arm/mach-orion5x/Kconfig" 670 671source "arch/arm/mach-oxnas/Kconfig" 672 673source "arch/arm/mach-pxa/Kconfig" 674source "arch/arm/plat-pxa/Kconfig" 675 676source "arch/arm/mach-qcom/Kconfig" 677 678source "arch/arm/mach-rda/Kconfig" 679 680source "arch/arm/mach-realtek/Kconfig" 681 682source "arch/arm/mach-realview/Kconfig" 683 684source "arch/arm/mach-rockchip/Kconfig" 685 686source "arch/arm/mach-s3c/Kconfig" 687 688source "arch/arm/mach-s5pv210/Kconfig" 689 690source "arch/arm/mach-sa1100/Kconfig" 691 692source "arch/arm/mach-shmobile/Kconfig" 693 694source "arch/arm/mach-socfpga/Kconfig" 695 696source "arch/arm/mach-spear/Kconfig" 697 698source "arch/arm/mach-sti/Kconfig" 699 700source "arch/arm/mach-stm32/Kconfig" 701 702source "arch/arm/mach-sunxi/Kconfig" 703 704source "arch/arm/mach-tegra/Kconfig" 705 706source "arch/arm/mach-uniphier/Kconfig" 707 708source "arch/arm/mach-ux500/Kconfig" 709 710source "arch/arm/mach-versatile/Kconfig" 711 712source "arch/arm/mach-vexpress/Kconfig" 713 714source "arch/arm/mach-vt8500/Kconfig" 715 716source "arch/arm/mach-zynq/Kconfig" 717 718# ARMv7-M architecture 719config ARCH_LPC18XX 720 bool "NXP LPC18xx/LPC43xx" 721 depends on ARM_SINGLE_ARMV7M 722 select ARCH_HAS_RESET_CONTROLLER 723 select ARM_AMBA 724 select CLKSRC_LPC32XX 725 select PINCTRL 726 help 727 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 728 high performance microcontrollers. 729 730config ARCH_MPS2 731 bool "ARM MPS2 platform" 732 depends on ARM_SINGLE_ARMV7M 733 select ARM_AMBA 734 select CLKSRC_MPS2 735 help 736 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 737 with a range of available cores like Cortex-M3/M4/M7. 738 739 Please, note that depends which Application Note is used memory map 740 for the platform may vary, so adjustment of RAM base might be needed. 741 742# Definitions to make life easier 743config ARCH_ACORN 744 bool 745 746config PLAT_IOP 747 bool 748 749config PLAT_ORION 750 bool 751 select CLKSRC_MMIO 752 select COMMON_CLK 753 select GENERIC_IRQ_CHIP 754 select IRQ_DOMAIN 755 756config PLAT_ORION_LEGACY 757 bool 758 select PLAT_ORION 759 760config PLAT_PXA 761 bool 762 763config PLAT_VERSATILE 764 bool 765 766source "arch/arm/mm/Kconfig" 767 768config IWMMXT 769 bool "Enable iWMMXt support" 770 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 771 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 772 help 773 Enable support for iWMMXt context switching at run time if 774 running on a CPU that supports it. 775 776if !MMU 777source "arch/arm/Kconfig-nommu" 778endif 779 780config PJ4B_ERRATA_4742 781 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 782 depends on CPU_PJ4B && MACH_ARMADA_370 783 default y 784 help 785 When coming out of either a Wait for Interrupt (WFI) or a Wait for 786 Event (WFE) IDLE states, a specific timing sensitivity exists between 787 the retiring WFI/WFE instructions and the newly issued subsequent 788 instructions. This sensitivity can result in a CPU hang scenario. 789 Workaround: 790 The software must insert either a Data Synchronization Barrier (DSB) 791 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 792 instruction 793 794config ARM_ERRATA_326103 795 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 796 depends on CPU_V6 797 help 798 Executing a SWP instruction to read-only memory does not set bit 11 799 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 800 treat the access as a read, preventing a COW from occurring and 801 causing the faulting task to livelock. 802 803config ARM_ERRATA_411920 804 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 805 depends on CPU_V6 || CPU_V6K 806 help 807 Invalidation of the Instruction Cache operation can 808 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 809 It does not affect the MPCore. This option enables the ARM Ltd. 810 recommended workaround. 811 812config ARM_ERRATA_430973 813 bool "ARM errata: Stale prediction on replaced interworking branch" 814 depends on CPU_V7 815 help 816 This option enables the workaround for the 430973 Cortex-A8 817 r1p* erratum. If a code sequence containing an ARM/Thumb 818 interworking branch is replaced with another code sequence at the 819 same virtual address, whether due to self-modifying code or virtual 820 to physical address re-mapping, Cortex-A8 does not recover from the 821 stale interworking branch prediction. This results in Cortex-A8 822 executing the new code sequence in the incorrect ARM or Thumb state. 823 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 824 and also flushes the branch target cache at every context switch. 825 Note that setting specific bits in the ACTLR register may not be 826 available in non-secure mode. 827 828config ARM_ERRATA_458693 829 bool "ARM errata: Processor deadlock when a false hazard is created" 830 depends on CPU_V7 831 depends on !ARCH_MULTIPLATFORM 832 help 833 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 834 erratum. For very specific sequences of memory operations, it is 835 possible for a hazard condition intended for a cache line to instead 836 be incorrectly associated with a different cache line. This false 837 hazard might then cause a processor deadlock. The workaround enables 838 the L1 caching of the NEON accesses and disables the PLD instruction 839 in the ACTLR register. Note that setting specific bits in the ACTLR 840 register may not be available in non-secure mode. 841 842config ARM_ERRATA_460075 843 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 844 depends on CPU_V7 845 depends on !ARCH_MULTIPLATFORM 846 help 847 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 848 erratum. Any asynchronous access to the L2 cache may encounter a 849 situation in which recent store transactions to the L2 cache are lost 850 and overwritten with stale memory contents from external memory. The 851 workaround disables the write-allocate mode for the L2 cache via the 852 ACTLR register. Note that setting specific bits in the ACTLR register 853 may not be available in non-secure mode. 854 855config ARM_ERRATA_742230 856 bool "ARM errata: DMB operation may be faulty" 857 depends on CPU_V7 && SMP 858 depends on !ARCH_MULTIPLATFORM 859 help 860 This option enables the workaround for the 742230 Cortex-A9 861 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 862 between two write operations may not ensure the correct visibility 863 ordering of the two writes. This workaround sets a specific bit in 864 the diagnostic register of the Cortex-A9 which causes the DMB 865 instruction to behave as a DSB, ensuring the correct behaviour of 866 the two writes. 867 868config ARM_ERRATA_742231 869 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 870 depends on CPU_V7 && SMP 871 depends on !ARCH_MULTIPLATFORM 872 help 873 This option enables the workaround for the 742231 Cortex-A9 874 (r2p0..r2p2) erratum. Under certain conditions, specific to the 875 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 876 accessing some data located in the same cache line, may get corrupted 877 data due to bad handling of the address hazard when the line gets 878 replaced from one of the CPUs at the same time as another CPU is 879 accessing it. This workaround sets specific bits in the diagnostic 880 register of the Cortex-A9 which reduces the linefill issuing 881 capabilities of the processor. 882 883config ARM_ERRATA_643719 884 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 885 depends on CPU_V7 && SMP 886 default y 887 help 888 This option enables the workaround for the 643719 Cortex-A9 (prior to 889 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 890 register returns zero when it should return one. The workaround 891 corrects this value, ensuring cache maintenance operations which use 892 it behave as intended and avoiding data corruption. 893 894config ARM_ERRATA_720789 895 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 896 depends on CPU_V7 897 help 898 This option enables the workaround for the 720789 Cortex-A9 (prior to 899 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 900 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 901 As a consequence of this erratum, some TLB entries which should be 902 invalidated are not, resulting in an incoherency in the system page 903 tables. The workaround changes the TLB flushing routines to invalidate 904 entries regardless of the ASID. 905 906config ARM_ERRATA_743622 907 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 908 depends on CPU_V7 909 depends on !ARCH_MULTIPLATFORM 910 help 911 This option enables the workaround for the 743622 Cortex-A9 912 (r2p*) erratum. Under very rare conditions, a faulty 913 optimisation in the Cortex-A9 Store Buffer may lead to data 914 corruption. This workaround sets a specific bit in the diagnostic 915 register of the Cortex-A9 which disables the Store Buffer 916 optimisation, preventing the defect from occurring. This has no 917 visible impact on the overall performance or power consumption of the 918 processor. 919 920config ARM_ERRATA_751472 921 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 922 depends on CPU_V7 923 depends on !ARCH_MULTIPLATFORM 924 help 925 This option enables the workaround for the 751472 Cortex-A9 (prior 926 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 927 completion of a following broadcasted operation if the second 928 operation is received by a CPU before the ICIALLUIS has completed, 929 potentially leading to corrupted entries in the cache or TLB. 930 931config ARM_ERRATA_754322 932 bool "ARM errata: possible faulty MMU translations following an ASID switch" 933 depends on CPU_V7 934 help 935 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 936 r3p*) erratum. A speculative memory access may cause a page table walk 937 which starts prior to an ASID switch but completes afterwards. This 938 can populate the micro-TLB with a stale entry which may be hit with 939 the new ASID. This workaround places two dsb instructions in the mm 940 switching code so that no page table walks can cross the ASID switch. 941 942config ARM_ERRATA_754327 943 bool "ARM errata: no automatic Store Buffer drain" 944 depends on CPU_V7 && SMP 945 help 946 This option enables the workaround for the 754327 Cortex-A9 (prior to 947 r2p0) erratum. The Store Buffer does not have any automatic draining 948 mechanism and therefore a livelock may occur if an external agent 949 continuously polls a memory location waiting to observe an update. 950 This workaround defines cpu_relax() as smp_mb(), preventing correctly 951 written polling loops from denying visibility of updates to memory. 952 953config ARM_ERRATA_364296 954 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 955 depends on CPU_V6 956 help 957 This options enables the workaround for the 364296 ARM1136 958 r0p2 erratum (possible cache data corruption with 959 hit-under-miss enabled). It sets the undocumented bit 31 in 960 the auxiliary control register and the FI bit in the control 961 register, thus disabling hit-under-miss without putting the 962 processor into full low interrupt latency mode. ARM11MPCore 963 is not affected. 964 965config ARM_ERRATA_764369 966 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 967 depends on CPU_V7 && SMP 968 help 969 This option enables the workaround for erratum 764369 970 affecting Cortex-A9 MPCore with two or more processors (all 971 current revisions). Under certain timing circumstances, a data 972 cache line maintenance operation by MVA targeting an Inner 973 Shareable memory region may fail to proceed up to either the 974 Point of Coherency or to the Point of Unification of the 975 system. This workaround adds a DSB instruction before the 976 relevant cache maintenance functions and sets a specific bit 977 in the diagnostic control register of the SCU. 978 979config ARM_ERRATA_775420 980 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 981 depends on CPU_V7 982 help 983 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 984 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 985 operation aborts with MMU exception, it might cause the processor 986 to deadlock. This workaround puts DSB before executing ISB if 987 an abort may occur on cache maintenance. 988 989config ARM_ERRATA_798181 990 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 991 depends on CPU_V7 && SMP 992 help 993 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 994 adequately shooting down all use of the old entries. This 995 option enables the Linux kernel workaround for this erratum 996 which sends an IPI to the CPUs that are running the same ASID 997 as the one being invalidated. 998 999config ARM_ERRATA_773022 1000 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1001 depends on CPU_V7 1002 help 1003 This option enables the workaround for the 773022 Cortex-A15 1004 (up to r0p4) erratum. In certain rare sequences of code, the 1005 loop buffer may deliver incorrect instructions. This 1006 workaround disables the loop buffer to avoid the erratum. 1007 1008config ARM_ERRATA_818325_852422 1009 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1010 depends on CPU_V7 1011 help 1012 This option enables the workaround for: 1013 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1014 instruction might deadlock. Fixed in r0p1. 1015 - Cortex-A12 852422: Execution of a sequence of instructions might 1016 lead to either a data corruption or a CPU deadlock. Not fixed in 1017 any Cortex-A12 cores yet. 1018 This workaround for all both errata involves setting bit[12] of the 1019 Feature Register. This bit disables an optimisation applied to a 1020 sequence of 2 instructions that use opposing condition codes. 1021 1022config ARM_ERRATA_821420 1023 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1024 depends on CPU_V7 1025 help 1026 This option enables the workaround for the 821420 Cortex-A12 1027 (all revs) erratum. In very rare timing conditions, a sequence 1028 of VMOV to Core registers instructions, for which the second 1029 one is in the shadow of a branch or abort, can lead to a 1030 deadlock when the VMOV instructions are issued out-of-order. 1031 1032config ARM_ERRATA_825619 1033 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1034 depends on CPU_V7 1035 help 1036 This option enables the workaround for the 825619 Cortex-A12 1037 (all revs) erratum. Within rare timing constraints, executing a 1038 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1039 and Device/Strongly-Ordered loads and stores might cause deadlock 1040 1041config ARM_ERRATA_857271 1042 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1043 depends on CPU_V7 1044 help 1045 This option enables the workaround for the 857271 Cortex-A12 1046 (all revs) erratum. Under very rare timing conditions, the CPU might 1047 hang. The workaround is expected to have a < 1% performance impact. 1048 1049config ARM_ERRATA_852421 1050 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1051 depends on CPU_V7 1052 help 1053 This option enables the workaround for the 852421 Cortex-A17 1054 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1055 execution of a DMB ST instruction might fail to properly order 1056 stores from GroupA and stores from GroupB. 1057 1058config ARM_ERRATA_852423 1059 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1060 depends on CPU_V7 1061 help 1062 This option enables the workaround for: 1063 - Cortex-A17 852423: Execution of a sequence of instructions might 1064 lead to either a data corruption or a CPU deadlock. Not fixed in 1065 any Cortex-A17 cores yet. 1066 This is identical to Cortex-A12 erratum 852422. It is a separate 1067 config option from the A12 erratum due to the way errata are checked 1068 for and handled. 1069 1070config ARM_ERRATA_857272 1071 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1072 depends on CPU_V7 1073 help 1074 This option enables the workaround for the 857272 Cortex-A17 erratum. 1075 This erratum is not known to be fixed in any A17 revision. 1076 This is identical to Cortex-A12 erratum 857271. It is a separate 1077 config option from the A12 erratum due to the way errata are checked 1078 for and handled. 1079 1080endmenu 1081 1082source "arch/arm/common/Kconfig" 1083 1084menu "Bus support" 1085 1086config ISA 1087 bool 1088 help 1089 Find out whether you have ISA slots on your motherboard. ISA is the 1090 name of a bus system, i.e. the way the CPU talks to the other stuff 1091 inside your box. Other bus systems are PCI, EISA, MicroChannel 1092 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1093 newer boards don't support it. If you have ISA, say Y, otherwise N. 1094 1095# Select ISA DMA controller support 1096config ISA_DMA 1097 bool 1098 select ISA_DMA_API 1099 1100# Select ISA DMA interface 1101config ISA_DMA_API 1102 bool 1103 1104config PCI_NANOENGINE 1105 bool "BSE nanoEngine PCI support" 1106 depends on SA1100_NANOENGINE 1107 help 1108 Enable PCI on the BSE nanoEngine board. 1109 1110config ARM_ERRATA_814220 1111 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1112 depends on CPU_V7 1113 help 1114 The v7 ARM states that all cache and branch predictor maintenance 1115 operations that do not specify an address execute, relative to 1116 each other, in program order. 1117 However, because of this erratum, an L2 set/way cache maintenance 1118 operation can overtake an L1 set/way cache maintenance operation. 1119 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1120 r0p4, r0p5. 1121 1122endmenu 1123 1124menu "Kernel Features" 1125 1126config HAVE_SMP 1127 bool 1128 help 1129 This option should be selected by machines which have an SMP- 1130 capable CPU. 1131 1132 The only effect of this option is to make the SMP-related 1133 options available to the user for configuration. 1134 1135config SMP 1136 bool "Symmetric Multi-Processing" 1137 depends on CPU_V6K || CPU_V7 1138 depends on HAVE_SMP 1139 depends on MMU || ARM_MPU 1140 select IRQ_WORK 1141 help 1142 This enables support for systems with more than one CPU. If you have 1143 a system with only one CPU, say N. If you have a system with more 1144 than one CPU, say Y. 1145 1146 If you say N here, the kernel will run on uni- and multiprocessor 1147 machines, but will use only one CPU of a multiprocessor machine. If 1148 you say Y here, the kernel will run on many, but not all, 1149 uniprocessor machines. On a uniprocessor machine, the kernel 1150 will run faster if you say N here. 1151 1152 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1153 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1154 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1155 1156 If you don't know what to do here, say N. 1157 1158config SMP_ON_UP 1159 bool "Allow booting SMP kernel on uniprocessor systems" 1160 depends on SMP && !XIP_KERNEL && MMU 1161 default y 1162 help 1163 SMP kernels contain instructions which fail on non-SMP processors. 1164 Enabling this option allows the kernel to modify itself to make 1165 these instructions safe. Disabling it allows about 1K of space 1166 savings. 1167 1168 If you don't know what to do here, say Y. 1169 1170config ARM_CPU_TOPOLOGY 1171 bool "Support cpu topology definition" 1172 depends on SMP && CPU_V7 1173 default y 1174 help 1175 Support ARM cpu topology definition. The MPIDR register defines 1176 affinity between processors which is then used to describe the cpu 1177 topology of an ARM System. 1178 1179config SCHED_MC 1180 bool "Multi-core scheduler support" 1181 depends on ARM_CPU_TOPOLOGY 1182 help 1183 Multi-core scheduler support improves the CPU scheduler's decision 1184 making when dealing with multi-core CPU chips at a cost of slightly 1185 increased overhead in some places. If unsure say N here. 1186 1187config SCHED_SMT 1188 bool "SMT scheduler support" 1189 depends on ARM_CPU_TOPOLOGY 1190 help 1191 Improves the CPU scheduler's decision making when dealing with 1192 MultiThreading at a cost of slightly increased overhead in some 1193 places. If unsure say N here. 1194 1195config HAVE_ARM_SCU 1196 bool 1197 help 1198 This option enables support for the ARM snoop control unit 1199 1200config HAVE_ARM_ARCH_TIMER 1201 bool "Architected timer support" 1202 depends on CPU_V7 1203 select ARM_ARCH_TIMER 1204 help 1205 This option enables support for the ARM architected timer 1206 1207config HAVE_ARM_TWD 1208 bool 1209 help 1210 This options enables support for the ARM timer and watchdog unit 1211 1212config MCPM 1213 bool "Multi-Cluster Power Management" 1214 depends on CPU_V7 && SMP 1215 help 1216 This option provides the common power management infrastructure 1217 for (multi-)cluster based systems, such as big.LITTLE based 1218 systems. 1219 1220config MCPM_QUAD_CLUSTER 1221 bool 1222 depends on MCPM 1223 help 1224 To avoid wasting resources unnecessarily, MCPM only supports up 1225 to 2 clusters by default. 1226 Platforms with 3 or 4 clusters that use MCPM must select this 1227 option to allow the additional clusters to be managed. 1228 1229config BIG_LITTLE 1230 bool "big.LITTLE support (Experimental)" 1231 depends on CPU_V7 && SMP 1232 select MCPM 1233 help 1234 This option enables support selections for the big.LITTLE 1235 system architecture. 1236 1237config BL_SWITCHER 1238 bool "big.LITTLE switcher support" 1239 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1240 select CPU_PM 1241 help 1242 The big.LITTLE "switcher" provides the core functionality to 1243 transparently handle transition between a cluster of A15's 1244 and a cluster of A7's in a big.LITTLE system. 1245 1246config BL_SWITCHER_DUMMY_IF 1247 tristate "Simple big.LITTLE switcher user interface" 1248 depends on BL_SWITCHER && DEBUG_KERNEL 1249 help 1250 This is a simple and dummy char dev interface to control 1251 the big.LITTLE switcher core code. It is meant for 1252 debugging purposes only. 1253 1254choice 1255 prompt "Memory split" 1256 depends on MMU 1257 default VMSPLIT_3G 1258 help 1259 Select the desired split between kernel and user memory. 1260 1261 If you are not absolutely sure what you are doing, leave this 1262 option alone! 1263 1264 config VMSPLIT_3G 1265 bool "3G/1G user/kernel split" 1266 config VMSPLIT_3G_OPT 1267 depends on !ARM_LPAE 1268 bool "3G/1G user/kernel split (for full 1G low memory)" 1269 config VMSPLIT_2G 1270 bool "2G/2G user/kernel split" 1271 config VMSPLIT_1G 1272 bool "1G/3G user/kernel split" 1273endchoice 1274 1275config PAGE_OFFSET 1276 hex 1277 default PHYS_OFFSET if !MMU 1278 default 0x40000000 if VMSPLIT_1G 1279 default 0x80000000 if VMSPLIT_2G 1280 default 0xB0000000 if VMSPLIT_3G_OPT 1281 default 0xC0000000 1282 1283config KASAN_SHADOW_OFFSET 1284 hex 1285 depends on KASAN 1286 default 0x1f000000 if PAGE_OFFSET=0x40000000 1287 default 0x5f000000 if PAGE_OFFSET=0x80000000 1288 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1289 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1290 default 0xffffffff 1291 1292config NR_CPUS 1293 int "Maximum number of CPUs (2-32)" 1294 range 2 16 if DEBUG_KMAP_LOCAL 1295 range 2 32 if !DEBUG_KMAP_LOCAL 1296 depends on SMP 1297 default "4" 1298 help 1299 The maximum number of CPUs that the kernel can support. 1300 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1301 debugging is enabled, which uses half of the per-CPU fixmap 1302 slots as guard regions. 1303 1304config HOTPLUG_CPU 1305 bool "Support for hot-pluggable CPUs" 1306 depends on SMP 1307 select GENERIC_IRQ_MIGRATION 1308 help 1309 Say Y here to experiment with turning CPUs off and on. CPUs 1310 can be controlled through /sys/devices/system/cpu. 1311 1312config ARM_PSCI 1313 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1314 depends on HAVE_ARM_SMCCC 1315 select ARM_PSCI_FW 1316 help 1317 Say Y here if you want Linux to communicate with system firmware 1318 implementing the PSCI specification for CPU-centric power 1319 management operations described in ARM document number ARM DEN 1320 0022A ("Power State Coordination Interface System Software on 1321 ARM processors"). 1322 1323# The GPIO number here must be sorted by descending number. In case of 1324# a multiplatform kernel, we just want the highest value required by the 1325# selected platforms. 1326config ARCH_NR_GPIO 1327 int 1328 default 2048 if ARCH_INTEL_SOCFPGA 1329 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1330 ARCH_ZYNQ || ARCH_ASPEED 1331 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1332 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1333 default 416 if ARCH_SUNXI 1334 default 392 if ARCH_U8500 1335 default 352 if ARCH_VT8500 1336 default 288 if ARCH_ROCKCHIP 1337 default 264 if MACH_H4700 1338 default 0 1339 help 1340 Maximum number of GPIOs in the system. 1341 1342 If unsure, leave the default value. 1343 1344config HZ_FIXED 1345 int 1346 default 128 if SOC_AT91RM9200 1347 default 0 1348 1349choice 1350 depends on HZ_FIXED = 0 1351 prompt "Timer frequency" 1352 1353config HZ_100 1354 bool "100 Hz" 1355 1356config HZ_200 1357 bool "200 Hz" 1358 1359config HZ_250 1360 bool "250 Hz" 1361 1362config HZ_300 1363 bool "300 Hz" 1364 1365config HZ_500 1366 bool "500 Hz" 1367 1368config HZ_1000 1369 bool "1000 Hz" 1370 1371endchoice 1372 1373config HZ 1374 int 1375 default HZ_FIXED if HZ_FIXED != 0 1376 default 100 if HZ_100 1377 default 200 if HZ_200 1378 default 250 if HZ_250 1379 default 300 if HZ_300 1380 default 500 if HZ_500 1381 default 1000 1382 1383config SCHED_HRTICK 1384 def_bool HIGH_RES_TIMERS 1385 1386config THUMB2_KERNEL 1387 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1388 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1389 default y if CPU_THUMBONLY 1390 select ARM_UNWIND 1391 help 1392 By enabling this option, the kernel will be compiled in 1393 Thumb-2 mode. 1394 1395 If unsure, say N. 1396 1397config ARM_PATCH_IDIV 1398 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1399 depends on CPU_32v7 && !XIP_KERNEL 1400 default y 1401 help 1402 The ARM compiler inserts calls to __aeabi_idiv() and 1403 __aeabi_uidiv() when it needs to perform division on signed 1404 and unsigned integers. Some v7 CPUs have support for the sdiv 1405 and udiv instructions that can be used to implement those 1406 functions. 1407 1408 Enabling this option allows the kernel to modify itself to 1409 replace the first two instructions of these library functions 1410 with the sdiv or udiv plus "bx lr" instructions when the CPU 1411 it is running on supports them. Typically this will be faster 1412 and less power intensive than running the original library 1413 code to do integer division. 1414 1415config AEABI 1416 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1417 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1418 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1419 help 1420 This option allows for the kernel to be compiled using the latest 1421 ARM ABI (aka EABI). This is only useful if you are using a user 1422 space environment that is also compiled with EABI. 1423 1424 Since there are major incompatibilities between the legacy ABI and 1425 EABI, especially with regard to structure member alignment, this 1426 option also changes the kernel syscall calling convention to 1427 disambiguate both ABIs and allow for backward compatibility support 1428 (selected with CONFIG_OABI_COMPAT). 1429 1430 To use this you need GCC version 4.0.0 or later. 1431 1432config OABI_COMPAT 1433 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1434 depends on AEABI && !THUMB2_KERNEL 1435 help 1436 This option preserves the old syscall interface along with the 1437 new (ARM EABI) one. It also provides a compatibility layer to 1438 intercept syscalls that have structure arguments which layout 1439 in memory differs between the legacy ABI and the new ARM EABI 1440 (only for non "thumb" binaries). This option adds a tiny 1441 overhead to all syscalls and produces a slightly larger kernel. 1442 1443 The seccomp filter system will not be available when this is 1444 selected, since there is no way yet to sensibly distinguish 1445 between calling conventions during filtering. 1446 1447 If you know you'll be using only pure EABI user space then you 1448 can say N here. If this option is not selected and you attempt 1449 to execute a legacy ABI binary then the result will be 1450 UNPREDICTABLE (in fact it can be predicted that it won't work 1451 at all). If in doubt say N. 1452 1453config ARCH_SELECT_MEMORY_MODEL 1454 bool 1455 1456config ARCH_FLATMEM_ENABLE 1457 bool 1458 1459config ARCH_SPARSEMEM_ENABLE 1460 bool 1461 select SPARSEMEM_STATIC if SPARSEMEM 1462 1463config HIGHMEM 1464 bool "High Memory Support" 1465 depends on MMU 1466 select KMAP_LOCAL 1467 help 1468 The address space of ARM processors is only 4 Gigabytes large 1469 and it has to accommodate user address space, kernel address 1470 space as well as some memory mapped IO. That means that, if you 1471 have a large amount of physical memory and/or IO, not all of the 1472 memory can be "permanently mapped" by the kernel. The physical 1473 memory that is not permanently mapped is called "high memory". 1474 1475 Depending on the selected kernel/user memory split, minimum 1476 vmalloc space and actual amount of RAM, you may not need this 1477 option which should result in a slightly faster kernel. 1478 1479 If unsure, say n. 1480 1481config HIGHPTE 1482 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1483 depends on HIGHMEM 1484 default y 1485 help 1486 The VM uses one page of physical memory for each page table. 1487 For systems with a lot of processes, this can use a lot of 1488 precious low memory, eventually leading to low memory being 1489 consumed by page tables. Setting this option will allow 1490 user-space 2nd level page tables to reside in high memory. 1491 1492config CPU_SW_DOMAIN_PAN 1493 bool "Enable use of CPU domains to implement privileged no-access" 1494 depends on MMU && !ARM_LPAE 1495 default y 1496 help 1497 Increase kernel security by ensuring that normal kernel accesses 1498 are unable to access userspace addresses. This can help prevent 1499 use-after-free bugs becoming an exploitable privilege escalation 1500 by ensuring that magic values (such as LIST_POISON) will always 1501 fault when dereferenced. 1502 1503 CPUs with low-vector mappings use a best-efforts implementation. 1504 Their lower 1MB needs to remain accessible for the vectors, but 1505 the remainder of userspace will become appropriately inaccessible. 1506 1507config HW_PERF_EVENTS 1508 def_bool y 1509 depends on ARM_PMU 1510 1511config ARCH_WANT_GENERAL_HUGETLB 1512 def_bool y 1513 1514config ARM_MODULE_PLTS 1515 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1516 depends on MODULES 1517 default y 1518 help 1519 Allocate PLTs when loading modules so that jumps and calls whose 1520 targets are too far away for their relative offsets to be encoded 1521 in the instructions themselves can be bounced via veneers in the 1522 module's PLT. This allows modules to be allocated in the generic 1523 vmalloc area after the dedicated module memory area has been 1524 exhausted. The modules will use slightly more memory, but after 1525 rounding up to page size, the actual memory footprint is usually 1526 the same. 1527 1528 Disabling this is usually safe for small single-platform 1529 configurations. If unsure, say y. 1530 1531config FORCE_MAX_ZONEORDER 1532 int "Maximum zone order" 1533 default "12" if SOC_AM33XX 1534 default "9" if SA1111 1535 default "11" 1536 help 1537 The kernel memory allocator divides physically contiguous memory 1538 blocks into "zones", where each zone is a power of two number of 1539 pages. This option selects the largest power of two that the kernel 1540 keeps in the memory allocator. If you need to allocate very large 1541 blocks of physically contiguous memory, then you may need to 1542 increase this value. 1543 1544 This config option is actually maximum order plus one. For example, 1545 a value of 11 means that the largest free memory block is 2^10 pages. 1546 1547config ALIGNMENT_TRAP 1548 def_bool CPU_CP15_MMU 1549 select HAVE_PROC_CPU if PROC_FS 1550 help 1551 ARM processors cannot fetch/store information which is not 1552 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1553 address divisible by 4. On 32-bit ARM processors, these non-aligned 1554 fetch/store instructions will be emulated in software if you say 1555 here, which has a severe performance impact. This is necessary for 1556 correct operation of some network protocols. With an IP-only 1557 configuration it is safe to say N, otherwise say Y. 1558 1559config UACCESS_WITH_MEMCPY 1560 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1561 depends on MMU 1562 default y if CPU_FEROCEON 1563 help 1564 Implement faster copy_to_user and clear_user methods for CPU 1565 cores where a 8-word STM instruction give significantly higher 1566 memory write throughput than a sequence of individual 32bit stores. 1567 1568 A possible side effect is a slight increase in scheduling latency 1569 between threads sharing the same address space if they invoke 1570 such copy operations with large buffers. 1571 1572 However, if the CPU data cache is using a write-allocate mode, 1573 this option is unlikely to provide any performance gain. 1574 1575config PARAVIRT 1576 bool "Enable paravirtualization code" 1577 help 1578 This changes the kernel so it can modify itself when it is run 1579 under a hypervisor, potentially improving performance significantly 1580 over full virtualization. 1581 1582config PARAVIRT_TIME_ACCOUNTING 1583 bool "Paravirtual steal time accounting" 1584 select PARAVIRT 1585 help 1586 Select this option to enable fine granularity task steal time 1587 accounting. Time spent executing other tasks in parallel with 1588 the current vCPU is discounted from the vCPU power. To account for 1589 that, there can be a small performance impact. 1590 1591 If in doubt, say N here. 1592 1593config XEN_DOM0 1594 def_bool y 1595 depends on XEN 1596 1597config XEN 1598 bool "Xen guest support on ARM" 1599 depends on ARM && AEABI && OF 1600 depends on CPU_V7 && !CPU_V6 1601 depends on !GENERIC_ATOMIC64 1602 depends on MMU 1603 select ARCH_DMA_ADDR_T_64BIT 1604 select ARM_PSCI 1605 select SWIOTLB 1606 select SWIOTLB_XEN 1607 select PARAVIRT 1608 help 1609 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1610 1611config STACKPROTECTOR_PER_TASK 1612 bool "Use a unique stack canary value for each task" 1613 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1614 select GCC_PLUGIN_ARM_SSP_PER_TASK 1615 default y 1616 help 1617 Due to the fact that GCC uses an ordinary symbol reference from 1618 which to load the value of the stack canary, this value can only 1619 change at reboot time on SMP systems, and all tasks running in the 1620 kernel's address space are forced to use the same canary value for 1621 the entire duration that the system is up. 1622 1623 Enable this option to switch to a different method that uses a 1624 different canary value for each task. 1625 1626endmenu 1627 1628menu "Boot options" 1629 1630config USE_OF 1631 bool "Flattened Device Tree support" 1632 select IRQ_DOMAIN 1633 select OF 1634 help 1635 Include support for flattened device tree machine descriptions. 1636 1637config ATAGS 1638 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1639 default y 1640 help 1641 This is the traditional way of passing data to the kernel at boot 1642 time. If you are solely relying on the flattened device tree (or 1643 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1644 to remove ATAGS support from your kernel binary. If unsure, 1645 leave this to y. 1646 1647config DEPRECATED_PARAM_STRUCT 1648 bool "Provide old way to pass kernel parameters" 1649 depends on ATAGS 1650 help 1651 This was deprecated in 2001 and announced to live on for 5 years. 1652 Some old boot loaders still use this way. 1653 1654# Compressed boot loader in ROM. Yes, we really want to ask about 1655# TEXT and BSS so we preserve their values in the config files. 1656config ZBOOT_ROM_TEXT 1657 hex "Compressed ROM boot loader base address" 1658 default 0x0 1659 help 1660 The physical address at which the ROM-able zImage is to be 1661 placed in the target. Platforms which normally make use of 1662 ROM-able zImage formats normally set this to a suitable 1663 value in their defconfig file. 1664 1665 If ZBOOT_ROM is not enabled, this has no effect. 1666 1667config ZBOOT_ROM_BSS 1668 hex "Compressed ROM boot loader BSS address" 1669 default 0x0 1670 help 1671 The base address of an area of read/write memory in the target 1672 for the ROM-able zImage which must be available while the 1673 decompressor is running. It must be large enough to hold the 1674 entire decompressed kernel plus an additional 128 KiB. 1675 Platforms which normally make use of ROM-able zImage formats 1676 normally set this to a suitable value in their defconfig file. 1677 1678 If ZBOOT_ROM is not enabled, this has no effect. 1679 1680config ZBOOT_ROM 1681 bool "Compressed boot loader in ROM/flash" 1682 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1683 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1684 help 1685 Say Y here if you intend to execute your compressed kernel image 1686 (zImage) directly from ROM or flash. If unsure, say N. 1687 1688config ARM_APPENDED_DTB 1689 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1690 depends on OF 1691 help 1692 With this option, the boot code will look for a device tree binary 1693 (DTB) appended to zImage 1694 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1695 1696 This is meant as a backward compatibility convenience for those 1697 systems with a bootloader that can't be upgraded to accommodate 1698 the documented boot protocol using a device tree. 1699 1700 Beware that there is very little in terms of protection against 1701 this option being confused by leftover garbage in memory that might 1702 look like a DTB header after a reboot if no actual DTB is appended 1703 to zImage. Do not leave this option active in a production kernel 1704 if you don't intend to always append a DTB. Proper passing of the 1705 location into r2 of a bootloader provided DTB is always preferable 1706 to this option. 1707 1708config ARM_ATAG_DTB_COMPAT 1709 bool "Supplement the appended DTB with traditional ATAG information" 1710 depends on ARM_APPENDED_DTB 1711 help 1712 Some old bootloaders can't be updated to a DTB capable one, yet 1713 they provide ATAGs with memory configuration, the ramdisk address, 1714 the kernel cmdline string, etc. Such information is dynamically 1715 provided by the bootloader and can't always be stored in a static 1716 DTB. To allow a device tree enabled kernel to be used with such 1717 bootloaders, this option allows zImage to extract the information 1718 from the ATAG list and store it at run time into the appended DTB. 1719 1720choice 1721 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1722 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1723 1724config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1725 bool "Use bootloader kernel arguments if available" 1726 help 1727 Uses the command-line options passed by the boot loader instead of 1728 the device tree bootargs property. If the boot loader doesn't provide 1729 any, the device tree bootargs property will be used. 1730 1731config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1732 bool "Extend with bootloader kernel arguments" 1733 help 1734 The command-line arguments provided by the boot loader will be 1735 appended to the the device tree bootargs property. 1736 1737endchoice 1738 1739config CMDLINE 1740 string "Default kernel command string" 1741 default "" 1742 help 1743 On some architectures (e.g. CATS), there is currently no way 1744 for the boot loader to pass arguments to the kernel. For these 1745 architectures, you should supply some command-line options at build 1746 time by entering them here. As a minimum, you should specify the 1747 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1748 1749choice 1750 prompt "Kernel command line type" if CMDLINE != "" 1751 default CMDLINE_FROM_BOOTLOADER 1752 depends on ATAGS 1753 1754config CMDLINE_FROM_BOOTLOADER 1755 bool "Use bootloader kernel arguments if available" 1756 help 1757 Uses the command-line options passed by the boot loader. If 1758 the boot loader doesn't provide any, the default kernel command 1759 string provided in CMDLINE will be used. 1760 1761config CMDLINE_EXTEND 1762 bool "Extend bootloader kernel arguments" 1763 help 1764 The command-line arguments provided by the boot loader will be 1765 appended to the default kernel command string. 1766 1767config CMDLINE_FORCE 1768 bool "Always use the default kernel command string" 1769 help 1770 Always use the default kernel command string, even if the boot 1771 loader passes other arguments to the kernel. 1772 This is useful if you cannot or don't want to change the 1773 command-line options your boot loader passes to the kernel. 1774endchoice 1775 1776config XIP_KERNEL 1777 bool "Kernel Execute-In-Place from ROM" 1778 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1779 help 1780 Execute-In-Place allows the kernel to run from non-volatile storage 1781 directly addressable by the CPU, such as NOR flash. This saves RAM 1782 space since the text section of the kernel is not loaded from flash 1783 to RAM. Read-write sections, such as the data section and stack, 1784 are still copied to RAM. The XIP kernel is not compressed since 1785 it has to run directly from flash, so it will take more space to 1786 store it. The flash address used to link the kernel object files, 1787 and for storing it, is configuration dependent. Therefore, if you 1788 say Y here, you must know the proper physical address where to 1789 store the kernel image depending on your own flash memory usage. 1790 1791 Also note that the make target becomes "make xipImage" rather than 1792 "make zImage" or "make Image". The final kernel binary to put in 1793 ROM memory will be arch/arm/boot/xipImage. 1794 1795 If unsure, say N. 1796 1797config XIP_PHYS_ADDR 1798 hex "XIP Kernel Physical Location" 1799 depends on XIP_KERNEL 1800 default "0x00080000" 1801 help 1802 This is the physical address in your flash memory the kernel will 1803 be linked for and stored to. This address is dependent on your 1804 own flash usage. 1805 1806config XIP_DEFLATED_DATA 1807 bool "Store kernel .data section compressed in ROM" 1808 depends on XIP_KERNEL 1809 select ZLIB_INFLATE 1810 help 1811 Before the kernel is actually executed, its .data section has to be 1812 copied to RAM from ROM. This option allows for storing that data 1813 in compressed form and decompressed to RAM rather than merely being 1814 copied, saving some precious ROM space. A possible drawback is a 1815 slightly longer boot delay. 1816 1817config KEXEC 1818 bool "Kexec system call (EXPERIMENTAL)" 1819 depends on (!SMP || PM_SLEEP_SMP) 1820 depends on MMU 1821 select KEXEC_CORE 1822 help 1823 kexec is a system call that implements the ability to shutdown your 1824 current kernel, and to start another kernel. It is like a reboot 1825 but it is independent of the system firmware. And like a reboot 1826 you can start any kernel with it, not just Linux. 1827 1828 It is an ongoing process to be certain the hardware in a machine 1829 is properly shutdown, so do not be surprised if this code does not 1830 initially work for you. 1831 1832config ATAGS_PROC 1833 bool "Export atags in procfs" 1834 depends on ATAGS && KEXEC 1835 default y 1836 help 1837 Should the atags used to boot the kernel be exported in an "atags" 1838 file in procfs. Useful with kexec. 1839 1840config CRASH_DUMP 1841 bool "Build kdump crash kernel (EXPERIMENTAL)" 1842 help 1843 Generate crash dump after being started by kexec. This should 1844 be normally only set in special crash dump kernels which are 1845 loaded in the main kernel with kexec-tools into a specially 1846 reserved region and then later executed after a crash by 1847 kdump/kexec. The crash dump kernel must be compiled to a 1848 memory address not used by the main kernel 1849 1850 For more details see Documentation/admin-guide/kdump/kdump.rst 1851 1852config AUTO_ZRELADDR 1853 bool "Auto calculation of the decompressed kernel image address" 1854 help 1855 ZRELADDR is the physical address where the decompressed kernel 1856 image will be placed. If AUTO_ZRELADDR is selected, the address 1857 will be determined at run-time, either by masking the current IP 1858 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1859 This assumes the zImage being placed in the first 128MB from 1860 start of memory. 1861 1862config EFI_STUB 1863 bool 1864 1865config EFI 1866 bool "UEFI runtime support" 1867 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1868 select UCS2_STRING 1869 select EFI_PARAMS_FROM_FDT 1870 select EFI_STUB 1871 select EFI_GENERIC_STUB 1872 select EFI_RUNTIME_WRAPPERS 1873 help 1874 This option provides support for runtime services provided 1875 by UEFI firmware (such as non-volatile variables, realtime 1876 clock, and platform reset). A UEFI stub is also provided to 1877 allow the kernel to be booted as an EFI application. This 1878 is only useful for kernels that may run on systems that have 1879 UEFI firmware. 1880 1881config DMI 1882 bool "Enable support for SMBIOS (DMI) tables" 1883 depends on EFI 1884 default y 1885 help 1886 This enables SMBIOS/DMI feature for systems. 1887 1888 This option is only useful on systems that have UEFI firmware. 1889 However, even with this option, the resultant kernel should 1890 continue to boot on existing non-UEFI platforms. 1891 1892 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1893 i.e., the the practice of identifying the platform via DMI to 1894 decide whether certain workarounds for buggy hardware and/or 1895 firmware need to be enabled. This would require the DMI subsystem 1896 to be enabled much earlier than we do on ARM, which is non-trivial. 1897 1898endmenu 1899 1900menu "CPU Power Management" 1901 1902source "drivers/cpufreq/Kconfig" 1903 1904source "drivers/cpuidle/Kconfig" 1905 1906endmenu 1907 1908menu "Floating point emulation" 1909 1910comment "At least one emulation must be selected" 1911 1912config FPE_NWFPE 1913 bool "NWFPE math emulation" 1914 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1915 help 1916 Say Y to include the NWFPE floating point emulator in the kernel. 1917 This is necessary to run most binaries. Linux does not currently 1918 support floating point hardware so you need to say Y here even if 1919 your machine has an FPA or floating point co-processor podule. 1920 1921 You may say N here if you are going to load the Acorn FPEmulator 1922 early in the bootup. 1923 1924config FPE_NWFPE_XP 1925 bool "Support extended precision" 1926 depends on FPE_NWFPE 1927 help 1928 Say Y to include 80-bit support in the kernel floating-point 1929 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1930 Note that gcc does not generate 80-bit operations by default, 1931 so in most cases this option only enlarges the size of the 1932 floating point emulator without any good reason. 1933 1934 You almost surely want to say N here. 1935 1936config FPE_FASTFPE 1937 bool "FastFPE math emulation (EXPERIMENTAL)" 1938 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1939 help 1940 Say Y here to include the FAST floating point emulator in the kernel. 1941 This is an experimental much faster emulator which now also has full 1942 precision for the mantissa. It does not support any exceptions. 1943 It is very simple, and approximately 3-6 times faster than NWFPE. 1944 1945 It should be sufficient for most programs. It may be not suitable 1946 for scientific calculations, but you have to check this for yourself. 1947 If you do not feel you need a faster FP emulation you should better 1948 choose NWFPE. 1949 1950config VFP 1951 bool "VFP-format floating point maths" 1952 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1953 help 1954 Say Y to include VFP support code in the kernel. This is needed 1955 if your hardware includes a VFP unit. 1956 1957 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1958 release notes and additional status information. 1959 1960 Say N if your target does not have VFP hardware. 1961 1962config VFPv3 1963 bool 1964 depends on VFP 1965 default y if CPU_V7 1966 1967config NEON 1968 bool "Advanced SIMD (NEON) Extension support" 1969 depends on VFPv3 && CPU_V7 1970 help 1971 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1972 Extension. 1973 1974config KERNEL_MODE_NEON 1975 bool "Support for NEON in kernel mode" 1976 depends on NEON && AEABI 1977 help 1978 Say Y to include support for NEON in kernel mode. 1979 1980endmenu 1981 1982menu "Power management options" 1983 1984source "kernel/power/Kconfig" 1985 1986config ARCH_SUSPEND_POSSIBLE 1987 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1988 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1989 def_bool y 1990 1991config ARM_CPU_SUSPEND 1992 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1993 depends on ARCH_SUSPEND_POSSIBLE 1994 1995config ARCH_HIBERNATION_POSSIBLE 1996 bool 1997 depends on MMU 1998 default y if ARCH_SUSPEND_POSSIBLE 1999 2000endmenu 2001 2002source "drivers/firmware/Kconfig" 2003 2004if CRYPTO 2005source "arch/arm/crypto/Kconfig" 2006endif 2007 2008source "arch/arm/Kconfig.assembler" 2009