1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CC_CAN_LINK 10 select ARCH_HAS_CPU_CACHE_ALIASING 11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_HAS_DEBUG_VIRTUAL if MMU 14 select ARCH_HAS_DELAY_TIMER 15 select ARCH_HAS_DMA_ALLOC if MMU 16 select ARCH_HAS_DMA_OPS 17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 18 select ARCH_HAS_ELF_RANDOMIZE 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_KEEPINITRD 21 select ARCH_HAS_KCOV 22 select ARCH_HAS_MEMBARRIER_SYNC_CORE 23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 25 select ARCH_HAS_SETUP_DMA_OPS 26 select ARCH_HAS_SET_MEMORY 27 select ARCH_STACKWALK 28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 29 select ARCH_HAS_STRICT_MODULE_RWX if MMU 30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 31 select ARCH_HAS_SYNC_DMA_FOR_CPU 32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 35 select ARCH_HAS_GCOV_PROFILE_ALL 36 select ARCH_KEEP_MEMBLOCK 37 select ARCH_HAS_UBSAN 38 select ARCH_MIGHT_HAVE_PC_PARPORT 39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 42 select ARCH_SUPPORTS_ATOMIC_RMW 43 select ARCH_SUPPORTS_CFI 44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 45 select ARCH_SUPPORTS_PER_VMA_LOCK 46 select ARCH_SUPPORTS_RT 47 select ARCH_USE_BUILTIN_BSWAP 48 select ARCH_USE_CMPXCHG_LOCKREF 49 select ARCH_USE_MEMTEST 50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 51 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 52 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 53 select ARCH_WANT_GENERAL_HUGETLB 54 select ARCH_WANT_IPC_PARSE_VERSION 55 select ARCH_WANT_LD_ORPHAN_WARN 56 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 57 select BUILDTIME_TABLE_SORT if MMU 58 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 59 select CLONE_BACKWARDS 60 select CPU_PM if SUSPEND || CPU_IDLE 61 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 62 select DMA_DECLARE_COHERENT 63 select DMA_GLOBAL_POOL if !MMU 64 select DMA_NONCOHERENT_MMAP if MMU 65 select EDAC_SUPPORT 66 select EDAC_ATOMIC_SCRUB 67 select GENERIC_ALLOCATOR 68 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 69 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 70 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 71 select GENERIC_IRQ_IPI if SMP 72 select GENERIC_CPU_AUTOPROBE 73 select GENERIC_CPU_DEVICES 74 select GENERIC_EARLY_IOREMAP 75 select GENERIC_IDLE_POLL_SETUP 76 select GENERIC_IRQ_MULTI_HANDLER 77 select GENERIC_IRQ_PROBE 78 select GENERIC_IRQ_SHOW 79 select GENERIC_IRQ_SHOW_LEVEL 80 select GENERIC_LIB_DEVMEM_IS_ALLOWED 81 select GENERIC_PCI_IOMAP 82 select GENERIC_SCHED_CLOCK 83 select GENERIC_SMP_IDLE_THREAD 84 select HARDIRQS_SW_RESEND 85 select HAS_IOPORT 86 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 87 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 && BITREVERSE 88 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP) 89 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 90 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 91 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 92 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 93 select HAVE_ARCH_KSTACK_ERASE 94 select HAVE_ARCH_MMAP_RND_BITS if MMU 95 select HAVE_ARCH_PFN_VALID 96 select HAVE_ARCH_SECCOMP 97 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 98 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 99 select HAVE_ARCH_TRACEHOOK 100 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 101 select HAVE_ARM_SMCCC if CPU_V7 102 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 103 select HAVE_CONTEXT_TRACKING_USER 104 select HAVE_C_RECORDMCOUNT 105 select HAVE_BUILDTIME_MCOUNT_SORT 106 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 107 select HAVE_DMA_CONTIGUOUS if MMU 108 select HAVE_EXTRA_IPI_TRACEPOINTS 109 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 110 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 111 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 112 select HAVE_EXIT_THREAD 113 select HAVE_GUP_FAST if ARM_LPAE 114 select HAVE_FUNCTION_ERROR_INJECTION 115 select HAVE_FUNCTION_GRAPH_TRACER 116 select HAVE_FUNCTION_GRAPH_FREGS 117 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 118 select HAVE_GCC_PLUGINS 119 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 120 select HAVE_IRQ_TIME_ACCOUNTING 121 select HAVE_KERNEL_GZIP 122 select HAVE_KERNEL_LZ4 123 select HAVE_KERNEL_LZMA 124 select HAVE_KERNEL_LZO 125 select HAVE_KERNEL_XZ 126 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 127 select HAVE_KRETPROBES if HAVE_KPROBES 128 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 129 select HAVE_MOD_ARCH_SPECIFIC 130 select HAVE_NMI 131 select HAVE_OPTPROBES if !THUMB2_KERNEL 132 select HAVE_PAGE_SIZE_4KB 133 select HAVE_PCI if MMU 134 select HAVE_PERF_EVENTS 135 select HAVE_PERF_REGS 136 select HAVE_PERF_USER_STACK_DUMP 137 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 138 select HAVE_REGS_AND_STACK_ACCESS_API 139 select HAVE_RSEQ 140 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN 141 select HAVE_STACKPROTECTOR 142 select HAVE_SYSCALL_TRACEPOINTS 143 select HAVE_UID16 144 select HAVE_VIRT_CPU_ACCOUNTING_GEN 145 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 146 select IRQ_FORCED_THREADING 147 select LOCK_MM_AND_FIND_VMA 148 select MODULES_USE_ELF_REL 149 select NEED_DMA_MAP_STATE 150 select OF_EARLY_FLATTREE if OF 151 select OLD_SIGACTION 152 select OLD_SIGSUSPEND3 153 select PCI_DOMAINS_GENERIC if PCI 154 select PCI_SYSCALL if PCI 155 select PERF_USE_VMALLOC 156 select RTC_LIB 157 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 158 select SYS_SUPPORTS_APM_EMULATION 159 select THREAD_INFO_IN_TASK 160 select TIMER_OF if OF 161 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 162 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 163 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 164 # Above selects are sorted alphabetically; please add new ones 165 # according to that. Thanks. 166 help 167 The ARM series is a line of low-power-consumption RISC chip designs 168 licensed by ARM Ltd and targeted at embedded applications and 169 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 170 manufactured, but legacy ARM-based PC hardware remains popular in 171 Europe. There is an ARM Linux project with a web page at 172 <http://www.arm.linux.org.uk/>. 173 174config ARM_HAS_GROUP_RELOCS 175 def_bool !COMPILE_TEST 176 help 177 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 178 relocations. The combined range is -/+ 256 MiB, which is usually 179 sufficient, but not for allyesconfig, so we disable this feature 180 when doing compile testing. 181 182config ARM_DMA_USE_IOMMU 183 bool 184 select NEED_SG_DMA_LENGTH 185 186if ARM_DMA_USE_IOMMU 187 188config ARM_DMA_IOMMU_ALIGNMENT 189 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 190 range 4 9 191 default 8 192 help 193 DMA mapping framework by default aligns all buffers to the smallest 194 PAGE_SIZE order which is greater than or equal to the requested buffer 195 size. This works well for buffers up to a few hundreds kilobytes, but 196 for larger buffers it just a waste of address space. Drivers which has 197 relatively small addressing window (like 64Mib) might run out of 198 virtual space with just a few allocations. 199 200 With this parameter you can specify the maximum PAGE_SIZE order for 201 DMA IOMMU buffers. Larger buffers will be aligned only to this 202 specified order. The order is expressed as a power of two multiplied 203 by the PAGE_SIZE. 204 205endif 206 207config SYS_SUPPORTS_APM_EMULATION 208 bool 209 210config HAVE_TCM 211 bool 212 select GENERIC_ALLOCATOR 213 214config HAVE_PROC_CPU 215 bool 216 217config NO_IOPORT_MAP 218 bool 219 220config SBUS 221 bool 222 223config STACKTRACE_SUPPORT 224 bool 225 default y 226 227config LOCKDEP_SUPPORT 228 bool 229 default y 230 231config ARCH_HAS_ILOG2_U32 232 bool 233 234config ARCH_HAS_ILOG2_U64 235 bool 236 237config ARCH_HAS_BANDGAP 238 bool 239 240config FIX_EARLYCON_MEM 241 def_bool y if MMU 242 243config GENERIC_HWEIGHT 244 bool 245 default y 246 247config GENERIC_CALIBRATE_DELAY 248 bool 249 default y 250 251config ARCH_MAY_HAVE_PC_FDC 252 bool 253 254config ARCH_SUPPORTS_UPROBES 255 def_bool y 256 257config GENERIC_ISA_DMA 258 bool 259 260config FIQ 261 bool 262 263config ARCH_MTD_XIP 264 bool 265 266config ARM_PATCH_PHYS_VIRT 267 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 268 default y 269 depends on MMU 270 help 271 Patch phys-to-virt and virt-to-phys translation functions at 272 boot and module load time according to the position of the 273 kernel in system memory. 274 275 This can only be used with non-XIP MMU kernels where the base 276 of physical memory is at a 2 MiB boundary. 277 278 Only disable this option if you know that you do not require 279 this feature (eg, building a kernel for a single machine) and 280 you need to shrink the kernel to the minimal size. 281 282config NEED_MACH_IO_H 283 bool 284 help 285 Select this when mach/io.h is required to provide special 286 definitions for this platform. The need for mach/io.h should 287 be avoided when possible. 288 289config NEED_MACH_MEMORY_H 290 bool 291 help 292 Select this when mach/memory.h is required to provide special 293 definitions for this platform. The need for mach/memory.h should 294 be avoided when possible. 295 296config PHYS_OFFSET 297 hex "Physical address of main memory" if MMU 298 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 299 default DRAM_BASE if !MMU 300 default 0x00000000 if ARCH_FOOTBRIDGE 301 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 302 default 0xa0000000 if ARCH_PXA 303 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 304 default 0 305 help 306 Please provide the physical address corresponding to the 307 location of main memory in your system. 308 309config GENERIC_BUG 310 def_bool y 311 depends on BUG 312 313config PGTABLE_LEVELS 314 int 315 default 3 if ARM_LPAE 316 default 2 317 318menu "System Type" 319 320config MMU 321 bool "MMU-based Paged Memory Management Support" 322 default y 323 help 324 Select if you want MMU-based virtualised addressing space 325 support by paged memory management. If unsure, say 'Y'. 326 327config ARM_SINGLE_ARMV7M 328 def_bool !MMU 329 select ARM_NVIC 330 select CPU_V7M 331 select NO_IOPORT_MAP 332 333config ARCH_MMAP_RND_BITS_MIN 334 default 8 335 336config ARCH_MMAP_RND_BITS_MAX 337 default 14 if PAGE_OFFSET=0x40000000 338 default 15 if PAGE_OFFSET=0x80000000 339 default 16 340 341config ARCH_MULTIPLATFORM 342 bool "Require kernel to be portable to multiple machines" if EXPERT 343 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 344 default y 345 help 346 In general, all Arm machines can be supported in a single 347 kernel image, covering either Armv4/v5 or Armv6/v7. 348 349 However, some configuration options require hardcoding machine 350 specific physical addresses or enable errata workarounds that may 351 break other machines. 352 353 Selecting N here allows using those options, including 354 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 355 356source "arch/arm/Kconfig.platforms" 357 358# 359# This is sorted alphabetically by mach-* pathname. However, plat-* 360# Kconfigs may be included either alphabetically (according to the 361# plat- suffix) or along side the corresponding mach-* source. 362# 363source "arch/arm/mach-actions/Kconfig" 364 365source "arch/arm/mach-alpine/Kconfig" 366 367source "arch/arm/mach-artpec/Kconfig" 368 369source "arch/arm/mach-aspeed/Kconfig" 370 371source "arch/arm/mach-at91/Kconfig" 372 373source "arch/arm/mach-axxia/Kconfig" 374 375source "arch/arm/mach-bcm/Kconfig" 376 377source "arch/arm/mach-berlin/Kconfig" 378 379source "arch/arm/mach-clps711x/Kconfig" 380 381source "arch/arm/mach-davinci/Kconfig" 382 383source "arch/arm/mach-digicolor/Kconfig" 384 385source "arch/arm/mach-dove/Kconfig" 386 387source "arch/arm/mach-ep93xx/Kconfig" 388 389source "arch/arm/mach-exynos/Kconfig" 390 391source "arch/arm/mach-footbridge/Kconfig" 392 393source "arch/arm/mach-gemini/Kconfig" 394 395source "arch/arm/mach-highbank/Kconfig" 396 397source "arch/arm/mach-hisi/Kconfig" 398 399source "arch/arm/mach-imx/Kconfig" 400 401source "arch/arm/mach-ixp4xx/Kconfig" 402 403source "arch/arm/mach-keystone/Kconfig" 404 405source "arch/arm/mach-lpc32xx/Kconfig" 406 407source "arch/arm/mach-mediatek/Kconfig" 408 409source "arch/arm/mach-meson/Kconfig" 410 411source "arch/arm/mach-milbeaut/Kconfig" 412 413source "arch/arm/mach-mmp/Kconfig" 414 415source "arch/arm/mach-mstar/Kconfig" 416 417source "arch/arm/mach-mv78xx0/Kconfig" 418 419source "arch/arm/mach-mvebu/Kconfig" 420 421source "arch/arm/mach-mxs/Kconfig" 422 423source "arch/arm/mach-nomadik/Kconfig" 424 425source "arch/arm/mach-npcm/Kconfig" 426 427source "arch/arm/mach-omap1/Kconfig" 428 429source "arch/arm/mach-omap2/Kconfig" 430 431source "arch/arm/mach-orion5x/Kconfig" 432 433source "arch/arm/mach-pxa/Kconfig" 434 435source "arch/arm/mach-qcom/Kconfig" 436 437source "arch/arm/mach-realtek/Kconfig" 438 439source "arch/arm/mach-rpc/Kconfig" 440 441source "arch/arm/mach-rockchip/Kconfig" 442 443source "arch/arm/mach-s3c/Kconfig" 444 445source "arch/arm/mach-s5pv210/Kconfig" 446 447source "arch/arm/mach-sa1100/Kconfig" 448 449source "arch/arm/mach-shmobile/Kconfig" 450 451source "arch/arm/mach-socfpga/Kconfig" 452 453source "arch/arm/mach-spear/Kconfig" 454 455source "arch/arm/mach-sti/Kconfig" 456 457source "arch/arm/mach-stm32/Kconfig" 458 459source "arch/arm/mach-sunxi/Kconfig" 460 461source "arch/arm/mach-tegra/Kconfig" 462 463source "arch/arm/mach-ux500/Kconfig" 464 465source "arch/arm/mach-versatile/Kconfig" 466 467source "arch/arm/mach-vt8500/Kconfig" 468 469source "arch/arm/mach-zte/Kconfig" 470 471source "arch/arm/mach-zynq/Kconfig" 472 473# ARMv7-M architecture 474config ARCH_LPC18XX 475 bool "NXP LPC18xx/LPC43xx" 476 depends on ARM_SINGLE_ARMV7M 477 select ARCH_HAS_RESET_CONTROLLER 478 select ARM_AMBA 479 select CLKSRC_LPC32XX 480 select PINCTRL 481 help 482 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 483 high performance microcontrollers. 484 485config ARCH_MPS2 486 bool "ARM MPS2 platform" 487 depends on ARM_SINGLE_ARMV7M 488 select ARM_AMBA 489 select CLKSRC_MPS2 490 help 491 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 492 with a range of available cores like Cortex-M3/M4/M7. 493 494 Please, note that depends which Application Note is used memory map 495 for the platform may vary, so adjustment of RAM base might be needed. 496 497# Definitions to make life easier 498config ARCH_ACORN 499 bool 500 501config PLAT_ORION 502 bool 503 select CLKSRC_MMIO 504 select GENERIC_IRQ_CHIP 505 select IRQ_DOMAIN 506 507config PLAT_ORION_LEGACY 508 bool 509 select PLAT_ORION 510 511config PLAT_VERSATILE 512 bool 513 514source "arch/arm/mm/Kconfig" 515 516config IWMMXT 517 bool "Enable iWMMXt support" 518 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 519 default y if PXA27x || PXA3xx || ARCH_MMP 520 help 521 Enable support for iWMMXt context switching at run time if 522 running on a CPU that supports it. 523 524if !MMU 525source "arch/arm/Kconfig-nommu" 526endif 527 528config PJ4B_ERRATA_4742 529 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 530 depends on CPU_PJ4B && MACH_ARMADA_370 531 default y 532 help 533 When coming out of either a Wait for Interrupt (WFI) or a Wait for 534 Event (WFE) IDLE states, a specific timing sensitivity exists between 535 the retiring WFI/WFE instructions and the newly issued subsequent 536 instructions. This sensitivity can result in a CPU hang scenario. 537 Workaround: 538 The software must insert either a Data Synchronization Barrier (DSB) 539 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 540 instruction 541 542config ARM_ERRATA_326103 543 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 544 depends on CPU_V6 545 help 546 Executing a SWP instruction to read-only memory does not set bit 11 547 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 548 treat the access as a read, preventing a COW from occurring and 549 causing the faulting task to livelock. 550 551config ARM_ERRATA_411920 552 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 553 depends on CPU_V6 || CPU_V6K 554 help 555 Invalidation of the Instruction Cache operation can 556 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 557 It does not affect the MPCore. This option enables the ARM Ltd. 558 recommended workaround. 559 560config ARM_ERRATA_430973 561 bool "ARM errata: Stale prediction on replaced interworking branch" 562 depends on CPU_V7 563 help 564 This option enables the workaround for the 430973 Cortex-A8 565 r1p* erratum. If a code sequence containing an ARM/Thumb 566 interworking branch is replaced with another code sequence at the 567 same virtual address, whether due to self-modifying code or virtual 568 to physical address re-mapping, Cortex-A8 does not recover from the 569 stale interworking branch prediction. This results in Cortex-A8 570 executing the new code sequence in the incorrect ARM or Thumb state. 571 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 572 and also flushes the branch target cache at every context switch. 573 Note that setting specific bits in the ACTLR register may not be 574 available in non-secure mode. 575 576config ARM_ERRATA_458693 577 bool "ARM errata: Processor deadlock when a false hazard is created" 578 depends on CPU_V7 579 depends on !ARCH_MULTIPLATFORM 580 help 581 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 582 erratum. For very specific sequences of memory operations, it is 583 possible for a hazard condition intended for a cache line to instead 584 be incorrectly associated with a different cache line. This false 585 hazard might then cause a processor deadlock. The workaround enables 586 the L1 caching of the NEON accesses and disables the PLD instruction 587 in the ACTLR register. Note that setting specific bits in the ACTLR 588 register may not be available in non-secure mode and thus is not 589 available on a multiplatform kernel. This should be applied by the 590 bootloader instead. 591 592config ARM_ERRATA_460075 593 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 594 depends on CPU_V7 595 depends on !ARCH_MULTIPLATFORM 596 help 597 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 598 erratum. Any asynchronous access to the L2 cache may encounter a 599 situation in which recent store transactions to the L2 cache are lost 600 and overwritten with stale memory contents from external memory. The 601 workaround disables the write-allocate mode for the L2 cache via the 602 ACTLR register. Note that setting specific bits in the ACTLR register 603 may not be available in non-secure mode and thus is not available on 604 a multiplatform kernel. This should be applied by the bootloader 605 instead. 606 607config ARM_ERRATA_742230 608 bool "ARM errata: DMB operation may be faulty" 609 depends on CPU_V7 && SMP 610 depends on !ARCH_MULTIPLATFORM 611 help 612 This option enables the workaround for the 742230 Cortex-A9 613 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 614 between two write operations may not ensure the correct visibility 615 ordering of the two writes. This workaround sets a specific bit in 616 the diagnostic register of the Cortex-A9 which causes the DMB 617 instruction to behave as a DSB, ensuring the correct behaviour of 618 the two writes. Note that setting specific bits in the diagnostics 619 register may not be available in non-secure mode and thus is not 620 available on a multiplatform kernel. This should be applied by the 621 bootloader instead. 622 623config ARM_ERRATA_742231 624 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 625 depends on CPU_V7 && SMP 626 depends on !ARCH_MULTIPLATFORM 627 help 628 This option enables the workaround for the 742231 Cortex-A9 629 (r2p0..r2p2) erratum. Under certain conditions, specific to the 630 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 631 accessing some data located in the same cache line, may get corrupted 632 data due to bad handling of the address hazard when the line gets 633 replaced from one of the CPUs at the same time as another CPU is 634 accessing it. This workaround sets specific bits in the diagnostic 635 register of the Cortex-A9 which reduces the linefill issuing 636 capabilities of the processor. Note that setting specific bits in the 637 diagnostics register may not be available in non-secure mode and thus 638 is not available on a multiplatform kernel. This should be applied by 639 the bootloader instead. 640 641config ARM_ERRATA_643719 642 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 643 depends on CPU_V7 && SMP 644 default y 645 help 646 This option enables the workaround for the 643719 Cortex-A9 (prior to 647 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 648 register returns zero when it should return one. The workaround 649 corrects this value, ensuring cache maintenance operations which use 650 it behave as intended and avoiding data corruption. 651 652config ARM_ERRATA_720789 653 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 654 depends on CPU_V7 655 help 656 This option enables the workaround for the 720789 Cortex-A9 (prior to 657 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 658 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 659 As a consequence of this erratum, some TLB entries which should be 660 invalidated are not, resulting in an incoherency in the system page 661 tables. The workaround changes the TLB flushing routines to invalidate 662 entries regardless of the ASID. 663 664config ARM_ERRATA_743622 665 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 666 depends on CPU_V7 667 depends on !ARCH_MULTIPLATFORM 668 help 669 This option enables the workaround for the 743622 Cortex-A9 670 (r2p*) erratum. Under very rare conditions, a faulty 671 optimisation in the Cortex-A9 Store Buffer may lead to data 672 corruption. This workaround sets a specific bit in the diagnostic 673 register of the Cortex-A9 which disables the Store Buffer 674 optimisation, preventing the defect from occurring. This has no 675 visible impact on the overall performance or power consumption of the 676 processor. Note that setting specific bits in the diagnostics register 677 may not be available in non-secure mode and thus is not available on a 678 multiplatform kernel. This should be applied by the bootloader instead. 679 680config ARM_ERRATA_751472 681 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 682 depends on CPU_V7 683 depends on !ARCH_MULTIPLATFORM 684 help 685 This option enables the workaround for the 751472 Cortex-A9 (prior 686 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 687 completion of a following broadcasted operation if the second 688 operation is received by a CPU before the ICIALLUIS has completed, 689 potentially leading to corrupted entries in the cache or TLB. 690 Note that setting specific bits in the diagnostics register may 691 not be available in non-secure mode and thus is not available on 692 a multiplatform kernel. This should be applied by the bootloader 693 instead. 694 695config ARM_ERRATA_754322 696 bool "ARM errata: possible faulty MMU translations following an ASID switch" 697 depends on CPU_V7 698 help 699 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 700 r3p*) erratum. A speculative memory access may cause a page table walk 701 which starts prior to an ASID switch but completes afterwards. This 702 can populate the micro-TLB with a stale entry which may be hit with 703 the new ASID. This workaround places two dsb instructions in the mm 704 switching code so that no page table walks can cross the ASID switch. 705 706config ARM_ERRATA_754327 707 bool "ARM errata: no automatic Store Buffer drain" 708 depends on CPU_V7 && SMP 709 help 710 This option enables the workaround for the 754327 Cortex-A9 (prior to 711 r2p0) erratum. The Store Buffer does not have any automatic draining 712 mechanism and therefore a livelock may occur if an external agent 713 continuously polls a memory location waiting to observe an update. 714 This workaround defines cpu_relax() as smp_mb(), preventing correctly 715 written polling loops from denying visibility of updates to memory. 716 717config ARM_ERRATA_364296 718 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 719 depends on CPU_V6 720 help 721 This options enables the workaround for the 364296 ARM1136 722 r0p2 erratum (possible cache data corruption with 723 hit-under-miss enabled). It sets the undocumented bit 31 in 724 the auxiliary control register and the FI bit in the control 725 register, thus disabling hit-under-miss without putting the 726 processor into full low interrupt latency mode. ARM11MPCore 727 is not affected. 728 729config ARM_ERRATA_764369 730 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 731 depends on CPU_V7 && SMP 732 help 733 This option enables the workaround for erratum 764369 734 affecting Cortex-A9 MPCore with two or more processors (all 735 current revisions). Under certain timing circumstances, a data 736 cache line maintenance operation by MVA targeting an Inner 737 Shareable memory region may fail to proceed up to either the 738 Point of Coherency or to the Point of Unification of the 739 system. This workaround adds a DSB instruction before the 740 relevant cache maintenance functions and sets a specific bit 741 in the diagnostic control register of the SCU. 742 743config ARM_ERRATA_764319 744 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 745 depends on CPU_V7 746 help 747 This option enables the workaround for the 764319 Cortex-A9 erratum. 748 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 749 unexpected Undefined Instruction exception when the DBGSWENABLE 750 external pin is set to 0, even when the CP14 accesses are performed 751 from a privileged mode. This work around catches the exception in a 752 way the kernel does not stop execution. 753 754config ARM_ERRATA_775420 755 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 756 depends on CPU_V7 757 help 758 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 759 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 760 operation aborts with MMU exception, it might cause the processor 761 to deadlock. This workaround puts DSB before executing ISB if 762 an abort may occur on cache maintenance. 763 764config ARM_ERRATA_798181 765 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 766 depends on CPU_V7 && SMP 767 help 768 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 769 adequately shooting down all use of the old entries. This 770 option enables the Linux kernel workaround for this erratum 771 which sends an IPI to the CPUs that are running the same ASID 772 as the one being invalidated. 773 774config ARM_ERRATA_773022 775 bool "ARM errata: incorrect instructions may be executed from loop buffer" 776 depends on CPU_V7 777 help 778 This option enables the workaround for the 773022 Cortex-A15 779 (up to r0p4) erratum. In certain rare sequences of code, the 780 loop buffer may deliver incorrect instructions. This 781 workaround disables the loop buffer to avoid the erratum. 782 783config ARM_ERRATA_818325_852422 784 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 785 depends on CPU_V7 786 help 787 This option enables the workaround for: 788 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 789 instruction might deadlock. Fixed in r0p1. 790 - Cortex-A12 852422: Execution of a sequence of instructions might 791 lead to either a data corruption or a CPU deadlock. Not fixed in 792 any Cortex-A12 cores yet. 793 This workaround for all both errata involves setting bit[12] of the 794 Feature Register. This bit disables an optimisation applied to a 795 sequence of 2 instructions that use opposing condition codes. 796 797config ARM_ERRATA_821420 798 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 799 depends on CPU_V7 800 help 801 This option enables the workaround for the 821420 Cortex-A12 802 (all revs) erratum. In very rare timing conditions, a sequence 803 of VMOV to Core registers instructions, for which the second 804 one is in the shadow of a branch or abort, can lead to a 805 deadlock when the VMOV instructions are issued out-of-order. 806 807config ARM_ERRATA_825619 808 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 809 depends on CPU_V7 810 help 811 This option enables the workaround for the 825619 Cortex-A12 812 (all revs) erratum. Within rare timing constraints, executing a 813 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 814 and Device/Strongly-Ordered loads and stores might cause deadlock 815 816config ARM_ERRATA_857271 817 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 818 depends on CPU_V7 819 help 820 This option enables the workaround for the 857271 Cortex-A12 821 (all revs) erratum. Under very rare timing conditions, the CPU might 822 hang. The workaround is expected to have a < 1% performance impact. 823 824config ARM_ERRATA_852421 825 bool "ARM errata: A17: DMB ST might fail to create order between stores" 826 depends on CPU_V7 827 help 828 This option enables the workaround for the 852421 Cortex-A17 829 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 830 execution of a DMB ST instruction might fail to properly order 831 stores from GroupA and stores from GroupB. 832 833config ARM_ERRATA_852423 834 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 835 depends on CPU_V7 836 help 837 This option enables the workaround for: 838 - Cortex-A17 852423: Execution of a sequence of instructions might 839 lead to either a data corruption or a CPU deadlock. Not fixed in 840 any Cortex-A17 cores yet. 841 This is identical to Cortex-A12 erratum 852422. It is a separate 842 config option from the A12 erratum due to the way errata are checked 843 for and handled. 844 845config ARM_ERRATA_857272 846 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 847 depends on CPU_V7 848 help 849 This option enables the workaround for the 857272 Cortex-A17 erratum. 850 This erratum is not known to be fixed in any A17 revision. 851 This is identical to Cortex-A12 erratum 857271. It is a separate 852 config option from the A12 erratum due to the way errata are checked 853 for and handled. 854 855endmenu 856 857source "arch/arm/common/Kconfig" 858 859menu "Bus support" 860 861config ISA 862 bool 863 help 864 Find out whether you have ISA slots on your motherboard. ISA is the 865 name of a bus system, i.e. the way the CPU talks to the other stuff 866 inside your box. Other bus systems are PCI, EISA, MicroChannel 867 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 868 newer boards don't support it. If you have ISA, say Y, otherwise N. 869 870# Select ISA DMA interface 871config ISA_DMA_API 872 bool 873 874config ARM_ERRATA_814220 875 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 876 depends on CPU_V7 877 help 878 The v7 ARM states that all cache and branch predictor maintenance 879 operations that do not specify an address execute, relative to 880 each other, in program order. 881 However, because of this erratum, an L2 set/way cache maintenance 882 operation can overtake an L1 set/way cache maintenance operation. 883 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 884 r0p4, r0p5. 885 886endmenu 887 888menu "Kernel Features" 889 890config HAVE_SMP 891 bool 892 help 893 This option should be selected by machines which have an SMP- 894 capable CPU. 895 896 The only effect of this option is to make the SMP-related 897 options available to the user for configuration. 898 899config SMP 900 bool "Symmetric Multi-Processing" 901 depends on CPU_V6K || CPU_V7 902 depends on HAVE_SMP 903 depends on MMU || ARM_MPU 904 select IRQ_WORK 905 help 906 This enables support for systems with more than one CPU. If you have 907 a system with only one CPU, say N. If you have a system with more 908 than one CPU, say Y. 909 910 If you say N here, the kernel will run on uni- and multiprocessor 911 machines, but will use only one CPU of a multiprocessor machine. If 912 you say Y here, the kernel will run on many, but not all, 913 uniprocessor machines. On a uniprocessor machine, the kernel 914 will run faster if you say N here. 915 916 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 917 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 918 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 919 920 If you don't know what to do here, say N. 921 922config SMP_ON_UP 923 bool "Allow booting SMP kernel on uniprocessor systems" 924 depends on SMP && MMU 925 default y 926 help 927 SMP kernels contain instructions which fail on non-SMP processors. 928 Enabling this option allows the kernel to modify itself to make 929 these instructions safe. Disabling it allows about 1K of space 930 savings. 931 932 If you don't know what to do here, say Y. 933 934 935config CURRENT_POINTER_IN_TPIDRURO 936 def_bool y 937 depends on CPU_32v6K && !CPU_V6 938 939config IRQSTACKS 940 def_bool y 941 select HAVE_IRQ_EXIT_ON_IRQ_STACK 942 select HAVE_SOFTIRQ_ON_OWN_STACK 943 944config ARM_CPU_TOPOLOGY 945 bool "Support cpu topology definition" 946 depends on SMP && CPU_V7 947 select ARCH_SUPPORTS_SCHED_MC 948 select ARCH_SUPPORTS_SCHED_SMT 949 default y 950 help 951 Support ARM cpu topology definition. The MPIDR register defines 952 affinity between processors which is then used to describe the cpu 953 topology of an ARM System. 954 955config HAVE_ARM_SCU 956 bool 957 help 958 This option enables support for the ARM snoop control unit 959 960config HAVE_ARM_ARCH_TIMER 961 bool "Architected timer support" 962 depends on CPU_V7 963 select ARM_ARCH_TIMER 964 help 965 This option enables support for the ARM architected timer 966 967config HAVE_ARM_TWD 968 bool 969 help 970 This options enables support for the ARM timer and watchdog unit 971 972config MCPM 973 bool "Multi-Cluster Power Management" 974 depends on CPU_V7 && SMP 975 help 976 This option provides the common power management infrastructure 977 for (multi-)cluster based systems, such as big.LITTLE based 978 systems. 979 980config MCPM_QUAD_CLUSTER 981 bool 982 depends on MCPM 983 help 984 To avoid wasting resources unnecessarily, MCPM only supports up 985 to 2 clusters by default. 986 Platforms with 3 or 4 clusters that use MCPM must select this 987 option to allow the additional clusters to be managed. 988 989config BIG_LITTLE 990 bool "big.LITTLE support (Experimental)" 991 depends on CPU_V7 && SMP 992 select MCPM 993 help 994 This option enables support selections for the big.LITTLE 995 system architecture. 996 997config BL_SWITCHER 998 bool "big.LITTLE switcher support" 999 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1000 select CPU_PM 1001 help 1002 The big.LITTLE "switcher" provides the core functionality to 1003 transparently handle transition between a cluster of A15's 1004 and a cluster of A7's in a big.LITTLE system. 1005 1006config BL_SWITCHER_DUMMY_IF 1007 tristate "Simple big.LITTLE switcher user interface" 1008 depends on BL_SWITCHER && DEBUG_KERNEL 1009 help 1010 This is a simple and dummy char dev interface to control 1011 the big.LITTLE switcher core code. It is meant for 1012 debugging purposes only. 1013 1014choice 1015 prompt "Memory split" 1016 depends on MMU 1017 default VMSPLIT_3G 1018 help 1019 Select the desired split between kernel and user memory. 1020 1021 If you are not absolutely sure what you are doing, leave this 1022 option alone! 1023 1024 config VMSPLIT_3G 1025 bool "3G/1G user/kernel split" 1026 config VMSPLIT_3G_OPT 1027 depends on !ARM_LPAE 1028 bool "3G/1G user/kernel split (for full 1G low memory)" 1029 config VMSPLIT_2G 1030 bool "2G/2G user/kernel split" 1031 config VMSPLIT_1G 1032 bool "1G/3G user/kernel split" 1033endchoice 1034 1035config PAGE_OFFSET 1036 hex 1037 default PHYS_OFFSET if !MMU 1038 default 0x40000000 if VMSPLIT_1G 1039 default 0x80000000 if VMSPLIT_2G 1040 default 0xB0000000 if VMSPLIT_3G_OPT 1041 default 0xC0000000 1042 1043config KASAN_SHADOW_OFFSET 1044 hex 1045 depends on KASAN 1046 default 0x1f000000 if PAGE_OFFSET=0x40000000 1047 default 0x5f000000 if PAGE_OFFSET=0x80000000 1048 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1049 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1050 default 0xffffffff 1051 1052config NR_CPUS 1053 int "Maximum number of CPUs (2-32)" 1054 range 2 16 if DEBUG_KMAP_LOCAL 1055 range 2 32 if !DEBUG_KMAP_LOCAL 1056 depends on SMP 1057 default "4" 1058 help 1059 The maximum number of CPUs that the kernel can support. 1060 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1061 debugging is enabled, which uses half of the per-CPU fixmap 1062 slots as guard regions. 1063 1064config HOTPLUG_CPU 1065 bool "Support for hot-pluggable CPUs" 1066 depends on SMP 1067 select GENERIC_IRQ_MIGRATION 1068 help 1069 Say Y here to experiment with turning CPUs off and on. CPUs 1070 can be controlled through /sys/devices/system/cpu. 1071 1072config ARM_PSCI 1073 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1074 depends on HAVE_ARM_SMCCC 1075 select ARM_PSCI_FW 1076 help 1077 Say Y here if you want Linux to communicate with system firmware 1078 implementing the PSCI specification for CPU-centric power 1079 management operations described in ARM document number ARM DEN 1080 0022A ("Power State Coordination Interface System Software on 1081 ARM processors"). 1082 1083config HZ_FIXED 1084 int 1085 default 128 if SOC_AT91RM9200 1086 default 0 1087 1088choice 1089 depends on HZ_FIXED = 0 1090 prompt "Timer frequency" 1091 1092config HZ_100 1093 bool "100 Hz" 1094 1095config HZ_200 1096 bool "200 Hz" 1097 1098config HZ_250 1099 bool "250 Hz" 1100 1101config HZ_300 1102 bool "300 Hz" 1103 1104config HZ_500 1105 bool "500 Hz" 1106 1107config HZ_1000 1108 bool "1000 Hz" 1109 1110endchoice 1111 1112config HZ 1113 int 1114 default HZ_FIXED if HZ_FIXED != 0 1115 default 100 if HZ_100 1116 default 200 if HZ_200 1117 default 250 if HZ_250 1118 default 300 if HZ_300 1119 default 500 if HZ_500 1120 default 1000 1121 1122config SCHED_HRTICK 1123 def_bool HIGH_RES_TIMERS 1124 1125config THUMB2_KERNEL 1126 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1127 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1128 default y if CPU_THUMBONLY 1129 select ARM_UNWIND 1130 help 1131 By enabling this option, the kernel will be compiled in 1132 Thumb-2 mode. 1133 1134 If unsure, say N. 1135 1136config ARM_PATCH_IDIV 1137 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1138 depends on CPU_32v7 1139 default y 1140 help 1141 The ARM compiler inserts calls to __aeabi_idiv() and 1142 __aeabi_uidiv() when it needs to perform division on signed 1143 and unsigned integers. Some v7 CPUs have support for the sdiv 1144 and udiv instructions that can be used to implement those 1145 functions. 1146 1147 Enabling this option allows the kernel to modify itself to 1148 replace the first two instructions of these library functions 1149 with the sdiv or udiv plus "bx lr" instructions when the CPU 1150 it is running on supports them. Typically this will be faster 1151 and less power intensive than running the original library 1152 code to do integer division. 1153 1154config AEABI 1155 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1156 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1157 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1158 help 1159 This option allows for the kernel to be compiled using the latest 1160 ARM ABI (aka EABI). This is only useful if you are using a user 1161 space environment that is also compiled with EABI. 1162 1163 Since there are major incompatibilities between the legacy ABI and 1164 EABI, especially with regard to structure member alignment, this 1165 option also changes the kernel syscall calling convention to 1166 disambiguate both ABIs and allow for backward compatibility support 1167 (selected with CONFIG_OABI_COMPAT). 1168 1169config OABI_COMPAT 1170 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1171 depends on AEABI && !THUMB2_KERNEL 1172 help 1173 This option preserves the old syscall interface along with the 1174 new (ARM EABI) one. It also provides a compatibility layer to 1175 intercept syscalls that have structure arguments which layout 1176 in memory differs between the legacy ABI and the new ARM EABI 1177 (only for non "thumb" binaries). This option adds a tiny 1178 overhead to all syscalls and produces a slightly larger kernel. 1179 1180 The seccomp filter system will not be available when this is 1181 selected, since there is no way yet to sensibly distinguish 1182 between calling conventions during filtering. 1183 1184 If you know you'll be using only pure EABI user space then you 1185 can say N here. If this option is not selected and you attempt 1186 to execute a legacy ABI binary then the result will be 1187 UNPREDICTABLE (in fact it can be predicted that it won't work 1188 at all). If in doubt say N. 1189 1190config ARCH_SELECT_MEMORY_MODEL 1191 def_bool y 1192 1193config ARCH_FLATMEM_ENABLE 1194 def_bool !(ARCH_RPC || ARCH_SA1100) 1195 1196config ARCH_SPARSEMEM_ENABLE 1197 def_bool !ARCH_FOOTBRIDGE 1198 select SPARSEMEM_STATIC if SPARSEMEM 1199 1200config HIGHMEM 1201 bool "High Memory Support" 1202 depends on MMU 1203 select KMAP_LOCAL 1204 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1205 help 1206 The address space of ARM processors is only 4 Gigabytes large 1207 and it has to accommodate user address space, kernel address 1208 space as well as some memory mapped IO. That means that, if you 1209 have a large amount of physical memory and/or IO, not all of the 1210 memory can be "permanently mapped" by the kernel. The physical 1211 memory that is not permanently mapped is called "high memory". 1212 1213 Depending on the selected kernel/user memory split, minimum 1214 vmalloc space and actual amount of RAM, you may not need this 1215 option which should result in a slightly faster kernel. 1216 1217 If unsure, say n. 1218 1219config HIGHPTE 1220 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1221 depends on HIGHMEM && !PREEMPT_RT 1222 default y 1223 help 1224 The VM uses one page of physical memory for each page table. 1225 For systems with a lot of processes, this can use a lot of 1226 precious low memory, eventually leading to low memory being 1227 consumed by page tables. Setting this option will allow 1228 user-space 2nd level page tables to reside in high memory. 1229 1230config ARM_PAN 1231 bool "Enable privileged no-access" 1232 depends on MMU 1233 default y 1234 help 1235 Increase kernel security by ensuring that normal kernel accesses 1236 are unable to access userspace addresses. This can help prevent 1237 use-after-free bugs becoming an exploitable privilege escalation 1238 by ensuring that magic values (such as LIST_POISON) will always 1239 fault when dereferenced. 1240 1241 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1242 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1243 1244config CPU_SW_DOMAIN_PAN 1245 def_bool y 1246 depends on ARM_PAN && !ARM_LPAE 1247 help 1248 Enable use of CPU domains to implement privileged no-access. 1249 1250 CPUs with low-vector mappings use a best-efforts implementation. 1251 Their lower 1MB needs to remain accessible for the vectors, but 1252 the remainder of userspace will become appropriately inaccessible. 1253 1254config CPU_TTBR0_PAN 1255 def_bool y 1256 depends on ARM_PAN && ARM_LPAE 1257 help 1258 Enable privileged no-access by disabling TTBR0 page table walks when 1259 running in kernel mode. 1260 1261config HW_PERF_EVENTS 1262 def_bool y 1263 depends on ARM_PMU 1264 1265config ARM_MODULE_PLTS 1266 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1267 depends on MODULES 1268 select KASAN_VMALLOC if KASAN 1269 default y 1270 help 1271 Allocate PLTs when loading modules so that jumps and calls whose 1272 targets are too far away for their relative offsets to be encoded 1273 in the instructions themselves can be bounced via veneers in the 1274 module's PLT. This allows modules to be allocated in the generic 1275 vmalloc area after the dedicated module memory area has been 1276 exhausted. The modules will use slightly more memory, but after 1277 rounding up to page size, the actual memory footprint is usually 1278 the same. 1279 1280 Disabling this is usually safe for small single-platform 1281 configurations. If unsure, say y. 1282 1283config ARCH_FORCE_MAX_ORDER 1284 int "Order of maximal physically contiguous allocations" 1285 default "11" if SOC_AM33XX 1286 default "8" if SA1111 1287 default "10" 1288 help 1289 The kernel page allocator limits the size of maximal physically 1290 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1291 defines the maximal power of two of number of pages that can be 1292 allocated as a single contiguous block. This option allows 1293 overriding the default setting when ability to allocate very 1294 large blocks of physically contiguous memory is required. 1295 1296 Don't change if unsure. 1297 1298config ALIGNMENT_TRAP 1299 def_bool CPU_CP15_MMU 1300 select HAVE_PROC_CPU if PROC_FS 1301 help 1302 ARM processors cannot fetch/store information which is not 1303 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1304 address divisible by 4. On 32-bit ARM processors, these non-aligned 1305 fetch/store instructions will be emulated in software if you say 1306 here, which has a severe performance impact. This is necessary for 1307 correct operation of some network protocols. With an IP-only 1308 configuration it is safe to say N, otherwise say Y. 1309 1310config UACCESS_WITH_MEMCPY 1311 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1312 depends on MMU 1313 default y if CPU_FEROCEON 1314 help 1315 Implement faster copy_to_user and clear_user methods for CPU 1316 cores where a 8-word STM instruction give significantly higher 1317 memory write throughput than a sequence of individual 32bit stores. 1318 1319 A possible side effect is a slight increase in scheduling latency 1320 between threads sharing the same address space if they invoke 1321 such copy operations with large buffers. 1322 1323 However, if the CPU data cache is using a write-allocate mode, 1324 this option is unlikely to provide any performance gain. 1325 1326config PARAVIRT 1327 bool "Enable paravirtualization code" 1328 select HAVE_PV_STEAL_CLOCK_GEN 1329 help 1330 This changes the kernel so it can modify itself when it is run 1331 under a hypervisor, potentially improving performance significantly 1332 over full virtualization. 1333 1334config PARAVIRT_TIME_ACCOUNTING 1335 bool "Paravirtual steal time accounting" 1336 select PARAVIRT 1337 help 1338 Select this option to enable fine granularity task steal time 1339 accounting. Time spent executing other tasks in parallel with 1340 the current vCPU is discounted from the vCPU power. To account for 1341 that, there can be a small performance impact. 1342 1343 If in doubt, say N here. 1344 1345config XEN_DOM0 1346 def_bool y 1347 depends on XEN 1348 1349config XEN 1350 bool "Xen guest support on ARM" 1351 depends on ARM && AEABI && OF 1352 depends on CPU_V7 && !CPU_V6 1353 depends on !GENERIC_ATOMIC64 1354 depends on MMU 1355 select ARCH_DMA_ADDR_T_64BIT 1356 select ARM_PSCI 1357 select SWIOTLB 1358 select SWIOTLB_XEN 1359 select PARAVIRT 1360 help 1361 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1362 1363config CC_HAVE_STACKPROTECTOR_TLS 1364 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1365 1366config STACKPROTECTOR_PER_TASK 1367 bool "Use a unique stack canary value for each task" 1368 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1369 depends on CC_HAVE_STACKPROTECTOR_TLS 1370 default y 1371 help 1372 Due to the fact that GCC uses an ordinary symbol reference from 1373 which to load the value of the stack canary, this value can only 1374 change at reboot time on SMP systems, and all tasks running in the 1375 kernel's address space are forced to use the same canary value for 1376 the entire duration that the system is up. 1377 1378 Enable this option to switch to a different method that uses a 1379 different canary value for each task. 1380 1381endmenu 1382 1383menu "Boot options" 1384 1385config USE_OF 1386 bool "Flattened Device Tree support" 1387 select IRQ_DOMAIN 1388 select OF 1389 help 1390 Include support for flattened device tree machine descriptions. 1391 1392config ARCH_WANT_FLAT_DTB_INSTALL 1393 def_bool y 1394 1395config ATAGS 1396 bool "Support for the traditional ATAGS boot data passing" 1397 default y 1398 help 1399 This is the traditional way of passing data to the kernel at boot 1400 time. If you are solely relying on the flattened device tree (or 1401 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1402 to remove ATAGS support from your kernel binary. 1403 1404config DEPRECATED_PARAM_STRUCT 1405 bool "Provide old way to pass kernel parameters" 1406 depends on ATAGS 1407 help 1408 This was deprecated in 2001 and announced to live on for 5 years. 1409 Some old boot loaders still use this way. 1410 1411# Compressed boot loader in ROM. Yes, we really want to ask about 1412# TEXT and BSS so we preserve their values in the config files. 1413config ZBOOT_ROM_TEXT 1414 hex "Compressed ROM boot loader base address" 1415 default 0x0 1416 help 1417 The physical address at which the ROM-able zImage is to be 1418 placed in the target. Platforms which normally make use of 1419 ROM-able zImage formats normally set this to a suitable 1420 value in their defconfig file. 1421 1422 If ZBOOT_ROM is not enabled, this has no effect. 1423 1424config ZBOOT_ROM_BSS 1425 hex "Compressed ROM boot loader BSS address" 1426 default 0x0 1427 help 1428 The base address of an area of read/write memory in the target 1429 for the ROM-able zImage which must be available while the 1430 decompressor is running. It must be large enough to hold the 1431 entire decompressed kernel plus an additional 128 KiB. 1432 Platforms which normally make use of ROM-able zImage formats 1433 normally set this to a suitable value in their defconfig file. 1434 1435 If ZBOOT_ROM is not enabled, this has no effect. 1436 1437config ZBOOT_ROM 1438 bool "Compressed boot loader in ROM/flash" 1439 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1440 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1441 help 1442 Say Y here if you intend to execute your compressed kernel image 1443 (zImage) directly from ROM or flash. If unsure, say N. 1444 1445config ARM_APPENDED_DTB 1446 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1447 depends on OF 1448 help 1449 With this option, the boot code will look for a device tree binary 1450 (DTB) appended to zImage 1451 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1452 1453 This is meant as a backward compatibility convenience for those 1454 systems with a bootloader that can't be upgraded to accommodate 1455 the documented boot protocol using a device tree. 1456 1457 Beware that there is very little in terms of protection against 1458 this option being confused by leftover garbage in memory that might 1459 look like a DTB header after a reboot if no actual DTB is appended 1460 to zImage. Do not leave this option active in a production kernel 1461 if you don't intend to always append a DTB. Proper passing of the 1462 location into r2 of a bootloader provided DTB is always preferable 1463 to this option. 1464 1465config ARM_ATAG_DTB_COMPAT 1466 bool "Supplement the appended DTB with traditional ATAG information" 1467 depends on ARM_APPENDED_DTB 1468 help 1469 Some old bootloaders can't be updated to a DTB capable one, yet 1470 they provide ATAGs with memory configuration, the ramdisk address, 1471 the kernel cmdline string, etc. Such information is dynamically 1472 provided by the bootloader and can't always be stored in a static 1473 DTB. To allow a device tree enabled kernel to be used with such 1474 bootloaders, this option allows zImage to extract the information 1475 from the ATAG list and store it at run time into the appended DTB. 1476 1477choice 1478 prompt "Kernel command line type" 1479 depends on ARM_ATAG_DTB_COMPAT 1480 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1481 1482config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1483 bool "Use bootloader kernel arguments if available" 1484 help 1485 Uses the command-line options passed by the boot loader instead of 1486 the device tree bootargs property. If the boot loader doesn't provide 1487 any, the device tree bootargs property will be used. 1488 1489config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1490 bool "Extend with bootloader kernel arguments" 1491 help 1492 The command-line arguments provided by the boot loader will be 1493 appended to the the device tree bootargs property. 1494 1495endchoice 1496 1497config CMDLINE 1498 string "Default kernel command string" 1499 default "" 1500 help 1501 On some architectures (e.g. CATS), there is currently no way 1502 for the boot loader to pass arguments to the kernel. For these 1503 architectures, you should supply some command-line options at build 1504 time by entering them here. As a minimum, you should specify the 1505 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1506 1507choice 1508 prompt "Kernel command line type" 1509 depends on CMDLINE != "" 1510 default CMDLINE_FROM_BOOTLOADER 1511 1512config CMDLINE_FROM_BOOTLOADER 1513 bool "Use bootloader kernel arguments if available" 1514 help 1515 Uses the command-line options passed by the boot loader. If 1516 the boot loader doesn't provide any, the default kernel command 1517 string provided in CMDLINE will be used. 1518 1519config CMDLINE_EXTEND 1520 bool "Extend bootloader kernel arguments" 1521 help 1522 The command-line arguments provided by the boot loader will be 1523 appended to the default kernel command string. 1524 1525config CMDLINE_FORCE 1526 bool "Always use the default kernel command string" 1527 help 1528 Always use the default kernel command string, even if the boot 1529 loader passes other arguments to the kernel. 1530 This is useful if you cannot or don't want to change the 1531 command-line options your boot loader passes to the kernel. 1532endchoice 1533 1534config XIP_KERNEL 1535 bool "Kernel Execute-In-Place from ROM" 1536 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1537 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1538 help 1539 Execute-In-Place allows the kernel to run from non-volatile storage 1540 directly addressable by the CPU, such as NOR flash. This saves RAM 1541 space since the text section of the kernel is not loaded from flash 1542 to RAM. Read-write sections, such as the data section and stack, 1543 are still copied to RAM. The XIP kernel is not compressed since 1544 it has to run directly from flash, so it will take more space to 1545 store it. The flash address used to link the kernel object files, 1546 and for storing it, is configuration dependent. Therefore, if you 1547 say Y here, you must know the proper physical address where to 1548 store the kernel image depending on your own flash memory usage. 1549 1550 Also note that the make target becomes "make xipImage" rather than 1551 "make zImage" or "make Image". The final kernel binary to put in 1552 ROM memory will be arch/arm/boot/xipImage. 1553 1554 If unsure, say N. 1555 1556config XIP_PHYS_ADDR 1557 hex "XIP Kernel Physical Location" 1558 depends on XIP_KERNEL 1559 default "0x00080000" 1560 help 1561 This is the physical address in your flash memory the kernel will 1562 be linked for and stored to. This address is dependent on your 1563 own flash usage. 1564 1565config XIP_DEFLATED_DATA 1566 bool "Store kernel .data section compressed in ROM" 1567 depends on XIP_KERNEL 1568 select ZLIB_INFLATE 1569 help 1570 Before the kernel is actually executed, its .data section has to be 1571 copied to RAM from ROM. This option allows for storing that data 1572 in compressed form and decompressed to RAM rather than merely being 1573 copied, saving some precious ROM space. A possible drawback is a 1574 slightly longer boot delay. 1575 1576config ARCH_SUPPORTS_KEXEC 1577 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1578 1579config ATAGS_PROC 1580 bool "Export atags in procfs" 1581 depends on ATAGS && KEXEC 1582 default y 1583 help 1584 Should the atags used to boot the kernel be exported in an "atags" 1585 file in procfs. Useful with kexec. 1586 1587config ARCH_SUPPORTS_CRASH_DUMP 1588 def_bool y 1589 1590config ARCH_DEFAULT_CRASH_DUMP 1591 def_bool y 1592 1593config AUTO_ZRELADDR 1594 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1595 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1596 help 1597 ZRELADDR is the physical address where the decompressed kernel 1598 image will be placed. If AUTO_ZRELADDR is selected, the address 1599 will be determined at run-time, either by masking the current IP 1600 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1601 This assumes the zImage being placed in the first 128MB from 1602 start of memory. 1603 1604config EFI_STUB 1605 bool 1606 1607config EFI 1608 bool "UEFI runtime support" 1609 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1610 select UCS2_STRING 1611 select EFI_PARAMS_FROM_FDT 1612 select EFI_STUB 1613 select EFI_GENERIC_STUB 1614 select EFI_RUNTIME_WRAPPERS 1615 help 1616 This option provides support for runtime services provided 1617 by UEFI firmware (such as non-volatile variables, realtime 1618 clock, and platform reset). A UEFI stub is also provided to 1619 allow the kernel to be booted as an EFI application. This 1620 is only useful for kernels that may run on systems that have 1621 UEFI firmware. 1622 1623config DMI 1624 bool "Enable support for SMBIOS (DMI) tables" 1625 depends on EFI 1626 default y 1627 help 1628 This enables SMBIOS/DMI feature for systems. 1629 1630 This option is only useful on systems that have UEFI firmware. 1631 However, even with this option, the resultant kernel should 1632 continue to boot on existing non-UEFI platforms. 1633 1634 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1635 i.e., the the practice of identifying the platform via DMI to 1636 decide whether certain workarounds for buggy hardware and/or 1637 firmware need to be enabled. This would require the DMI subsystem 1638 to be enabled much earlier than we do on ARM, which is non-trivial. 1639 1640endmenu 1641 1642menu "CPU Power Management" 1643 1644source "drivers/cpufreq/Kconfig" 1645 1646source "drivers/cpuidle/Kconfig" 1647 1648endmenu 1649 1650menu "Floating point emulation" 1651 1652comment "At least one emulation must be selected" 1653 1654config FPE_NWFPE 1655 bool "NWFPE math emulation" 1656 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1657 help 1658 Say Y to include the NWFPE floating point emulator in the kernel. 1659 This is necessary to run most binaries. Linux does not currently 1660 support floating point hardware so you need to say Y here even if 1661 your machine has an FPA or floating point co-processor podule. 1662 1663 You may say N here if you are going to load the Acorn FPEmulator 1664 early in the bootup. 1665 1666config FPE_NWFPE_XP 1667 bool "Support extended precision" 1668 depends on FPE_NWFPE 1669 help 1670 Say Y to include 80-bit support in the kernel floating-point 1671 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1672 Note that gcc does not generate 80-bit operations by default, 1673 so in most cases this option only enlarges the size of the 1674 floating point emulator without any good reason. 1675 1676 You almost surely want to say N here. 1677 1678config FPE_FASTFPE 1679 bool "FastFPE math emulation (EXPERIMENTAL)" 1680 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1681 help 1682 Say Y here to include the FAST floating point emulator in the kernel. 1683 This is an experimental much faster emulator which now also has full 1684 precision for the mantissa. It does not support any exceptions. 1685 It is very simple, and approximately 3-6 times faster than NWFPE. 1686 1687 It should be sufficient for most programs. It may be not suitable 1688 for scientific calculations, but you have to check this for yourself. 1689 If you do not feel you need a faster FP emulation you should better 1690 choose NWFPE. 1691 1692config VFP 1693 bool "VFP-format floating point maths" 1694 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1695 help 1696 Say Y to include VFP support code in the kernel. This is needed 1697 if your hardware includes a VFP unit. 1698 1699 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1700 release notes and additional status information. 1701 1702 Say N if your target does not have VFP hardware. 1703 1704config VFPv3 1705 bool 1706 depends on VFP 1707 default y if CPU_V7 1708 1709config NEON 1710 bool "Advanced SIMD (NEON) Extension support" 1711 depends on VFPv3 && CPU_V7 1712 help 1713 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1714 Extension. 1715 1716config KERNEL_MODE_NEON 1717 bool "Support for NEON in kernel mode" 1718 depends on NEON && AEABI 1719 help 1720 Say Y to include support for NEON in kernel mode. 1721 1722endmenu 1723 1724config ARCH_CC_CAN_LINK 1725 bool 1726 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN 1727 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8 1728 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32 1729 1730config ARCH_USERFLAGS 1731 string 1732 default "-mlittle-endian" if CPU_LITTLE_ENDIAN 1733 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8 1734 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32 1735 1736menu "Power management options" 1737 1738source "kernel/power/Kconfig" 1739 1740config ARCH_SUSPEND_POSSIBLE 1741 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1742 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1743 def_bool y 1744 1745config ARM_CPU_SUSPEND 1746 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1747 depends on ARCH_SUSPEND_POSSIBLE 1748 1749config ARCH_HIBERNATION_POSSIBLE 1750 bool 1751 depends on MMU 1752 default y if ARCH_SUSPEND_POSSIBLE 1753 1754endmenu 1755