1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_CACHE_ALIASING 9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 10 select ARCH_HAS_CURRENT_STACK_POINTER 11 select ARCH_HAS_DEBUG_VIRTUAL if MMU 12 select ARCH_HAS_DMA_ALLOC if MMU 13 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 14 select ARCH_HAS_ELF_RANDOMIZE 15 select ARCH_HAS_FORTIFY_SOURCE 16 select ARCH_HAS_KEEPINITRD 17 select ARCH_HAS_KCOV 18 select ARCH_HAS_MEMBARRIER_SYNC_CORE 19 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 20 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 21 select ARCH_HAS_SETUP_DMA_OPS 22 select ARCH_HAS_SET_MEMORY 23 select ARCH_STACKWALK 24 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 25 select ARCH_HAS_STRICT_MODULE_RWX if MMU 26 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 27 select ARCH_HAS_SYNC_DMA_FOR_CPU 28 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 29 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 30 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 31 select ARCH_HAS_GCOV_PROFILE_ALL 32 select ARCH_KEEP_MEMBLOCK 33 select ARCH_HAS_UBSAN 34 select ARCH_MIGHT_HAVE_PC_PARPORT 35 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 36 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 37 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 38 select ARCH_SUPPORTS_ATOMIC_RMW 39 select ARCH_SUPPORTS_CFI_CLANG 40 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 41 select ARCH_SUPPORTS_PER_VMA_LOCK 42 select ARCH_USE_BUILTIN_BSWAP 43 select ARCH_USE_CMPXCHG_LOCKREF 44 select ARCH_USE_MEMTEST 45 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 46 select ARCH_WANT_GENERAL_HUGETLB 47 select ARCH_WANT_IPC_PARSE_VERSION 48 select ARCH_WANT_LD_ORPHAN_WARN 49 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 50 select BUILDTIME_TABLE_SORT if MMU 51 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 52 select CLONE_BACKWARDS 53 select CPU_PM if SUSPEND || CPU_IDLE 54 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 55 select DMA_DECLARE_COHERENT 56 select DMA_GLOBAL_POOL if !MMU 57 select DMA_OPS 58 select DMA_NONCOHERENT_MMAP if MMU 59 select EDAC_SUPPORT 60 select EDAC_ATOMIC_SCRUB 61 select GENERIC_ALLOCATOR 62 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 63 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 64 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 65 select GENERIC_IRQ_IPI if SMP 66 select GENERIC_CPU_AUTOPROBE 67 select GENERIC_EARLY_IOREMAP 68 select GENERIC_IDLE_POLL_SETUP 69 select GENERIC_IRQ_MULTI_HANDLER 70 select GENERIC_IRQ_PROBE 71 select GENERIC_IRQ_SHOW 72 select GENERIC_IRQ_SHOW_LEVEL 73 select GENERIC_LIB_DEVMEM_IS_ALLOWED 74 select GENERIC_PCI_IOMAP 75 select GENERIC_SCHED_CLOCK 76 select GENERIC_SMP_IDLE_THREAD 77 select HARDIRQS_SW_RESEND 78 select HAS_IOPORT 79 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 80 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 81 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 83 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 86 select HAVE_ARCH_MMAP_RND_BITS if MMU 87 select HAVE_ARCH_PFN_VALID 88 select HAVE_ARCH_SECCOMP 89 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 90 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 91 select HAVE_ARCH_TRACEHOOK 92 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 93 select HAVE_ARM_SMCCC if CPU_V7 94 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 95 select HAVE_CONTEXT_TRACKING_USER 96 select HAVE_C_RECORDMCOUNT 97 select HAVE_BUILDTIME_MCOUNT_SORT 98 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 99 select HAVE_DMA_CONTIGUOUS if MMU 100 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 101 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 102 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 103 select HAVE_EXIT_THREAD 104 select HAVE_GUP_FAST if ARM_LPAE 105 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 106 select HAVE_FUNCTION_ERROR_INJECTION 107 select HAVE_FUNCTION_GRAPH_TRACER 108 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 109 select HAVE_GCC_PLUGINS 110 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 111 select HAVE_IRQ_TIME_ACCOUNTING 112 select HAVE_KERNEL_GZIP 113 select HAVE_KERNEL_LZ4 114 select HAVE_KERNEL_LZMA 115 select HAVE_KERNEL_LZO 116 select HAVE_KERNEL_XZ 117 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 118 select HAVE_KRETPROBES if HAVE_KPROBES 119 select HAVE_MOD_ARCH_SPECIFIC 120 select HAVE_NMI 121 select HAVE_OPTPROBES if !THUMB2_KERNEL 122 select HAVE_PAGE_SIZE_4KB 123 select HAVE_PCI if MMU 124 select HAVE_PERF_EVENTS 125 select HAVE_PERF_REGS 126 select HAVE_PERF_USER_STACK_DUMP 127 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 128 select HAVE_REGS_AND_STACK_ACCESS_API 129 select HAVE_RSEQ 130 select HAVE_STACKPROTECTOR 131 select HAVE_SYSCALL_TRACEPOINTS 132 select HAVE_UID16 133 select HAVE_VIRT_CPU_ACCOUNTING_GEN 134 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 135 select IRQ_FORCED_THREADING 136 select LOCK_MM_AND_FIND_VMA 137 select MODULES_USE_ELF_REL 138 select NEED_DMA_MAP_STATE 139 select OF_EARLY_FLATTREE if OF 140 select OLD_SIGACTION 141 select OLD_SIGSUSPEND3 142 select PCI_DOMAINS_GENERIC if PCI 143 select PCI_SYSCALL if PCI 144 select PERF_USE_VMALLOC 145 select RTC_LIB 146 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 147 select SYS_SUPPORTS_APM_EMULATION 148 select THREAD_INFO_IN_TASK 149 select TIMER_OF if OF 150 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 151 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 152 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 153 # Above selects are sorted alphabetically; please add new ones 154 # according to that. Thanks. 155 help 156 The ARM series is a line of low-power-consumption RISC chip designs 157 licensed by ARM Ltd and targeted at embedded applications and 158 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 159 manufactured, but legacy ARM-based PC hardware remains popular in 160 Europe. There is an ARM Linux project with a web page at 161 <http://www.arm.linux.org.uk/>. 162 163config ARM_HAS_GROUP_RELOCS 164 def_bool y 165 depends on !LD_IS_LLD || LLD_VERSION >= 140000 166 depends on !COMPILE_TEST 167 help 168 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 169 relocations, which have been around for a long time, but were not 170 supported in LLD until version 14. The combined range is -/+ 256 MiB, 171 which is usually sufficient, but not for allyesconfig, so we disable 172 this feature when doing compile testing. 173 174config ARM_DMA_USE_IOMMU 175 bool 176 select NEED_SG_DMA_LENGTH 177 178if ARM_DMA_USE_IOMMU 179 180config ARM_DMA_IOMMU_ALIGNMENT 181 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 182 range 4 9 183 default 8 184 help 185 DMA mapping framework by default aligns all buffers to the smallest 186 PAGE_SIZE order which is greater than or equal to the requested buffer 187 size. This works well for buffers up to a few hundreds kilobytes, but 188 for larger buffers it just a waste of address space. Drivers which has 189 relatively small addressing window (like 64Mib) might run out of 190 virtual space with just a few allocations. 191 192 With this parameter you can specify the maximum PAGE_SIZE order for 193 DMA IOMMU buffers. Larger buffers will be aligned only to this 194 specified order. The order is expressed as a power of two multiplied 195 by the PAGE_SIZE. 196 197endif 198 199config SYS_SUPPORTS_APM_EMULATION 200 bool 201 202config HAVE_TCM 203 bool 204 select GENERIC_ALLOCATOR 205 206config HAVE_PROC_CPU 207 bool 208 209config NO_IOPORT_MAP 210 bool 211 212config SBUS 213 bool 214 215config STACKTRACE_SUPPORT 216 bool 217 default y 218 219config LOCKDEP_SUPPORT 220 bool 221 default y 222 223config ARCH_HAS_ILOG2_U32 224 bool 225 226config ARCH_HAS_ILOG2_U64 227 bool 228 229config ARCH_HAS_BANDGAP 230 bool 231 232config FIX_EARLYCON_MEM 233 def_bool y if MMU 234 235config GENERIC_HWEIGHT 236 bool 237 default y 238 239config GENERIC_CALIBRATE_DELAY 240 bool 241 default y 242 243config ARCH_MAY_HAVE_PC_FDC 244 bool 245 246config ARCH_SUPPORTS_UPROBES 247 def_bool y 248 249config GENERIC_ISA_DMA 250 bool 251 252config FIQ 253 bool 254 255config ARCH_MTD_XIP 256 bool 257 258config ARM_PATCH_PHYS_VIRT 259 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 260 default y 261 depends on MMU 262 help 263 Patch phys-to-virt and virt-to-phys translation functions at 264 boot and module load time according to the position of the 265 kernel in system memory. 266 267 This can only be used with non-XIP MMU kernels where the base 268 of physical memory is at a 2 MiB boundary. 269 270 Only disable this option if you know that you do not require 271 this feature (eg, building a kernel for a single machine) and 272 you need to shrink the kernel to the minimal size. 273 274config NEED_MACH_IO_H 275 bool 276 help 277 Select this when mach/io.h is required to provide special 278 definitions for this platform. The need for mach/io.h should 279 be avoided when possible. 280 281config NEED_MACH_MEMORY_H 282 bool 283 help 284 Select this when mach/memory.h is required to provide special 285 definitions for this platform. The need for mach/memory.h should 286 be avoided when possible. 287 288config PHYS_OFFSET 289 hex "Physical address of main memory" if MMU 290 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 291 default DRAM_BASE if !MMU 292 default 0x00000000 if ARCH_FOOTBRIDGE 293 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 294 default 0xa0000000 if ARCH_PXA 295 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 296 default 0 297 help 298 Please provide the physical address corresponding to the 299 location of main memory in your system. 300 301config GENERIC_BUG 302 def_bool y 303 depends on BUG 304 305config PGTABLE_LEVELS 306 int 307 default 3 if ARM_LPAE 308 default 2 309 310menu "System Type" 311 312config MMU 313 bool "MMU-based Paged Memory Management Support" 314 default y 315 help 316 Select if you want MMU-based virtualised addressing space 317 support by paged memory management. If unsure, say 'Y'. 318 319config ARM_SINGLE_ARMV7M 320 def_bool !MMU 321 select ARM_NVIC 322 select CPU_V7M 323 select NO_IOPORT_MAP 324 325config ARCH_MMAP_RND_BITS_MIN 326 default 8 327 328config ARCH_MMAP_RND_BITS_MAX 329 default 14 if PAGE_OFFSET=0x40000000 330 default 15 if PAGE_OFFSET=0x80000000 331 default 16 332 333config ARCH_MULTIPLATFORM 334 bool "Require kernel to be portable to multiple machines" if EXPERT 335 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 336 default y 337 help 338 In general, all Arm machines can be supported in a single 339 kernel image, covering either Armv4/v5 or Armv6/v7. 340 341 However, some configuration options require hardcoding machine 342 specific physical addresses or enable errata workarounds that may 343 break other machines. 344 345 Selecting N here allows using those options, including 346 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 347 348source "arch/arm/Kconfig.platforms" 349 350# 351# This is sorted alphabetically by mach-* pathname. However, plat-* 352# Kconfigs may be included either alphabetically (according to the 353# plat- suffix) or along side the corresponding mach-* source. 354# 355source "arch/arm/mach-actions/Kconfig" 356 357source "arch/arm/mach-alpine/Kconfig" 358 359source "arch/arm/mach-artpec/Kconfig" 360 361source "arch/arm/mach-aspeed/Kconfig" 362 363source "arch/arm/mach-at91/Kconfig" 364 365source "arch/arm/mach-axxia/Kconfig" 366 367source "arch/arm/mach-bcm/Kconfig" 368 369source "arch/arm/mach-berlin/Kconfig" 370 371source "arch/arm/mach-clps711x/Kconfig" 372 373source "arch/arm/mach-davinci/Kconfig" 374 375source "arch/arm/mach-digicolor/Kconfig" 376 377source "arch/arm/mach-dove/Kconfig" 378 379source "arch/arm/mach-ep93xx/Kconfig" 380 381source "arch/arm/mach-exynos/Kconfig" 382 383source "arch/arm/mach-footbridge/Kconfig" 384 385source "arch/arm/mach-gemini/Kconfig" 386 387source "arch/arm/mach-highbank/Kconfig" 388 389source "arch/arm/mach-hisi/Kconfig" 390 391source "arch/arm/mach-hpe/Kconfig" 392 393source "arch/arm/mach-imx/Kconfig" 394 395source "arch/arm/mach-ixp4xx/Kconfig" 396 397source "arch/arm/mach-keystone/Kconfig" 398 399source "arch/arm/mach-lpc32xx/Kconfig" 400 401source "arch/arm/mach-mediatek/Kconfig" 402 403source "arch/arm/mach-meson/Kconfig" 404 405source "arch/arm/mach-milbeaut/Kconfig" 406 407source "arch/arm/mach-mmp/Kconfig" 408 409source "arch/arm/mach-mstar/Kconfig" 410 411source "arch/arm/mach-mv78xx0/Kconfig" 412 413source "arch/arm/mach-mvebu/Kconfig" 414 415source "arch/arm/mach-mxs/Kconfig" 416 417source "arch/arm/mach-nomadik/Kconfig" 418 419source "arch/arm/mach-npcm/Kconfig" 420 421source "arch/arm/mach-omap1/Kconfig" 422 423source "arch/arm/mach-omap2/Kconfig" 424 425source "arch/arm/mach-orion5x/Kconfig" 426 427source "arch/arm/mach-pxa/Kconfig" 428 429source "arch/arm/mach-qcom/Kconfig" 430 431source "arch/arm/mach-realtek/Kconfig" 432 433source "arch/arm/mach-rpc/Kconfig" 434 435source "arch/arm/mach-rockchip/Kconfig" 436 437source "arch/arm/mach-s3c/Kconfig" 438 439source "arch/arm/mach-s5pv210/Kconfig" 440 441source "arch/arm/mach-sa1100/Kconfig" 442 443source "arch/arm/mach-shmobile/Kconfig" 444 445source "arch/arm/mach-socfpga/Kconfig" 446 447source "arch/arm/mach-spear/Kconfig" 448 449source "arch/arm/mach-sti/Kconfig" 450 451source "arch/arm/mach-stm32/Kconfig" 452 453source "arch/arm/mach-sunxi/Kconfig" 454 455source "arch/arm/mach-tegra/Kconfig" 456 457source "arch/arm/mach-ux500/Kconfig" 458 459source "arch/arm/mach-versatile/Kconfig" 460 461source "arch/arm/mach-vt8500/Kconfig" 462 463source "arch/arm/mach-zynq/Kconfig" 464 465# ARMv7-M architecture 466config ARCH_LPC18XX 467 bool "NXP LPC18xx/LPC43xx" 468 depends on ARM_SINGLE_ARMV7M 469 select ARCH_HAS_RESET_CONTROLLER 470 select ARM_AMBA 471 select CLKSRC_LPC32XX 472 select PINCTRL 473 help 474 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 475 high performance microcontrollers. 476 477config ARCH_MPS2 478 bool "ARM MPS2 platform" 479 depends on ARM_SINGLE_ARMV7M 480 select ARM_AMBA 481 select CLKSRC_MPS2 482 help 483 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 484 with a range of available cores like Cortex-M3/M4/M7. 485 486 Please, note that depends which Application Note is used memory map 487 for the platform may vary, so adjustment of RAM base might be needed. 488 489# Definitions to make life easier 490config ARCH_ACORN 491 bool 492 493config PLAT_ORION 494 bool 495 select CLKSRC_MMIO 496 select GENERIC_IRQ_CHIP 497 select IRQ_DOMAIN 498 499config PLAT_ORION_LEGACY 500 bool 501 select PLAT_ORION 502 503config PLAT_VERSATILE 504 bool 505 506source "arch/arm/mm/Kconfig" 507 508config IWMMXT 509 bool "Enable iWMMXt support" 510 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 511 default y if PXA27x || PXA3xx || ARCH_MMP 512 help 513 Enable support for iWMMXt context switching at run time if 514 running on a CPU that supports it. 515 516if !MMU 517source "arch/arm/Kconfig-nommu" 518endif 519 520config PJ4B_ERRATA_4742 521 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 522 depends on CPU_PJ4B && MACH_ARMADA_370 523 default y 524 help 525 When coming out of either a Wait for Interrupt (WFI) or a Wait for 526 Event (WFE) IDLE states, a specific timing sensitivity exists between 527 the retiring WFI/WFE instructions and the newly issued subsequent 528 instructions. This sensitivity can result in a CPU hang scenario. 529 Workaround: 530 The software must insert either a Data Synchronization Barrier (DSB) 531 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 532 instruction 533 534config ARM_ERRATA_326103 535 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 536 depends on CPU_V6 537 help 538 Executing a SWP instruction to read-only memory does not set bit 11 539 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 540 treat the access as a read, preventing a COW from occurring and 541 causing the faulting task to livelock. 542 543config ARM_ERRATA_411920 544 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 545 depends on CPU_V6 || CPU_V6K 546 help 547 Invalidation of the Instruction Cache operation can 548 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 549 It does not affect the MPCore. This option enables the ARM Ltd. 550 recommended workaround. 551 552config ARM_ERRATA_430973 553 bool "ARM errata: Stale prediction on replaced interworking branch" 554 depends on CPU_V7 555 help 556 This option enables the workaround for the 430973 Cortex-A8 557 r1p* erratum. If a code sequence containing an ARM/Thumb 558 interworking branch is replaced with another code sequence at the 559 same virtual address, whether due to self-modifying code or virtual 560 to physical address re-mapping, Cortex-A8 does not recover from the 561 stale interworking branch prediction. This results in Cortex-A8 562 executing the new code sequence in the incorrect ARM or Thumb state. 563 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 564 and also flushes the branch target cache at every context switch. 565 Note that setting specific bits in the ACTLR register may not be 566 available in non-secure mode. 567 568config ARM_ERRATA_458693 569 bool "ARM errata: Processor deadlock when a false hazard is created" 570 depends on CPU_V7 571 depends on !ARCH_MULTIPLATFORM 572 help 573 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 574 erratum. For very specific sequences of memory operations, it is 575 possible for a hazard condition intended for a cache line to instead 576 be incorrectly associated with a different cache line. This false 577 hazard might then cause a processor deadlock. The workaround enables 578 the L1 caching of the NEON accesses and disables the PLD instruction 579 in the ACTLR register. Note that setting specific bits in the ACTLR 580 register may not be available in non-secure mode and thus is not 581 available on a multiplatform kernel. This should be applied by the 582 bootloader instead. 583 584config ARM_ERRATA_460075 585 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 586 depends on CPU_V7 587 depends on !ARCH_MULTIPLATFORM 588 help 589 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 590 erratum. Any asynchronous access to the L2 cache may encounter a 591 situation in which recent store transactions to the L2 cache are lost 592 and overwritten with stale memory contents from external memory. The 593 workaround disables the write-allocate mode for the L2 cache via the 594 ACTLR register. Note that setting specific bits in the ACTLR register 595 may not be available in non-secure mode and thus is not available on 596 a multiplatform kernel. This should be applied by the bootloader 597 instead. 598 599config ARM_ERRATA_742230 600 bool "ARM errata: DMB operation may be faulty" 601 depends on CPU_V7 && SMP 602 depends on !ARCH_MULTIPLATFORM 603 help 604 This option enables the workaround for the 742230 Cortex-A9 605 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 606 between two write operations may not ensure the correct visibility 607 ordering of the two writes. This workaround sets a specific bit in 608 the diagnostic register of the Cortex-A9 which causes the DMB 609 instruction to behave as a DSB, ensuring the correct behaviour of 610 the two writes. Note that setting specific bits in the diagnostics 611 register may not be available in non-secure mode and thus is not 612 available on a multiplatform kernel. This should be applied by the 613 bootloader instead. 614 615config ARM_ERRATA_742231 616 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 617 depends on CPU_V7 && SMP 618 depends on !ARCH_MULTIPLATFORM 619 help 620 This option enables the workaround for the 742231 Cortex-A9 621 (r2p0..r2p2) erratum. Under certain conditions, specific to the 622 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 623 accessing some data located in the same cache line, may get corrupted 624 data due to bad handling of the address hazard when the line gets 625 replaced from one of the CPUs at the same time as another CPU is 626 accessing it. This workaround sets specific bits in the diagnostic 627 register of the Cortex-A9 which reduces the linefill issuing 628 capabilities of the processor. Note that setting specific bits in the 629 diagnostics register may not be available in non-secure mode and thus 630 is not available on a multiplatform kernel. This should be applied by 631 the bootloader instead. 632 633config ARM_ERRATA_643719 634 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 635 depends on CPU_V7 && SMP 636 default y 637 help 638 This option enables the workaround for the 643719 Cortex-A9 (prior to 639 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 640 register returns zero when it should return one. The workaround 641 corrects this value, ensuring cache maintenance operations which use 642 it behave as intended and avoiding data corruption. 643 644config ARM_ERRATA_720789 645 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 646 depends on CPU_V7 647 help 648 This option enables the workaround for the 720789 Cortex-A9 (prior to 649 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 650 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 651 As a consequence of this erratum, some TLB entries which should be 652 invalidated are not, resulting in an incoherency in the system page 653 tables. The workaround changes the TLB flushing routines to invalidate 654 entries regardless of the ASID. 655 656config ARM_ERRATA_743622 657 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 658 depends on CPU_V7 659 depends on !ARCH_MULTIPLATFORM 660 help 661 This option enables the workaround for the 743622 Cortex-A9 662 (r2p*) erratum. Under very rare conditions, a faulty 663 optimisation in the Cortex-A9 Store Buffer may lead to data 664 corruption. This workaround sets a specific bit in the diagnostic 665 register of the Cortex-A9 which disables the Store Buffer 666 optimisation, preventing the defect from occurring. This has no 667 visible impact on the overall performance or power consumption of the 668 processor. Note that setting specific bits in the diagnostics register 669 may not be available in non-secure mode and thus is not available on a 670 multiplatform kernel. This should be applied by the bootloader instead. 671 672config ARM_ERRATA_751472 673 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 674 depends on CPU_V7 675 depends on !ARCH_MULTIPLATFORM 676 help 677 This option enables the workaround for the 751472 Cortex-A9 (prior 678 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 679 completion of a following broadcasted operation if the second 680 operation is received by a CPU before the ICIALLUIS has completed, 681 potentially leading to corrupted entries in the cache or TLB. 682 Note that setting specific bits in the diagnostics register may 683 not be available in non-secure mode and thus is not available on 684 a multiplatform kernel. This should be applied by the bootloader 685 instead. 686 687config ARM_ERRATA_754322 688 bool "ARM errata: possible faulty MMU translations following an ASID switch" 689 depends on CPU_V7 690 help 691 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 692 r3p*) erratum. A speculative memory access may cause a page table walk 693 which starts prior to an ASID switch but completes afterwards. This 694 can populate the micro-TLB with a stale entry which may be hit with 695 the new ASID. This workaround places two dsb instructions in the mm 696 switching code so that no page table walks can cross the ASID switch. 697 698config ARM_ERRATA_754327 699 bool "ARM errata: no automatic Store Buffer drain" 700 depends on CPU_V7 && SMP 701 help 702 This option enables the workaround for the 754327 Cortex-A9 (prior to 703 r2p0) erratum. The Store Buffer does not have any automatic draining 704 mechanism and therefore a livelock may occur if an external agent 705 continuously polls a memory location waiting to observe an update. 706 This workaround defines cpu_relax() as smp_mb(), preventing correctly 707 written polling loops from denying visibility of updates to memory. 708 709config ARM_ERRATA_364296 710 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 711 depends on CPU_V6 712 help 713 This options enables the workaround for the 364296 ARM1136 714 r0p2 erratum (possible cache data corruption with 715 hit-under-miss enabled). It sets the undocumented bit 31 in 716 the auxiliary control register and the FI bit in the control 717 register, thus disabling hit-under-miss without putting the 718 processor into full low interrupt latency mode. ARM11MPCore 719 is not affected. 720 721config ARM_ERRATA_764369 722 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 723 depends on CPU_V7 && SMP 724 help 725 This option enables the workaround for erratum 764369 726 affecting Cortex-A9 MPCore with two or more processors (all 727 current revisions). Under certain timing circumstances, a data 728 cache line maintenance operation by MVA targeting an Inner 729 Shareable memory region may fail to proceed up to either the 730 Point of Coherency or to the Point of Unification of the 731 system. This workaround adds a DSB instruction before the 732 relevant cache maintenance functions and sets a specific bit 733 in the diagnostic control register of the SCU. 734 735config ARM_ERRATA_764319 736 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 737 depends on CPU_V7 738 help 739 This option enables the workaround for the 764319 Cortex A-9 erratum. 740 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 741 unexpected Undefined Instruction exception when the DBGSWENABLE 742 external pin is set to 0, even when the CP14 accesses are performed 743 from a privileged mode. This work around catches the exception in a 744 way the kernel does not stop execution. 745 746config ARM_ERRATA_775420 747 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 748 depends on CPU_V7 749 help 750 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 751 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 752 operation aborts with MMU exception, it might cause the processor 753 to deadlock. This workaround puts DSB before executing ISB if 754 an abort may occur on cache maintenance. 755 756config ARM_ERRATA_798181 757 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 758 depends on CPU_V7 && SMP 759 help 760 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 761 adequately shooting down all use of the old entries. This 762 option enables the Linux kernel workaround for this erratum 763 which sends an IPI to the CPUs that are running the same ASID 764 as the one being invalidated. 765 766config ARM_ERRATA_773022 767 bool "ARM errata: incorrect instructions may be executed from loop buffer" 768 depends on CPU_V7 769 help 770 This option enables the workaround for the 773022 Cortex-A15 771 (up to r0p4) erratum. In certain rare sequences of code, the 772 loop buffer may deliver incorrect instructions. This 773 workaround disables the loop buffer to avoid the erratum. 774 775config ARM_ERRATA_818325_852422 776 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 777 depends on CPU_V7 778 help 779 This option enables the workaround for: 780 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 781 instruction might deadlock. Fixed in r0p1. 782 - Cortex-A12 852422: Execution of a sequence of instructions might 783 lead to either a data corruption or a CPU deadlock. Not fixed in 784 any Cortex-A12 cores yet. 785 This workaround for all both errata involves setting bit[12] of the 786 Feature Register. This bit disables an optimisation applied to a 787 sequence of 2 instructions that use opposing condition codes. 788 789config ARM_ERRATA_821420 790 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 791 depends on CPU_V7 792 help 793 This option enables the workaround for the 821420 Cortex-A12 794 (all revs) erratum. In very rare timing conditions, a sequence 795 of VMOV to Core registers instructions, for which the second 796 one is in the shadow of a branch or abort, can lead to a 797 deadlock when the VMOV instructions are issued out-of-order. 798 799config ARM_ERRATA_825619 800 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 801 depends on CPU_V7 802 help 803 This option enables the workaround for the 825619 Cortex-A12 804 (all revs) erratum. Within rare timing constraints, executing a 805 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 806 and Device/Strongly-Ordered loads and stores might cause deadlock 807 808config ARM_ERRATA_857271 809 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 857271 Cortex-A12 813 (all revs) erratum. Under very rare timing conditions, the CPU might 814 hang. The workaround is expected to have a < 1% performance impact. 815 816config ARM_ERRATA_852421 817 bool "ARM errata: A17: DMB ST might fail to create order between stores" 818 depends on CPU_V7 819 help 820 This option enables the workaround for the 852421 Cortex-A17 821 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 822 execution of a DMB ST instruction might fail to properly order 823 stores from GroupA and stores from GroupB. 824 825config ARM_ERRATA_852423 826 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 827 depends on CPU_V7 828 help 829 This option enables the workaround for: 830 - Cortex-A17 852423: Execution of a sequence of instructions might 831 lead to either a data corruption or a CPU deadlock. Not fixed in 832 any Cortex-A17 cores yet. 833 This is identical to Cortex-A12 erratum 852422. It is a separate 834 config option from the A12 erratum due to the way errata are checked 835 for and handled. 836 837config ARM_ERRATA_857272 838 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 839 depends on CPU_V7 840 help 841 This option enables the workaround for the 857272 Cortex-A17 erratum. 842 This erratum is not known to be fixed in any A17 revision. 843 This is identical to Cortex-A12 erratum 857271. It is a separate 844 config option from the A12 erratum due to the way errata are checked 845 for and handled. 846 847endmenu 848 849source "arch/arm/common/Kconfig" 850 851menu "Bus support" 852 853config ISA 854 bool 855 help 856 Find out whether you have ISA slots on your motherboard. ISA is the 857 name of a bus system, i.e. the way the CPU talks to the other stuff 858 inside your box. Other bus systems are PCI, EISA, MicroChannel 859 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 860 newer boards don't support it. If you have ISA, say Y, otherwise N. 861 862# Select ISA DMA interface 863config ISA_DMA_API 864 bool 865 866config ARM_ERRATA_814220 867 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 868 depends on CPU_V7 869 help 870 The v7 ARM states that all cache and branch predictor maintenance 871 operations that do not specify an address execute, relative to 872 each other, in program order. 873 However, because of this erratum, an L2 set/way cache maintenance 874 operation can overtake an L1 set/way cache maintenance operation. 875 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 876 r0p4, r0p5. 877 878endmenu 879 880menu "Kernel Features" 881 882config HAVE_SMP 883 bool 884 help 885 This option should be selected by machines which have an SMP- 886 capable CPU. 887 888 The only effect of this option is to make the SMP-related 889 options available to the user for configuration. 890 891config SMP 892 bool "Symmetric Multi-Processing" 893 depends on CPU_V6K || CPU_V7 894 depends on HAVE_SMP 895 depends on MMU || ARM_MPU 896 select IRQ_WORK 897 help 898 This enables support for systems with more than one CPU. If you have 899 a system with only one CPU, say N. If you have a system with more 900 than one CPU, say Y. 901 902 If you say N here, the kernel will run on uni- and multiprocessor 903 machines, but will use only one CPU of a multiprocessor machine. If 904 you say Y here, the kernel will run on many, but not all, 905 uniprocessor machines. On a uniprocessor machine, the kernel 906 will run faster if you say N here. 907 908 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 909 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 910 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 911 912 If you don't know what to do here, say N. 913 914config SMP_ON_UP 915 bool "Allow booting SMP kernel on uniprocessor systems" 916 depends on SMP && MMU 917 default y 918 help 919 SMP kernels contain instructions which fail on non-SMP processors. 920 Enabling this option allows the kernel to modify itself to make 921 these instructions safe. Disabling it allows about 1K of space 922 savings. 923 924 If you don't know what to do here, say Y. 925 926 927config CURRENT_POINTER_IN_TPIDRURO 928 def_bool y 929 depends on CPU_32v6K && !CPU_V6 930 931config IRQSTACKS 932 def_bool y 933 select HAVE_IRQ_EXIT_ON_IRQ_STACK 934 select HAVE_SOFTIRQ_ON_OWN_STACK 935 936config ARM_CPU_TOPOLOGY 937 bool "Support cpu topology definition" 938 depends on SMP && CPU_V7 939 default y 940 help 941 Support ARM cpu topology definition. The MPIDR register defines 942 affinity between processors which is then used to describe the cpu 943 topology of an ARM System. 944 945config SCHED_MC 946 bool "Multi-core scheduler support" 947 depends on ARM_CPU_TOPOLOGY 948 help 949 Multi-core scheduler support improves the CPU scheduler's decision 950 making when dealing with multi-core CPU chips at a cost of slightly 951 increased overhead in some places. If unsure say N here. 952 953config SCHED_SMT 954 bool "SMT scheduler support" 955 depends on ARM_CPU_TOPOLOGY 956 help 957 Improves the CPU scheduler's decision making when dealing with 958 MultiThreading at a cost of slightly increased overhead in some 959 places. If unsure say N here. 960 961config HAVE_ARM_SCU 962 bool 963 help 964 This option enables support for the ARM snoop control unit 965 966config HAVE_ARM_ARCH_TIMER 967 bool "Architected timer support" 968 depends on CPU_V7 969 select ARM_ARCH_TIMER 970 help 971 This option enables support for the ARM architected timer 972 973config HAVE_ARM_TWD 974 bool 975 help 976 This options enables support for the ARM timer and watchdog unit 977 978config MCPM 979 bool "Multi-Cluster Power Management" 980 depends on CPU_V7 && SMP 981 help 982 This option provides the common power management infrastructure 983 for (multi-)cluster based systems, such as big.LITTLE based 984 systems. 985 986config MCPM_QUAD_CLUSTER 987 bool 988 depends on MCPM 989 help 990 To avoid wasting resources unnecessarily, MCPM only supports up 991 to 2 clusters by default. 992 Platforms with 3 or 4 clusters that use MCPM must select this 993 option to allow the additional clusters to be managed. 994 995config BIG_LITTLE 996 bool "big.LITTLE support (Experimental)" 997 depends on CPU_V7 && SMP 998 select MCPM 999 help 1000 This option enables support selections for the big.LITTLE 1001 system architecture. 1002 1003config BL_SWITCHER 1004 bool "big.LITTLE switcher support" 1005 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1006 select CPU_PM 1007 help 1008 The big.LITTLE "switcher" provides the core functionality to 1009 transparently handle transition between a cluster of A15's 1010 and a cluster of A7's in a big.LITTLE system. 1011 1012config BL_SWITCHER_DUMMY_IF 1013 tristate "Simple big.LITTLE switcher user interface" 1014 depends on BL_SWITCHER && DEBUG_KERNEL 1015 help 1016 This is a simple and dummy char dev interface to control 1017 the big.LITTLE switcher core code. It is meant for 1018 debugging purposes only. 1019 1020choice 1021 prompt "Memory split" 1022 depends on MMU 1023 default VMSPLIT_3G 1024 help 1025 Select the desired split between kernel and user memory. 1026 1027 If you are not absolutely sure what you are doing, leave this 1028 option alone! 1029 1030 config VMSPLIT_3G 1031 bool "3G/1G user/kernel split" 1032 config VMSPLIT_3G_OPT 1033 depends on !ARM_LPAE 1034 bool "3G/1G user/kernel split (for full 1G low memory)" 1035 config VMSPLIT_2G 1036 bool "2G/2G user/kernel split" 1037 config VMSPLIT_1G 1038 bool "1G/3G user/kernel split" 1039endchoice 1040 1041config PAGE_OFFSET 1042 hex 1043 default PHYS_OFFSET if !MMU 1044 default 0x40000000 if VMSPLIT_1G 1045 default 0x80000000 if VMSPLIT_2G 1046 default 0xB0000000 if VMSPLIT_3G_OPT 1047 default 0xC0000000 1048 1049config KASAN_SHADOW_OFFSET 1050 hex 1051 depends on KASAN 1052 default 0x1f000000 if PAGE_OFFSET=0x40000000 1053 default 0x5f000000 if PAGE_OFFSET=0x80000000 1054 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1055 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1056 default 0xffffffff 1057 1058config NR_CPUS 1059 int "Maximum number of CPUs (2-32)" 1060 range 2 16 if DEBUG_KMAP_LOCAL 1061 range 2 32 if !DEBUG_KMAP_LOCAL 1062 depends on SMP 1063 default "4" 1064 help 1065 The maximum number of CPUs that the kernel can support. 1066 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1067 debugging is enabled, which uses half of the per-CPU fixmap 1068 slots as guard regions. 1069 1070config HOTPLUG_CPU 1071 bool "Support for hot-pluggable CPUs" 1072 depends on SMP 1073 select GENERIC_IRQ_MIGRATION 1074 help 1075 Say Y here to experiment with turning CPUs off and on. CPUs 1076 can be controlled through /sys/devices/system/cpu. 1077 1078config ARM_PSCI 1079 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1080 depends on HAVE_ARM_SMCCC 1081 select ARM_PSCI_FW 1082 help 1083 Say Y here if you want Linux to communicate with system firmware 1084 implementing the PSCI specification for CPU-centric power 1085 management operations described in ARM document number ARM DEN 1086 0022A ("Power State Coordination Interface System Software on 1087 ARM processors"). 1088 1089config HZ_FIXED 1090 int 1091 default 128 if SOC_AT91RM9200 1092 default 0 1093 1094choice 1095 depends on HZ_FIXED = 0 1096 prompt "Timer frequency" 1097 1098config HZ_100 1099 bool "100 Hz" 1100 1101config HZ_200 1102 bool "200 Hz" 1103 1104config HZ_250 1105 bool "250 Hz" 1106 1107config HZ_300 1108 bool "300 Hz" 1109 1110config HZ_500 1111 bool "500 Hz" 1112 1113config HZ_1000 1114 bool "1000 Hz" 1115 1116endchoice 1117 1118config HZ 1119 int 1120 default HZ_FIXED if HZ_FIXED != 0 1121 default 100 if HZ_100 1122 default 200 if HZ_200 1123 default 250 if HZ_250 1124 default 300 if HZ_300 1125 default 500 if HZ_500 1126 default 1000 1127 1128config SCHED_HRTICK 1129 def_bool HIGH_RES_TIMERS 1130 1131config THUMB2_KERNEL 1132 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1133 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1134 default y if CPU_THUMBONLY 1135 select ARM_UNWIND 1136 help 1137 By enabling this option, the kernel will be compiled in 1138 Thumb-2 mode. 1139 1140 If unsure, say N. 1141 1142config ARM_PATCH_IDIV 1143 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1144 depends on CPU_32v7 1145 default y 1146 help 1147 The ARM compiler inserts calls to __aeabi_idiv() and 1148 __aeabi_uidiv() when it needs to perform division on signed 1149 and unsigned integers. Some v7 CPUs have support for the sdiv 1150 and udiv instructions that can be used to implement those 1151 functions. 1152 1153 Enabling this option allows the kernel to modify itself to 1154 replace the first two instructions of these library functions 1155 with the sdiv or udiv plus "bx lr" instructions when the CPU 1156 it is running on supports them. Typically this will be faster 1157 and less power intensive than running the original library 1158 code to do integer division. 1159 1160config AEABI 1161 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1162 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1163 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1164 help 1165 This option allows for the kernel to be compiled using the latest 1166 ARM ABI (aka EABI). This is only useful if you are using a user 1167 space environment that is also compiled with EABI. 1168 1169 Since there are major incompatibilities between the legacy ABI and 1170 EABI, especially with regard to structure member alignment, this 1171 option also changes the kernel syscall calling convention to 1172 disambiguate both ABIs and allow for backward compatibility support 1173 (selected with CONFIG_OABI_COMPAT). 1174 1175 To use this you need GCC version 4.0.0 or later. 1176 1177config OABI_COMPAT 1178 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1179 depends on AEABI && !THUMB2_KERNEL 1180 help 1181 This option preserves the old syscall interface along with the 1182 new (ARM EABI) one. It also provides a compatibility layer to 1183 intercept syscalls that have structure arguments which layout 1184 in memory differs between the legacy ABI and the new ARM EABI 1185 (only for non "thumb" binaries). This option adds a tiny 1186 overhead to all syscalls and produces a slightly larger kernel. 1187 1188 The seccomp filter system will not be available when this is 1189 selected, since there is no way yet to sensibly distinguish 1190 between calling conventions during filtering. 1191 1192 If you know you'll be using only pure EABI user space then you 1193 can say N here. If this option is not selected and you attempt 1194 to execute a legacy ABI binary then the result will be 1195 UNPREDICTABLE (in fact it can be predicted that it won't work 1196 at all). If in doubt say N. 1197 1198config ARCH_SELECT_MEMORY_MODEL 1199 def_bool y 1200 1201config ARCH_FLATMEM_ENABLE 1202 def_bool !(ARCH_RPC || ARCH_SA1100) 1203 1204config ARCH_SPARSEMEM_ENABLE 1205 def_bool !ARCH_FOOTBRIDGE 1206 select SPARSEMEM_STATIC if SPARSEMEM 1207 1208config HIGHMEM 1209 bool "High Memory Support" 1210 depends on MMU 1211 select KMAP_LOCAL 1212 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1213 help 1214 The address space of ARM processors is only 4 Gigabytes large 1215 and it has to accommodate user address space, kernel address 1216 space as well as some memory mapped IO. That means that, if you 1217 have a large amount of physical memory and/or IO, not all of the 1218 memory can be "permanently mapped" by the kernel. The physical 1219 memory that is not permanently mapped is called "high memory". 1220 1221 Depending on the selected kernel/user memory split, minimum 1222 vmalloc space and actual amount of RAM, you may not need this 1223 option which should result in a slightly faster kernel. 1224 1225 If unsure, say n. 1226 1227config HIGHPTE 1228 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1229 depends on HIGHMEM 1230 default y 1231 help 1232 The VM uses one page of physical memory for each page table. 1233 For systems with a lot of processes, this can use a lot of 1234 precious low memory, eventually leading to low memory being 1235 consumed by page tables. Setting this option will allow 1236 user-space 2nd level page tables to reside in high memory. 1237 1238config ARM_PAN 1239 bool "Enable privileged no-access" 1240 depends on MMU 1241 default y 1242 help 1243 Increase kernel security by ensuring that normal kernel accesses 1244 are unable to access userspace addresses. This can help prevent 1245 use-after-free bugs becoming an exploitable privilege escalation 1246 by ensuring that magic values (such as LIST_POISON) will always 1247 fault when dereferenced. 1248 1249 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1250 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1251 1252config CPU_SW_DOMAIN_PAN 1253 def_bool y 1254 depends on ARM_PAN && !ARM_LPAE 1255 help 1256 Enable use of CPU domains to implement privileged no-access. 1257 1258 CPUs with low-vector mappings use a best-efforts implementation. 1259 Their lower 1MB needs to remain accessible for the vectors, but 1260 the remainder of userspace will become appropriately inaccessible. 1261 1262config CPU_TTBR0_PAN 1263 def_bool y 1264 depends on ARM_PAN && ARM_LPAE 1265 help 1266 Enable privileged no-access by disabling TTBR0 page table walks when 1267 running in kernel mode. 1268 1269config HW_PERF_EVENTS 1270 def_bool y 1271 depends on ARM_PMU 1272 1273config ARM_MODULE_PLTS 1274 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1275 depends on MODULES 1276 select KASAN_VMALLOC if KASAN 1277 default y 1278 help 1279 Allocate PLTs when loading modules so that jumps and calls whose 1280 targets are too far away for their relative offsets to be encoded 1281 in the instructions themselves can be bounced via veneers in the 1282 module's PLT. This allows modules to be allocated in the generic 1283 vmalloc area after the dedicated module memory area has been 1284 exhausted. The modules will use slightly more memory, but after 1285 rounding up to page size, the actual memory footprint is usually 1286 the same. 1287 1288 Disabling this is usually safe for small single-platform 1289 configurations. If unsure, say y. 1290 1291config ARCH_FORCE_MAX_ORDER 1292 int "Order of maximal physically contiguous allocations" 1293 default "11" if SOC_AM33XX 1294 default "8" if SA1111 1295 default "10" 1296 help 1297 The kernel page allocator limits the size of maximal physically 1298 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1299 defines the maximal power of two of number of pages that can be 1300 allocated as a single contiguous block. This option allows 1301 overriding the default setting when ability to allocate very 1302 large blocks of physically contiguous memory is required. 1303 1304 Don't change if unsure. 1305 1306config ALIGNMENT_TRAP 1307 def_bool CPU_CP15_MMU 1308 select HAVE_PROC_CPU if PROC_FS 1309 help 1310 ARM processors cannot fetch/store information which is not 1311 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1312 address divisible by 4. On 32-bit ARM processors, these non-aligned 1313 fetch/store instructions will be emulated in software if you say 1314 here, which has a severe performance impact. This is necessary for 1315 correct operation of some network protocols. With an IP-only 1316 configuration it is safe to say N, otherwise say Y. 1317 1318config UACCESS_WITH_MEMCPY 1319 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1320 depends on MMU 1321 default y if CPU_FEROCEON 1322 help 1323 Implement faster copy_to_user and clear_user methods for CPU 1324 cores where a 8-word STM instruction give significantly higher 1325 memory write throughput than a sequence of individual 32bit stores. 1326 1327 A possible side effect is a slight increase in scheduling latency 1328 between threads sharing the same address space if they invoke 1329 such copy operations with large buffers. 1330 1331 However, if the CPU data cache is using a write-allocate mode, 1332 this option is unlikely to provide any performance gain. 1333 1334config PARAVIRT 1335 bool "Enable paravirtualization code" 1336 help 1337 This changes the kernel so it can modify itself when it is run 1338 under a hypervisor, potentially improving performance significantly 1339 over full virtualization. 1340 1341config PARAVIRT_TIME_ACCOUNTING 1342 bool "Paravirtual steal time accounting" 1343 select PARAVIRT 1344 help 1345 Select this option to enable fine granularity task steal time 1346 accounting. Time spent executing other tasks in parallel with 1347 the current vCPU is discounted from the vCPU power. To account for 1348 that, there can be a small performance impact. 1349 1350 If in doubt, say N here. 1351 1352config XEN_DOM0 1353 def_bool y 1354 depends on XEN 1355 1356config XEN 1357 bool "Xen guest support on ARM" 1358 depends on ARM && AEABI && OF 1359 depends on CPU_V7 && !CPU_V6 1360 depends on !GENERIC_ATOMIC64 1361 depends on MMU 1362 select ARCH_DMA_ADDR_T_64BIT 1363 select ARM_PSCI 1364 select SWIOTLB 1365 select SWIOTLB_XEN 1366 select PARAVIRT 1367 help 1368 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1369 1370config CC_HAVE_STACKPROTECTOR_TLS 1371 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1372 1373config STACKPROTECTOR_PER_TASK 1374 bool "Use a unique stack canary value for each task" 1375 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1376 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1377 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1378 default y 1379 help 1380 Due to the fact that GCC uses an ordinary symbol reference from 1381 which to load the value of the stack canary, this value can only 1382 change at reboot time on SMP systems, and all tasks running in the 1383 kernel's address space are forced to use the same canary value for 1384 the entire duration that the system is up. 1385 1386 Enable this option to switch to a different method that uses a 1387 different canary value for each task. 1388 1389endmenu 1390 1391menu "Boot options" 1392 1393config USE_OF 1394 bool "Flattened Device Tree support" 1395 select IRQ_DOMAIN 1396 select OF 1397 help 1398 Include support for flattened device tree machine descriptions. 1399 1400config ARCH_WANT_FLAT_DTB_INSTALL 1401 def_bool y 1402 1403config ATAGS 1404 bool "Support for the traditional ATAGS boot data passing" 1405 default y 1406 help 1407 This is the traditional way of passing data to the kernel at boot 1408 time. If you are solely relying on the flattened device tree (or 1409 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1410 to remove ATAGS support from your kernel binary. 1411 1412config DEPRECATED_PARAM_STRUCT 1413 bool "Provide old way to pass kernel parameters" 1414 depends on ATAGS 1415 help 1416 This was deprecated in 2001 and announced to live on for 5 years. 1417 Some old boot loaders still use this way. 1418 1419# Compressed boot loader in ROM. Yes, we really want to ask about 1420# TEXT and BSS so we preserve their values in the config files. 1421config ZBOOT_ROM_TEXT 1422 hex "Compressed ROM boot loader base address" 1423 default 0x0 1424 help 1425 The physical address at which the ROM-able zImage is to be 1426 placed in the target. Platforms which normally make use of 1427 ROM-able zImage formats normally set this to a suitable 1428 value in their defconfig file. 1429 1430 If ZBOOT_ROM is not enabled, this has no effect. 1431 1432config ZBOOT_ROM_BSS 1433 hex "Compressed ROM boot loader BSS address" 1434 default 0x0 1435 help 1436 The base address of an area of read/write memory in the target 1437 for the ROM-able zImage which must be available while the 1438 decompressor is running. It must be large enough to hold the 1439 entire decompressed kernel plus an additional 128 KiB. 1440 Platforms which normally make use of ROM-able zImage formats 1441 normally set this to a suitable value in their defconfig file. 1442 1443 If ZBOOT_ROM is not enabled, this has no effect. 1444 1445config ZBOOT_ROM 1446 bool "Compressed boot loader in ROM/flash" 1447 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1448 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1449 help 1450 Say Y here if you intend to execute your compressed kernel image 1451 (zImage) directly from ROM or flash. If unsure, say N. 1452 1453config ARM_APPENDED_DTB 1454 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1455 depends on OF 1456 help 1457 With this option, the boot code will look for a device tree binary 1458 (DTB) appended to zImage 1459 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1460 1461 This is meant as a backward compatibility convenience for those 1462 systems with a bootloader that can't be upgraded to accommodate 1463 the documented boot protocol using a device tree. 1464 1465 Beware that there is very little in terms of protection against 1466 this option being confused by leftover garbage in memory that might 1467 look like a DTB header after a reboot if no actual DTB is appended 1468 to zImage. Do not leave this option active in a production kernel 1469 if you don't intend to always append a DTB. Proper passing of the 1470 location into r2 of a bootloader provided DTB is always preferable 1471 to this option. 1472 1473config ARM_ATAG_DTB_COMPAT 1474 bool "Supplement the appended DTB with traditional ATAG information" 1475 depends on ARM_APPENDED_DTB 1476 help 1477 Some old bootloaders can't be updated to a DTB capable one, yet 1478 they provide ATAGs with memory configuration, the ramdisk address, 1479 the kernel cmdline string, etc. Such information is dynamically 1480 provided by the bootloader and can't always be stored in a static 1481 DTB. To allow a device tree enabled kernel to be used with such 1482 bootloaders, this option allows zImage to extract the information 1483 from the ATAG list and store it at run time into the appended DTB. 1484 1485choice 1486 prompt "Kernel command line type" 1487 depends on ARM_ATAG_DTB_COMPAT 1488 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1489 1490config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1491 bool "Use bootloader kernel arguments if available" 1492 help 1493 Uses the command-line options passed by the boot loader instead of 1494 the device tree bootargs property. If the boot loader doesn't provide 1495 any, the device tree bootargs property will be used. 1496 1497config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1498 bool "Extend with bootloader kernel arguments" 1499 help 1500 The command-line arguments provided by the boot loader will be 1501 appended to the the device tree bootargs property. 1502 1503endchoice 1504 1505config CMDLINE 1506 string "Default kernel command string" 1507 default "" 1508 help 1509 On some architectures (e.g. CATS), there is currently no way 1510 for the boot loader to pass arguments to the kernel. For these 1511 architectures, you should supply some command-line options at build 1512 time by entering them here. As a minimum, you should specify the 1513 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1514 1515choice 1516 prompt "Kernel command line type" 1517 depends on CMDLINE != "" 1518 default CMDLINE_FROM_BOOTLOADER 1519 1520config CMDLINE_FROM_BOOTLOADER 1521 bool "Use bootloader kernel arguments if available" 1522 help 1523 Uses the command-line options passed by the boot loader. If 1524 the boot loader doesn't provide any, the default kernel command 1525 string provided in CMDLINE will be used. 1526 1527config CMDLINE_EXTEND 1528 bool "Extend bootloader kernel arguments" 1529 help 1530 The command-line arguments provided by the boot loader will be 1531 appended to the default kernel command string. 1532 1533config CMDLINE_FORCE 1534 bool "Always use the default kernel command string" 1535 help 1536 Always use the default kernel command string, even if the boot 1537 loader passes other arguments to the kernel. 1538 This is useful if you cannot or don't want to change the 1539 command-line options your boot loader passes to the kernel. 1540endchoice 1541 1542config XIP_KERNEL 1543 bool "Kernel Execute-In-Place from ROM" 1544 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1545 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1546 help 1547 Execute-In-Place allows the kernel to run from non-volatile storage 1548 directly addressable by the CPU, such as NOR flash. This saves RAM 1549 space since the text section of the kernel is not loaded from flash 1550 to RAM. Read-write sections, such as the data section and stack, 1551 are still copied to RAM. The XIP kernel is not compressed since 1552 it has to run directly from flash, so it will take more space to 1553 store it. The flash address used to link the kernel object files, 1554 and for storing it, is configuration dependent. Therefore, if you 1555 say Y here, you must know the proper physical address where to 1556 store the kernel image depending on your own flash memory usage. 1557 1558 Also note that the make target becomes "make xipImage" rather than 1559 "make zImage" or "make Image". The final kernel binary to put in 1560 ROM memory will be arch/arm/boot/xipImage. 1561 1562 If unsure, say N. 1563 1564config XIP_PHYS_ADDR 1565 hex "XIP Kernel Physical Location" 1566 depends on XIP_KERNEL 1567 default "0x00080000" 1568 help 1569 This is the physical address in your flash memory the kernel will 1570 be linked for and stored to. This address is dependent on your 1571 own flash usage. 1572 1573config XIP_DEFLATED_DATA 1574 bool "Store kernel .data section compressed in ROM" 1575 depends on XIP_KERNEL 1576 select ZLIB_INFLATE 1577 help 1578 Before the kernel is actually executed, its .data section has to be 1579 copied to RAM from ROM. This option allows for storing that data 1580 in compressed form and decompressed to RAM rather than merely being 1581 copied, saving some precious ROM space. A possible drawback is a 1582 slightly longer boot delay. 1583 1584config ARCH_SUPPORTS_KEXEC 1585 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1586 1587config ATAGS_PROC 1588 bool "Export atags in procfs" 1589 depends on ATAGS && KEXEC 1590 default y 1591 help 1592 Should the atags used to boot the kernel be exported in an "atags" 1593 file in procfs. Useful with kexec. 1594 1595config ARCH_SUPPORTS_CRASH_DUMP 1596 def_bool y 1597 1598config AUTO_ZRELADDR 1599 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1600 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1601 help 1602 ZRELADDR is the physical address where the decompressed kernel 1603 image will be placed. If AUTO_ZRELADDR is selected, the address 1604 will be determined at run-time, either by masking the current IP 1605 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1606 This assumes the zImage being placed in the first 128MB from 1607 start of memory. 1608 1609config EFI_STUB 1610 bool 1611 1612config EFI 1613 bool "UEFI runtime support" 1614 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1615 select UCS2_STRING 1616 select EFI_PARAMS_FROM_FDT 1617 select EFI_STUB 1618 select EFI_GENERIC_STUB 1619 select EFI_RUNTIME_WRAPPERS 1620 help 1621 This option provides support for runtime services provided 1622 by UEFI firmware (such as non-volatile variables, realtime 1623 clock, and platform reset). A UEFI stub is also provided to 1624 allow the kernel to be booted as an EFI application. This 1625 is only useful for kernels that may run on systems that have 1626 UEFI firmware. 1627 1628config DMI 1629 bool "Enable support for SMBIOS (DMI) tables" 1630 depends on EFI 1631 default y 1632 help 1633 This enables SMBIOS/DMI feature for systems. 1634 1635 This option is only useful on systems that have UEFI firmware. 1636 However, even with this option, the resultant kernel should 1637 continue to boot on existing non-UEFI platforms. 1638 1639 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1640 i.e., the the practice of identifying the platform via DMI to 1641 decide whether certain workarounds for buggy hardware and/or 1642 firmware need to be enabled. This would require the DMI subsystem 1643 to be enabled much earlier than we do on ARM, which is non-trivial. 1644 1645endmenu 1646 1647menu "CPU Power Management" 1648 1649source "drivers/cpufreq/Kconfig" 1650 1651source "drivers/cpuidle/Kconfig" 1652 1653endmenu 1654 1655menu "Floating point emulation" 1656 1657comment "At least one emulation must be selected" 1658 1659config FPE_NWFPE 1660 bool "NWFPE math emulation" 1661 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1662 help 1663 Say Y to include the NWFPE floating point emulator in the kernel. 1664 This is necessary to run most binaries. Linux does not currently 1665 support floating point hardware so you need to say Y here even if 1666 your machine has an FPA or floating point co-processor podule. 1667 1668 You may say N here if you are going to load the Acorn FPEmulator 1669 early in the bootup. 1670 1671config FPE_NWFPE_XP 1672 bool "Support extended precision" 1673 depends on FPE_NWFPE 1674 help 1675 Say Y to include 80-bit support in the kernel floating-point 1676 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1677 Note that gcc does not generate 80-bit operations by default, 1678 so in most cases this option only enlarges the size of the 1679 floating point emulator without any good reason. 1680 1681 You almost surely want to say N here. 1682 1683config FPE_FASTFPE 1684 bool "FastFPE math emulation (EXPERIMENTAL)" 1685 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1686 help 1687 Say Y here to include the FAST floating point emulator in the kernel. 1688 This is an experimental much faster emulator which now also has full 1689 precision for the mantissa. It does not support any exceptions. 1690 It is very simple, and approximately 3-6 times faster than NWFPE. 1691 1692 It should be sufficient for most programs. It may be not suitable 1693 for scientific calculations, but you have to check this for yourself. 1694 If you do not feel you need a faster FP emulation you should better 1695 choose NWFPE. 1696 1697config VFP 1698 bool "VFP-format floating point maths" 1699 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1700 help 1701 Say Y to include VFP support code in the kernel. This is needed 1702 if your hardware includes a VFP unit. 1703 1704 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1705 release notes and additional status information. 1706 1707 Say N if your target does not have VFP hardware. 1708 1709config VFPv3 1710 bool 1711 depends on VFP 1712 default y if CPU_V7 1713 1714config NEON 1715 bool "Advanced SIMD (NEON) Extension support" 1716 depends on VFPv3 && CPU_V7 1717 help 1718 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1719 Extension. 1720 1721config KERNEL_MODE_NEON 1722 bool "Support for NEON in kernel mode" 1723 depends on NEON && AEABI 1724 help 1725 Say Y to include support for NEON in kernel mode. 1726 1727endmenu 1728 1729menu "Power management options" 1730 1731source "kernel/power/Kconfig" 1732 1733config ARCH_SUSPEND_POSSIBLE 1734 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1735 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1736 def_bool y 1737 1738config ARM_CPU_SUSPEND 1739 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1740 depends on ARCH_SUSPEND_POSSIBLE 1741 1742config ARCH_HIBERNATION_POSSIBLE 1743 bool 1744 depends on MMU 1745 default y if ARCH_SUSPEND_POSSIBLE 1746 1747endmenu 1748 1749source "arch/arm/Kconfig.assembler" 1750