1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_CACHE_ALIASING 9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 10 select ARCH_HAS_CRC32 if KERNEL_MODE_NEON 11 select ARCH_HAS_CURRENT_STACK_POINTER 12 select ARCH_HAS_DEBUG_VIRTUAL if MMU 13 select ARCH_HAS_DMA_ALLOC if MMU 14 select ARCH_HAS_DMA_OPS 15 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 16 select ARCH_HAS_ELF_RANDOMIZE 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_KEEPINITRD 19 select ARCH_HAS_KCOV 20 select ARCH_HAS_MEMBARRIER_SYNC_CORE 21 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 22 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 23 select ARCH_HAS_SETUP_DMA_OPS 24 select ARCH_HAS_SET_MEMORY 25 select ARCH_STACKWALK 26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 27 select ARCH_HAS_STRICT_MODULE_RWX if MMU 28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 29 select ARCH_HAS_SYNC_DMA_FOR_CPU 30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 32 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_KEEP_MEMBLOCK 35 select ARCH_HAS_UBSAN 36 select ARCH_MIGHT_HAVE_PC_PARPORT 37 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 38 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 39 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 40 select ARCH_SUPPORTS_ATOMIC_RMW 41 select ARCH_SUPPORTS_CFI_CLANG 42 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 43 select ARCH_SUPPORTS_PER_VMA_LOCK 44 select ARCH_USE_BUILTIN_BSWAP 45 select ARCH_USE_CMPXCHG_LOCKREF 46 select ARCH_USE_MEMTEST 47 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 48 select ARCH_WANT_GENERAL_HUGETLB 49 select ARCH_WANT_IPC_PARSE_VERSION 50 select ARCH_WANT_LD_ORPHAN_WARN 51 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 52 select BUILDTIME_TABLE_SORT if MMU 53 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 54 select CLONE_BACKWARDS 55 select CPU_PM if SUSPEND || CPU_IDLE 56 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 57 select DMA_DECLARE_COHERENT 58 select DMA_GLOBAL_POOL if !MMU 59 select DMA_NONCOHERENT_MMAP if MMU 60 select EDAC_SUPPORT 61 select EDAC_ATOMIC_SCRUB 62 select GENERIC_ALLOCATOR 63 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 64 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 65 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 66 select GENERIC_IRQ_IPI if SMP 67 select GENERIC_CPU_AUTOPROBE 68 select GENERIC_CPU_DEVICES 69 select GENERIC_EARLY_IOREMAP 70 select GENERIC_IDLE_POLL_SETUP 71 select GENERIC_IRQ_MULTI_HANDLER 72 select GENERIC_IRQ_PROBE 73 select GENERIC_IRQ_SHOW 74 select GENERIC_IRQ_SHOW_LEVEL 75 select GENERIC_LIB_DEVMEM_IS_ALLOWED 76 select GENERIC_PCI_IOMAP 77 select GENERIC_SCHED_CLOCK 78 select GENERIC_SMP_IDLE_THREAD 79 select HARDIRQS_SW_RESEND 80 select HAS_IOPORT 81 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 83 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 88 select HAVE_ARCH_MMAP_RND_BITS if MMU 89 select HAVE_ARCH_PFN_VALID 90 select HAVE_ARCH_SECCOMP 91 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 92 select HAVE_ARCH_STACKLEAK 93 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 94 select HAVE_ARCH_TRACEHOOK 95 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 96 select HAVE_ARM_SMCCC if CPU_V7 97 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 98 select HAVE_CONTEXT_TRACKING_USER 99 select HAVE_C_RECORDMCOUNT 100 select HAVE_BUILDTIME_MCOUNT_SORT 101 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 102 select HAVE_DMA_CONTIGUOUS if MMU 103 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 104 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 105 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 106 select HAVE_EXIT_THREAD 107 select HAVE_GUP_FAST if ARM_LPAE 108 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 109 select HAVE_FUNCTION_ERROR_INJECTION 110 select HAVE_FUNCTION_GRAPH_TRACER 111 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 112 select HAVE_GCC_PLUGINS 113 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 114 select HAVE_IRQ_TIME_ACCOUNTING 115 select HAVE_KERNEL_GZIP 116 select HAVE_KERNEL_LZ4 117 select HAVE_KERNEL_LZMA 118 select HAVE_KERNEL_LZO 119 select HAVE_KERNEL_XZ 120 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 121 select HAVE_KRETPROBES if HAVE_KPROBES 122 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) 123 select HAVE_MOD_ARCH_SPECIFIC 124 select HAVE_NMI 125 select HAVE_OPTPROBES if !THUMB2_KERNEL 126 select HAVE_PAGE_SIZE_4KB 127 select HAVE_PCI if MMU 128 select HAVE_PERF_EVENTS 129 select HAVE_PERF_REGS 130 select HAVE_PERF_USER_STACK_DUMP 131 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 132 select HAVE_REGS_AND_STACK_ACCESS_API 133 select HAVE_RSEQ 134 select HAVE_STACKPROTECTOR 135 select HAVE_SYSCALL_TRACEPOINTS 136 select HAVE_UID16 137 select HAVE_VIRT_CPU_ACCOUNTING_GEN 138 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 139 select IRQ_FORCED_THREADING 140 select LOCK_MM_AND_FIND_VMA 141 select MODULES_USE_ELF_REL 142 select NEED_DMA_MAP_STATE 143 select OF_EARLY_FLATTREE if OF 144 select OLD_SIGACTION 145 select OLD_SIGSUSPEND3 146 select PCI_DOMAINS_GENERIC if PCI 147 select PCI_SYSCALL if PCI 148 select PERF_USE_VMALLOC 149 select RTC_LIB 150 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 151 select SYS_SUPPORTS_APM_EMULATION 152 select THREAD_INFO_IN_TASK 153 select TIMER_OF if OF 154 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 155 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 156 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 157 # Above selects are sorted alphabetically; please add new ones 158 # according to that. Thanks. 159 help 160 The ARM series is a line of low-power-consumption RISC chip designs 161 licensed by ARM Ltd and targeted at embedded applications and 162 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 163 manufactured, but legacy ARM-based PC hardware remains popular in 164 Europe. There is an ARM Linux project with a web page at 165 <http://www.arm.linux.org.uk/>. 166 167config ARM_HAS_GROUP_RELOCS 168 def_bool y 169 depends on !LD_IS_LLD || LLD_VERSION >= 140000 170 depends on !COMPILE_TEST 171 help 172 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 173 relocations, which have been around for a long time, but were not 174 supported in LLD until version 14. The combined range is -/+ 256 MiB, 175 which is usually sufficient, but not for allyesconfig, so we disable 176 this feature when doing compile testing. 177 178config ARM_DMA_USE_IOMMU 179 bool 180 select NEED_SG_DMA_LENGTH 181 182if ARM_DMA_USE_IOMMU 183 184config ARM_DMA_IOMMU_ALIGNMENT 185 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 186 range 4 9 187 default 8 188 help 189 DMA mapping framework by default aligns all buffers to the smallest 190 PAGE_SIZE order which is greater than or equal to the requested buffer 191 size. This works well for buffers up to a few hundreds kilobytes, but 192 for larger buffers it just a waste of address space. Drivers which has 193 relatively small addressing window (like 64Mib) might run out of 194 virtual space with just a few allocations. 195 196 With this parameter you can specify the maximum PAGE_SIZE order for 197 DMA IOMMU buffers. Larger buffers will be aligned only to this 198 specified order. The order is expressed as a power of two multiplied 199 by the PAGE_SIZE. 200 201endif 202 203config SYS_SUPPORTS_APM_EMULATION 204 bool 205 206config HAVE_TCM 207 bool 208 select GENERIC_ALLOCATOR 209 210config HAVE_PROC_CPU 211 bool 212 213config NO_IOPORT_MAP 214 bool 215 216config SBUS 217 bool 218 219config STACKTRACE_SUPPORT 220 bool 221 default y 222 223config LOCKDEP_SUPPORT 224 bool 225 default y 226 227config ARCH_HAS_ILOG2_U32 228 bool 229 230config ARCH_HAS_ILOG2_U64 231 bool 232 233config ARCH_HAS_BANDGAP 234 bool 235 236config FIX_EARLYCON_MEM 237 def_bool y if MMU 238 239config GENERIC_HWEIGHT 240 bool 241 default y 242 243config GENERIC_CALIBRATE_DELAY 244 bool 245 default y 246 247config ARCH_MAY_HAVE_PC_FDC 248 bool 249 250config ARCH_SUPPORTS_UPROBES 251 def_bool y 252 253config GENERIC_ISA_DMA 254 bool 255 256config FIQ 257 bool 258 259config ARCH_MTD_XIP 260 bool 261 262config ARM_PATCH_PHYS_VIRT 263 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 264 default y 265 depends on MMU 266 help 267 Patch phys-to-virt and virt-to-phys translation functions at 268 boot and module load time according to the position of the 269 kernel in system memory. 270 271 This can only be used with non-XIP MMU kernels where the base 272 of physical memory is at a 2 MiB boundary. 273 274 Only disable this option if you know that you do not require 275 this feature (eg, building a kernel for a single machine) and 276 you need to shrink the kernel to the minimal size. 277 278config NEED_MACH_IO_H 279 bool 280 help 281 Select this when mach/io.h is required to provide special 282 definitions for this platform. The need for mach/io.h should 283 be avoided when possible. 284 285config NEED_MACH_MEMORY_H 286 bool 287 help 288 Select this when mach/memory.h is required to provide special 289 definitions for this platform. The need for mach/memory.h should 290 be avoided when possible. 291 292config PHYS_OFFSET 293 hex "Physical address of main memory" if MMU 294 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 295 default DRAM_BASE if !MMU 296 default 0x00000000 if ARCH_FOOTBRIDGE 297 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 298 default 0xa0000000 if ARCH_PXA 299 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 300 default 0 301 help 302 Please provide the physical address corresponding to the 303 location of main memory in your system. 304 305config GENERIC_BUG 306 def_bool y 307 depends on BUG 308 309config PGTABLE_LEVELS 310 int 311 default 3 if ARM_LPAE 312 default 2 313 314menu "System Type" 315 316config MMU 317 bool "MMU-based Paged Memory Management Support" 318 default y 319 help 320 Select if you want MMU-based virtualised addressing space 321 support by paged memory management. If unsure, say 'Y'. 322 323config ARM_SINGLE_ARMV7M 324 def_bool !MMU 325 select ARM_NVIC 326 select CPU_V7M 327 select NO_IOPORT_MAP 328 329config ARCH_MMAP_RND_BITS_MIN 330 default 8 331 332config ARCH_MMAP_RND_BITS_MAX 333 default 14 if PAGE_OFFSET=0x40000000 334 default 15 if PAGE_OFFSET=0x80000000 335 default 16 336 337config ARCH_MULTIPLATFORM 338 bool "Require kernel to be portable to multiple machines" if EXPERT 339 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 340 default y 341 help 342 In general, all Arm machines can be supported in a single 343 kernel image, covering either Armv4/v5 or Armv6/v7. 344 345 However, some configuration options require hardcoding machine 346 specific physical addresses or enable errata workarounds that may 347 break other machines. 348 349 Selecting N here allows using those options, including 350 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 351 352source "arch/arm/Kconfig.platforms" 353 354# 355# This is sorted alphabetically by mach-* pathname. However, plat-* 356# Kconfigs may be included either alphabetically (according to the 357# plat- suffix) or along side the corresponding mach-* source. 358# 359source "arch/arm/mach-actions/Kconfig" 360 361source "arch/arm/mach-alpine/Kconfig" 362 363source "arch/arm/mach-artpec/Kconfig" 364 365source "arch/arm/mach-aspeed/Kconfig" 366 367source "arch/arm/mach-at91/Kconfig" 368 369source "arch/arm/mach-axxia/Kconfig" 370 371source "arch/arm/mach-bcm/Kconfig" 372 373source "arch/arm/mach-berlin/Kconfig" 374 375source "arch/arm/mach-clps711x/Kconfig" 376 377source "arch/arm/mach-davinci/Kconfig" 378 379source "arch/arm/mach-digicolor/Kconfig" 380 381source "arch/arm/mach-dove/Kconfig" 382 383source "arch/arm/mach-ep93xx/Kconfig" 384 385source "arch/arm/mach-exynos/Kconfig" 386 387source "arch/arm/mach-footbridge/Kconfig" 388 389source "arch/arm/mach-gemini/Kconfig" 390 391source "arch/arm/mach-highbank/Kconfig" 392 393source "arch/arm/mach-hisi/Kconfig" 394 395source "arch/arm/mach-hpe/Kconfig" 396 397source "arch/arm/mach-imx/Kconfig" 398 399source "arch/arm/mach-ixp4xx/Kconfig" 400 401source "arch/arm/mach-keystone/Kconfig" 402 403source "arch/arm/mach-lpc32xx/Kconfig" 404 405source "arch/arm/mach-mediatek/Kconfig" 406 407source "arch/arm/mach-meson/Kconfig" 408 409source "arch/arm/mach-milbeaut/Kconfig" 410 411source "arch/arm/mach-mmp/Kconfig" 412 413source "arch/arm/mach-mstar/Kconfig" 414 415source "arch/arm/mach-mv78xx0/Kconfig" 416 417source "arch/arm/mach-mvebu/Kconfig" 418 419source "arch/arm/mach-mxs/Kconfig" 420 421source "arch/arm/mach-nomadik/Kconfig" 422 423source "arch/arm/mach-npcm/Kconfig" 424 425source "arch/arm/mach-omap1/Kconfig" 426 427source "arch/arm/mach-omap2/Kconfig" 428 429source "arch/arm/mach-orion5x/Kconfig" 430 431source "arch/arm/mach-pxa/Kconfig" 432 433source "arch/arm/mach-qcom/Kconfig" 434 435source "arch/arm/mach-realtek/Kconfig" 436 437source "arch/arm/mach-rpc/Kconfig" 438 439source "arch/arm/mach-rockchip/Kconfig" 440 441source "arch/arm/mach-s3c/Kconfig" 442 443source "arch/arm/mach-s5pv210/Kconfig" 444 445source "arch/arm/mach-sa1100/Kconfig" 446 447source "arch/arm/mach-shmobile/Kconfig" 448 449source "arch/arm/mach-socfpga/Kconfig" 450 451source "arch/arm/mach-spear/Kconfig" 452 453source "arch/arm/mach-sti/Kconfig" 454 455source "arch/arm/mach-stm32/Kconfig" 456 457source "arch/arm/mach-sunxi/Kconfig" 458 459source "arch/arm/mach-tegra/Kconfig" 460 461source "arch/arm/mach-ux500/Kconfig" 462 463source "arch/arm/mach-versatile/Kconfig" 464 465source "arch/arm/mach-vt8500/Kconfig" 466 467source "arch/arm/mach-zynq/Kconfig" 468 469# ARMv7-M architecture 470config ARCH_LPC18XX 471 bool "NXP LPC18xx/LPC43xx" 472 depends on ARM_SINGLE_ARMV7M 473 select ARCH_HAS_RESET_CONTROLLER 474 select ARM_AMBA 475 select CLKSRC_LPC32XX 476 select PINCTRL 477 help 478 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 479 high performance microcontrollers. 480 481config ARCH_MPS2 482 bool "ARM MPS2 platform" 483 depends on ARM_SINGLE_ARMV7M 484 select ARM_AMBA 485 select CLKSRC_MPS2 486 help 487 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 488 with a range of available cores like Cortex-M3/M4/M7. 489 490 Please, note that depends which Application Note is used memory map 491 for the platform may vary, so adjustment of RAM base might be needed. 492 493# Definitions to make life easier 494config ARCH_ACORN 495 bool 496 497config PLAT_ORION 498 bool 499 select CLKSRC_MMIO 500 select GENERIC_IRQ_CHIP 501 select IRQ_DOMAIN 502 503config PLAT_ORION_LEGACY 504 bool 505 select PLAT_ORION 506 507config PLAT_VERSATILE 508 bool 509 510source "arch/arm/mm/Kconfig" 511 512config IWMMXT 513 bool "Enable iWMMXt support" 514 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 515 default y if PXA27x || PXA3xx || ARCH_MMP 516 help 517 Enable support for iWMMXt context switching at run time if 518 running on a CPU that supports it. 519 520if !MMU 521source "arch/arm/Kconfig-nommu" 522endif 523 524config PJ4B_ERRATA_4742 525 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 526 depends on CPU_PJ4B && MACH_ARMADA_370 527 default y 528 help 529 When coming out of either a Wait for Interrupt (WFI) or a Wait for 530 Event (WFE) IDLE states, a specific timing sensitivity exists between 531 the retiring WFI/WFE instructions and the newly issued subsequent 532 instructions. This sensitivity can result in a CPU hang scenario. 533 Workaround: 534 The software must insert either a Data Synchronization Barrier (DSB) 535 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 536 instruction 537 538config ARM_ERRATA_326103 539 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 540 depends on CPU_V6 541 help 542 Executing a SWP instruction to read-only memory does not set bit 11 543 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 544 treat the access as a read, preventing a COW from occurring and 545 causing the faulting task to livelock. 546 547config ARM_ERRATA_411920 548 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 549 depends on CPU_V6 || CPU_V6K 550 help 551 Invalidation of the Instruction Cache operation can 552 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 553 It does not affect the MPCore. This option enables the ARM Ltd. 554 recommended workaround. 555 556config ARM_ERRATA_430973 557 bool "ARM errata: Stale prediction on replaced interworking branch" 558 depends on CPU_V7 559 help 560 This option enables the workaround for the 430973 Cortex-A8 561 r1p* erratum. If a code sequence containing an ARM/Thumb 562 interworking branch is replaced with another code sequence at the 563 same virtual address, whether due to self-modifying code or virtual 564 to physical address re-mapping, Cortex-A8 does not recover from the 565 stale interworking branch prediction. This results in Cortex-A8 566 executing the new code sequence in the incorrect ARM or Thumb state. 567 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 568 and also flushes the branch target cache at every context switch. 569 Note that setting specific bits in the ACTLR register may not be 570 available in non-secure mode. 571 572config ARM_ERRATA_458693 573 bool "ARM errata: Processor deadlock when a false hazard is created" 574 depends on CPU_V7 575 depends on !ARCH_MULTIPLATFORM 576 help 577 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 578 erratum. For very specific sequences of memory operations, it is 579 possible for a hazard condition intended for a cache line to instead 580 be incorrectly associated with a different cache line. This false 581 hazard might then cause a processor deadlock. The workaround enables 582 the L1 caching of the NEON accesses and disables the PLD instruction 583 in the ACTLR register. Note that setting specific bits in the ACTLR 584 register may not be available in non-secure mode and thus is not 585 available on a multiplatform kernel. This should be applied by the 586 bootloader instead. 587 588config ARM_ERRATA_460075 589 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 590 depends on CPU_V7 591 depends on !ARCH_MULTIPLATFORM 592 help 593 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 594 erratum. Any asynchronous access to the L2 cache may encounter a 595 situation in which recent store transactions to the L2 cache are lost 596 and overwritten with stale memory contents from external memory. The 597 workaround disables the write-allocate mode for the L2 cache via the 598 ACTLR register. Note that setting specific bits in the ACTLR register 599 may not be available in non-secure mode and thus is not available on 600 a multiplatform kernel. This should be applied by the bootloader 601 instead. 602 603config ARM_ERRATA_742230 604 bool "ARM errata: DMB operation may be faulty" 605 depends on CPU_V7 && SMP 606 depends on !ARCH_MULTIPLATFORM 607 help 608 This option enables the workaround for the 742230 Cortex-A9 609 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 610 between two write operations may not ensure the correct visibility 611 ordering of the two writes. This workaround sets a specific bit in 612 the diagnostic register of the Cortex-A9 which causes the DMB 613 instruction to behave as a DSB, ensuring the correct behaviour of 614 the two writes. Note that setting specific bits in the diagnostics 615 register may not be available in non-secure mode and thus is not 616 available on a multiplatform kernel. This should be applied by the 617 bootloader instead. 618 619config ARM_ERRATA_742231 620 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 621 depends on CPU_V7 && SMP 622 depends on !ARCH_MULTIPLATFORM 623 help 624 This option enables the workaround for the 742231 Cortex-A9 625 (r2p0..r2p2) erratum. Under certain conditions, specific to the 626 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 627 accessing some data located in the same cache line, may get corrupted 628 data due to bad handling of the address hazard when the line gets 629 replaced from one of the CPUs at the same time as another CPU is 630 accessing it. This workaround sets specific bits in the diagnostic 631 register of the Cortex-A9 which reduces the linefill issuing 632 capabilities of the processor. Note that setting specific bits in the 633 diagnostics register may not be available in non-secure mode and thus 634 is not available on a multiplatform kernel. This should be applied by 635 the bootloader instead. 636 637config ARM_ERRATA_643719 638 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 639 depends on CPU_V7 && SMP 640 default y 641 help 642 This option enables the workaround for the 643719 Cortex-A9 (prior to 643 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 644 register returns zero when it should return one. The workaround 645 corrects this value, ensuring cache maintenance operations which use 646 it behave as intended and avoiding data corruption. 647 648config ARM_ERRATA_720789 649 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 650 depends on CPU_V7 651 help 652 This option enables the workaround for the 720789 Cortex-A9 (prior to 653 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 654 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 655 As a consequence of this erratum, some TLB entries which should be 656 invalidated are not, resulting in an incoherency in the system page 657 tables. The workaround changes the TLB flushing routines to invalidate 658 entries regardless of the ASID. 659 660config ARM_ERRATA_743622 661 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 662 depends on CPU_V7 663 depends on !ARCH_MULTIPLATFORM 664 help 665 This option enables the workaround for the 743622 Cortex-A9 666 (r2p*) erratum. Under very rare conditions, a faulty 667 optimisation in the Cortex-A9 Store Buffer may lead to data 668 corruption. This workaround sets a specific bit in the diagnostic 669 register of the Cortex-A9 which disables the Store Buffer 670 optimisation, preventing the defect from occurring. This has no 671 visible impact on the overall performance or power consumption of the 672 processor. Note that setting specific bits in the diagnostics register 673 may not be available in non-secure mode and thus is not available on a 674 multiplatform kernel. This should be applied by the bootloader instead. 675 676config ARM_ERRATA_751472 677 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 678 depends on CPU_V7 679 depends on !ARCH_MULTIPLATFORM 680 help 681 This option enables the workaround for the 751472 Cortex-A9 (prior 682 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 683 completion of a following broadcasted operation if the second 684 operation is received by a CPU before the ICIALLUIS has completed, 685 potentially leading to corrupted entries in the cache or TLB. 686 Note that setting specific bits in the diagnostics register may 687 not be available in non-secure mode and thus is not available on 688 a multiplatform kernel. This should be applied by the bootloader 689 instead. 690 691config ARM_ERRATA_754322 692 bool "ARM errata: possible faulty MMU translations following an ASID switch" 693 depends on CPU_V7 694 help 695 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 696 r3p*) erratum. A speculative memory access may cause a page table walk 697 which starts prior to an ASID switch but completes afterwards. This 698 can populate the micro-TLB with a stale entry which may be hit with 699 the new ASID. This workaround places two dsb instructions in the mm 700 switching code so that no page table walks can cross the ASID switch. 701 702config ARM_ERRATA_754327 703 bool "ARM errata: no automatic Store Buffer drain" 704 depends on CPU_V7 && SMP 705 help 706 This option enables the workaround for the 754327 Cortex-A9 (prior to 707 r2p0) erratum. The Store Buffer does not have any automatic draining 708 mechanism and therefore a livelock may occur if an external agent 709 continuously polls a memory location waiting to observe an update. 710 This workaround defines cpu_relax() as smp_mb(), preventing correctly 711 written polling loops from denying visibility of updates to memory. 712 713config ARM_ERRATA_364296 714 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 715 depends on CPU_V6 716 help 717 This options enables the workaround for the 364296 ARM1136 718 r0p2 erratum (possible cache data corruption with 719 hit-under-miss enabled). It sets the undocumented bit 31 in 720 the auxiliary control register and the FI bit in the control 721 register, thus disabling hit-under-miss without putting the 722 processor into full low interrupt latency mode. ARM11MPCore 723 is not affected. 724 725config ARM_ERRATA_764369 726 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 727 depends on CPU_V7 && SMP 728 help 729 This option enables the workaround for erratum 764369 730 affecting Cortex-A9 MPCore with two or more processors (all 731 current revisions). Under certain timing circumstances, a data 732 cache line maintenance operation by MVA targeting an Inner 733 Shareable memory region may fail to proceed up to either the 734 Point of Coherency or to the Point of Unification of the 735 system. This workaround adds a DSB instruction before the 736 relevant cache maintenance functions and sets a specific bit 737 in the diagnostic control register of the SCU. 738 739config ARM_ERRATA_764319 740 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 741 depends on CPU_V7 742 help 743 This option enables the workaround for the 764319 Cortex-A9 erratum. 744 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 745 unexpected Undefined Instruction exception when the DBGSWENABLE 746 external pin is set to 0, even when the CP14 accesses are performed 747 from a privileged mode. This work around catches the exception in a 748 way the kernel does not stop execution. 749 750config ARM_ERRATA_775420 751 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 752 depends on CPU_V7 753 help 754 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 755 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 756 operation aborts with MMU exception, it might cause the processor 757 to deadlock. This workaround puts DSB before executing ISB if 758 an abort may occur on cache maintenance. 759 760config ARM_ERRATA_798181 761 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 762 depends on CPU_V7 && SMP 763 help 764 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 765 adequately shooting down all use of the old entries. This 766 option enables the Linux kernel workaround for this erratum 767 which sends an IPI to the CPUs that are running the same ASID 768 as the one being invalidated. 769 770config ARM_ERRATA_773022 771 bool "ARM errata: incorrect instructions may be executed from loop buffer" 772 depends on CPU_V7 773 help 774 This option enables the workaround for the 773022 Cortex-A15 775 (up to r0p4) erratum. In certain rare sequences of code, the 776 loop buffer may deliver incorrect instructions. This 777 workaround disables the loop buffer to avoid the erratum. 778 779config ARM_ERRATA_818325_852422 780 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 781 depends on CPU_V7 782 help 783 This option enables the workaround for: 784 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 785 instruction might deadlock. Fixed in r0p1. 786 - Cortex-A12 852422: Execution of a sequence of instructions might 787 lead to either a data corruption or a CPU deadlock. Not fixed in 788 any Cortex-A12 cores yet. 789 This workaround for all both errata involves setting bit[12] of the 790 Feature Register. This bit disables an optimisation applied to a 791 sequence of 2 instructions that use opposing condition codes. 792 793config ARM_ERRATA_821420 794 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 795 depends on CPU_V7 796 help 797 This option enables the workaround for the 821420 Cortex-A12 798 (all revs) erratum. In very rare timing conditions, a sequence 799 of VMOV to Core registers instructions, for which the second 800 one is in the shadow of a branch or abort, can lead to a 801 deadlock when the VMOV instructions are issued out-of-order. 802 803config ARM_ERRATA_825619 804 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 805 depends on CPU_V7 806 help 807 This option enables the workaround for the 825619 Cortex-A12 808 (all revs) erratum. Within rare timing constraints, executing a 809 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 810 and Device/Strongly-Ordered loads and stores might cause deadlock 811 812config ARM_ERRATA_857271 813 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 814 depends on CPU_V7 815 help 816 This option enables the workaround for the 857271 Cortex-A12 817 (all revs) erratum. Under very rare timing conditions, the CPU might 818 hang. The workaround is expected to have a < 1% performance impact. 819 820config ARM_ERRATA_852421 821 bool "ARM errata: A17: DMB ST might fail to create order between stores" 822 depends on CPU_V7 823 help 824 This option enables the workaround for the 852421 Cortex-A17 825 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 826 execution of a DMB ST instruction might fail to properly order 827 stores from GroupA and stores from GroupB. 828 829config ARM_ERRATA_852423 830 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 831 depends on CPU_V7 832 help 833 This option enables the workaround for: 834 - Cortex-A17 852423: Execution of a sequence of instructions might 835 lead to either a data corruption or a CPU deadlock. Not fixed in 836 any Cortex-A17 cores yet. 837 This is identical to Cortex-A12 erratum 852422. It is a separate 838 config option from the A12 erratum due to the way errata are checked 839 for and handled. 840 841config ARM_ERRATA_857272 842 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 843 depends on CPU_V7 844 help 845 This option enables the workaround for the 857272 Cortex-A17 erratum. 846 This erratum is not known to be fixed in any A17 revision. 847 This is identical to Cortex-A12 erratum 857271. It is a separate 848 config option from the A12 erratum due to the way errata are checked 849 for and handled. 850 851endmenu 852 853source "arch/arm/common/Kconfig" 854 855menu "Bus support" 856 857config ISA 858 bool 859 help 860 Find out whether you have ISA slots on your motherboard. ISA is the 861 name of a bus system, i.e. the way the CPU talks to the other stuff 862 inside your box. Other bus systems are PCI, EISA, MicroChannel 863 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 864 newer boards don't support it. If you have ISA, say Y, otherwise N. 865 866# Select ISA DMA interface 867config ISA_DMA_API 868 bool 869 870config ARM_ERRATA_814220 871 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 872 depends on CPU_V7 873 help 874 The v7 ARM states that all cache and branch predictor maintenance 875 operations that do not specify an address execute, relative to 876 each other, in program order. 877 However, because of this erratum, an L2 set/way cache maintenance 878 operation can overtake an L1 set/way cache maintenance operation. 879 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 880 r0p4, r0p5. 881 882endmenu 883 884menu "Kernel Features" 885 886config HAVE_SMP 887 bool 888 help 889 This option should be selected by machines which have an SMP- 890 capable CPU. 891 892 The only effect of this option is to make the SMP-related 893 options available to the user for configuration. 894 895config SMP 896 bool "Symmetric Multi-Processing" 897 depends on CPU_V6K || CPU_V7 898 depends on HAVE_SMP 899 depends on MMU || ARM_MPU 900 select IRQ_WORK 901 help 902 This enables support for systems with more than one CPU. If you have 903 a system with only one CPU, say N. If you have a system with more 904 than one CPU, say Y. 905 906 If you say N here, the kernel will run on uni- and multiprocessor 907 machines, but will use only one CPU of a multiprocessor machine. If 908 you say Y here, the kernel will run on many, but not all, 909 uniprocessor machines. On a uniprocessor machine, the kernel 910 will run faster if you say N here. 911 912 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 913 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 914 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 915 916 If you don't know what to do here, say N. 917 918config SMP_ON_UP 919 bool "Allow booting SMP kernel on uniprocessor systems" 920 depends on SMP && MMU 921 default y 922 help 923 SMP kernels contain instructions which fail on non-SMP processors. 924 Enabling this option allows the kernel to modify itself to make 925 these instructions safe. Disabling it allows about 1K of space 926 savings. 927 928 If you don't know what to do here, say Y. 929 930 931config CURRENT_POINTER_IN_TPIDRURO 932 def_bool y 933 depends on CPU_32v6K && !CPU_V6 934 935config IRQSTACKS 936 def_bool y 937 select HAVE_IRQ_EXIT_ON_IRQ_STACK 938 select HAVE_SOFTIRQ_ON_OWN_STACK 939 940config ARM_CPU_TOPOLOGY 941 bool "Support cpu topology definition" 942 depends on SMP && CPU_V7 943 default y 944 help 945 Support ARM cpu topology definition. The MPIDR register defines 946 affinity between processors which is then used to describe the cpu 947 topology of an ARM System. 948 949config SCHED_MC 950 bool "Multi-core scheduler support" 951 depends on ARM_CPU_TOPOLOGY 952 help 953 Multi-core scheduler support improves the CPU scheduler's decision 954 making when dealing with multi-core CPU chips at a cost of slightly 955 increased overhead in some places. If unsure say N here. 956 957config SCHED_SMT 958 bool "SMT scheduler support" 959 depends on ARM_CPU_TOPOLOGY 960 help 961 Improves the CPU scheduler's decision making when dealing with 962 MultiThreading at a cost of slightly increased overhead in some 963 places. If unsure say N here. 964 965config HAVE_ARM_SCU 966 bool 967 help 968 This option enables support for the ARM snoop control unit 969 970config HAVE_ARM_ARCH_TIMER 971 bool "Architected timer support" 972 depends on CPU_V7 973 select ARM_ARCH_TIMER 974 help 975 This option enables support for the ARM architected timer 976 977config HAVE_ARM_TWD 978 bool 979 help 980 This options enables support for the ARM timer and watchdog unit 981 982config MCPM 983 bool "Multi-Cluster Power Management" 984 depends on CPU_V7 && SMP 985 help 986 This option provides the common power management infrastructure 987 for (multi-)cluster based systems, such as big.LITTLE based 988 systems. 989 990config MCPM_QUAD_CLUSTER 991 bool 992 depends on MCPM 993 help 994 To avoid wasting resources unnecessarily, MCPM only supports up 995 to 2 clusters by default. 996 Platforms with 3 or 4 clusters that use MCPM must select this 997 option to allow the additional clusters to be managed. 998 999config BIG_LITTLE 1000 bool "big.LITTLE support (Experimental)" 1001 depends on CPU_V7 && SMP 1002 select MCPM 1003 help 1004 This option enables support selections for the big.LITTLE 1005 system architecture. 1006 1007config BL_SWITCHER 1008 bool "big.LITTLE switcher support" 1009 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1010 select CPU_PM 1011 help 1012 The big.LITTLE "switcher" provides the core functionality to 1013 transparently handle transition between a cluster of A15's 1014 and a cluster of A7's in a big.LITTLE system. 1015 1016config BL_SWITCHER_DUMMY_IF 1017 tristate "Simple big.LITTLE switcher user interface" 1018 depends on BL_SWITCHER && DEBUG_KERNEL 1019 help 1020 This is a simple and dummy char dev interface to control 1021 the big.LITTLE switcher core code. It is meant for 1022 debugging purposes only. 1023 1024choice 1025 prompt "Memory split" 1026 depends on MMU 1027 default VMSPLIT_3G 1028 help 1029 Select the desired split between kernel and user memory. 1030 1031 If you are not absolutely sure what you are doing, leave this 1032 option alone! 1033 1034 config VMSPLIT_3G 1035 bool "3G/1G user/kernel split" 1036 config VMSPLIT_3G_OPT 1037 depends on !ARM_LPAE 1038 bool "3G/1G user/kernel split (for full 1G low memory)" 1039 config VMSPLIT_2G 1040 bool "2G/2G user/kernel split" 1041 config VMSPLIT_1G 1042 bool "1G/3G user/kernel split" 1043endchoice 1044 1045config PAGE_OFFSET 1046 hex 1047 default PHYS_OFFSET if !MMU 1048 default 0x40000000 if VMSPLIT_1G 1049 default 0x80000000 if VMSPLIT_2G 1050 default 0xB0000000 if VMSPLIT_3G_OPT 1051 default 0xC0000000 1052 1053config KASAN_SHADOW_OFFSET 1054 hex 1055 depends on KASAN 1056 default 0x1f000000 if PAGE_OFFSET=0x40000000 1057 default 0x5f000000 if PAGE_OFFSET=0x80000000 1058 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1059 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1060 default 0xffffffff 1061 1062config NR_CPUS 1063 int "Maximum number of CPUs (2-32)" 1064 range 2 16 if DEBUG_KMAP_LOCAL 1065 range 2 32 if !DEBUG_KMAP_LOCAL 1066 depends on SMP 1067 default "4" 1068 help 1069 The maximum number of CPUs that the kernel can support. 1070 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1071 debugging is enabled, which uses half of the per-CPU fixmap 1072 slots as guard regions. 1073 1074config HOTPLUG_CPU 1075 bool "Support for hot-pluggable CPUs" 1076 depends on SMP 1077 select GENERIC_IRQ_MIGRATION 1078 help 1079 Say Y here to experiment with turning CPUs off and on. CPUs 1080 can be controlled through /sys/devices/system/cpu. 1081 1082config ARM_PSCI 1083 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1084 depends on HAVE_ARM_SMCCC 1085 select ARM_PSCI_FW 1086 help 1087 Say Y here if you want Linux to communicate with system firmware 1088 implementing the PSCI specification for CPU-centric power 1089 management operations described in ARM document number ARM DEN 1090 0022A ("Power State Coordination Interface System Software on 1091 ARM processors"). 1092 1093config HZ_FIXED 1094 int 1095 default 128 if SOC_AT91RM9200 1096 default 0 1097 1098choice 1099 depends on HZ_FIXED = 0 1100 prompt "Timer frequency" 1101 1102config HZ_100 1103 bool "100 Hz" 1104 1105config HZ_200 1106 bool "200 Hz" 1107 1108config HZ_250 1109 bool "250 Hz" 1110 1111config HZ_300 1112 bool "300 Hz" 1113 1114config HZ_500 1115 bool "500 Hz" 1116 1117config HZ_1000 1118 bool "1000 Hz" 1119 1120endchoice 1121 1122config HZ 1123 int 1124 default HZ_FIXED if HZ_FIXED != 0 1125 default 100 if HZ_100 1126 default 200 if HZ_200 1127 default 250 if HZ_250 1128 default 300 if HZ_300 1129 default 500 if HZ_500 1130 default 1000 1131 1132config SCHED_HRTICK 1133 def_bool HIGH_RES_TIMERS 1134 1135config THUMB2_KERNEL 1136 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1137 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1138 default y if CPU_THUMBONLY 1139 select ARM_UNWIND 1140 help 1141 By enabling this option, the kernel will be compiled in 1142 Thumb-2 mode. 1143 1144 If unsure, say N. 1145 1146config ARM_PATCH_IDIV 1147 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1148 depends on CPU_32v7 1149 default y 1150 help 1151 The ARM compiler inserts calls to __aeabi_idiv() and 1152 __aeabi_uidiv() when it needs to perform division on signed 1153 and unsigned integers. Some v7 CPUs have support for the sdiv 1154 and udiv instructions that can be used to implement those 1155 functions. 1156 1157 Enabling this option allows the kernel to modify itself to 1158 replace the first two instructions of these library functions 1159 with the sdiv or udiv plus "bx lr" instructions when the CPU 1160 it is running on supports them. Typically this will be faster 1161 and less power intensive than running the original library 1162 code to do integer division. 1163 1164config AEABI 1165 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1166 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1167 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1168 help 1169 This option allows for the kernel to be compiled using the latest 1170 ARM ABI (aka EABI). This is only useful if you are using a user 1171 space environment that is also compiled with EABI. 1172 1173 Since there are major incompatibilities between the legacy ABI and 1174 EABI, especially with regard to structure member alignment, this 1175 option also changes the kernel syscall calling convention to 1176 disambiguate both ABIs and allow for backward compatibility support 1177 (selected with CONFIG_OABI_COMPAT). 1178 1179 To use this you need GCC version 4.0.0 or later. 1180 1181config OABI_COMPAT 1182 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1183 depends on AEABI && !THUMB2_KERNEL 1184 help 1185 This option preserves the old syscall interface along with the 1186 new (ARM EABI) one. It also provides a compatibility layer to 1187 intercept syscalls that have structure arguments which layout 1188 in memory differs between the legacy ABI and the new ARM EABI 1189 (only for non "thumb" binaries). This option adds a tiny 1190 overhead to all syscalls and produces a slightly larger kernel. 1191 1192 The seccomp filter system will not be available when this is 1193 selected, since there is no way yet to sensibly distinguish 1194 between calling conventions during filtering. 1195 1196 If you know you'll be using only pure EABI user space then you 1197 can say N here. If this option is not selected and you attempt 1198 to execute a legacy ABI binary then the result will be 1199 UNPREDICTABLE (in fact it can be predicted that it won't work 1200 at all). If in doubt say N. 1201 1202config ARCH_SELECT_MEMORY_MODEL 1203 def_bool y 1204 1205config ARCH_FLATMEM_ENABLE 1206 def_bool !(ARCH_RPC || ARCH_SA1100) 1207 1208config ARCH_SPARSEMEM_ENABLE 1209 def_bool !ARCH_FOOTBRIDGE 1210 select SPARSEMEM_STATIC if SPARSEMEM 1211 1212config HIGHMEM 1213 bool "High Memory Support" 1214 depends on MMU 1215 select KMAP_LOCAL 1216 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1217 help 1218 The address space of ARM processors is only 4 Gigabytes large 1219 and it has to accommodate user address space, kernel address 1220 space as well as some memory mapped IO. That means that, if you 1221 have a large amount of physical memory and/or IO, not all of the 1222 memory can be "permanently mapped" by the kernel. The physical 1223 memory that is not permanently mapped is called "high memory". 1224 1225 Depending on the selected kernel/user memory split, minimum 1226 vmalloc space and actual amount of RAM, you may not need this 1227 option which should result in a slightly faster kernel. 1228 1229 If unsure, say n. 1230 1231config HIGHPTE 1232 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1233 depends on HIGHMEM 1234 default y 1235 help 1236 The VM uses one page of physical memory for each page table. 1237 For systems with a lot of processes, this can use a lot of 1238 precious low memory, eventually leading to low memory being 1239 consumed by page tables. Setting this option will allow 1240 user-space 2nd level page tables to reside in high memory. 1241 1242config ARM_PAN 1243 bool "Enable privileged no-access" 1244 depends on MMU 1245 default y 1246 help 1247 Increase kernel security by ensuring that normal kernel accesses 1248 are unable to access userspace addresses. This can help prevent 1249 use-after-free bugs becoming an exploitable privilege escalation 1250 by ensuring that magic values (such as LIST_POISON) will always 1251 fault when dereferenced. 1252 1253 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1254 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1255 1256config CPU_SW_DOMAIN_PAN 1257 def_bool y 1258 depends on ARM_PAN && !ARM_LPAE 1259 help 1260 Enable use of CPU domains to implement privileged no-access. 1261 1262 CPUs with low-vector mappings use a best-efforts implementation. 1263 Their lower 1MB needs to remain accessible for the vectors, but 1264 the remainder of userspace will become appropriately inaccessible. 1265 1266config CPU_TTBR0_PAN 1267 def_bool y 1268 depends on ARM_PAN && ARM_LPAE 1269 help 1270 Enable privileged no-access by disabling TTBR0 page table walks when 1271 running in kernel mode. 1272 1273config HW_PERF_EVENTS 1274 def_bool y 1275 depends on ARM_PMU 1276 1277config ARM_MODULE_PLTS 1278 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1279 depends on MODULES 1280 select KASAN_VMALLOC if KASAN 1281 default y 1282 help 1283 Allocate PLTs when loading modules so that jumps and calls whose 1284 targets are too far away for their relative offsets to be encoded 1285 in the instructions themselves can be bounced via veneers in the 1286 module's PLT. This allows modules to be allocated in the generic 1287 vmalloc area after the dedicated module memory area has been 1288 exhausted. The modules will use slightly more memory, but after 1289 rounding up to page size, the actual memory footprint is usually 1290 the same. 1291 1292 Disabling this is usually safe for small single-platform 1293 configurations. If unsure, say y. 1294 1295config ARCH_FORCE_MAX_ORDER 1296 int "Order of maximal physically contiguous allocations" 1297 default "11" if SOC_AM33XX 1298 default "8" if SA1111 1299 default "10" 1300 help 1301 The kernel page allocator limits the size of maximal physically 1302 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1303 defines the maximal power of two of number of pages that can be 1304 allocated as a single contiguous block. This option allows 1305 overriding the default setting when ability to allocate very 1306 large blocks of physically contiguous memory is required. 1307 1308 Don't change if unsure. 1309 1310config ALIGNMENT_TRAP 1311 def_bool CPU_CP15_MMU 1312 select HAVE_PROC_CPU if PROC_FS 1313 help 1314 ARM processors cannot fetch/store information which is not 1315 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1316 address divisible by 4. On 32-bit ARM processors, these non-aligned 1317 fetch/store instructions will be emulated in software if you say 1318 here, which has a severe performance impact. This is necessary for 1319 correct operation of some network protocols. With an IP-only 1320 configuration it is safe to say N, otherwise say Y. 1321 1322config UACCESS_WITH_MEMCPY 1323 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1324 depends on MMU 1325 default y if CPU_FEROCEON 1326 help 1327 Implement faster copy_to_user and clear_user methods for CPU 1328 cores where a 8-word STM instruction give significantly higher 1329 memory write throughput than a sequence of individual 32bit stores. 1330 1331 A possible side effect is a slight increase in scheduling latency 1332 between threads sharing the same address space if they invoke 1333 such copy operations with large buffers. 1334 1335 However, if the CPU data cache is using a write-allocate mode, 1336 this option is unlikely to provide any performance gain. 1337 1338config PARAVIRT 1339 bool "Enable paravirtualization code" 1340 help 1341 This changes the kernel so it can modify itself when it is run 1342 under a hypervisor, potentially improving performance significantly 1343 over full virtualization. 1344 1345config PARAVIRT_TIME_ACCOUNTING 1346 bool "Paravirtual steal time accounting" 1347 select PARAVIRT 1348 help 1349 Select this option to enable fine granularity task steal time 1350 accounting. Time spent executing other tasks in parallel with 1351 the current vCPU is discounted from the vCPU power. To account for 1352 that, there can be a small performance impact. 1353 1354 If in doubt, say N here. 1355 1356config XEN_DOM0 1357 def_bool y 1358 depends on XEN 1359 1360config XEN 1361 bool "Xen guest support on ARM" 1362 depends on ARM && AEABI && OF 1363 depends on CPU_V7 && !CPU_V6 1364 depends on !GENERIC_ATOMIC64 1365 depends on MMU 1366 select ARCH_DMA_ADDR_T_64BIT 1367 select ARM_PSCI 1368 select SWIOTLB 1369 select SWIOTLB_XEN 1370 select PARAVIRT 1371 help 1372 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1373 1374config CC_HAVE_STACKPROTECTOR_TLS 1375 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1376 1377config STACKPROTECTOR_PER_TASK 1378 bool "Use a unique stack canary value for each task" 1379 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1380 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1381 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1382 default y 1383 help 1384 Due to the fact that GCC uses an ordinary symbol reference from 1385 which to load the value of the stack canary, this value can only 1386 change at reboot time on SMP systems, and all tasks running in the 1387 kernel's address space are forced to use the same canary value for 1388 the entire duration that the system is up. 1389 1390 Enable this option to switch to a different method that uses a 1391 different canary value for each task. 1392 1393endmenu 1394 1395menu "Boot options" 1396 1397config USE_OF 1398 bool "Flattened Device Tree support" 1399 select IRQ_DOMAIN 1400 select OF 1401 help 1402 Include support for flattened device tree machine descriptions. 1403 1404config ARCH_WANT_FLAT_DTB_INSTALL 1405 def_bool y 1406 1407config ATAGS 1408 bool "Support for the traditional ATAGS boot data passing" 1409 default y 1410 help 1411 This is the traditional way of passing data to the kernel at boot 1412 time. If you are solely relying on the flattened device tree (or 1413 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1414 to remove ATAGS support from your kernel binary. 1415 1416config DEPRECATED_PARAM_STRUCT 1417 bool "Provide old way to pass kernel parameters" 1418 depends on ATAGS 1419 help 1420 This was deprecated in 2001 and announced to live on for 5 years. 1421 Some old boot loaders still use this way. 1422 1423# Compressed boot loader in ROM. Yes, we really want to ask about 1424# TEXT and BSS so we preserve their values in the config files. 1425config ZBOOT_ROM_TEXT 1426 hex "Compressed ROM boot loader base address" 1427 default 0x0 1428 help 1429 The physical address at which the ROM-able zImage is to be 1430 placed in the target. Platforms which normally make use of 1431 ROM-able zImage formats normally set this to a suitable 1432 value in their defconfig file. 1433 1434 If ZBOOT_ROM is not enabled, this has no effect. 1435 1436config ZBOOT_ROM_BSS 1437 hex "Compressed ROM boot loader BSS address" 1438 default 0x0 1439 help 1440 The base address of an area of read/write memory in the target 1441 for the ROM-able zImage which must be available while the 1442 decompressor is running. It must be large enough to hold the 1443 entire decompressed kernel plus an additional 128 KiB. 1444 Platforms which normally make use of ROM-able zImage formats 1445 normally set this to a suitable value in their defconfig file. 1446 1447 If ZBOOT_ROM is not enabled, this has no effect. 1448 1449config ZBOOT_ROM 1450 bool "Compressed boot loader in ROM/flash" 1451 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1452 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1453 help 1454 Say Y here if you intend to execute your compressed kernel image 1455 (zImage) directly from ROM or flash. If unsure, say N. 1456 1457config ARM_APPENDED_DTB 1458 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1459 depends on OF 1460 help 1461 With this option, the boot code will look for a device tree binary 1462 (DTB) appended to zImage 1463 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1464 1465 This is meant as a backward compatibility convenience for those 1466 systems with a bootloader that can't be upgraded to accommodate 1467 the documented boot protocol using a device tree. 1468 1469 Beware that there is very little in terms of protection against 1470 this option being confused by leftover garbage in memory that might 1471 look like a DTB header after a reboot if no actual DTB is appended 1472 to zImage. Do not leave this option active in a production kernel 1473 if you don't intend to always append a DTB. Proper passing of the 1474 location into r2 of a bootloader provided DTB is always preferable 1475 to this option. 1476 1477config ARM_ATAG_DTB_COMPAT 1478 bool "Supplement the appended DTB with traditional ATAG information" 1479 depends on ARM_APPENDED_DTB 1480 help 1481 Some old bootloaders can't be updated to a DTB capable one, yet 1482 they provide ATAGs with memory configuration, the ramdisk address, 1483 the kernel cmdline string, etc. Such information is dynamically 1484 provided by the bootloader and can't always be stored in a static 1485 DTB. To allow a device tree enabled kernel to be used with such 1486 bootloaders, this option allows zImage to extract the information 1487 from the ATAG list and store it at run time into the appended DTB. 1488 1489choice 1490 prompt "Kernel command line type" 1491 depends on ARM_ATAG_DTB_COMPAT 1492 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1493 1494config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1495 bool "Use bootloader kernel arguments if available" 1496 help 1497 Uses the command-line options passed by the boot loader instead of 1498 the device tree bootargs property. If the boot loader doesn't provide 1499 any, the device tree bootargs property will be used. 1500 1501config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1502 bool "Extend with bootloader kernel arguments" 1503 help 1504 The command-line arguments provided by the boot loader will be 1505 appended to the the device tree bootargs property. 1506 1507endchoice 1508 1509config CMDLINE 1510 string "Default kernel command string" 1511 default "" 1512 help 1513 On some architectures (e.g. CATS), there is currently no way 1514 for the boot loader to pass arguments to the kernel. For these 1515 architectures, you should supply some command-line options at build 1516 time by entering them here. As a minimum, you should specify the 1517 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1518 1519choice 1520 prompt "Kernel command line type" 1521 depends on CMDLINE != "" 1522 default CMDLINE_FROM_BOOTLOADER 1523 1524config CMDLINE_FROM_BOOTLOADER 1525 bool "Use bootloader kernel arguments if available" 1526 help 1527 Uses the command-line options passed by the boot loader. If 1528 the boot loader doesn't provide any, the default kernel command 1529 string provided in CMDLINE will be used. 1530 1531config CMDLINE_EXTEND 1532 bool "Extend bootloader kernel arguments" 1533 help 1534 The command-line arguments provided by the boot loader will be 1535 appended to the default kernel command string. 1536 1537config CMDLINE_FORCE 1538 bool "Always use the default kernel command string" 1539 help 1540 Always use the default kernel command string, even if the boot 1541 loader passes other arguments to the kernel. 1542 This is useful if you cannot or don't want to change the 1543 command-line options your boot loader passes to the kernel. 1544endchoice 1545 1546config XIP_KERNEL 1547 bool "Kernel Execute-In-Place from ROM" 1548 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1549 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1550 help 1551 Execute-In-Place allows the kernel to run from non-volatile storage 1552 directly addressable by the CPU, such as NOR flash. This saves RAM 1553 space since the text section of the kernel is not loaded from flash 1554 to RAM. Read-write sections, such as the data section and stack, 1555 are still copied to RAM. The XIP kernel is not compressed since 1556 it has to run directly from flash, so it will take more space to 1557 store it. The flash address used to link the kernel object files, 1558 and for storing it, is configuration dependent. Therefore, if you 1559 say Y here, you must know the proper physical address where to 1560 store the kernel image depending on your own flash memory usage. 1561 1562 Also note that the make target becomes "make xipImage" rather than 1563 "make zImage" or "make Image". The final kernel binary to put in 1564 ROM memory will be arch/arm/boot/xipImage. 1565 1566 If unsure, say N. 1567 1568config XIP_PHYS_ADDR 1569 hex "XIP Kernel Physical Location" 1570 depends on XIP_KERNEL 1571 default "0x00080000" 1572 help 1573 This is the physical address in your flash memory the kernel will 1574 be linked for and stored to. This address is dependent on your 1575 own flash usage. 1576 1577config XIP_DEFLATED_DATA 1578 bool "Store kernel .data section compressed in ROM" 1579 depends on XIP_KERNEL 1580 select ZLIB_INFLATE 1581 help 1582 Before the kernel is actually executed, its .data section has to be 1583 copied to RAM from ROM. This option allows for storing that data 1584 in compressed form and decompressed to RAM rather than merely being 1585 copied, saving some precious ROM space. A possible drawback is a 1586 slightly longer boot delay. 1587 1588config ARCH_SUPPORTS_KEXEC 1589 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1590 1591config ATAGS_PROC 1592 bool "Export atags in procfs" 1593 depends on ATAGS && KEXEC 1594 default y 1595 help 1596 Should the atags used to boot the kernel be exported in an "atags" 1597 file in procfs. Useful with kexec. 1598 1599config ARCH_SUPPORTS_CRASH_DUMP 1600 def_bool y 1601 1602config ARCH_DEFAULT_CRASH_DUMP 1603 def_bool y 1604 1605config AUTO_ZRELADDR 1606 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1607 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1608 help 1609 ZRELADDR is the physical address where the decompressed kernel 1610 image will be placed. If AUTO_ZRELADDR is selected, the address 1611 will be determined at run-time, either by masking the current IP 1612 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1613 This assumes the zImage being placed in the first 128MB from 1614 start of memory. 1615 1616config EFI_STUB 1617 bool 1618 1619config EFI 1620 bool "UEFI runtime support" 1621 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1622 select UCS2_STRING 1623 select EFI_PARAMS_FROM_FDT 1624 select EFI_STUB 1625 select EFI_GENERIC_STUB 1626 select EFI_RUNTIME_WRAPPERS 1627 help 1628 This option provides support for runtime services provided 1629 by UEFI firmware (such as non-volatile variables, realtime 1630 clock, and platform reset). A UEFI stub is also provided to 1631 allow the kernel to be booted as an EFI application. This 1632 is only useful for kernels that may run on systems that have 1633 UEFI firmware. 1634 1635config DMI 1636 bool "Enable support for SMBIOS (DMI) tables" 1637 depends on EFI 1638 default y 1639 help 1640 This enables SMBIOS/DMI feature for systems. 1641 1642 This option is only useful on systems that have UEFI firmware. 1643 However, even with this option, the resultant kernel should 1644 continue to boot on existing non-UEFI platforms. 1645 1646 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1647 i.e., the the practice of identifying the platform via DMI to 1648 decide whether certain workarounds for buggy hardware and/or 1649 firmware need to be enabled. This would require the DMI subsystem 1650 to be enabled much earlier than we do on ARM, which is non-trivial. 1651 1652endmenu 1653 1654menu "CPU Power Management" 1655 1656source "drivers/cpufreq/Kconfig" 1657 1658source "drivers/cpuidle/Kconfig" 1659 1660endmenu 1661 1662menu "Floating point emulation" 1663 1664comment "At least one emulation must be selected" 1665 1666config FPE_NWFPE 1667 bool "NWFPE math emulation" 1668 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1669 help 1670 Say Y to include the NWFPE floating point emulator in the kernel. 1671 This is necessary to run most binaries. Linux does not currently 1672 support floating point hardware so you need to say Y here even if 1673 your machine has an FPA or floating point co-processor podule. 1674 1675 You may say N here if you are going to load the Acorn FPEmulator 1676 early in the bootup. 1677 1678config FPE_NWFPE_XP 1679 bool "Support extended precision" 1680 depends on FPE_NWFPE 1681 help 1682 Say Y to include 80-bit support in the kernel floating-point 1683 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1684 Note that gcc does not generate 80-bit operations by default, 1685 so in most cases this option only enlarges the size of the 1686 floating point emulator without any good reason. 1687 1688 You almost surely want to say N here. 1689 1690config FPE_FASTFPE 1691 bool "FastFPE math emulation (EXPERIMENTAL)" 1692 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1693 help 1694 Say Y here to include the FAST floating point emulator in the kernel. 1695 This is an experimental much faster emulator which now also has full 1696 precision for the mantissa. It does not support any exceptions. 1697 It is very simple, and approximately 3-6 times faster than NWFPE. 1698 1699 It should be sufficient for most programs. It may be not suitable 1700 for scientific calculations, but you have to check this for yourself. 1701 If you do not feel you need a faster FP emulation you should better 1702 choose NWFPE. 1703 1704config VFP 1705 bool "VFP-format floating point maths" 1706 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1707 help 1708 Say Y to include VFP support code in the kernel. This is needed 1709 if your hardware includes a VFP unit. 1710 1711 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1712 release notes and additional status information. 1713 1714 Say N if your target does not have VFP hardware. 1715 1716config VFPv3 1717 bool 1718 depends on VFP 1719 default y if CPU_V7 1720 1721config NEON 1722 bool "Advanced SIMD (NEON) Extension support" 1723 depends on VFPv3 && CPU_V7 1724 help 1725 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1726 Extension. 1727 1728config KERNEL_MODE_NEON 1729 bool "Support for NEON in kernel mode" 1730 depends on NEON && AEABI 1731 help 1732 Say Y to include support for NEON in kernel mode. 1733 1734endmenu 1735 1736menu "Power management options" 1737 1738source "kernel/power/Kconfig" 1739 1740config ARCH_SUSPEND_POSSIBLE 1741 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1742 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1743 def_bool y 1744 1745config ARM_CPU_SUSPEND 1746 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1747 depends on ARCH_SUSPEND_POSSIBLE 1748 1749config ARCH_HIBERNATION_POSSIBLE 1750 bool 1751 depends on MMU 1752 default y if ARCH_SUSPEND_POSSIBLE 1753 1754endmenu 1755 1756source "arch/arm/Kconfig.assembler" 1757