1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_MEMBARRIER_SYNC_CORE 13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 14 select ARCH_HAS_PHYS_TO_DMA 15 select ARCH_HAS_SET_MEMORY 16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 17 select ARCH_HAS_STRICT_MODULE_RWX if MMU 18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 19 select ARCH_HAVE_CUSTOM_GPIO_H 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_MIGHT_HAVE_PC_PARPORT 22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 24 select ARCH_SUPPORTS_ATOMIC_RMW 25 select ARCH_USE_BUILTIN_BSWAP 26 select ARCH_USE_CMPXCHG_LOCKREF 27 select ARCH_WANT_IPC_PARSE_VERSION 28 select BUILDTIME_EXTABLE_SORT if MMU 29 select CLONE_BACKWARDS 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 32 select DMA_DIRECT_OPS if !MMU 33 select EDAC_SUPPORT 34 select EDAC_ATOMIC_SCRUB 35 select GENERIC_ALLOCATOR 36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 39 select GENERIC_CPU_AUTOPROBE 40 select GENERIC_EARLY_IOREMAP 41 select GENERIC_IDLE_POLL_SETUP 42 select GENERIC_IRQ_PROBE 43 select GENERIC_IRQ_SHOW 44 select GENERIC_IRQ_SHOW_LEVEL 45 select GENERIC_PCI_IOMAP 46 select GENERIC_SCHED_CLOCK 47 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_STRNCPY_FROM_USER 49 select GENERIC_STRNLEN_USER 50 select HANDLE_DOMAIN_IRQ 51 select HARDIRQS_SW_RESEND 52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 56 select HAVE_ARCH_MMAP_RND_BITS if MMU 57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 59 select HAVE_ARCH_TRACEHOOK 60 select HAVE_ARM_SMCCC if CPU_V7 61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 62 select HAVE_CONTEXT_TRACKING 63 select HAVE_C_RECORDMCOUNT 64 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DMA_CONTIGUOUS if MMU 66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 69 select HAVE_EXIT_THREAD 70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 73 select HAVE_GCC_PLUGINS 74 select HAVE_GENERIC_DMA_COHERENT 75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 76 select HAVE_IDE if PCI || ISA || PCMCIA 77 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_KERNEL_GZIP 79 select HAVE_KERNEL_LZ4 80 select HAVE_KERNEL_LZMA 81 select HAVE_KERNEL_LZO 82 select HAVE_KERNEL_XZ 83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 84 select HAVE_KRETPROBES if (HAVE_KPROBES) 85 select HAVE_MEMBLOCK 86 select HAVE_MOD_ARCH_SPECIFIC 87 select HAVE_NMI 88 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 89 select HAVE_OPTPROBES if !THUMB2_KERNEL 90 select HAVE_PERF_EVENTS 91 select HAVE_PERF_REGS 92 select HAVE_PERF_USER_STACK_DUMP 93 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 94 select HAVE_REGS_AND_STACK_ACCESS_API 95 select HAVE_RSEQ 96 select HAVE_STACKPROTECTOR 97 select HAVE_SYSCALL_TRACEPOINTS 98 select HAVE_UID16 99 select HAVE_VIRT_CPU_ACCOUNTING_GEN 100 select IRQ_FORCED_THREADING 101 select MODULES_USE_ELF_REL 102 select NEED_DMA_MAP_STATE 103 select NO_BOOTMEM 104 select OF_EARLY_FLATTREE if OF 105 select OF_RESERVED_MEM if OF 106 select OLD_SIGACTION 107 select OLD_SIGSUSPEND3 108 select PERF_USE_VMALLOC 109 select REFCOUNT_FULL 110 select RTC_LIB 111 select SYS_SUPPORTS_APM_EMULATION 112 # Above selects are sorted alphabetically; please add new ones 113 # according to that. Thanks. 114 help 115 The ARM series is a line of low-power-consumption RISC chip designs 116 licensed by ARM Ltd and targeted at embedded applications and 117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 118 manufactured, but legacy ARM-based PC hardware remains popular in 119 Europe. There is an ARM Linux project with a web page at 120 <http://www.arm.linux.org.uk/>. 121 122config ARM_HAS_SG_CHAIN 123 select ARCH_HAS_SG_CHAIN 124 bool 125 126config ARM_DMA_USE_IOMMU 127 bool 128 select ARM_HAS_SG_CHAIN 129 select NEED_SG_DMA_LENGTH 130 131if ARM_DMA_USE_IOMMU 132 133config ARM_DMA_IOMMU_ALIGNMENT 134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 135 range 4 9 136 default 8 137 help 138 DMA mapping framework by default aligns all buffers to the smallest 139 PAGE_SIZE order which is greater than or equal to the requested buffer 140 size. This works well for buffers up to a few hundreds kilobytes, but 141 for larger buffers it just a waste of address space. Drivers which has 142 relatively small addressing window (like 64Mib) might run out of 143 virtual space with just a few allocations. 144 145 With this parameter you can specify the maximum PAGE_SIZE order for 146 DMA IOMMU buffers. Larger buffers will be aligned only to this 147 specified order. The order is expressed as a power of two multiplied 148 by the PAGE_SIZE. 149 150endif 151 152config MIGHT_HAVE_PCI 153 bool 154 155config SYS_SUPPORTS_APM_EMULATION 156 bool 157 158config HAVE_TCM 159 bool 160 select GENERIC_ALLOCATOR 161 162config HAVE_PROC_CPU 163 bool 164 165config NO_IOPORT_MAP 166 bool 167 168config EISA 169 bool 170 ---help--- 171 The Extended Industry Standard Architecture (EISA) bus was 172 developed as an open alternative to the IBM MicroChannel bus. 173 174 The EISA bus provided some of the features of the IBM MicroChannel 175 bus while maintaining backward compatibility with cards made for 176 the older ISA bus. The EISA bus saw limited use between 1988 and 177 1995 when it was made obsolete by the PCI bus. 178 179 Say Y here if you are building a kernel for an EISA-based machine. 180 181 Otherwise, say N. 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config RWSEM_XCHGADD_ALGORITHM 199 bool 200 default y 201 202config ARCH_HAS_ILOG2_U32 203 bool 204 205config ARCH_HAS_ILOG2_U64 206 bool 207 208config ARCH_HAS_BANDGAP 209 bool 210 211config FIX_EARLYCON_MEM 212 def_bool y if MMU 213 214config GENERIC_HWEIGHT 215 bool 216 default y 217 218config GENERIC_CALIBRATE_DELAY 219 bool 220 default y 221 222config ARCH_MAY_HAVE_PC_FDC 223 bool 224 225config ZONE_DMA 226 bool 227 228config ARCH_SUPPORTS_UPROBES 229 def_bool y 230 231config ARCH_HAS_DMA_SET_COHERENT_MASK 232 bool 233 234config GENERIC_ISA_DMA 235 bool 236 237config FIQ 238 bool 239 240config NEED_RET_TO_USER 241 bool 242 243config ARCH_MTD_XIP 244 bool 245 246config ARM_PATCH_PHYS_VIRT 247 bool "Patch physical to virtual translations at runtime" if EMBEDDED 248 default y 249 depends on !XIP_KERNEL && MMU 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 16MB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_EBSA110 || \ 281 ARCH_FOOTBRIDGE || \ 282 ARCH_INTEGRATOR || \ 283 ARCH_IOP13XX || \ 284 ARCH_KS8695 || \ 285 ARCH_REALVIEW 286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 287 default 0x20000000 if ARCH_S5PV210 288 default 0xc0000000 if ARCH_SA1100 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARCH_MMAP_RND_BITS_MIN 312 default 8 313 314config ARCH_MMAP_RND_BITS_MAX 315 default 14 if PAGE_OFFSET=0x40000000 316 default 15 if PAGE_OFFSET=0x80000000 317 default 16 318 319# 320# The "ARM system type" choice list is ordered alphabetically by option 321# text. Please add new entries in the option alphabetic order. 322# 323choice 324 prompt "ARM system type" 325 default ARM_SINGLE_ARMV7M if !MMU 326 default ARCH_MULTIPLATFORM if MMU 327 328config ARCH_MULTIPLATFORM 329 bool "Allow multiple platforms to be selected" 330 depends on MMU 331 select ARM_HAS_SG_CHAIN 332 select ARM_PATCH_PHYS_VIRT 333 select AUTO_ZRELADDR 334 select TIMER_OF 335 select COMMON_CLK 336 select GENERIC_CLOCKEVENTS 337 select GENERIC_IRQ_MULTI_HANDLER 338 select MIGHT_HAVE_PCI 339 select PCI_DOMAINS if PCI 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARM_SINGLE_ARMV7M 344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 345 depends on !MMU 346 select ARM_NVIC 347 select AUTO_ZRELADDR 348 select TIMER_OF 349 select COMMON_CLK 350 select CPU_V7M 351 select GENERIC_CLOCKEVENTS 352 select NO_IOPORT_MAP 353 select SPARSE_IRQ 354 select USE_OF 355 356config ARCH_EBSA110 357 bool "EBSA-110" 358 select ARCH_USES_GETTIMEOFFSET 359 select CPU_SA110 360 select ISA 361 select NEED_MACH_IO_H 362 select NEED_MACH_MEMORY_H 363 select NO_IOPORT_MAP 364 help 365 This is an evaluation board for the StrongARM processor available 366 from Digital. It has limited hardware on-board, including an 367 Ethernet interface, two PCMCIA sockets, two serial ports and a 368 parallel port. 369 370config ARCH_EP93XX 371 bool "EP93xx-based" 372 select ARCH_SPARSEMEM_ENABLE 373 select ARM_AMBA 374 imply ARM_PATCH_PHYS_VIRT 375 select ARM_VIC 376 select AUTO_ZRELADDR 377 select CLKDEV_LOOKUP 378 select CLKSRC_MMIO 379 select CPU_ARM920T 380 select GENERIC_CLOCKEVENTS 381 select GPIOLIB 382 help 383 This enables support for the Cirrus EP93xx series of CPUs. 384 385config ARCH_FOOTBRIDGE 386 bool "FootBridge" 387 select CPU_SA110 388 select FOOTBRIDGE 389 select GENERIC_CLOCKEVENTS 390 select HAVE_IDE 391 select NEED_MACH_IO_H if !MMU 392 select NEED_MACH_MEMORY_H 393 help 394 Support for systems based on the DC21285 companion chip 395 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 396 397config ARCH_NETX 398 bool "Hilscher NetX based" 399 select ARM_VIC 400 select CLKSRC_MMIO 401 select CPU_ARM926T 402 select GENERIC_CLOCKEVENTS 403 help 404 This enables support for systems based on the Hilscher NetX Soc 405 406config ARCH_IOP13XX 407 bool "IOP13xx-based" 408 depends on MMU 409 select CPU_XSC3 410 select NEED_MACH_MEMORY_H 411 select NEED_RET_TO_USER 412 select PCI 413 select PLAT_IOP 414 select VMSPLIT_1G 415 select SPARSE_IRQ 416 help 417 Support for Intel's IOP13XX (XScale) family of processors. 418 419config ARCH_IOP32X 420 bool "IOP32x-based" 421 depends on MMU 422 select CPU_XSCALE 423 select GPIO_IOP 424 select GPIOLIB 425 select NEED_RET_TO_USER 426 select PCI 427 select PLAT_IOP 428 help 429 Support for Intel's 80219 and IOP32X (XScale) family of 430 processors. 431 432config ARCH_IOP33X 433 bool "IOP33x-based" 434 depends on MMU 435 select CPU_XSCALE 436 select GPIO_IOP 437 select GPIOLIB 438 select NEED_RET_TO_USER 439 select PCI 440 select PLAT_IOP 441 help 442 Support for Intel's IOP33X (XScale) family of processors. 443 444config ARCH_IXP4XX 445 bool "IXP4xx-based" 446 depends on MMU 447 select ARCH_HAS_DMA_SET_COHERENT_MASK 448 select ARCH_SUPPORTS_BIG_ENDIAN 449 select CLKSRC_MMIO 450 select CPU_XSCALE 451 select DMABOUNCE if PCI 452 select GENERIC_CLOCKEVENTS 453 select GPIOLIB 454 select MIGHT_HAVE_PCI 455 select NEED_MACH_IO_H 456 select USB_EHCI_BIG_ENDIAN_DESC 457 select USB_EHCI_BIG_ENDIAN_MMIO 458 help 459 Support for Intel's IXP4XX (XScale) family of processors. 460 461config ARCH_DOVE 462 bool "Marvell Dove" 463 select CPU_PJ4 464 select GENERIC_CLOCKEVENTS 465 select GENERIC_IRQ_MULTI_HANDLER 466 select GPIOLIB 467 select MIGHT_HAVE_PCI 468 select MVEBU_MBUS 469 select PINCTRL 470 select PINCTRL_DOVE 471 select PLAT_ORION_LEGACY 472 select SPARSE_IRQ 473 select PM_GENERIC_DOMAINS if PM 474 help 475 Support for the Marvell Dove SoC 88AP510 476 477config ARCH_KS8695 478 bool "Micrel/Kendin KS8695" 479 select CLKSRC_MMIO 480 select CPU_ARM922T 481 select GENERIC_CLOCKEVENTS 482 select GPIOLIB 483 select NEED_MACH_MEMORY_H 484 help 485 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 486 System-on-Chip devices. 487 488config ARCH_W90X900 489 bool "Nuvoton W90X900 CPU" 490 select CLKDEV_LOOKUP 491 select CLKSRC_MMIO 492 select CPU_ARM926T 493 select GENERIC_CLOCKEVENTS 494 select GPIOLIB 495 help 496 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 497 At present, the w90x900 has been renamed nuc900, regarding 498 the ARM series product line, you can login the following 499 link address to know more. 500 501 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 502 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 503 504config ARCH_LPC32XX 505 bool "NXP LPC32XX" 506 select ARM_AMBA 507 select CLKDEV_LOOKUP 508 select CLKSRC_LPC32XX 509 select COMMON_CLK 510 select CPU_ARM926T 511 select GENERIC_CLOCKEVENTS 512 select GENERIC_IRQ_MULTI_HANDLER 513 select GPIOLIB 514 select SPARSE_IRQ 515 select USE_OF 516 help 517 Support for the NXP LPC32XX family of processors 518 519config ARCH_PXA 520 bool "PXA2xx/PXA3xx-based" 521 depends on MMU 522 select ARCH_MTD_XIP 523 select ARM_CPU_SUSPEND if PM 524 select AUTO_ZRELADDR 525 select COMMON_CLK 526 select CLKDEV_LOOKUP 527 select CLKSRC_PXA 528 select CLKSRC_MMIO 529 select TIMER_OF 530 select CPU_XSCALE if !CPU_XSC3 531 select GENERIC_CLOCKEVENTS 532 select GENERIC_IRQ_MULTI_HANDLER 533 select GPIO_PXA 534 select GPIOLIB 535 select HAVE_IDE 536 select IRQ_DOMAIN 537 select PLAT_PXA 538 select SPARSE_IRQ 539 help 540 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 541 542config ARCH_RPC 543 bool "RiscPC" 544 depends on MMU 545 select ARCH_ACORN 546 select ARCH_MAY_HAVE_PC_FDC 547 select ARCH_SPARSEMEM_ENABLE 548 select ARCH_USES_GETTIMEOFFSET 549 select CPU_SA110 550 select FIQ 551 select HAVE_IDE 552 select HAVE_PATA_PLATFORM 553 select ISA_DMA_API 554 select NEED_MACH_IO_H 555 select NEED_MACH_MEMORY_H 556 select NO_IOPORT_MAP 557 help 558 On the Acorn Risc-PC, Linux can support the internal IDE disk and 559 CD-ROM interface, serial and parallel port, and the floppy drive. 560 561config ARCH_SA1100 562 bool "SA1100-based" 563 select ARCH_MTD_XIP 564 select ARCH_SPARSEMEM_ENABLE 565 select CLKDEV_LOOKUP 566 select CLKSRC_MMIO 567 select CLKSRC_PXA 568 select TIMER_OF if OF 569 select CPU_FREQ 570 select CPU_SA1100 571 select GENERIC_CLOCKEVENTS 572 select GENERIC_IRQ_MULTI_HANDLER 573 select GPIOLIB 574 select HAVE_IDE 575 select IRQ_DOMAIN 576 select ISA 577 select NEED_MACH_MEMORY_H 578 select SPARSE_IRQ 579 help 580 Support for StrongARM 11x0 based boards. 581 582config ARCH_S3C24XX 583 bool "Samsung S3C24XX SoCs" 584 select ATAGS 585 select CLKDEV_LOOKUP 586 select CLKSRC_SAMSUNG_PWM 587 select GENERIC_CLOCKEVENTS 588 select GPIO_SAMSUNG 589 select GPIOLIB 590 select GENERIC_IRQ_MULTI_HANDLER 591 select HAVE_S3C2410_I2C if I2C 592 select HAVE_S3C2410_WATCHDOG if WATCHDOG 593 select HAVE_S3C_RTC if RTC_CLASS 594 select NEED_MACH_IO_H 595 select SAMSUNG_ATAGS 596 select USE_OF 597 help 598 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 599 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 600 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 601 Samsung SMDK2410 development board (and derivatives). 602 603config ARCH_DAVINCI 604 bool "TI DaVinci" 605 select ARCH_HAS_HOLES_MEMORYMODEL 606 select COMMON_CLK 607 select CPU_ARM926T 608 select GENERIC_ALLOCATOR 609 select GENERIC_CLOCKEVENTS 610 select GENERIC_IRQ_CHIP 611 select GPIOLIB 612 select HAVE_IDE 613 select PM_GENERIC_DOMAINS if PM 614 select PM_GENERIC_DOMAINS_OF if PM && OF 615 select RESET_CONTROLLER 616 select USE_OF 617 select ZONE_DMA 618 help 619 Support for TI's DaVinci platform. 620 621config ARCH_OMAP1 622 bool "TI OMAP1" 623 depends on MMU 624 select ARCH_HAS_HOLES_MEMORYMODEL 625 select ARCH_OMAP 626 select CLKDEV_LOOKUP 627 select CLKSRC_MMIO 628 select GENERIC_CLOCKEVENTS 629 select GENERIC_IRQ_CHIP 630 select GENERIC_IRQ_MULTI_HANDLER 631 select GPIOLIB 632 select HAVE_IDE 633 select IRQ_DOMAIN 634 select NEED_MACH_IO_H if PCCARD 635 select NEED_MACH_MEMORY_H 636 select SPARSE_IRQ 637 help 638 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 639 640endchoice 641 642menu "Multiple platform selection" 643 depends on ARCH_MULTIPLATFORM 644 645comment "CPU Core family selection" 646 647config ARCH_MULTI_V4 648 bool "ARMv4 based platforms (FA526)" 649 depends on !ARCH_MULTI_V6_V7 650 select ARCH_MULTI_V4_V5 651 select CPU_FA526 652 653config ARCH_MULTI_V4T 654 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 655 depends on !ARCH_MULTI_V6_V7 656 select ARCH_MULTI_V4_V5 657 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 658 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 659 CPU_ARM925T || CPU_ARM940T) 660 661config ARCH_MULTI_V5 662 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 663 depends on !ARCH_MULTI_V6_V7 664 select ARCH_MULTI_V4_V5 665 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 666 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 667 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 668 669config ARCH_MULTI_V4_V5 670 bool 671 672config ARCH_MULTI_V6 673 bool "ARMv6 based platforms (ARM11)" 674 select ARCH_MULTI_V6_V7 675 select CPU_V6K 676 677config ARCH_MULTI_V7 678 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 679 default y 680 select ARCH_MULTI_V6_V7 681 select CPU_V7 682 select HAVE_SMP 683 684config ARCH_MULTI_V6_V7 685 bool 686 select MIGHT_HAVE_CACHE_L2X0 687 688config ARCH_MULTI_CPU_AUTO 689 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 690 select ARCH_MULTI_V5 691 692endmenu 693 694config ARCH_VIRT 695 bool "Dummy Virtual Machine" 696 depends on ARCH_MULTI_V7 697 select ARM_AMBA 698 select ARM_GIC 699 select ARM_GIC_V2M if PCI 700 select ARM_GIC_V3 701 select ARM_GIC_V3_ITS if PCI 702 select ARM_PSCI 703 select HAVE_ARM_ARCH_TIMER 704 select ARCH_SUPPORTS_BIG_ENDIAN 705 706# 707# This is sorted alphabetically by mach-* pathname. However, plat-* 708# Kconfigs may be included either alphabetically (according to the 709# plat- suffix) or along side the corresponding mach-* source. 710# 711source "arch/arm/mach-actions/Kconfig" 712 713source "arch/arm/mach-alpine/Kconfig" 714 715source "arch/arm/mach-artpec/Kconfig" 716 717source "arch/arm/mach-asm9260/Kconfig" 718 719source "arch/arm/mach-aspeed/Kconfig" 720 721source "arch/arm/mach-at91/Kconfig" 722 723source "arch/arm/mach-axxia/Kconfig" 724 725source "arch/arm/mach-bcm/Kconfig" 726 727source "arch/arm/mach-berlin/Kconfig" 728 729source "arch/arm/mach-clps711x/Kconfig" 730 731source "arch/arm/mach-cns3xxx/Kconfig" 732 733source "arch/arm/mach-davinci/Kconfig" 734 735source "arch/arm/mach-digicolor/Kconfig" 736 737source "arch/arm/mach-dove/Kconfig" 738 739source "arch/arm/mach-ep93xx/Kconfig" 740 741source "arch/arm/mach-exynos/Kconfig" 742source "arch/arm/plat-samsung/Kconfig" 743 744source "arch/arm/mach-footbridge/Kconfig" 745 746source "arch/arm/mach-gemini/Kconfig" 747 748source "arch/arm/mach-highbank/Kconfig" 749 750source "arch/arm/mach-hisi/Kconfig" 751 752source "arch/arm/mach-imx/Kconfig" 753 754source "arch/arm/mach-integrator/Kconfig" 755 756source "arch/arm/mach-iop13xx/Kconfig" 757 758source "arch/arm/mach-iop32x/Kconfig" 759 760source "arch/arm/mach-iop33x/Kconfig" 761 762source "arch/arm/mach-ixp4xx/Kconfig" 763 764source "arch/arm/mach-keystone/Kconfig" 765 766source "arch/arm/mach-ks8695/Kconfig" 767 768source "arch/arm/mach-mediatek/Kconfig" 769 770source "arch/arm/mach-meson/Kconfig" 771 772source "arch/arm/mach-mmp/Kconfig" 773 774source "arch/arm/mach-moxart/Kconfig" 775 776source "arch/arm/mach-mv78xx0/Kconfig" 777 778source "arch/arm/mach-mvebu/Kconfig" 779 780source "arch/arm/mach-mxs/Kconfig" 781 782source "arch/arm/mach-netx/Kconfig" 783 784source "arch/arm/mach-nomadik/Kconfig" 785 786source "arch/arm/mach-npcm/Kconfig" 787 788source "arch/arm/mach-nspire/Kconfig" 789 790source "arch/arm/plat-omap/Kconfig" 791 792source "arch/arm/mach-omap1/Kconfig" 793 794source "arch/arm/mach-omap2/Kconfig" 795 796source "arch/arm/mach-orion5x/Kconfig" 797 798source "arch/arm/mach-oxnas/Kconfig" 799 800source "arch/arm/mach-picoxcell/Kconfig" 801 802source "arch/arm/mach-prima2/Kconfig" 803 804source "arch/arm/mach-pxa/Kconfig" 805source "arch/arm/plat-pxa/Kconfig" 806 807source "arch/arm/mach-qcom/Kconfig" 808 809source "arch/arm/mach-realview/Kconfig" 810 811source "arch/arm/mach-rockchip/Kconfig" 812 813source "arch/arm/mach-s3c24xx/Kconfig" 814 815source "arch/arm/mach-s3c64xx/Kconfig" 816 817source "arch/arm/mach-s5pv210/Kconfig" 818 819source "arch/arm/mach-sa1100/Kconfig" 820 821source "arch/arm/mach-shmobile/Kconfig" 822 823source "arch/arm/mach-socfpga/Kconfig" 824 825source "arch/arm/mach-spear/Kconfig" 826 827source "arch/arm/mach-sti/Kconfig" 828 829source "arch/arm/mach-stm32/Kconfig" 830 831source "arch/arm/mach-sunxi/Kconfig" 832 833source "arch/arm/mach-tango/Kconfig" 834 835source "arch/arm/mach-tegra/Kconfig" 836 837source "arch/arm/mach-u300/Kconfig" 838 839source "arch/arm/mach-uniphier/Kconfig" 840 841source "arch/arm/mach-ux500/Kconfig" 842 843source "arch/arm/mach-versatile/Kconfig" 844 845source "arch/arm/mach-vexpress/Kconfig" 846source "arch/arm/plat-versatile/Kconfig" 847 848source "arch/arm/mach-vt8500/Kconfig" 849 850source "arch/arm/mach-w90x900/Kconfig" 851 852source "arch/arm/mach-zx/Kconfig" 853 854source "arch/arm/mach-zynq/Kconfig" 855 856# ARMv7-M architecture 857config ARCH_EFM32 858 bool "Energy Micro efm32" 859 depends on ARM_SINGLE_ARMV7M 860 select GPIOLIB 861 help 862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 863 processors. 864 865config ARCH_LPC18XX 866 bool "NXP LPC18xx/LPC43xx" 867 depends on ARM_SINGLE_ARMV7M 868 select ARCH_HAS_RESET_CONTROLLER 869 select ARM_AMBA 870 select CLKSRC_LPC32XX 871 select PINCTRL 872 help 873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 874 high performance microcontrollers. 875 876config ARCH_MPS2 877 bool "ARM MPS2 platform" 878 depends on ARM_SINGLE_ARMV7M 879 select ARM_AMBA 880 select CLKSRC_MPS2 881 help 882 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 883 with a range of available cores like Cortex-M3/M4/M7. 884 885 Please, note that depends which Application Note is used memory map 886 for the platform may vary, so adjustment of RAM base might be needed. 887 888# Definitions to make life easier 889config ARCH_ACORN 890 bool 891 892config PLAT_IOP 893 bool 894 select GENERIC_CLOCKEVENTS 895 896config PLAT_ORION 897 bool 898 select CLKSRC_MMIO 899 select COMMON_CLK 900 select GENERIC_IRQ_CHIP 901 select IRQ_DOMAIN 902 903config PLAT_ORION_LEGACY 904 bool 905 select PLAT_ORION 906 907config PLAT_PXA 908 bool 909 910config PLAT_VERSATILE 911 bool 912 913source "arch/arm/firmware/Kconfig" 914 915source arch/arm/mm/Kconfig 916 917config IWMMXT 918 bool "Enable iWMMXt support" 919 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 920 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 921 help 922 Enable support for iWMMXt context switching at run time if 923 running on a CPU that supports it. 924 925if !MMU 926source "arch/arm/Kconfig-nommu" 927endif 928 929config PJ4B_ERRATA_4742 930 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 931 depends on CPU_PJ4B && MACH_ARMADA_370 932 default y 933 help 934 When coming out of either a Wait for Interrupt (WFI) or a Wait for 935 Event (WFE) IDLE states, a specific timing sensitivity exists between 936 the retiring WFI/WFE instructions and the newly issued subsequent 937 instructions. This sensitivity can result in a CPU hang scenario. 938 Workaround: 939 The software must insert either a Data Synchronization Barrier (DSB) 940 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 941 instruction 942 943config ARM_ERRATA_326103 944 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 945 depends on CPU_V6 946 help 947 Executing a SWP instruction to read-only memory does not set bit 11 948 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 949 treat the access as a read, preventing a COW from occurring and 950 causing the faulting task to livelock. 951 952config ARM_ERRATA_411920 953 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 954 depends on CPU_V6 || CPU_V6K 955 help 956 Invalidation of the Instruction Cache operation can 957 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 958 It does not affect the MPCore. This option enables the ARM Ltd. 959 recommended workaround. 960 961config ARM_ERRATA_430973 962 bool "ARM errata: Stale prediction on replaced interworking branch" 963 depends on CPU_V7 964 help 965 This option enables the workaround for the 430973 Cortex-A8 966 r1p* erratum. If a code sequence containing an ARM/Thumb 967 interworking branch is replaced with another code sequence at the 968 same virtual address, whether due to self-modifying code or virtual 969 to physical address re-mapping, Cortex-A8 does not recover from the 970 stale interworking branch prediction. This results in Cortex-A8 971 executing the new code sequence in the incorrect ARM or Thumb state. 972 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 973 and also flushes the branch target cache at every context switch. 974 Note that setting specific bits in the ACTLR register may not be 975 available in non-secure mode. 976 977config ARM_ERRATA_458693 978 bool "ARM errata: Processor deadlock when a false hazard is created" 979 depends on CPU_V7 980 depends on !ARCH_MULTIPLATFORM 981 help 982 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 983 erratum. For very specific sequences of memory operations, it is 984 possible for a hazard condition intended for a cache line to instead 985 be incorrectly associated with a different cache line. This false 986 hazard might then cause a processor deadlock. The workaround enables 987 the L1 caching of the NEON accesses and disables the PLD instruction 988 in the ACTLR register. Note that setting specific bits in the ACTLR 989 register may not be available in non-secure mode. 990 991config ARM_ERRATA_460075 992 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 993 depends on CPU_V7 994 depends on !ARCH_MULTIPLATFORM 995 help 996 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 997 erratum. Any asynchronous access to the L2 cache may encounter a 998 situation in which recent store transactions to the L2 cache are lost 999 and overwritten with stale memory contents from external memory. The 1000 workaround disables the write-allocate mode for the L2 cache via the 1001 ACTLR register. Note that setting specific bits in the ACTLR register 1002 may not be available in non-secure mode. 1003 1004config ARM_ERRATA_742230 1005 bool "ARM errata: DMB operation may be faulty" 1006 depends on CPU_V7 && SMP 1007 depends on !ARCH_MULTIPLATFORM 1008 help 1009 This option enables the workaround for the 742230 Cortex-A9 1010 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1011 between two write operations may not ensure the correct visibility 1012 ordering of the two writes. This workaround sets a specific bit in 1013 the diagnostic register of the Cortex-A9 which causes the DMB 1014 instruction to behave as a DSB, ensuring the correct behaviour of 1015 the two writes. 1016 1017config ARM_ERRATA_742231 1018 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1019 depends on CPU_V7 && SMP 1020 depends on !ARCH_MULTIPLATFORM 1021 help 1022 This option enables the workaround for the 742231 Cortex-A9 1023 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1024 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1025 accessing some data located in the same cache line, may get corrupted 1026 data due to bad handling of the address hazard when the line gets 1027 replaced from one of the CPUs at the same time as another CPU is 1028 accessing it. This workaround sets specific bits in the diagnostic 1029 register of the Cortex-A9 which reduces the linefill issuing 1030 capabilities of the processor. 1031 1032config ARM_ERRATA_643719 1033 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1034 depends on CPU_V7 && SMP 1035 default y 1036 help 1037 This option enables the workaround for the 643719 Cortex-A9 (prior to 1038 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1039 register returns zero when it should return one. The workaround 1040 corrects this value, ensuring cache maintenance operations which use 1041 it behave as intended and avoiding data corruption. 1042 1043config ARM_ERRATA_720789 1044 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1045 depends on CPU_V7 1046 help 1047 This option enables the workaround for the 720789 Cortex-A9 (prior to 1048 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1049 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1050 As a consequence of this erratum, some TLB entries which should be 1051 invalidated are not, resulting in an incoherency in the system page 1052 tables. The workaround changes the TLB flushing routines to invalidate 1053 entries regardless of the ASID. 1054 1055config ARM_ERRATA_743622 1056 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1057 depends on CPU_V7 1058 depends on !ARCH_MULTIPLATFORM 1059 help 1060 This option enables the workaround for the 743622 Cortex-A9 1061 (r2p*) erratum. Under very rare conditions, a faulty 1062 optimisation in the Cortex-A9 Store Buffer may lead to data 1063 corruption. This workaround sets a specific bit in the diagnostic 1064 register of the Cortex-A9 which disables the Store Buffer 1065 optimisation, preventing the defect from occurring. This has no 1066 visible impact on the overall performance or power consumption of the 1067 processor. 1068 1069config ARM_ERRATA_751472 1070 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1071 depends on CPU_V7 1072 depends on !ARCH_MULTIPLATFORM 1073 help 1074 This option enables the workaround for the 751472 Cortex-A9 (prior 1075 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1076 completion of a following broadcasted operation if the second 1077 operation is received by a CPU before the ICIALLUIS has completed, 1078 potentially leading to corrupted entries in the cache or TLB. 1079 1080config ARM_ERRATA_754322 1081 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1082 depends on CPU_V7 1083 help 1084 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1085 r3p*) erratum. A speculative memory access may cause a page table walk 1086 which starts prior to an ASID switch but completes afterwards. This 1087 can populate the micro-TLB with a stale entry which may be hit with 1088 the new ASID. This workaround places two dsb instructions in the mm 1089 switching code so that no page table walks can cross the ASID switch. 1090 1091config ARM_ERRATA_754327 1092 bool "ARM errata: no automatic Store Buffer drain" 1093 depends on CPU_V7 && SMP 1094 help 1095 This option enables the workaround for the 754327 Cortex-A9 (prior to 1096 r2p0) erratum. The Store Buffer does not have any automatic draining 1097 mechanism and therefore a livelock may occur if an external agent 1098 continuously polls a memory location waiting to observe an update. 1099 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1100 written polling loops from denying visibility of updates to memory. 1101 1102config ARM_ERRATA_364296 1103 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1104 depends on CPU_V6 1105 help 1106 This options enables the workaround for the 364296 ARM1136 1107 r0p2 erratum (possible cache data corruption with 1108 hit-under-miss enabled). It sets the undocumented bit 31 in 1109 the auxiliary control register and the FI bit in the control 1110 register, thus disabling hit-under-miss without putting the 1111 processor into full low interrupt latency mode. ARM11MPCore 1112 is not affected. 1113 1114config ARM_ERRATA_764369 1115 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1116 depends on CPU_V7 && SMP 1117 help 1118 This option enables the workaround for erratum 764369 1119 affecting Cortex-A9 MPCore with two or more processors (all 1120 current revisions). Under certain timing circumstances, a data 1121 cache line maintenance operation by MVA targeting an Inner 1122 Shareable memory region may fail to proceed up to either the 1123 Point of Coherency or to the Point of Unification of the 1124 system. This workaround adds a DSB instruction before the 1125 relevant cache maintenance functions and sets a specific bit 1126 in the diagnostic control register of the SCU. 1127 1128config ARM_ERRATA_775420 1129 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1130 depends on CPU_V7 1131 help 1132 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1133 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1134 operation aborts with MMU exception, it might cause the processor 1135 to deadlock. This workaround puts DSB before executing ISB if 1136 an abort may occur on cache maintenance. 1137 1138config ARM_ERRATA_798181 1139 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1140 depends on CPU_V7 && SMP 1141 help 1142 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1143 adequately shooting down all use of the old entries. This 1144 option enables the Linux kernel workaround for this erratum 1145 which sends an IPI to the CPUs that are running the same ASID 1146 as the one being invalidated. 1147 1148config ARM_ERRATA_773022 1149 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1150 depends on CPU_V7 1151 help 1152 This option enables the workaround for the 773022 Cortex-A15 1153 (up to r0p4) erratum. In certain rare sequences of code, the 1154 loop buffer may deliver incorrect instructions. This 1155 workaround disables the loop buffer to avoid the erratum. 1156 1157config ARM_ERRATA_818325_852422 1158 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1159 depends on CPU_V7 1160 help 1161 This option enables the workaround for: 1162 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1163 instruction might deadlock. Fixed in r0p1. 1164 - Cortex-A12 852422: Execution of a sequence of instructions might 1165 lead to either a data corruption or a CPU deadlock. Not fixed in 1166 any Cortex-A12 cores yet. 1167 This workaround for all both errata involves setting bit[12] of the 1168 Feature Register. This bit disables an optimisation applied to a 1169 sequence of 2 instructions that use opposing condition codes. 1170 1171config ARM_ERRATA_821420 1172 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1173 depends on CPU_V7 1174 help 1175 This option enables the workaround for the 821420 Cortex-A12 1176 (all revs) erratum. In very rare timing conditions, a sequence 1177 of VMOV to Core registers instructions, for which the second 1178 one is in the shadow of a branch or abort, can lead to a 1179 deadlock when the VMOV instructions are issued out-of-order. 1180 1181config ARM_ERRATA_825619 1182 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1183 depends on CPU_V7 1184 help 1185 This option enables the workaround for the 825619 Cortex-A12 1186 (all revs) erratum. Within rare timing constraints, executing a 1187 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1188 and Device/Strongly-Ordered loads and stores might cause deadlock 1189 1190config ARM_ERRATA_852421 1191 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1192 depends on CPU_V7 1193 help 1194 This option enables the workaround for the 852421 Cortex-A17 1195 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1196 execution of a DMB ST instruction might fail to properly order 1197 stores from GroupA and stores from GroupB. 1198 1199config ARM_ERRATA_852423 1200 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1201 depends on CPU_V7 1202 help 1203 This option enables the workaround for: 1204 - Cortex-A17 852423: Execution of a sequence of instructions might 1205 lead to either a data corruption or a CPU deadlock. Not fixed in 1206 any Cortex-A17 cores yet. 1207 This is identical to Cortex-A12 erratum 852422. It is a separate 1208 config option from the A12 erratum due to the way errata are checked 1209 for and handled. 1210 1211endmenu 1212 1213source "arch/arm/common/Kconfig" 1214 1215menu "Bus support" 1216 1217config ISA 1218 bool 1219 help 1220 Find out whether you have ISA slots on your motherboard. ISA is the 1221 name of a bus system, i.e. the way the CPU talks to the other stuff 1222 inside your box. Other bus systems are PCI, EISA, MicroChannel 1223 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1224 newer boards don't support it. If you have ISA, say Y, otherwise N. 1225 1226# Select ISA DMA controller support 1227config ISA_DMA 1228 bool 1229 select ISA_DMA_API 1230 1231# Select ISA DMA interface 1232config ISA_DMA_API 1233 bool 1234 1235config PCI 1236 bool "PCI support" if MIGHT_HAVE_PCI 1237 help 1238 Find out whether you have a PCI motherboard. PCI is the name of a 1239 bus system, i.e. the way the CPU talks to the other stuff inside 1240 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1241 VESA. If you have PCI, say Y, otherwise N. 1242 1243config PCI_DOMAINS 1244 bool "Support for multiple PCI domains" 1245 depends on PCI 1246 help 1247 Enable PCI domains kernel management. Say Y if your machine 1248 has a PCI bus hierarchy that requires more than one PCI 1249 domain (aka segment) to be correctly managed. Say N otherwise. 1250 1251 If you don't know what to do here, say N. 1252 1253config PCI_DOMAINS_GENERIC 1254 def_bool PCI_DOMAINS 1255 1256config PCI_NANOENGINE 1257 bool "BSE nanoEngine PCI support" 1258 depends on SA1100_NANOENGINE 1259 help 1260 Enable PCI on the BSE nanoEngine board. 1261 1262config PCI_SYSCALL 1263 def_bool PCI 1264 1265config PCI_HOST_ITE8152 1266 bool 1267 depends on PCI && MACH_ARMCORE 1268 default y 1269 select DMABOUNCE 1270 1271source "drivers/pci/Kconfig" 1272 1273source "drivers/pcmcia/Kconfig" 1274 1275endmenu 1276 1277menu "Kernel Features" 1278 1279config HAVE_SMP 1280 bool 1281 help 1282 This option should be selected by machines which have an SMP- 1283 capable CPU. 1284 1285 The only effect of this option is to make the SMP-related 1286 options available to the user for configuration. 1287 1288config SMP 1289 bool "Symmetric Multi-Processing" 1290 depends on CPU_V6K || CPU_V7 1291 depends on GENERIC_CLOCKEVENTS 1292 depends on HAVE_SMP 1293 depends on MMU || ARM_MPU 1294 select IRQ_WORK 1295 help 1296 This enables support for systems with more than one CPU. If you have 1297 a system with only one CPU, say N. If you have a system with more 1298 than one CPU, say Y. 1299 1300 If you say N here, the kernel will run on uni- and multiprocessor 1301 machines, but will use only one CPU of a multiprocessor machine. If 1302 you say Y here, the kernel will run on many, but not all, 1303 uniprocessor machines. On a uniprocessor machine, the kernel 1304 will run faster if you say N here. 1305 1306 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1307 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1308 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1309 1310 If you don't know what to do here, say N. 1311 1312config SMP_ON_UP 1313 bool "Allow booting SMP kernel on uniprocessor systems" 1314 depends on SMP && !XIP_KERNEL && MMU 1315 default y 1316 help 1317 SMP kernels contain instructions which fail on non-SMP processors. 1318 Enabling this option allows the kernel to modify itself to make 1319 these instructions safe. Disabling it allows about 1K of space 1320 savings. 1321 1322 If you don't know what to do here, say Y. 1323 1324config ARM_CPU_TOPOLOGY 1325 bool "Support cpu topology definition" 1326 depends on SMP && CPU_V7 1327 default y 1328 help 1329 Support ARM cpu topology definition. The MPIDR register defines 1330 affinity between processors which is then used to describe the cpu 1331 topology of an ARM System. 1332 1333config SCHED_MC 1334 bool "Multi-core scheduler support" 1335 depends on ARM_CPU_TOPOLOGY 1336 help 1337 Multi-core scheduler support improves the CPU scheduler's decision 1338 making when dealing with multi-core CPU chips at a cost of slightly 1339 increased overhead in some places. If unsure say N here. 1340 1341config SCHED_SMT 1342 bool "SMT scheduler support" 1343 depends on ARM_CPU_TOPOLOGY 1344 help 1345 Improves the CPU scheduler's decision making when dealing with 1346 MultiThreading at a cost of slightly increased overhead in some 1347 places. If unsure say N here. 1348 1349config HAVE_ARM_SCU 1350 bool 1351 help 1352 This option enables support for the ARM system coherency unit 1353 1354config HAVE_ARM_ARCH_TIMER 1355 bool "Architected timer support" 1356 depends on CPU_V7 1357 select ARM_ARCH_TIMER 1358 select GENERIC_CLOCKEVENTS 1359 help 1360 This option enables support for the ARM architected timer 1361 1362config HAVE_ARM_TWD 1363 bool 1364 select TIMER_OF if OF 1365 help 1366 This options enables support for the ARM timer and watchdog unit 1367 1368config MCPM 1369 bool "Multi-Cluster Power Management" 1370 depends on CPU_V7 && SMP 1371 help 1372 This option provides the common power management infrastructure 1373 for (multi-)cluster based systems, such as big.LITTLE based 1374 systems. 1375 1376config MCPM_QUAD_CLUSTER 1377 bool 1378 depends on MCPM 1379 help 1380 To avoid wasting resources unnecessarily, MCPM only supports up 1381 to 2 clusters by default. 1382 Platforms with 3 or 4 clusters that use MCPM must select this 1383 option to allow the additional clusters to be managed. 1384 1385config BIG_LITTLE 1386 bool "big.LITTLE support (Experimental)" 1387 depends on CPU_V7 && SMP 1388 select MCPM 1389 help 1390 This option enables support selections for the big.LITTLE 1391 system architecture. 1392 1393config BL_SWITCHER 1394 bool "big.LITTLE switcher support" 1395 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1396 select CPU_PM 1397 help 1398 The big.LITTLE "switcher" provides the core functionality to 1399 transparently handle transition between a cluster of A15's 1400 and a cluster of A7's in a big.LITTLE system. 1401 1402config BL_SWITCHER_DUMMY_IF 1403 tristate "Simple big.LITTLE switcher user interface" 1404 depends on BL_SWITCHER && DEBUG_KERNEL 1405 help 1406 This is a simple and dummy char dev interface to control 1407 the big.LITTLE switcher core code. It is meant for 1408 debugging purposes only. 1409 1410choice 1411 prompt "Memory split" 1412 depends on MMU 1413 default VMSPLIT_3G 1414 help 1415 Select the desired split between kernel and user memory. 1416 1417 If you are not absolutely sure what you are doing, leave this 1418 option alone! 1419 1420 config VMSPLIT_3G 1421 bool "3G/1G user/kernel split" 1422 config VMSPLIT_3G_OPT 1423 depends on !ARM_LPAE 1424 bool "3G/1G user/kernel split (for full 1G low memory)" 1425 config VMSPLIT_2G 1426 bool "2G/2G user/kernel split" 1427 config VMSPLIT_1G 1428 bool "1G/3G user/kernel split" 1429endchoice 1430 1431config PAGE_OFFSET 1432 hex 1433 default PHYS_OFFSET if !MMU 1434 default 0x40000000 if VMSPLIT_1G 1435 default 0x80000000 if VMSPLIT_2G 1436 default 0xB0000000 if VMSPLIT_3G_OPT 1437 default 0xC0000000 1438 1439config NR_CPUS 1440 int "Maximum number of CPUs (2-32)" 1441 range 2 32 1442 depends on SMP 1443 default "4" 1444 1445config HOTPLUG_CPU 1446 bool "Support for hot-pluggable CPUs" 1447 depends on SMP 1448 help 1449 Say Y here to experiment with turning CPUs off and on. CPUs 1450 can be controlled through /sys/devices/system/cpu. 1451 1452config ARM_PSCI 1453 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1454 depends on HAVE_ARM_SMCCC 1455 select ARM_PSCI_FW 1456 help 1457 Say Y here if you want Linux to communicate with system firmware 1458 implementing the PSCI specification for CPU-centric power 1459 management operations described in ARM document number ARM DEN 1460 0022A ("Power State Coordination Interface System Software on 1461 ARM processors"). 1462 1463# The GPIO number here must be sorted by descending number. In case of 1464# a multiplatform kernel, we just want the highest value required by the 1465# selected platforms. 1466config ARCH_NR_GPIO 1467 int 1468 default 2048 if ARCH_SOCFPGA 1469 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1470 ARCH_ZYNQ 1471 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1472 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1473 default 416 if ARCH_SUNXI 1474 default 392 if ARCH_U8500 1475 default 352 if ARCH_VT8500 1476 default 288 if ARCH_ROCKCHIP 1477 default 264 if MACH_H4700 1478 default 0 1479 help 1480 Maximum number of GPIOs in the system. 1481 1482 If unsure, leave the default value. 1483 1484config HZ_FIXED 1485 int 1486 default 200 if ARCH_EBSA110 1487 default 128 if SOC_AT91RM9200 1488 default 0 1489 1490choice 1491 depends on HZ_FIXED = 0 1492 prompt "Timer frequency" 1493 1494config HZ_100 1495 bool "100 Hz" 1496 1497config HZ_200 1498 bool "200 Hz" 1499 1500config HZ_250 1501 bool "250 Hz" 1502 1503config HZ_300 1504 bool "300 Hz" 1505 1506config HZ_500 1507 bool "500 Hz" 1508 1509config HZ_1000 1510 bool "1000 Hz" 1511 1512endchoice 1513 1514config HZ 1515 int 1516 default HZ_FIXED if HZ_FIXED != 0 1517 default 100 if HZ_100 1518 default 200 if HZ_200 1519 default 250 if HZ_250 1520 default 300 if HZ_300 1521 default 500 if HZ_500 1522 default 1000 1523 1524config SCHED_HRTICK 1525 def_bool HIGH_RES_TIMERS 1526 1527config THUMB2_KERNEL 1528 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1529 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1530 default y if CPU_THUMBONLY 1531 select ARM_UNWIND 1532 help 1533 By enabling this option, the kernel will be compiled in 1534 Thumb-2 mode. 1535 1536 If unsure, say N. 1537 1538config THUMB2_AVOID_R_ARM_THM_JUMP11 1539 bool "Work around buggy Thumb-2 short branch relocations in gas" 1540 depends on THUMB2_KERNEL && MODULES 1541 default y 1542 help 1543 Various binutils versions can resolve Thumb-2 branches to 1544 locally-defined, preemptible global symbols as short-range "b.n" 1545 branch instructions. 1546 1547 This is a problem, because there's no guarantee the final 1548 destination of the symbol, or any candidate locations for a 1549 trampoline, are within range of the branch. For this reason, the 1550 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1551 relocation in modules at all, and it makes little sense to add 1552 support. 1553 1554 The symptom is that the kernel fails with an "unsupported 1555 relocation" error when loading some modules. 1556 1557 Until fixed tools are available, passing 1558 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1559 code which hits this problem, at the cost of a bit of extra runtime 1560 stack usage in some cases. 1561 1562 The problem is described in more detail at: 1563 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1564 1565 Only Thumb-2 kernels are affected. 1566 1567 Unless you are sure your tools don't have this problem, say Y. 1568 1569config ARM_PATCH_IDIV 1570 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1571 depends on CPU_32v7 && !XIP_KERNEL 1572 default y 1573 help 1574 The ARM compiler inserts calls to __aeabi_idiv() and 1575 __aeabi_uidiv() when it needs to perform division on signed 1576 and unsigned integers. Some v7 CPUs have support for the sdiv 1577 and udiv instructions that can be used to implement those 1578 functions. 1579 1580 Enabling this option allows the kernel to modify itself to 1581 replace the first two instructions of these library functions 1582 with the sdiv or udiv plus "bx lr" instructions when the CPU 1583 it is running on supports them. Typically this will be faster 1584 and less power intensive than running the original library 1585 code to do integer division. 1586 1587config AEABI 1588 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1589 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1590 help 1591 This option allows for the kernel to be compiled using the latest 1592 ARM ABI (aka EABI). This is only useful if you are using a user 1593 space environment that is also compiled with EABI. 1594 1595 Since there are major incompatibilities between the legacy ABI and 1596 EABI, especially with regard to structure member alignment, this 1597 option also changes the kernel syscall calling convention to 1598 disambiguate both ABIs and allow for backward compatibility support 1599 (selected with CONFIG_OABI_COMPAT). 1600 1601 To use this you need GCC version 4.0.0 or later. 1602 1603config OABI_COMPAT 1604 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1605 depends on AEABI && !THUMB2_KERNEL 1606 help 1607 This option preserves the old syscall interface along with the 1608 new (ARM EABI) one. It also provides a compatibility layer to 1609 intercept syscalls that have structure arguments which layout 1610 in memory differs between the legacy ABI and the new ARM EABI 1611 (only for non "thumb" binaries). This option adds a tiny 1612 overhead to all syscalls and produces a slightly larger kernel. 1613 1614 The seccomp filter system will not be available when this is 1615 selected, since there is no way yet to sensibly distinguish 1616 between calling conventions during filtering. 1617 1618 If you know you'll be using only pure EABI user space then you 1619 can say N here. If this option is not selected and you attempt 1620 to execute a legacy ABI binary then the result will be 1621 UNPREDICTABLE (in fact it can be predicted that it won't work 1622 at all). If in doubt say N. 1623 1624config ARCH_HAS_HOLES_MEMORYMODEL 1625 bool 1626 1627config ARCH_SPARSEMEM_ENABLE 1628 bool 1629 1630config ARCH_SPARSEMEM_DEFAULT 1631 def_bool ARCH_SPARSEMEM_ENABLE 1632 1633config ARCH_SELECT_MEMORY_MODEL 1634 def_bool ARCH_SPARSEMEM_ENABLE 1635 1636config HAVE_ARCH_PFN_VALID 1637 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1638 1639config HAVE_GENERIC_GUP 1640 def_bool y 1641 depends on ARM_LPAE 1642 1643config HIGHMEM 1644 bool "High Memory Support" 1645 depends on MMU 1646 help 1647 The address space of ARM processors is only 4 Gigabytes large 1648 and it has to accommodate user address space, kernel address 1649 space as well as some memory mapped IO. That means that, if you 1650 have a large amount of physical memory and/or IO, not all of the 1651 memory can be "permanently mapped" by the kernel. The physical 1652 memory that is not permanently mapped is called "high memory". 1653 1654 Depending on the selected kernel/user memory split, minimum 1655 vmalloc space and actual amount of RAM, you may not need this 1656 option which should result in a slightly faster kernel. 1657 1658 If unsure, say n. 1659 1660config HIGHPTE 1661 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1662 depends on HIGHMEM 1663 default y 1664 help 1665 The VM uses one page of physical memory for each page table. 1666 For systems with a lot of processes, this can use a lot of 1667 precious low memory, eventually leading to low memory being 1668 consumed by page tables. Setting this option will allow 1669 user-space 2nd level page tables to reside in high memory. 1670 1671config CPU_SW_DOMAIN_PAN 1672 bool "Enable use of CPU domains to implement privileged no-access" 1673 depends on MMU && !ARM_LPAE 1674 default y 1675 help 1676 Increase kernel security by ensuring that normal kernel accesses 1677 are unable to access userspace addresses. This can help prevent 1678 use-after-free bugs becoming an exploitable privilege escalation 1679 by ensuring that magic values (such as LIST_POISON) will always 1680 fault when dereferenced. 1681 1682 CPUs with low-vector mappings use a best-efforts implementation. 1683 Their lower 1MB needs to remain accessible for the vectors, but 1684 the remainder of userspace will become appropriately inaccessible. 1685 1686config HW_PERF_EVENTS 1687 def_bool y 1688 depends on ARM_PMU 1689 1690config SYS_SUPPORTS_HUGETLBFS 1691 def_bool y 1692 depends on ARM_LPAE 1693 1694config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1695 def_bool y 1696 depends on ARM_LPAE 1697 1698config ARCH_WANT_GENERAL_HUGETLB 1699 def_bool y 1700 1701config ARM_MODULE_PLTS 1702 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1703 depends on MODULES 1704 default y 1705 help 1706 Allocate PLTs when loading modules so that jumps and calls whose 1707 targets are too far away for their relative offsets to be encoded 1708 in the instructions themselves can be bounced via veneers in the 1709 module's PLT. This allows modules to be allocated in the generic 1710 vmalloc area after the dedicated module memory area has been 1711 exhausted. The modules will use slightly more memory, but after 1712 rounding up to page size, the actual memory footprint is usually 1713 the same. 1714 1715 Disabling this is usually safe for small single-platform 1716 configurations. If unsure, say y. 1717 1718config FORCE_MAX_ZONEORDER 1719 int "Maximum zone order" 1720 default "12" if SOC_AM33XX 1721 default "9" if SA1111 || ARCH_EFM32 1722 default "11" 1723 help 1724 The kernel memory allocator divides physically contiguous memory 1725 blocks into "zones", where each zone is a power of two number of 1726 pages. This option selects the largest power of two that the kernel 1727 keeps in the memory allocator. If you need to allocate very large 1728 blocks of physically contiguous memory, then you may need to 1729 increase this value. 1730 1731 This config option is actually maximum order plus one. For example, 1732 a value of 11 means that the largest free memory block is 2^10 pages. 1733 1734config ALIGNMENT_TRAP 1735 bool 1736 depends on CPU_CP15_MMU 1737 default y if !ARCH_EBSA110 1738 select HAVE_PROC_CPU if PROC_FS 1739 help 1740 ARM processors cannot fetch/store information which is not 1741 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1742 address divisible by 4. On 32-bit ARM processors, these non-aligned 1743 fetch/store instructions will be emulated in software if you say 1744 here, which has a severe performance impact. This is necessary for 1745 correct operation of some network protocols. With an IP-only 1746 configuration it is safe to say N, otherwise say Y. 1747 1748config UACCESS_WITH_MEMCPY 1749 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1750 depends on MMU 1751 default y if CPU_FEROCEON 1752 help 1753 Implement faster copy_to_user and clear_user methods for CPU 1754 cores where a 8-word STM instruction give significantly higher 1755 memory write throughput than a sequence of individual 32bit stores. 1756 1757 A possible side effect is a slight increase in scheduling latency 1758 between threads sharing the same address space if they invoke 1759 such copy operations with large buffers. 1760 1761 However, if the CPU data cache is using a write-allocate mode, 1762 this option is unlikely to provide any performance gain. 1763 1764config SECCOMP 1765 bool 1766 prompt "Enable seccomp to safely compute untrusted bytecode" 1767 ---help--- 1768 This kernel feature is useful for number crunching applications 1769 that may need to compute untrusted bytecode during their 1770 execution. By using pipes or other transports made available to 1771 the process as file descriptors supporting the read/write 1772 syscalls, it's possible to isolate those applications in 1773 their own address space using seccomp. Once seccomp is 1774 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1775 and the task is only allowed to execute a few safe syscalls 1776 defined by each seccomp mode. 1777 1778config PARAVIRT 1779 bool "Enable paravirtualization code" 1780 help 1781 This changes the kernel so it can modify itself when it is run 1782 under a hypervisor, potentially improving performance significantly 1783 over full virtualization. 1784 1785config PARAVIRT_TIME_ACCOUNTING 1786 bool "Paravirtual steal time accounting" 1787 select PARAVIRT 1788 default n 1789 help 1790 Select this option to enable fine granularity task steal time 1791 accounting. Time spent executing other tasks in parallel with 1792 the current vCPU is discounted from the vCPU power. To account for 1793 that, there can be a small performance impact. 1794 1795 If in doubt, say N here. 1796 1797config XEN_DOM0 1798 def_bool y 1799 depends on XEN 1800 1801config XEN 1802 bool "Xen guest support on ARM" 1803 depends on ARM && AEABI && OF 1804 depends on CPU_V7 && !CPU_V6 1805 depends on !GENERIC_ATOMIC64 1806 depends on MMU 1807 select ARCH_DMA_ADDR_T_64BIT 1808 select ARM_PSCI 1809 select SWIOTLB 1810 select SWIOTLB_XEN 1811 select PARAVIRT 1812 help 1813 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1814 1815endmenu 1816 1817menu "Boot options" 1818 1819config USE_OF 1820 bool "Flattened Device Tree support" 1821 select IRQ_DOMAIN 1822 select OF 1823 help 1824 Include support for flattened device tree machine descriptions. 1825 1826config ATAGS 1827 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1828 default y 1829 help 1830 This is the traditional way of passing data to the kernel at boot 1831 time. If you are solely relying on the flattened device tree (or 1832 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1833 to remove ATAGS support from your kernel binary. If unsure, 1834 leave this to y. 1835 1836config DEPRECATED_PARAM_STRUCT 1837 bool "Provide old way to pass kernel parameters" 1838 depends on ATAGS 1839 help 1840 This was deprecated in 2001 and announced to live on for 5 years. 1841 Some old boot loaders still use this way. 1842 1843# Compressed boot loader in ROM. Yes, we really want to ask about 1844# TEXT and BSS so we preserve their values in the config files. 1845config ZBOOT_ROM_TEXT 1846 hex "Compressed ROM boot loader base address" 1847 default "0" 1848 help 1849 The physical address at which the ROM-able zImage is to be 1850 placed in the target. Platforms which normally make use of 1851 ROM-able zImage formats normally set this to a suitable 1852 value in their defconfig file. 1853 1854 If ZBOOT_ROM is not enabled, this has no effect. 1855 1856config ZBOOT_ROM_BSS 1857 hex "Compressed ROM boot loader BSS address" 1858 default "0" 1859 help 1860 The base address of an area of read/write memory in the target 1861 for the ROM-able zImage which must be available while the 1862 decompressor is running. It must be large enough to hold the 1863 entire decompressed kernel plus an additional 128 KiB. 1864 Platforms which normally make use of ROM-able zImage formats 1865 normally set this to a suitable value in their defconfig file. 1866 1867 If ZBOOT_ROM is not enabled, this has no effect. 1868 1869config ZBOOT_ROM 1870 bool "Compressed boot loader in ROM/flash" 1871 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1872 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1873 help 1874 Say Y here if you intend to execute your compressed kernel image 1875 (zImage) directly from ROM or flash. If unsure, say N. 1876 1877config ARM_APPENDED_DTB 1878 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1879 depends on OF 1880 help 1881 With this option, the boot code will look for a device tree binary 1882 (DTB) appended to zImage 1883 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1884 1885 This is meant as a backward compatibility convenience for those 1886 systems with a bootloader that can't be upgraded to accommodate 1887 the documented boot protocol using a device tree. 1888 1889 Beware that there is very little in terms of protection against 1890 this option being confused by leftover garbage in memory that might 1891 look like a DTB header after a reboot if no actual DTB is appended 1892 to zImage. Do not leave this option active in a production kernel 1893 if you don't intend to always append a DTB. Proper passing of the 1894 location into r2 of a bootloader provided DTB is always preferable 1895 to this option. 1896 1897config ARM_ATAG_DTB_COMPAT 1898 bool "Supplement the appended DTB with traditional ATAG information" 1899 depends on ARM_APPENDED_DTB 1900 help 1901 Some old bootloaders can't be updated to a DTB capable one, yet 1902 they provide ATAGs with memory configuration, the ramdisk address, 1903 the kernel cmdline string, etc. Such information is dynamically 1904 provided by the bootloader and can't always be stored in a static 1905 DTB. To allow a device tree enabled kernel to be used with such 1906 bootloaders, this option allows zImage to extract the information 1907 from the ATAG list and store it at run time into the appended DTB. 1908 1909choice 1910 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1911 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1912 1913config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1914 bool "Use bootloader kernel arguments if available" 1915 help 1916 Uses the command-line options passed by the boot loader instead of 1917 the device tree bootargs property. If the boot loader doesn't provide 1918 any, the device tree bootargs property will be used. 1919 1920config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1921 bool "Extend with bootloader kernel arguments" 1922 help 1923 The command-line arguments provided by the boot loader will be 1924 appended to the the device tree bootargs property. 1925 1926endchoice 1927 1928config CMDLINE 1929 string "Default kernel command string" 1930 default "" 1931 help 1932 On some architectures (EBSA110 and CATS), there is currently no way 1933 for the boot loader to pass arguments to the kernel. For these 1934 architectures, you should supply some command-line options at build 1935 time by entering them here. As a minimum, you should specify the 1936 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1937 1938choice 1939 prompt "Kernel command line type" if CMDLINE != "" 1940 default CMDLINE_FROM_BOOTLOADER 1941 depends on ATAGS 1942 1943config CMDLINE_FROM_BOOTLOADER 1944 bool "Use bootloader kernel arguments if available" 1945 help 1946 Uses the command-line options passed by the boot loader. If 1947 the boot loader doesn't provide any, the default kernel command 1948 string provided in CMDLINE will be used. 1949 1950config CMDLINE_EXTEND 1951 bool "Extend bootloader kernel arguments" 1952 help 1953 The command-line arguments provided by the boot loader will be 1954 appended to the default kernel command string. 1955 1956config CMDLINE_FORCE 1957 bool "Always use the default kernel command string" 1958 help 1959 Always use the default kernel command string, even if the boot 1960 loader passes other arguments to the kernel. 1961 This is useful if you cannot or don't want to change the 1962 command-line options your boot loader passes to the kernel. 1963endchoice 1964 1965config XIP_KERNEL 1966 bool "Kernel Execute-In-Place from ROM" 1967 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1968 help 1969 Execute-In-Place allows the kernel to run from non-volatile storage 1970 directly addressable by the CPU, such as NOR flash. This saves RAM 1971 space since the text section of the kernel is not loaded from flash 1972 to RAM. Read-write sections, such as the data section and stack, 1973 are still copied to RAM. The XIP kernel is not compressed since 1974 it has to run directly from flash, so it will take more space to 1975 store it. The flash address used to link the kernel object files, 1976 and for storing it, is configuration dependent. Therefore, if you 1977 say Y here, you must know the proper physical address where to 1978 store the kernel image depending on your own flash memory usage. 1979 1980 Also note that the make target becomes "make xipImage" rather than 1981 "make zImage" or "make Image". The final kernel binary to put in 1982 ROM memory will be arch/arm/boot/xipImage. 1983 1984 If unsure, say N. 1985 1986config XIP_PHYS_ADDR 1987 hex "XIP Kernel Physical Location" 1988 depends on XIP_KERNEL 1989 default "0x00080000" 1990 help 1991 This is the physical address in your flash memory the kernel will 1992 be linked for and stored to. This address is dependent on your 1993 own flash usage. 1994 1995config XIP_DEFLATED_DATA 1996 bool "Store kernel .data section compressed in ROM" 1997 depends on XIP_KERNEL 1998 select ZLIB_INFLATE 1999 help 2000 Before the kernel is actually executed, its .data section has to be 2001 copied to RAM from ROM. This option allows for storing that data 2002 in compressed form and decompressed to RAM rather than merely being 2003 copied, saving some precious ROM space. A possible drawback is a 2004 slightly longer boot delay. 2005 2006config KEXEC 2007 bool "Kexec system call (EXPERIMENTAL)" 2008 depends on (!SMP || PM_SLEEP_SMP) 2009 depends on !CPU_V7M 2010 select KEXEC_CORE 2011 help 2012 kexec is a system call that implements the ability to shutdown your 2013 current kernel, and to start another kernel. It is like a reboot 2014 but it is independent of the system firmware. And like a reboot 2015 you can start any kernel with it, not just Linux. 2016 2017 It is an ongoing process to be certain the hardware in a machine 2018 is properly shutdown, so do not be surprised if this code does not 2019 initially work for you. 2020 2021config ATAGS_PROC 2022 bool "Export atags in procfs" 2023 depends on ATAGS && KEXEC 2024 default y 2025 help 2026 Should the atags used to boot the kernel be exported in an "atags" 2027 file in procfs. Useful with kexec. 2028 2029config CRASH_DUMP 2030 bool "Build kdump crash kernel (EXPERIMENTAL)" 2031 help 2032 Generate crash dump after being started by kexec. This should 2033 be normally only set in special crash dump kernels which are 2034 loaded in the main kernel with kexec-tools into a specially 2035 reserved region and then later executed after a crash by 2036 kdump/kexec. The crash dump kernel must be compiled to a 2037 memory address not used by the main kernel 2038 2039 For more details see Documentation/kdump/kdump.txt 2040 2041config AUTO_ZRELADDR 2042 bool "Auto calculation of the decompressed kernel image address" 2043 help 2044 ZRELADDR is the physical address where the decompressed kernel 2045 image will be placed. If AUTO_ZRELADDR is selected, the address 2046 will be determined at run-time by masking the current IP with 2047 0xf8000000. This assumes the zImage being placed in the first 128MB 2048 from start of memory. 2049 2050config EFI_STUB 2051 bool 2052 2053config EFI 2054 bool "UEFI runtime support" 2055 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2056 select UCS2_STRING 2057 select EFI_PARAMS_FROM_FDT 2058 select EFI_STUB 2059 select EFI_ARMSTUB 2060 select EFI_RUNTIME_WRAPPERS 2061 ---help--- 2062 This option provides support for runtime services provided 2063 by UEFI firmware (such as non-volatile variables, realtime 2064 clock, and platform reset). A UEFI stub is also provided to 2065 allow the kernel to be booted as an EFI application. This 2066 is only useful for kernels that may run on systems that have 2067 UEFI firmware. 2068 2069config DMI 2070 bool "Enable support for SMBIOS (DMI) tables" 2071 depends on EFI 2072 default y 2073 help 2074 This enables SMBIOS/DMI feature for systems. 2075 2076 This option is only useful on systems that have UEFI firmware. 2077 However, even with this option, the resultant kernel should 2078 continue to boot on existing non-UEFI platforms. 2079 2080 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2081 i.e., the the practice of identifying the platform via DMI to 2082 decide whether certain workarounds for buggy hardware and/or 2083 firmware need to be enabled. This would require the DMI subsystem 2084 to be enabled much earlier than we do on ARM, which is non-trivial. 2085 2086endmenu 2087 2088menu "CPU Power Management" 2089 2090source "drivers/cpufreq/Kconfig" 2091 2092source "drivers/cpuidle/Kconfig" 2093 2094endmenu 2095 2096menu "Floating point emulation" 2097 2098comment "At least one emulation must be selected" 2099 2100config FPE_NWFPE 2101 bool "NWFPE math emulation" 2102 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2103 ---help--- 2104 Say Y to include the NWFPE floating point emulator in the kernel. 2105 This is necessary to run most binaries. Linux does not currently 2106 support floating point hardware so you need to say Y here even if 2107 your machine has an FPA or floating point co-processor podule. 2108 2109 You may say N here if you are going to load the Acorn FPEmulator 2110 early in the bootup. 2111 2112config FPE_NWFPE_XP 2113 bool "Support extended precision" 2114 depends on FPE_NWFPE 2115 help 2116 Say Y to include 80-bit support in the kernel floating-point 2117 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2118 Note that gcc does not generate 80-bit operations by default, 2119 so in most cases this option only enlarges the size of the 2120 floating point emulator without any good reason. 2121 2122 You almost surely want to say N here. 2123 2124config FPE_FASTFPE 2125 bool "FastFPE math emulation (EXPERIMENTAL)" 2126 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2127 ---help--- 2128 Say Y here to include the FAST floating point emulator in the kernel. 2129 This is an experimental much faster emulator which now also has full 2130 precision for the mantissa. It does not support any exceptions. 2131 It is very simple, and approximately 3-6 times faster than NWFPE. 2132 2133 It should be sufficient for most programs. It may be not suitable 2134 for scientific calculations, but you have to check this for yourself. 2135 If you do not feel you need a faster FP emulation you should better 2136 choose NWFPE. 2137 2138config VFP 2139 bool "VFP-format floating point maths" 2140 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2141 help 2142 Say Y to include VFP support code in the kernel. This is needed 2143 if your hardware includes a VFP unit. 2144 2145 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2146 release notes and additional status information. 2147 2148 Say N if your target does not have VFP hardware. 2149 2150config VFPv3 2151 bool 2152 depends on VFP 2153 default y if CPU_V7 2154 2155config NEON 2156 bool "Advanced SIMD (NEON) Extension support" 2157 depends on VFPv3 && CPU_V7 2158 help 2159 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2160 Extension. 2161 2162config KERNEL_MODE_NEON 2163 bool "Support for NEON in kernel mode" 2164 depends on NEON && AEABI 2165 help 2166 Say Y to include support for NEON in kernel mode. 2167 2168endmenu 2169 2170menu "Power management options" 2171 2172source "kernel/power/Kconfig" 2173 2174config ARCH_SUSPEND_POSSIBLE 2175 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2176 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2177 def_bool y 2178 2179config ARM_CPU_SUSPEND 2180 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2181 depends on ARCH_SUSPEND_POSSIBLE 2182 2183config ARCH_HIBERNATION_POSSIBLE 2184 bool 2185 depends on MMU 2186 default y if ARCH_SUSPEND_POSSIBLE 2187 2188endmenu 2189 2190source "drivers/firmware/Kconfig" 2191 2192if CRYPTO 2193source "arch/arm/crypto/Kconfig" 2194endif 2195 2196source "arch/arm/kvm/Kconfig" 2197