1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_REMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_PROBE 64 select GENERIC_IRQ_SHOW 65 select GENERIC_IRQ_SHOW_LEVEL 66 select GENERIC_LIB_DEVMEM_IS_ALLOWED 67 select GENERIC_PCI_IOMAP 68 select GENERIC_SCHED_CLOCK 69 select GENERIC_SMP_IDLE_THREAD 70 select HARDIRQS_SW_RESEND 71 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 72 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 73 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 75 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 77 select HAVE_ARCH_MMAP_RND_BITS if MMU 78 select HAVE_ARCH_PFN_VALID 79 select HAVE_ARCH_SECCOMP 80 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 81 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 82 select HAVE_ARCH_TRACEHOOK 83 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 84 select HAVE_ARM_SMCCC if CPU_V7 85 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 86 select HAVE_CONTEXT_TRACKING 87 select HAVE_C_RECORDMCOUNT 88 select HAVE_BUILDTIME_MCOUNT_SORT 89 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 90 select HAVE_DMA_CONTIGUOUS if MMU 91 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 92 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 93 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 94 select HAVE_EXIT_THREAD 95 select HAVE_FAST_GUP if ARM_LPAE 96 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 97 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 98 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) 99 select HAVE_GCC_PLUGINS 100 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 101 select HAVE_IRQ_TIME_ACCOUNTING 102 select HAVE_KERNEL_GZIP 103 select HAVE_KERNEL_LZ4 104 select HAVE_KERNEL_LZMA 105 select HAVE_KERNEL_LZO 106 select HAVE_KERNEL_XZ 107 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 108 select HAVE_KRETPROBES if HAVE_KPROBES 109 select HAVE_MOD_ARCH_SPECIFIC 110 select HAVE_NMI 111 select HAVE_OPTPROBES if !THUMB2_KERNEL 112 select HAVE_PERF_EVENTS 113 select HAVE_PERF_REGS 114 select HAVE_PERF_USER_STACK_DUMP 115 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 116 select HAVE_REGS_AND_STACK_ACCESS_API 117 select HAVE_RSEQ 118 select HAVE_STACKPROTECTOR 119 select HAVE_SYSCALL_TRACEPOINTS 120 select HAVE_UID16 121 select HAVE_VIRT_CPU_ACCOUNTING_GEN 122 select IRQ_FORCED_THREADING 123 select MODULES_USE_ELF_REL 124 select NEED_DMA_MAP_STATE 125 select OF_EARLY_FLATTREE if OF 126 select OLD_SIGACTION 127 select OLD_SIGSUSPEND3 128 select PCI_SYSCALL if PCI 129 select PERF_USE_VMALLOC 130 select RTC_LIB 131 select SYS_SUPPORTS_APM_EMULATION 132 select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO 133 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 134 # Above selects are sorted alphabetically; please add new ones 135 # according to that. Thanks. 136 help 137 The ARM series is a line of low-power-consumption RISC chip designs 138 licensed by ARM Ltd and targeted at embedded applications and 139 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 140 manufactured, but legacy ARM-based PC hardware remains popular in 141 Europe. There is an ARM Linux project with a web page at 142 <http://www.arm.linux.org.uk/>. 143 144config ARM_HAS_SG_CHAIN 145 bool 146 147config ARM_DMA_USE_IOMMU 148 bool 149 select ARM_HAS_SG_CHAIN 150 select NEED_SG_DMA_LENGTH 151 152if ARM_DMA_USE_IOMMU 153 154config ARM_DMA_IOMMU_ALIGNMENT 155 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 156 range 4 9 157 default 8 158 help 159 DMA mapping framework by default aligns all buffers to the smallest 160 PAGE_SIZE order which is greater than or equal to the requested buffer 161 size. This works well for buffers up to a few hundreds kilobytes, but 162 for larger buffers it just a waste of address space. Drivers which has 163 relatively small addressing window (like 64Mib) might run out of 164 virtual space with just a few allocations. 165 166 With this parameter you can specify the maximum PAGE_SIZE order for 167 DMA IOMMU buffers. Larger buffers will be aligned only to this 168 specified order. The order is expressed as a power of two multiplied 169 by the PAGE_SIZE. 170 171endif 172 173config SYS_SUPPORTS_APM_EMULATION 174 bool 175 176config HAVE_TCM 177 bool 178 select GENERIC_ALLOCATOR 179 180config HAVE_PROC_CPU 181 bool 182 183config NO_IOPORT_MAP 184 bool 185 186config SBUS 187 bool 188 189config STACKTRACE_SUPPORT 190 bool 191 default y 192 193config LOCKDEP_SUPPORT 194 bool 195 default y 196 197config ARCH_HAS_ILOG2_U32 198 bool 199 200config ARCH_HAS_ILOG2_U64 201 bool 202 203config ARCH_HAS_BANDGAP 204 bool 205 206config FIX_EARLYCON_MEM 207 def_bool y if MMU 208 209config GENERIC_HWEIGHT 210 bool 211 default y 212 213config GENERIC_CALIBRATE_DELAY 214 bool 215 default y 216 217config ARCH_MAY_HAVE_PC_FDC 218 bool 219 220config ARCH_SUPPORTS_UPROBES 221 def_bool y 222 223config ARCH_HAS_DMA_SET_COHERENT_MASK 224 bool 225 226config GENERIC_ISA_DMA 227 bool 228 229config FIQ 230 bool 231 232config NEED_RET_TO_USER 233 bool 234 235config ARCH_MTD_XIP 236 bool 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 help 243 Patch phys-to-virt and virt-to-phys translation functions at 244 boot and module load time according to the position of the 245 kernel in system memory. 246 247 This can only be used with non-XIP MMU kernels where the base 248 of physical memory is at a 2 MiB boundary. 249 250 Only disable this option if you know that you do not require 251 this feature (eg, building a kernel for a single machine) and 252 you need to shrink the kernel to the minimal size. 253 254config NEED_MACH_IO_H 255 bool 256 help 257 Select this when mach/io.h is required to provide special 258 definitions for this platform. The need for mach/io.h should 259 be avoided when possible. 260 261config NEED_MACH_MEMORY_H 262 bool 263 help 264 Select this when mach/memory.h is required to provide special 265 definitions for this platform. The need for mach/memory.h should 266 be avoided when possible. 267 268config PHYS_OFFSET 269 hex "Physical address of main memory" if MMU 270 depends on !ARM_PATCH_PHYS_VIRT 271 default DRAM_BASE if !MMU 272 default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x30000000 if ARCH_S3C24XX 275 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 276 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 277 default 0 278 help 279 Please provide the physical address corresponding to the 280 location of main memory in your system. 281 282config GENERIC_BUG 283 def_bool y 284 depends on BUG 285 286config PGTABLE_LEVELS 287 int 288 default 3 if ARM_LPAE 289 default 2 290 291menu "System Type" 292 293config MMU 294 bool "MMU-based Paged Memory Management Support" 295 default y 296 help 297 Select if you want MMU-based virtualised addressing space 298 support by paged memory management. If unsure, say 'Y'. 299 300config ARCH_MMAP_RND_BITS_MIN 301 default 8 302 303config ARCH_MMAP_RND_BITS_MAX 304 default 14 if PAGE_OFFSET=0x40000000 305 default 15 if PAGE_OFFSET=0x80000000 306 default 16 307 308# 309# The "ARM system type" choice list is ordered alphabetically by option 310# text. Please add new entries in the option alphabetic order. 311# 312choice 313 prompt "ARM system type" 314 default ARM_SINGLE_ARMV7M if !MMU 315 default ARCH_MULTIPLATFORM if MMU 316 317config ARCH_MULTIPLATFORM 318 bool "Allow multiple platforms to be selected" 319 depends on MMU 320 select ARCH_FLATMEM_ENABLE 321 select ARCH_SPARSEMEM_ENABLE 322 select ARCH_SELECT_MEMORY_MODEL 323 select ARM_HAS_SG_CHAIN 324 select ARM_PATCH_PHYS_VIRT 325 select AUTO_ZRELADDR 326 select TIMER_OF 327 select COMMON_CLK 328 select GENERIC_IRQ_MULTI_HANDLER 329 select HAVE_PCI 330 select PCI_DOMAINS_GENERIC if PCI 331 select SPARSE_IRQ 332 select USE_OF 333 334config ARM_SINGLE_ARMV7M 335 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 336 depends on !MMU 337 select ARM_NVIC 338 select AUTO_ZRELADDR 339 select TIMER_OF 340 select COMMON_CLK 341 select CPU_V7M 342 select NO_IOPORT_MAP 343 select SPARSE_IRQ 344 select USE_OF 345 346config ARCH_EP93XX 347 bool "EP93xx-based" 348 select ARCH_SPARSEMEM_ENABLE 349 select ARM_AMBA 350 imply ARM_PATCH_PHYS_VIRT 351 select ARM_VIC 352 select GENERIC_IRQ_MULTI_HANDLER 353 select AUTO_ZRELADDR 354 select CLKSRC_MMIO 355 select CPU_ARM920T 356 select GPIOLIB 357 select COMMON_CLK 358 help 359 This enables support for the Cirrus EP93xx series of CPUs. 360 361config ARCH_FOOTBRIDGE 362 bool "FootBridge" 363 select CPU_SA110 364 select FOOTBRIDGE 365 select NEED_MACH_IO_H if !MMU 366 select NEED_MACH_MEMORY_H 367 help 368 Support for systems based on the DC21285 companion chip 369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 370 371config ARCH_IOP32X 372 bool "IOP32x-based" 373 depends on MMU 374 select CPU_XSCALE 375 select GPIO_IOP 376 select GPIOLIB 377 select NEED_RET_TO_USER 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 depends on MMU 387 select ARCH_HAS_DMA_SET_COHERENT_MASK 388 select ARCH_SUPPORTS_BIG_ENDIAN 389 select CPU_XSCALE 390 select DMABOUNCE if PCI 391 select GENERIC_IRQ_MULTI_HANDLER 392 select GPIO_IXP4XX 393 select GPIOLIB 394 select HAVE_PCI 395 select IXP4XX_IRQ 396 select IXP4XX_TIMER 397 # With the new PCI driver this is not needed 398 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 399 select USB_EHCI_BIG_ENDIAN_DESC 400 select USB_EHCI_BIG_ENDIAN_MMIO 401 help 402 Support for Intel's IXP4XX (XScale) family of processors. 403 404config ARCH_DOVE 405 bool "Marvell Dove" 406 select CPU_PJ4 407 select GENERIC_IRQ_MULTI_HANDLER 408 select GPIOLIB 409 select HAVE_PCI 410 select MVEBU_MBUS 411 select PINCTRL 412 select PINCTRL_DOVE 413 select PLAT_ORION_LEGACY 414 select SPARSE_IRQ 415 select PM_GENERIC_DOMAINS if PM 416 help 417 Support for the Marvell Dove SoC 88AP510 418 419config ARCH_PXA 420 bool "PXA2xx/PXA3xx-based" 421 depends on MMU 422 select ARCH_MTD_XIP 423 select ARM_CPU_SUSPEND if PM 424 select AUTO_ZRELADDR 425 select COMMON_CLK 426 select CLKSRC_PXA 427 select CLKSRC_MMIO 428 select TIMER_OF 429 select CPU_XSCALE if !CPU_XSC3 430 select GENERIC_IRQ_MULTI_HANDLER 431 select GPIO_PXA 432 select GPIOLIB 433 select IRQ_DOMAIN 434 select PLAT_PXA 435 select SPARSE_IRQ 436 help 437 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 438 439config ARCH_RPC 440 bool "RiscPC" 441 depends on MMU 442 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 443 select ARCH_ACORN 444 select ARCH_MAY_HAVE_PC_FDC 445 select ARCH_SPARSEMEM_ENABLE 446 select ARM_HAS_SG_CHAIN 447 select CPU_SA110 448 select FIQ 449 select HAVE_PATA_PLATFORM 450 select ISA_DMA_API 451 select LEGACY_TIMER_TICK 452 select NEED_MACH_IO_H 453 select NEED_MACH_MEMORY_H 454 select NO_IOPORT_MAP 455 help 456 On the Acorn Risc-PC, Linux can support the internal IDE disk and 457 CD-ROM interface, serial and parallel port, and the floppy drive. 458 459config ARCH_SA1100 460 bool "SA1100-based" 461 select ARCH_MTD_XIP 462 select ARCH_SPARSEMEM_ENABLE 463 select CLKSRC_MMIO 464 select CLKSRC_PXA 465 select TIMER_OF if OF 466 select COMMON_CLK 467 select CPU_FREQ 468 select CPU_SA1100 469 select GENERIC_IRQ_MULTI_HANDLER 470 select GPIOLIB 471 select IRQ_DOMAIN 472 select ISA 473 select NEED_MACH_MEMORY_H 474 select SPARSE_IRQ 475 help 476 Support for StrongARM 11x0 based boards. 477 478config ARCH_S3C24XX 479 bool "Samsung S3C24XX SoCs" 480 select ATAGS 481 select CLKSRC_SAMSUNG_PWM 482 select GPIO_SAMSUNG 483 select GPIOLIB 484 select GENERIC_IRQ_MULTI_HANDLER 485 select NEED_MACH_IO_H 486 select S3C2410_WATCHDOG 487 select SAMSUNG_ATAGS 488 select USE_OF 489 select WATCHDOG 490 help 491 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 492 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 493 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 494 Samsung SMDK2410 development board (and derivatives). 495 496config ARCH_OMAP1 497 bool "TI OMAP1" 498 depends on MMU 499 select ARCH_OMAP 500 select CLKSRC_MMIO 501 select GENERIC_IRQ_CHIP 502 select GENERIC_IRQ_MULTI_HANDLER 503 select GPIOLIB 504 select HAVE_LEGACY_CLK 505 select IRQ_DOMAIN 506 select NEED_MACH_IO_H if PCCARD 507 select NEED_MACH_MEMORY_H 508 select SPARSE_IRQ 509 help 510 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 511 512endchoice 513 514menu "Multiple platform selection" 515 depends on ARCH_MULTIPLATFORM 516 517comment "CPU Core family selection" 518 519config ARCH_MULTI_V4 520 bool "ARMv4 based platforms (FA526)" 521 depends on !ARCH_MULTI_V6_V7 522 select ARCH_MULTI_V4_V5 523 select CPU_FA526 524 525config ARCH_MULTI_V4T 526 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 527 depends on !ARCH_MULTI_V6_V7 528 select ARCH_MULTI_V4_V5 529 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 530 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 531 CPU_ARM925T || CPU_ARM940T) 532 533config ARCH_MULTI_V5 534 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 535 depends on !ARCH_MULTI_V6_V7 536 select ARCH_MULTI_V4_V5 537 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 538 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 539 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 540 541config ARCH_MULTI_V4_V5 542 bool 543 544config ARCH_MULTI_V6 545 bool "ARMv6 based platforms (ARM11)" 546 select ARCH_MULTI_V6_V7 547 select CPU_V6K 548 549config ARCH_MULTI_V7 550 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 551 default y 552 select ARCH_MULTI_V6_V7 553 select CPU_V7 554 select HAVE_SMP 555 556config ARCH_MULTI_V6_V7 557 bool 558 select MIGHT_HAVE_CACHE_L2X0 559 560config ARCH_MULTI_CPU_AUTO 561 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 562 select ARCH_MULTI_V5 563 564endmenu 565 566config ARCH_VIRT 567 bool "Dummy Virtual Machine" 568 depends on ARCH_MULTI_V7 569 select ARM_AMBA 570 select ARM_GIC 571 select ARM_GIC_V2M if PCI 572 select ARM_GIC_V3 573 select ARM_GIC_V3_ITS if PCI 574 select ARM_PSCI 575 select HAVE_ARM_ARCH_TIMER 576 select ARCH_SUPPORTS_BIG_ENDIAN 577 578# 579# This is sorted alphabetically by mach-* pathname. However, plat-* 580# Kconfigs may be included either alphabetically (according to the 581# plat- suffix) or along side the corresponding mach-* source. 582# 583source "arch/arm/mach-actions/Kconfig" 584 585source "arch/arm/mach-alpine/Kconfig" 586 587source "arch/arm/mach-artpec/Kconfig" 588 589source "arch/arm/mach-asm9260/Kconfig" 590 591source "arch/arm/mach-aspeed/Kconfig" 592 593source "arch/arm/mach-at91/Kconfig" 594 595source "arch/arm/mach-axxia/Kconfig" 596 597source "arch/arm/mach-bcm/Kconfig" 598 599source "arch/arm/mach-berlin/Kconfig" 600 601source "arch/arm/mach-clps711x/Kconfig" 602 603source "arch/arm/mach-cns3xxx/Kconfig" 604 605source "arch/arm/mach-davinci/Kconfig" 606 607source "arch/arm/mach-digicolor/Kconfig" 608 609source "arch/arm/mach-dove/Kconfig" 610 611source "arch/arm/mach-ep93xx/Kconfig" 612 613source "arch/arm/mach-exynos/Kconfig" 614 615source "arch/arm/mach-footbridge/Kconfig" 616 617source "arch/arm/mach-gemini/Kconfig" 618 619source "arch/arm/mach-highbank/Kconfig" 620 621source "arch/arm/mach-hisi/Kconfig" 622 623source "arch/arm/mach-imx/Kconfig" 624 625source "arch/arm/mach-integrator/Kconfig" 626 627source "arch/arm/mach-iop32x/Kconfig" 628 629source "arch/arm/mach-ixp4xx/Kconfig" 630 631source "arch/arm/mach-keystone/Kconfig" 632 633source "arch/arm/mach-lpc32xx/Kconfig" 634 635source "arch/arm/mach-mediatek/Kconfig" 636 637source "arch/arm/mach-meson/Kconfig" 638 639source "arch/arm/mach-milbeaut/Kconfig" 640 641source "arch/arm/mach-mmp/Kconfig" 642 643source "arch/arm/mach-moxart/Kconfig" 644 645source "arch/arm/mach-mstar/Kconfig" 646 647source "arch/arm/mach-mv78xx0/Kconfig" 648 649source "arch/arm/mach-mvebu/Kconfig" 650 651source "arch/arm/mach-mxs/Kconfig" 652 653source "arch/arm/mach-nomadik/Kconfig" 654 655source "arch/arm/mach-npcm/Kconfig" 656 657source "arch/arm/mach-nspire/Kconfig" 658 659source "arch/arm/plat-omap/Kconfig" 660 661source "arch/arm/mach-omap1/Kconfig" 662 663source "arch/arm/mach-omap2/Kconfig" 664 665source "arch/arm/mach-orion5x/Kconfig" 666 667source "arch/arm/mach-oxnas/Kconfig" 668 669source "arch/arm/mach-pxa/Kconfig" 670source "arch/arm/plat-pxa/Kconfig" 671 672source "arch/arm/mach-qcom/Kconfig" 673 674source "arch/arm/mach-rda/Kconfig" 675 676source "arch/arm/mach-realtek/Kconfig" 677 678source "arch/arm/mach-realview/Kconfig" 679 680source "arch/arm/mach-rockchip/Kconfig" 681 682source "arch/arm/mach-s3c/Kconfig" 683 684source "arch/arm/mach-s5pv210/Kconfig" 685 686source "arch/arm/mach-sa1100/Kconfig" 687 688source "arch/arm/mach-shmobile/Kconfig" 689 690source "arch/arm/mach-socfpga/Kconfig" 691 692source "arch/arm/mach-spear/Kconfig" 693 694source "arch/arm/mach-sti/Kconfig" 695 696source "arch/arm/mach-stm32/Kconfig" 697 698source "arch/arm/mach-sunxi/Kconfig" 699 700source "arch/arm/mach-tegra/Kconfig" 701 702source "arch/arm/mach-uniphier/Kconfig" 703 704source "arch/arm/mach-ux500/Kconfig" 705 706source "arch/arm/mach-versatile/Kconfig" 707 708source "arch/arm/mach-vexpress/Kconfig" 709 710source "arch/arm/mach-vt8500/Kconfig" 711 712source "arch/arm/mach-zynq/Kconfig" 713 714# ARMv7-M architecture 715config ARCH_LPC18XX 716 bool "NXP LPC18xx/LPC43xx" 717 depends on ARM_SINGLE_ARMV7M 718 select ARCH_HAS_RESET_CONTROLLER 719 select ARM_AMBA 720 select CLKSRC_LPC32XX 721 select PINCTRL 722 help 723 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 724 high performance microcontrollers. 725 726config ARCH_MPS2 727 bool "ARM MPS2 platform" 728 depends on ARM_SINGLE_ARMV7M 729 select ARM_AMBA 730 select CLKSRC_MPS2 731 help 732 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 733 with a range of available cores like Cortex-M3/M4/M7. 734 735 Please, note that depends which Application Note is used memory map 736 for the platform may vary, so adjustment of RAM base might be needed. 737 738# Definitions to make life easier 739config ARCH_ACORN 740 bool 741 742config PLAT_IOP 743 bool 744 745config PLAT_ORION 746 bool 747 select CLKSRC_MMIO 748 select COMMON_CLK 749 select GENERIC_IRQ_CHIP 750 select IRQ_DOMAIN 751 752config PLAT_ORION_LEGACY 753 bool 754 select PLAT_ORION 755 756config PLAT_PXA 757 bool 758 759config PLAT_VERSATILE 760 bool 761 762source "arch/arm/mm/Kconfig" 763 764config IWMMXT 765 bool "Enable iWMMXt support" 766 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 767 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 768 help 769 Enable support for iWMMXt context switching at run time if 770 running on a CPU that supports it. 771 772if !MMU 773source "arch/arm/Kconfig-nommu" 774endif 775 776config PJ4B_ERRATA_4742 777 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 778 depends on CPU_PJ4B && MACH_ARMADA_370 779 default y 780 help 781 When coming out of either a Wait for Interrupt (WFI) or a Wait for 782 Event (WFE) IDLE states, a specific timing sensitivity exists between 783 the retiring WFI/WFE instructions and the newly issued subsequent 784 instructions. This sensitivity can result in a CPU hang scenario. 785 Workaround: 786 The software must insert either a Data Synchronization Barrier (DSB) 787 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 788 instruction 789 790config ARM_ERRATA_326103 791 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 792 depends on CPU_V6 793 help 794 Executing a SWP instruction to read-only memory does not set bit 11 795 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 796 treat the access as a read, preventing a COW from occurring and 797 causing the faulting task to livelock. 798 799config ARM_ERRATA_411920 800 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 801 depends on CPU_V6 || CPU_V6K 802 help 803 Invalidation of the Instruction Cache operation can 804 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 805 It does not affect the MPCore. This option enables the ARM Ltd. 806 recommended workaround. 807 808config ARM_ERRATA_430973 809 bool "ARM errata: Stale prediction on replaced interworking branch" 810 depends on CPU_V7 811 help 812 This option enables the workaround for the 430973 Cortex-A8 813 r1p* erratum. If a code sequence containing an ARM/Thumb 814 interworking branch is replaced with another code sequence at the 815 same virtual address, whether due to self-modifying code or virtual 816 to physical address re-mapping, Cortex-A8 does not recover from the 817 stale interworking branch prediction. This results in Cortex-A8 818 executing the new code sequence in the incorrect ARM or Thumb state. 819 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 820 and also flushes the branch target cache at every context switch. 821 Note that setting specific bits in the ACTLR register may not be 822 available in non-secure mode. 823 824config ARM_ERRATA_458693 825 bool "ARM errata: Processor deadlock when a false hazard is created" 826 depends on CPU_V7 827 depends on !ARCH_MULTIPLATFORM 828 help 829 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 830 erratum. For very specific sequences of memory operations, it is 831 possible for a hazard condition intended for a cache line to instead 832 be incorrectly associated with a different cache line. This false 833 hazard might then cause a processor deadlock. The workaround enables 834 the L1 caching of the NEON accesses and disables the PLD instruction 835 in the ACTLR register. Note that setting specific bits in the ACTLR 836 register may not be available in non-secure mode. 837 838config ARM_ERRATA_460075 839 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 840 depends on CPU_V7 841 depends on !ARCH_MULTIPLATFORM 842 help 843 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 844 erratum. Any asynchronous access to the L2 cache may encounter a 845 situation in which recent store transactions to the L2 cache are lost 846 and overwritten with stale memory contents from external memory. The 847 workaround disables the write-allocate mode for the L2 cache via the 848 ACTLR register. Note that setting specific bits in the ACTLR register 849 may not be available in non-secure mode. 850 851config ARM_ERRATA_742230 852 bool "ARM errata: DMB operation may be faulty" 853 depends on CPU_V7 && SMP 854 depends on !ARCH_MULTIPLATFORM 855 help 856 This option enables the workaround for the 742230 Cortex-A9 857 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 858 between two write operations may not ensure the correct visibility 859 ordering of the two writes. This workaround sets a specific bit in 860 the diagnostic register of the Cortex-A9 which causes the DMB 861 instruction to behave as a DSB, ensuring the correct behaviour of 862 the two writes. 863 864config ARM_ERRATA_742231 865 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 866 depends on CPU_V7 && SMP 867 depends on !ARCH_MULTIPLATFORM 868 help 869 This option enables the workaround for the 742231 Cortex-A9 870 (r2p0..r2p2) erratum. Under certain conditions, specific to the 871 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 872 accessing some data located in the same cache line, may get corrupted 873 data due to bad handling of the address hazard when the line gets 874 replaced from one of the CPUs at the same time as another CPU is 875 accessing it. This workaround sets specific bits in the diagnostic 876 register of the Cortex-A9 which reduces the linefill issuing 877 capabilities of the processor. 878 879config ARM_ERRATA_643719 880 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 881 depends on CPU_V7 && SMP 882 default y 883 help 884 This option enables the workaround for the 643719 Cortex-A9 (prior to 885 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 886 register returns zero when it should return one. The workaround 887 corrects this value, ensuring cache maintenance operations which use 888 it behave as intended and avoiding data corruption. 889 890config ARM_ERRATA_720789 891 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 892 depends on CPU_V7 893 help 894 This option enables the workaround for the 720789 Cortex-A9 (prior to 895 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 896 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 897 As a consequence of this erratum, some TLB entries which should be 898 invalidated are not, resulting in an incoherency in the system page 899 tables. The workaround changes the TLB flushing routines to invalidate 900 entries regardless of the ASID. 901 902config ARM_ERRATA_743622 903 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 904 depends on CPU_V7 905 depends on !ARCH_MULTIPLATFORM 906 help 907 This option enables the workaround for the 743622 Cortex-A9 908 (r2p*) erratum. Under very rare conditions, a faulty 909 optimisation in the Cortex-A9 Store Buffer may lead to data 910 corruption. This workaround sets a specific bit in the diagnostic 911 register of the Cortex-A9 which disables the Store Buffer 912 optimisation, preventing the defect from occurring. This has no 913 visible impact on the overall performance or power consumption of the 914 processor. 915 916config ARM_ERRATA_751472 917 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 918 depends on CPU_V7 919 depends on !ARCH_MULTIPLATFORM 920 help 921 This option enables the workaround for the 751472 Cortex-A9 (prior 922 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 923 completion of a following broadcasted operation if the second 924 operation is received by a CPU before the ICIALLUIS has completed, 925 potentially leading to corrupted entries in the cache or TLB. 926 927config ARM_ERRATA_754322 928 bool "ARM errata: possible faulty MMU translations following an ASID switch" 929 depends on CPU_V7 930 help 931 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 932 r3p*) erratum. A speculative memory access may cause a page table walk 933 which starts prior to an ASID switch but completes afterwards. This 934 can populate the micro-TLB with a stale entry which may be hit with 935 the new ASID. This workaround places two dsb instructions in the mm 936 switching code so that no page table walks can cross the ASID switch. 937 938config ARM_ERRATA_754327 939 bool "ARM errata: no automatic Store Buffer drain" 940 depends on CPU_V7 && SMP 941 help 942 This option enables the workaround for the 754327 Cortex-A9 (prior to 943 r2p0) erratum. The Store Buffer does not have any automatic draining 944 mechanism and therefore a livelock may occur if an external agent 945 continuously polls a memory location waiting to observe an update. 946 This workaround defines cpu_relax() as smp_mb(), preventing correctly 947 written polling loops from denying visibility of updates to memory. 948 949config ARM_ERRATA_364296 950 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 951 depends on CPU_V6 952 help 953 This options enables the workaround for the 364296 ARM1136 954 r0p2 erratum (possible cache data corruption with 955 hit-under-miss enabled). It sets the undocumented bit 31 in 956 the auxiliary control register and the FI bit in the control 957 register, thus disabling hit-under-miss without putting the 958 processor into full low interrupt latency mode. ARM11MPCore 959 is not affected. 960 961config ARM_ERRATA_764369 962 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 963 depends on CPU_V7 && SMP 964 help 965 This option enables the workaround for erratum 764369 966 affecting Cortex-A9 MPCore with two or more processors (all 967 current revisions). Under certain timing circumstances, a data 968 cache line maintenance operation by MVA targeting an Inner 969 Shareable memory region may fail to proceed up to either the 970 Point of Coherency or to the Point of Unification of the 971 system. This workaround adds a DSB instruction before the 972 relevant cache maintenance functions and sets a specific bit 973 in the diagnostic control register of the SCU. 974 975config ARM_ERRATA_775420 976 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 980 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 981 operation aborts with MMU exception, it might cause the processor 982 to deadlock. This workaround puts DSB before executing ISB if 983 an abort may occur on cache maintenance. 984 985config ARM_ERRATA_798181 986 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 987 depends on CPU_V7 && SMP 988 help 989 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 990 adequately shooting down all use of the old entries. This 991 option enables the Linux kernel workaround for this erratum 992 which sends an IPI to the CPUs that are running the same ASID 993 as the one being invalidated. 994 995config ARM_ERRATA_773022 996 bool "ARM errata: incorrect instructions may be executed from loop buffer" 997 depends on CPU_V7 998 help 999 This option enables the workaround for the 773022 Cortex-A15 1000 (up to r0p4) erratum. In certain rare sequences of code, the 1001 loop buffer may deliver incorrect instructions. This 1002 workaround disables the loop buffer to avoid the erratum. 1003 1004config ARM_ERRATA_818325_852422 1005 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1006 depends on CPU_V7 1007 help 1008 This option enables the workaround for: 1009 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1010 instruction might deadlock. Fixed in r0p1. 1011 - Cortex-A12 852422: Execution of a sequence of instructions might 1012 lead to either a data corruption or a CPU deadlock. Not fixed in 1013 any Cortex-A12 cores yet. 1014 This workaround for all both errata involves setting bit[12] of the 1015 Feature Register. This bit disables an optimisation applied to a 1016 sequence of 2 instructions that use opposing condition codes. 1017 1018config ARM_ERRATA_821420 1019 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1020 depends on CPU_V7 1021 help 1022 This option enables the workaround for the 821420 Cortex-A12 1023 (all revs) erratum. In very rare timing conditions, a sequence 1024 of VMOV to Core registers instructions, for which the second 1025 one is in the shadow of a branch or abort, can lead to a 1026 deadlock when the VMOV instructions are issued out-of-order. 1027 1028config ARM_ERRATA_825619 1029 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1030 depends on CPU_V7 1031 help 1032 This option enables the workaround for the 825619 Cortex-A12 1033 (all revs) erratum. Within rare timing constraints, executing a 1034 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1035 and Device/Strongly-Ordered loads and stores might cause deadlock 1036 1037config ARM_ERRATA_857271 1038 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1039 depends on CPU_V7 1040 help 1041 This option enables the workaround for the 857271 Cortex-A12 1042 (all revs) erratum. Under very rare timing conditions, the CPU might 1043 hang. The workaround is expected to have a < 1% performance impact. 1044 1045config ARM_ERRATA_852421 1046 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1047 depends on CPU_V7 1048 help 1049 This option enables the workaround for the 852421 Cortex-A17 1050 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1051 execution of a DMB ST instruction might fail to properly order 1052 stores from GroupA and stores from GroupB. 1053 1054config ARM_ERRATA_852423 1055 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1056 depends on CPU_V7 1057 help 1058 This option enables the workaround for: 1059 - Cortex-A17 852423: Execution of a sequence of instructions might 1060 lead to either a data corruption or a CPU deadlock. Not fixed in 1061 any Cortex-A17 cores yet. 1062 This is identical to Cortex-A12 erratum 852422. It is a separate 1063 config option from the A12 erratum due to the way errata are checked 1064 for and handled. 1065 1066config ARM_ERRATA_857272 1067 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1068 depends on CPU_V7 1069 help 1070 This option enables the workaround for the 857272 Cortex-A17 erratum. 1071 This erratum is not known to be fixed in any A17 revision. 1072 This is identical to Cortex-A12 erratum 857271. It is a separate 1073 config option from the A12 erratum due to the way errata are checked 1074 for and handled. 1075 1076endmenu 1077 1078source "arch/arm/common/Kconfig" 1079 1080menu "Bus support" 1081 1082config ISA 1083 bool 1084 help 1085 Find out whether you have ISA slots on your motherboard. ISA is the 1086 name of a bus system, i.e. the way the CPU talks to the other stuff 1087 inside your box. Other bus systems are PCI, EISA, MicroChannel 1088 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1089 newer boards don't support it. If you have ISA, say Y, otherwise N. 1090 1091# Select ISA DMA controller support 1092config ISA_DMA 1093 bool 1094 select ISA_DMA_API 1095 1096# Select ISA DMA interface 1097config ISA_DMA_API 1098 bool 1099 1100config PCI_NANOENGINE 1101 bool "BSE nanoEngine PCI support" 1102 depends on SA1100_NANOENGINE 1103 help 1104 Enable PCI on the BSE nanoEngine board. 1105 1106config ARM_ERRATA_814220 1107 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1108 depends on CPU_V7 1109 help 1110 The v7 ARM states that all cache and branch predictor maintenance 1111 operations that do not specify an address execute, relative to 1112 each other, in program order. 1113 However, because of this erratum, an L2 set/way cache maintenance 1114 operation can overtake an L1 set/way cache maintenance operation. 1115 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1116 r0p4, r0p5. 1117 1118endmenu 1119 1120menu "Kernel Features" 1121 1122config HAVE_SMP 1123 bool 1124 help 1125 This option should be selected by machines which have an SMP- 1126 capable CPU. 1127 1128 The only effect of this option is to make the SMP-related 1129 options available to the user for configuration. 1130 1131config SMP 1132 bool "Symmetric Multi-Processing" 1133 depends on CPU_V6K || CPU_V7 1134 depends on HAVE_SMP 1135 depends on MMU || ARM_MPU 1136 select IRQ_WORK 1137 help 1138 This enables support for systems with more than one CPU. If you have 1139 a system with only one CPU, say N. If you have a system with more 1140 than one CPU, say Y. 1141 1142 If you say N here, the kernel will run on uni- and multiprocessor 1143 machines, but will use only one CPU of a multiprocessor machine. If 1144 you say Y here, the kernel will run on many, but not all, 1145 uniprocessor machines. On a uniprocessor machine, the kernel 1146 will run faster if you say N here. 1147 1148 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1149 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1150 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1151 1152 If you don't know what to do here, say N. 1153 1154config SMP_ON_UP 1155 bool "Allow booting SMP kernel on uniprocessor systems" 1156 depends on SMP && !XIP_KERNEL && MMU 1157 default y 1158 help 1159 SMP kernels contain instructions which fail on non-SMP processors. 1160 Enabling this option allows the kernel to modify itself to make 1161 these instructions safe. Disabling it allows about 1K of space 1162 savings. 1163 1164 If you don't know what to do here, say Y. 1165 1166 1167config CURRENT_POINTER_IN_TPIDRURO 1168 def_bool y 1169 depends on SMP && CPU_32v6K && !CPU_V6 1170 1171config ARM_CPU_TOPOLOGY 1172 bool "Support cpu topology definition" 1173 depends on SMP && CPU_V7 1174 default y 1175 help 1176 Support ARM cpu topology definition. The MPIDR register defines 1177 affinity between processors which is then used to describe the cpu 1178 topology of an ARM System. 1179 1180config SCHED_MC 1181 bool "Multi-core scheduler support" 1182 depends on ARM_CPU_TOPOLOGY 1183 help 1184 Multi-core scheduler support improves the CPU scheduler's decision 1185 making when dealing with multi-core CPU chips at a cost of slightly 1186 increased overhead in some places. If unsure say N here. 1187 1188config SCHED_SMT 1189 bool "SMT scheduler support" 1190 depends on ARM_CPU_TOPOLOGY 1191 help 1192 Improves the CPU scheduler's decision making when dealing with 1193 MultiThreading at a cost of slightly increased overhead in some 1194 places. If unsure say N here. 1195 1196config HAVE_ARM_SCU 1197 bool 1198 help 1199 This option enables support for the ARM snoop control unit 1200 1201config HAVE_ARM_ARCH_TIMER 1202 bool "Architected timer support" 1203 depends on CPU_V7 1204 select ARM_ARCH_TIMER 1205 help 1206 This option enables support for the ARM architected timer 1207 1208config HAVE_ARM_TWD 1209 bool 1210 help 1211 This options enables support for the ARM timer and watchdog unit 1212 1213config MCPM 1214 bool "Multi-Cluster Power Management" 1215 depends on CPU_V7 && SMP 1216 help 1217 This option provides the common power management infrastructure 1218 for (multi-)cluster based systems, such as big.LITTLE based 1219 systems. 1220 1221config MCPM_QUAD_CLUSTER 1222 bool 1223 depends on MCPM 1224 help 1225 To avoid wasting resources unnecessarily, MCPM only supports up 1226 to 2 clusters by default. 1227 Platforms with 3 or 4 clusters that use MCPM must select this 1228 option to allow the additional clusters to be managed. 1229 1230config BIG_LITTLE 1231 bool "big.LITTLE support (Experimental)" 1232 depends on CPU_V7 && SMP 1233 select MCPM 1234 help 1235 This option enables support selections for the big.LITTLE 1236 system architecture. 1237 1238config BL_SWITCHER 1239 bool "big.LITTLE switcher support" 1240 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1241 select CPU_PM 1242 help 1243 The big.LITTLE "switcher" provides the core functionality to 1244 transparently handle transition between a cluster of A15's 1245 and a cluster of A7's in a big.LITTLE system. 1246 1247config BL_SWITCHER_DUMMY_IF 1248 tristate "Simple big.LITTLE switcher user interface" 1249 depends on BL_SWITCHER && DEBUG_KERNEL 1250 help 1251 This is a simple and dummy char dev interface to control 1252 the big.LITTLE switcher core code. It is meant for 1253 debugging purposes only. 1254 1255choice 1256 prompt "Memory split" 1257 depends on MMU 1258 default VMSPLIT_3G 1259 help 1260 Select the desired split between kernel and user memory. 1261 1262 If you are not absolutely sure what you are doing, leave this 1263 option alone! 1264 1265 config VMSPLIT_3G 1266 bool "3G/1G user/kernel split" 1267 config VMSPLIT_3G_OPT 1268 depends on !ARM_LPAE 1269 bool "3G/1G user/kernel split (for full 1G low memory)" 1270 config VMSPLIT_2G 1271 bool "2G/2G user/kernel split" 1272 config VMSPLIT_1G 1273 bool "1G/3G user/kernel split" 1274endchoice 1275 1276config PAGE_OFFSET 1277 hex 1278 default PHYS_OFFSET if !MMU 1279 default 0x40000000 if VMSPLIT_1G 1280 default 0x80000000 if VMSPLIT_2G 1281 default 0xB0000000 if VMSPLIT_3G_OPT 1282 default 0xC0000000 1283 1284config KASAN_SHADOW_OFFSET 1285 hex 1286 depends on KASAN 1287 default 0x1f000000 if PAGE_OFFSET=0x40000000 1288 default 0x5f000000 if PAGE_OFFSET=0x80000000 1289 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1290 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1291 default 0xffffffff 1292 1293config NR_CPUS 1294 int "Maximum number of CPUs (2-32)" 1295 range 2 16 if DEBUG_KMAP_LOCAL 1296 range 2 32 if !DEBUG_KMAP_LOCAL 1297 depends on SMP 1298 default "4" 1299 help 1300 The maximum number of CPUs that the kernel can support. 1301 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1302 debugging is enabled, which uses half of the per-CPU fixmap 1303 slots as guard regions. 1304 1305config HOTPLUG_CPU 1306 bool "Support for hot-pluggable CPUs" 1307 depends on SMP 1308 select GENERIC_IRQ_MIGRATION 1309 help 1310 Say Y here to experiment with turning CPUs off and on. CPUs 1311 can be controlled through /sys/devices/system/cpu. 1312 1313config ARM_PSCI 1314 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1315 depends on HAVE_ARM_SMCCC 1316 select ARM_PSCI_FW 1317 help 1318 Say Y here if you want Linux to communicate with system firmware 1319 implementing the PSCI specification for CPU-centric power 1320 management operations described in ARM document number ARM DEN 1321 0022A ("Power State Coordination Interface System Software on 1322 ARM processors"). 1323 1324# The GPIO number here must be sorted by descending number. In case of 1325# a multiplatform kernel, we just want the highest value required by the 1326# selected platforms. 1327config ARCH_NR_GPIO 1328 int 1329 default 2048 if ARCH_INTEL_SOCFPGA 1330 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1331 ARCH_ZYNQ || ARCH_ASPEED 1332 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1333 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1334 default 416 if ARCH_SUNXI 1335 default 392 if ARCH_U8500 1336 default 352 if ARCH_VT8500 1337 default 288 if ARCH_ROCKCHIP 1338 default 264 if MACH_H4700 1339 default 0 1340 help 1341 Maximum number of GPIOs in the system. 1342 1343 If unsure, leave the default value. 1344 1345config HZ_FIXED 1346 int 1347 default 128 if SOC_AT91RM9200 1348 default 0 1349 1350choice 1351 depends on HZ_FIXED = 0 1352 prompt "Timer frequency" 1353 1354config HZ_100 1355 bool "100 Hz" 1356 1357config HZ_200 1358 bool "200 Hz" 1359 1360config HZ_250 1361 bool "250 Hz" 1362 1363config HZ_300 1364 bool "300 Hz" 1365 1366config HZ_500 1367 bool "500 Hz" 1368 1369config HZ_1000 1370 bool "1000 Hz" 1371 1372endchoice 1373 1374config HZ 1375 int 1376 default HZ_FIXED if HZ_FIXED != 0 1377 default 100 if HZ_100 1378 default 200 if HZ_200 1379 default 250 if HZ_250 1380 default 300 if HZ_300 1381 default 500 if HZ_500 1382 default 1000 1383 1384config SCHED_HRTICK 1385 def_bool HIGH_RES_TIMERS 1386 1387config THUMB2_KERNEL 1388 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1389 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1390 default y if CPU_THUMBONLY 1391 select ARM_UNWIND 1392 help 1393 By enabling this option, the kernel will be compiled in 1394 Thumb-2 mode. 1395 1396 If unsure, say N. 1397 1398config ARM_PATCH_IDIV 1399 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1400 depends on CPU_32v7 && !XIP_KERNEL 1401 default y 1402 help 1403 The ARM compiler inserts calls to __aeabi_idiv() and 1404 __aeabi_uidiv() when it needs to perform division on signed 1405 and unsigned integers. Some v7 CPUs have support for the sdiv 1406 and udiv instructions that can be used to implement those 1407 functions. 1408 1409 Enabling this option allows the kernel to modify itself to 1410 replace the first two instructions of these library functions 1411 with the sdiv or udiv plus "bx lr" instructions when the CPU 1412 it is running on supports them. Typically this will be faster 1413 and less power intensive than running the original library 1414 code to do integer division. 1415 1416config AEABI 1417 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1418 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1419 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1420 help 1421 This option allows for the kernel to be compiled using the latest 1422 ARM ABI (aka EABI). This is only useful if you are using a user 1423 space environment that is also compiled with EABI. 1424 1425 Since there are major incompatibilities between the legacy ABI and 1426 EABI, especially with regard to structure member alignment, this 1427 option also changes the kernel syscall calling convention to 1428 disambiguate both ABIs and allow for backward compatibility support 1429 (selected with CONFIG_OABI_COMPAT). 1430 1431 To use this you need GCC version 4.0.0 or later. 1432 1433config OABI_COMPAT 1434 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1435 depends on AEABI && !THUMB2_KERNEL 1436 help 1437 This option preserves the old syscall interface along with the 1438 new (ARM EABI) one. It also provides a compatibility layer to 1439 intercept syscalls that have structure arguments which layout 1440 in memory differs between the legacy ABI and the new ARM EABI 1441 (only for non "thumb" binaries). This option adds a tiny 1442 overhead to all syscalls and produces a slightly larger kernel. 1443 1444 The seccomp filter system will not be available when this is 1445 selected, since there is no way yet to sensibly distinguish 1446 between calling conventions during filtering. 1447 1448 If you know you'll be using only pure EABI user space then you 1449 can say N here. If this option is not selected and you attempt 1450 to execute a legacy ABI binary then the result will be 1451 UNPREDICTABLE (in fact it can be predicted that it won't work 1452 at all). If in doubt say N. 1453 1454config ARCH_SELECT_MEMORY_MODEL 1455 bool 1456 1457config ARCH_FLATMEM_ENABLE 1458 bool 1459 1460config ARCH_SPARSEMEM_ENABLE 1461 bool 1462 select SPARSEMEM_STATIC if SPARSEMEM 1463 1464config HIGHMEM 1465 bool "High Memory Support" 1466 depends on MMU 1467 select KMAP_LOCAL 1468 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1469 help 1470 The address space of ARM processors is only 4 Gigabytes large 1471 and it has to accommodate user address space, kernel address 1472 space as well as some memory mapped IO. That means that, if you 1473 have a large amount of physical memory and/or IO, not all of the 1474 memory can be "permanently mapped" by the kernel. The physical 1475 memory that is not permanently mapped is called "high memory". 1476 1477 Depending on the selected kernel/user memory split, minimum 1478 vmalloc space and actual amount of RAM, you may not need this 1479 option which should result in a slightly faster kernel. 1480 1481 If unsure, say n. 1482 1483config HIGHPTE 1484 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1485 depends on HIGHMEM 1486 default y 1487 help 1488 The VM uses one page of physical memory for each page table. 1489 For systems with a lot of processes, this can use a lot of 1490 precious low memory, eventually leading to low memory being 1491 consumed by page tables. Setting this option will allow 1492 user-space 2nd level page tables to reside in high memory. 1493 1494config CPU_SW_DOMAIN_PAN 1495 bool "Enable use of CPU domains to implement privileged no-access" 1496 depends on MMU && !ARM_LPAE 1497 default y 1498 help 1499 Increase kernel security by ensuring that normal kernel accesses 1500 are unable to access userspace addresses. This can help prevent 1501 use-after-free bugs becoming an exploitable privilege escalation 1502 by ensuring that magic values (such as LIST_POISON) will always 1503 fault when dereferenced. 1504 1505 CPUs with low-vector mappings use a best-efforts implementation. 1506 Their lower 1MB needs to remain accessible for the vectors, but 1507 the remainder of userspace will become appropriately inaccessible. 1508 1509config HW_PERF_EVENTS 1510 def_bool y 1511 depends on ARM_PMU 1512 1513config ARM_MODULE_PLTS 1514 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1515 depends on MODULES 1516 default y 1517 help 1518 Allocate PLTs when loading modules so that jumps and calls whose 1519 targets are too far away for their relative offsets to be encoded 1520 in the instructions themselves can be bounced via veneers in the 1521 module's PLT. This allows modules to be allocated in the generic 1522 vmalloc area after the dedicated module memory area has been 1523 exhausted. The modules will use slightly more memory, but after 1524 rounding up to page size, the actual memory footprint is usually 1525 the same. 1526 1527 Disabling this is usually safe for small single-platform 1528 configurations. If unsure, say y. 1529 1530config FORCE_MAX_ZONEORDER 1531 int "Maximum zone order" 1532 default "12" if SOC_AM33XX 1533 default "9" if SA1111 1534 default "11" 1535 help 1536 The kernel memory allocator divides physically contiguous memory 1537 blocks into "zones", where each zone is a power of two number of 1538 pages. This option selects the largest power of two that the kernel 1539 keeps in the memory allocator. If you need to allocate very large 1540 blocks of physically contiguous memory, then you may need to 1541 increase this value. 1542 1543 This config option is actually maximum order plus one. For example, 1544 a value of 11 means that the largest free memory block is 2^10 pages. 1545 1546config ALIGNMENT_TRAP 1547 def_bool CPU_CP15_MMU 1548 select HAVE_PROC_CPU if PROC_FS 1549 help 1550 ARM processors cannot fetch/store information which is not 1551 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1552 address divisible by 4. On 32-bit ARM processors, these non-aligned 1553 fetch/store instructions will be emulated in software if you say 1554 here, which has a severe performance impact. This is necessary for 1555 correct operation of some network protocols. With an IP-only 1556 configuration it is safe to say N, otherwise say Y. 1557 1558config UACCESS_WITH_MEMCPY 1559 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1560 depends on MMU 1561 default y if CPU_FEROCEON 1562 help 1563 Implement faster copy_to_user and clear_user methods for CPU 1564 cores where a 8-word STM instruction give significantly higher 1565 memory write throughput than a sequence of individual 32bit stores. 1566 1567 A possible side effect is a slight increase in scheduling latency 1568 between threads sharing the same address space if they invoke 1569 such copy operations with large buffers. 1570 1571 However, if the CPU data cache is using a write-allocate mode, 1572 this option is unlikely to provide any performance gain. 1573 1574config PARAVIRT 1575 bool "Enable paravirtualization code" 1576 help 1577 This changes the kernel so it can modify itself when it is run 1578 under a hypervisor, potentially improving performance significantly 1579 over full virtualization. 1580 1581config PARAVIRT_TIME_ACCOUNTING 1582 bool "Paravirtual steal time accounting" 1583 select PARAVIRT 1584 help 1585 Select this option to enable fine granularity task steal time 1586 accounting. Time spent executing other tasks in parallel with 1587 the current vCPU is discounted from the vCPU power. To account for 1588 that, there can be a small performance impact. 1589 1590 If in doubt, say N here. 1591 1592config XEN_DOM0 1593 def_bool y 1594 depends on XEN 1595 1596config XEN 1597 bool "Xen guest support on ARM" 1598 depends on ARM && AEABI && OF 1599 depends on CPU_V7 && !CPU_V6 1600 depends on !GENERIC_ATOMIC64 1601 depends on MMU 1602 select ARCH_DMA_ADDR_T_64BIT 1603 select ARM_PSCI 1604 select SWIOTLB 1605 select SWIOTLB_XEN 1606 select PARAVIRT 1607 help 1608 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1609 1610config STACKPROTECTOR_PER_TASK 1611 bool "Use a unique stack canary value for each task" 1612 depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA 1613 select GCC_PLUGIN_ARM_SSP_PER_TASK 1614 default y 1615 help 1616 Due to the fact that GCC uses an ordinary symbol reference from 1617 which to load the value of the stack canary, this value can only 1618 change at reboot time on SMP systems, and all tasks running in the 1619 kernel's address space are forced to use the same canary value for 1620 the entire duration that the system is up. 1621 1622 Enable this option to switch to a different method that uses a 1623 different canary value for each task. 1624 1625endmenu 1626 1627menu "Boot options" 1628 1629config USE_OF 1630 bool "Flattened Device Tree support" 1631 select IRQ_DOMAIN 1632 select OF 1633 help 1634 Include support for flattened device tree machine descriptions. 1635 1636config ATAGS 1637 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1638 default y 1639 help 1640 This is the traditional way of passing data to the kernel at boot 1641 time. If you are solely relying on the flattened device tree (or 1642 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1643 to remove ATAGS support from your kernel binary. If unsure, 1644 leave this to y. 1645 1646config DEPRECATED_PARAM_STRUCT 1647 bool "Provide old way to pass kernel parameters" 1648 depends on ATAGS 1649 help 1650 This was deprecated in 2001 and announced to live on for 5 years. 1651 Some old boot loaders still use this way. 1652 1653# Compressed boot loader in ROM. Yes, we really want to ask about 1654# TEXT and BSS so we preserve their values in the config files. 1655config ZBOOT_ROM_TEXT 1656 hex "Compressed ROM boot loader base address" 1657 default 0x0 1658 help 1659 The physical address at which the ROM-able zImage is to be 1660 placed in the target. Platforms which normally make use of 1661 ROM-able zImage formats normally set this to a suitable 1662 value in their defconfig file. 1663 1664 If ZBOOT_ROM is not enabled, this has no effect. 1665 1666config ZBOOT_ROM_BSS 1667 hex "Compressed ROM boot loader BSS address" 1668 default 0x0 1669 help 1670 The base address of an area of read/write memory in the target 1671 for the ROM-able zImage which must be available while the 1672 decompressor is running. It must be large enough to hold the 1673 entire decompressed kernel plus an additional 128 KiB. 1674 Platforms which normally make use of ROM-able zImage formats 1675 normally set this to a suitable value in their defconfig file. 1676 1677 If ZBOOT_ROM is not enabled, this has no effect. 1678 1679config ZBOOT_ROM 1680 bool "Compressed boot loader in ROM/flash" 1681 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1682 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1683 help 1684 Say Y here if you intend to execute your compressed kernel image 1685 (zImage) directly from ROM or flash. If unsure, say N. 1686 1687config ARM_APPENDED_DTB 1688 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1689 depends on OF 1690 help 1691 With this option, the boot code will look for a device tree binary 1692 (DTB) appended to zImage 1693 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1694 1695 This is meant as a backward compatibility convenience for those 1696 systems with a bootloader that can't be upgraded to accommodate 1697 the documented boot protocol using a device tree. 1698 1699 Beware that there is very little in terms of protection against 1700 this option being confused by leftover garbage in memory that might 1701 look like a DTB header after a reboot if no actual DTB is appended 1702 to zImage. Do not leave this option active in a production kernel 1703 if you don't intend to always append a DTB. Proper passing of the 1704 location into r2 of a bootloader provided DTB is always preferable 1705 to this option. 1706 1707config ARM_ATAG_DTB_COMPAT 1708 bool "Supplement the appended DTB with traditional ATAG information" 1709 depends on ARM_APPENDED_DTB 1710 help 1711 Some old bootloaders can't be updated to a DTB capable one, yet 1712 they provide ATAGs with memory configuration, the ramdisk address, 1713 the kernel cmdline string, etc. Such information is dynamically 1714 provided by the bootloader and can't always be stored in a static 1715 DTB. To allow a device tree enabled kernel to be used with such 1716 bootloaders, this option allows zImage to extract the information 1717 from the ATAG list and store it at run time into the appended DTB. 1718 1719choice 1720 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1721 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1722 1723config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1724 bool "Use bootloader kernel arguments if available" 1725 help 1726 Uses the command-line options passed by the boot loader instead of 1727 the device tree bootargs property. If the boot loader doesn't provide 1728 any, the device tree bootargs property will be used. 1729 1730config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1731 bool "Extend with bootloader kernel arguments" 1732 help 1733 The command-line arguments provided by the boot loader will be 1734 appended to the the device tree bootargs property. 1735 1736endchoice 1737 1738config CMDLINE 1739 string "Default kernel command string" 1740 default "" 1741 help 1742 On some architectures (e.g. CATS), there is currently no way 1743 for the boot loader to pass arguments to the kernel. For these 1744 architectures, you should supply some command-line options at build 1745 time by entering them here. As a minimum, you should specify the 1746 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1747 1748choice 1749 prompt "Kernel command line type" if CMDLINE != "" 1750 default CMDLINE_FROM_BOOTLOADER 1751 depends on ATAGS 1752 1753config CMDLINE_FROM_BOOTLOADER 1754 bool "Use bootloader kernel arguments if available" 1755 help 1756 Uses the command-line options passed by the boot loader. If 1757 the boot loader doesn't provide any, the default kernel command 1758 string provided in CMDLINE will be used. 1759 1760config CMDLINE_EXTEND 1761 bool "Extend bootloader kernel arguments" 1762 help 1763 The command-line arguments provided by the boot loader will be 1764 appended to the default kernel command string. 1765 1766config CMDLINE_FORCE 1767 bool "Always use the default kernel command string" 1768 help 1769 Always use the default kernel command string, even if the boot 1770 loader passes other arguments to the kernel. 1771 This is useful if you cannot or don't want to change the 1772 command-line options your boot loader passes to the kernel. 1773endchoice 1774 1775config XIP_KERNEL 1776 bool "Kernel Execute-In-Place from ROM" 1777 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1778 help 1779 Execute-In-Place allows the kernel to run from non-volatile storage 1780 directly addressable by the CPU, such as NOR flash. This saves RAM 1781 space since the text section of the kernel is not loaded from flash 1782 to RAM. Read-write sections, such as the data section and stack, 1783 are still copied to RAM. The XIP kernel is not compressed since 1784 it has to run directly from flash, so it will take more space to 1785 store it. The flash address used to link the kernel object files, 1786 and for storing it, is configuration dependent. Therefore, if you 1787 say Y here, you must know the proper physical address where to 1788 store the kernel image depending on your own flash memory usage. 1789 1790 Also note that the make target becomes "make xipImage" rather than 1791 "make zImage" or "make Image". The final kernel binary to put in 1792 ROM memory will be arch/arm/boot/xipImage. 1793 1794 If unsure, say N. 1795 1796config XIP_PHYS_ADDR 1797 hex "XIP Kernel Physical Location" 1798 depends on XIP_KERNEL 1799 default "0x00080000" 1800 help 1801 This is the physical address in your flash memory the kernel will 1802 be linked for and stored to. This address is dependent on your 1803 own flash usage. 1804 1805config XIP_DEFLATED_DATA 1806 bool "Store kernel .data section compressed in ROM" 1807 depends on XIP_KERNEL 1808 select ZLIB_INFLATE 1809 help 1810 Before the kernel is actually executed, its .data section has to be 1811 copied to RAM from ROM. This option allows for storing that data 1812 in compressed form and decompressed to RAM rather than merely being 1813 copied, saving some precious ROM space. A possible drawback is a 1814 slightly longer boot delay. 1815 1816config KEXEC 1817 bool "Kexec system call (EXPERIMENTAL)" 1818 depends on (!SMP || PM_SLEEP_SMP) 1819 depends on MMU 1820 select KEXEC_CORE 1821 help 1822 kexec is a system call that implements the ability to shutdown your 1823 current kernel, and to start another kernel. It is like a reboot 1824 but it is independent of the system firmware. And like a reboot 1825 you can start any kernel with it, not just Linux. 1826 1827 It is an ongoing process to be certain the hardware in a machine 1828 is properly shutdown, so do not be surprised if this code does not 1829 initially work for you. 1830 1831config ATAGS_PROC 1832 bool "Export atags in procfs" 1833 depends on ATAGS && KEXEC 1834 default y 1835 help 1836 Should the atags used to boot the kernel be exported in an "atags" 1837 file in procfs. Useful with kexec. 1838 1839config CRASH_DUMP 1840 bool "Build kdump crash kernel (EXPERIMENTAL)" 1841 help 1842 Generate crash dump after being started by kexec. This should 1843 be normally only set in special crash dump kernels which are 1844 loaded in the main kernel with kexec-tools into a specially 1845 reserved region and then later executed after a crash by 1846 kdump/kexec. The crash dump kernel must be compiled to a 1847 memory address not used by the main kernel 1848 1849 For more details see Documentation/admin-guide/kdump/kdump.rst 1850 1851config AUTO_ZRELADDR 1852 bool "Auto calculation of the decompressed kernel image address" 1853 help 1854 ZRELADDR is the physical address where the decompressed kernel 1855 image will be placed. If AUTO_ZRELADDR is selected, the address 1856 will be determined at run-time, either by masking the current IP 1857 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1858 This assumes the zImage being placed in the first 128MB from 1859 start of memory. 1860 1861config EFI_STUB 1862 bool 1863 1864config EFI 1865 bool "UEFI runtime support" 1866 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1867 select UCS2_STRING 1868 select EFI_PARAMS_FROM_FDT 1869 select EFI_STUB 1870 select EFI_GENERIC_STUB 1871 select EFI_RUNTIME_WRAPPERS 1872 help 1873 This option provides support for runtime services provided 1874 by UEFI firmware (such as non-volatile variables, realtime 1875 clock, and platform reset). A UEFI stub is also provided to 1876 allow the kernel to be booted as an EFI application. This 1877 is only useful for kernels that may run on systems that have 1878 UEFI firmware. 1879 1880config DMI 1881 bool "Enable support for SMBIOS (DMI) tables" 1882 depends on EFI 1883 default y 1884 help 1885 This enables SMBIOS/DMI feature for systems. 1886 1887 This option is only useful on systems that have UEFI firmware. 1888 However, even with this option, the resultant kernel should 1889 continue to boot on existing non-UEFI platforms. 1890 1891 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1892 i.e., the the practice of identifying the platform via DMI to 1893 decide whether certain workarounds for buggy hardware and/or 1894 firmware need to be enabled. This would require the DMI subsystem 1895 to be enabled much earlier than we do on ARM, which is non-trivial. 1896 1897endmenu 1898 1899menu "CPU Power Management" 1900 1901source "drivers/cpufreq/Kconfig" 1902 1903source "drivers/cpuidle/Kconfig" 1904 1905endmenu 1906 1907menu "Floating point emulation" 1908 1909comment "At least one emulation must be selected" 1910 1911config FPE_NWFPE 1912 bool "NWFPE math emulation" 1913 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1914 help 1915 Say Y to include the NWFPE floating point emulator in the kernel. 1916 This is necessary to run most binaries. Linux does not currently 1917 support floating point hardware so you need to say Y here even if 1918 your machine has an FPA or floating point co-processor podule. 1919 1920 You may say N here if you are going to load the Acorn FPEmulator 1921 early in the bootup. 1922 1923config FPE_NWFPE_XP 1924 bool "Support extended precision" 1925 depends on FPE_NWFPE 1926 help 1927 Say Y to include 80-bit support in the kernel floating-point 1928 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1929 Note that gcc does not generate 80-bit operations by default, 1930 so in most cases this option only enlarges the size of the 1931 floating point emulator without any good reason. 1932 1933 You almost surely want to say N here. 1934 1935config FPE_FASTFPE 1936 bool "FastFPE math emulation (EXPERIMENTAL)" 1937 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1938 help 1939 Say Y here to include the FAST floating point emulator in the kernel. 1940 This is an experimental much faster emulator which now also has full 1941 precision for the mantissa. It does not support any exceptions. 1942 It is very simple, and approximately 3-6 times faster than NWFPE. 1943 1944 It should be sufficient for most programs. It may be not suitable 1945 for scientific calculations, but you have to check this for yourself. 1946 If you do not feel you need a faster FP emulation you should better 1947 choose NWFPE. 1948 1949config VFP 1950 bool "VFP-format floating point maths" 1951 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1952 help 1953 Say Y to include VFP support code in the kernel. This is needed 1954 if your hardware includes a VFP unit. 1955 1956 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1957 release notes and additional status information. 1958 1959 Say N if your target does not have VFP hardware. 1960 1961config VFPv3 1962 bool 1963 depends on VFP 1964 default y if CPU_V7 1965 1966config NEON 1967 bool "Advanced SIMD (NEON) Extension support" 1968 depends on VFPv3 && CPU_V7 1969 help 1970 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1971 Extension. 1972 1973config KERNEL_MODE_NEON 1974 bool "Support for NEON in kernel mode" 1975 depends on NEON && AEABI 1976 help 1977 Say Y to include support for NEON in kernel mode. 1978 1979endmenu 1980 1981menu "Power management options" 1982 1983source "kernel/power/Kconfig" 1984 1985config ARCH_SUSPEND_POSSIBLE 1986 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1987 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1988 def_bool y 1989 1990config ARM_CPU_SUSPEND 1991 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1992 depends on ARCH_SUSPEND_POSSIBLE 1993 1994config ARCH_HIBERNATION_POSSIBLE 1995 bool 1996 depends on MMU 1997 default y if ARCH_SUSPEND_POSSIBLE 1998 1999endmenu 2000 2001if CRYPTO 2002source "arch/arm/crypto/Kconfig" 2003endif 2004 2005source "arch/arm/Kconfig.assembler" 2006