1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_USE_MEMTEST 39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 40 select ARCH_WANT_IPC_PARSE_VERSION 41 select ARCH_WANT_LD_ORPHAN_WARN 42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 43 select BUILDTIME_TABLE_SORT if MMU 44 select CLONE_BACKWARDS 45 select CPU_PM if SUSPEND || CPU_IDLE 46 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 47 select DMA_DECLARE_COHERENT 48 select DMA_GLOBAL_POOL if !MMU 49 select DMA_OPS 50 select DMA_REMAP if MMU 51 select EDAC_SUPPORT 52 select EDAC_ATOMIC_SCRUB 53 select GENERIC_ALLOCATOR 54 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 55 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 56 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 57 select GENERIC_IRQ_IPI if SMP 58 select GENERIC_CPU_AUTOPROBE 59 select GENERIC_EARLY_IOREMAP 60 select GENERIC_IDLE_POLL_SETUP 61 select GENERIC_IRQ_PROBE 62 select GENERIC_IRQ_SHOW 63 select GENERIC_IRQ_SHOW_LEVEL 64 select GENERIC_LIB_DEVMEM_IS_ALLOWED 65 select GENERIC_PCI_IOMAP 66 select GENERIC_SCHED_CLOCK 67 select GENERIC_SMP_IDLE_THREAD 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_BUILDTIME_MCOUNT_SORT 87 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 88 select HAVE_DMA_CONTIGUOUS if MMU 89 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 90 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 91 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 92 select HAVE_EXIT_THREAD 93 select HAVE_FAST_GUP if ARM_LPAE 94 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 95 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 96 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) 97 select HAVE_GCC_PLUGINS 98 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 99 select HAVE_IRQ_TIME_ACCOUNTING 100 select HAVE_KERNEL_GZIP 101 select HAVE_KERNEL_LZ4 102 select HAVE_KERNEL_LZMA 103 select HAVE_KERNEL_LZO 104 select HAVE_KERNEL_XZ 105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 106 select HAVE_KRETPROBES if HAVE_KPROBES 107 select HAVE_MOD_ARCH_SPECIFIC 108 select HAVE_NMI 109 select HAVE_OPTPROBES if !THUMB2_KERNEL 110 select HAVE_PERF_EVENTS 111 select HAVE_PERF_REGS 112 select HAVE_PERF_USER_STACK_DUMP 113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 114 select HAVE_REGS_AND_STACK_ACCESS_API 115 select HAVE_RSEQ 116 select HAVE_STACKPROTECTOR 117 select HAVE_SYSCALL_TRACEPOINTS 118 select HAVE_UID16 119 select HAVE_VIRT_CPU_ACCOUNTING_GEN 120 select IRQ_FORCED_THREADING 121 select MODULES_USE_ELF_REL 122 select NEED_DMA_MAP_STATE 123 select OF_EARLY_FLATTREE if OF 124 select OLD_SIGACTION 125 select OLD_SIGSUSPEND3 126 select PCI_SYSCALL if PCI 127 select PERF_USE_VMALLOC 128 select RTC_LIB 129 select SYS_SUPPORTS_APM_EMULATION 130 select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO 131 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 132 # Above selects are sorted alphabetically; please add new ones 133 # according to that. Thanks. 134 help 135 The ARM series is a line of low-power-consumption RISC chip designs 136 licensed by ARM Ltd and targeted at embedded applications and 137 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 138 manufactured, but legacy ARM-based PC hardware remains popular in 139 Europe. There is an ARM Linux project with a web page at 140 <http://www.arm.linux.org.uk/>. 141 142config ARM_HAS_SG_CHAIN 143 bool 144 145config ARM_DMA_USE_IOMMU 146 bool 147 select ARM_HAS_SG_CHAIN 148 select NEED_SG_DMA_LENGTH 149 150if ARM_DMA_USE_IOMMU 151 152config ARM_DMA_IOMMU_ALIGNMENT 153 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 154 range 4 9 155 default 8 156 help 157 DMA mapping framework by default aligns all buffers to the smallest 158 PAGE_SIZE order which is greater than or equal to the requested buffer 159 size. This works well for buffers up to a few hundreds kilobytes, but 160 for larger buffers it just a waste of address space. Drivers which has 161 relatively small addressing window (like 64Mib) might run out of 162 virtual space with just a few allocations. 163 164 With this parameter you can specify the maximum PAGE_SIZE order for 165 DMA IOMMU buffers. Larger buffers will be aligned only to this 166 specified order. The order is expressed as a power of two multiplied 167 by the PAGE_SIZE. 168 169endif 170 171config SYS_SUPPORTS_APM_EMULATION 172 bool 173 174config HAVE_TCM 175 bool 176 select GENERIC_ALLOCATOR 177 178config HAVE_PROC_CPU 179 bool 180 181config NO_IOPORT_MAP 182 bool 183 184config SBUS 185 bool 186 187config STACKTRACE_SUPPORT 188 bool 189 default y 190 191config LOCKDEP_SUPPORT 192 bool 193 default y 194 195config ARCH_HAS_ILOG2_U32 196 bool 197 198config ARCH_HAS_ILOG2_U64 199 bool 200 201config ARCH_HAS_BANDGAP 202 bool 203 204config FIX_EARLYCON_MEM 205 def_bool y if MMU 206 207config GENERIC_HWEIGHT 208 bool 209 default y 210 211config GENERIC_CALIBRATE_DELAY 212 bool 213 default y 214 215config ARCH_MAY_HAVE_PC_FDC 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 2 MiB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_FOOTBRIDGE 268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 269 default 0x30000000 if ARCH_S3C24XX 270 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 271 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 272 default 0 273 help 274 Please provide the physical address corresponding to the 275 location of main memory in your system. 276 277config GENERIC_BUG 278 def_bool y 279 depends on BUG 280 281config PGTABLE_LEVELS 282 int 283 default 3 if ARM_LPAE 284 default 2 285 286menu "System Type" 287 288config MMU 289 bool "MMU-based Paged Memory Management Support" 290 default y 291 help 292 Select if you want MMU-based virtualised addressing space 293 support by paged memory management. If unsure, say 'Y'. 294 295config ARCH_MMAP_RND_BITS_MIN 296 default 8 297 298config ARCH_MMAP_RND_BITS_MAX 299 default 14 if PAGE_OFFSET=0x40000000 300 default 15 if PAGE_OFFSET=0x80000000 301 default 16 302 303# 304# The "ARM system type" choice list is ordered alphabetically by option 305# text. Please add new entries in the option alphabetic order. 306# 307choice 308 prompt "ARM system type" 309 default ARM_SINGLE_ARMV7M if !MMU 310 default ARCH_MULTIPLATFORM if MMU 311 312config ARCH_MULTIPLATFORM 313 bool "Allow multiple platforms to be selected" 314 depends on MMU 315 select ARCH_FLATMEM_ENABLE 316 select ARCH_SPARSEMEM_ENABLE 317 select ARCH_SELECT_MEMORY_MODEL 318 select ARM_HAS_SG_CHAIN 319 select ARM_PATCH_PHYS_VIRT 320 select AUTO_ZRELADDR 321 select TIMER_OF 322 select COMMON_CLK 323 select GENERIC_IRQ_MULTI_HANDLER 324 select HAVE_PCI 325 select PCI_DOMAINS_GENERIC if PCI 326 select SPARSE_IRQ 327 select USE_OF 328 329config ARM_SINGLE_ARMV7M 330 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 331 depends on !MMU 332 select ARM_NVIC 333 select AUTO_ZRELADDR 334 select TIMER_OF 335 select COMMON_CLK 336 select CPU_V7M 337 select NO_IOPORT_MAP 338 select SPARSE_IRQ 339 select USE_OF 340 341config ARCH_EP93XX 342 bool "EP93xx-based" 343 select ARCH_SPARSEMEM_ENABLE 344 select ARM_AMBA 345 imply ARM_PATCH_PHYS_VIRT 346 select ARM_VIC 347 select GENERIC_IRQ_MULTI_HANDLER 348 select AUTO_ZRELADDR 349 select CLKSRC_MMIO 350 select CPU_ARM920T 351 select GPIOLIB 352 select COMMON_CLK 353 help 354 This enables support for the Cirrus EP93xx series of CPUs. 355 356config ARCH_FOOTBRIDGE 357 bool "FootBridge" 358 select CPU_SA110 359 select FOOTBRIDGE 360 select NEED_MACH_IO_H if !MMU 361 select NEED_MACH_MEMORY_H 362 help 363 Support for systems based on the DC21285 companion chip 364 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 365 366config ARCH_IOP32X 367 bool "IOP32x-based" 368 depends on MMU 369 select CPU_XSCALE 370 select GPIO_IOP 371 select GPIOLIB 372 select NEED_RET_TO_USER 373 select FORCE_PCI 374 select PLAT_IOP 375 help 376 Support for Intel's 80219 and IOP32X (XScale) family of 377 processors. 378 379config ARCH_IXP4XX 380 bool "IXP4xx-based" 381 depends on MMU 382 select ARCH_SUPPORTS_BIG_ENDIAN 383 select ARM_PATCH_PHYS_VIRT 384 select CPU_XSCALE 385 select GENERIC_IRQ_MULTI_HANDLER 386 select GPIO_IXP4XX 387 select GPIOLIB 388 select HAVE_PCI 389 select IXP4XX_IRQ 390 select IXP4XX_TIMER 391 select SPARSE_IRQ 392 select USB_EHCI_BIG_ENDIAN_DESC 393 select USB_EHCI_BIG_ENDIAN_MMIO 394 help 395 Support for Intel's IXP4XX (XScale) family of processors. 396 397config ARCH_DOVE 398 bool "Marvell Dove" 399 select CPU_PJ4 400 select GENERIC_IRQ_MULTI_HANDLER 401 select GPIOLIB 402 select HAVE_PCI 403 select MVEBU_MBUS 404 select PINCTRL 405 select PINCTRL_DOVE 406 select PLAT_ORION_LEGACY 407 select SPARSE_IRQ 408 select PM_GENERIC_DOMAINS if PM 409 help 410 Support for the Marvell Dove SoC 88AP510 411 412config ARCH_PXA 413 bool "PXA2xx/PXA3xx-based" 414 depends on MMU 415 select ARCH_MTD_XIP 416 select ARM_CPU_SUSPEND if PM 417 select AUTO_ZRELADDR 418 select COMMON_CLK 419 select CLKSRC_PXA 420 select CLKSRC_MMIO 421 select TIMER_OF 422 select CPU_XSCALE if !CPU_XSC3 423 select GENERIC_IRQ_MULTI_HANDLER 424 select GPIO_PXA 425 select GPIOLIB 426 select IRQ_DOMAIN 427 select PLAT_PXA 428 select SPARSE_IRQ 429 help 430 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 431 432config ARCH_RPC 433 bool "RiscPC" 434 depends on MMU 435 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 436 select ARCH_ACORN 437 select ARCH_MAY_HAVE_PC_FDC 438 select ARCH_SPARSEMEM_ENABLE 439 select ARM_HAS_SG_CHAIN 440 select CPU_SA110 441 select FIQ 442 select HAVE_PATA_PLATFORM 443 select ISA_DMA_API 444 select LEGACY_TIMER_TICK 445 select NEED_MACH_IO_H 446 select NEED_MACH_MEMORY_H 447 select NO_IOPORT_MAP 448 help 449 On the Acorn Risc-PC, Linux can support the internal IDE disk and 450 CD-ROM interface, serial and parallel port, and the floppy drive. 451 452config ARCH_SA1100 453 bool "SA1100-based" 454 select ARCH_MTD_XIP 455 select ARCH_SPARSEMEM_ENABLE 456 select CLKSRC_MMIO 457 select CLKSRC_PXA 458 select TIMER_OF if OF 459 select COMMON_CLK 460 select CPU_FREQ 461 select CPU_SA1100 462 select GENERIC_IRQ_MULTI_HANDLER 463 select GPIOLIB 464 select IRQ_DOMAIN 465 select ISA 466 select NEED_MACH_MEMORY_H 467 select SPARSE_IRQ 468 help 469 Support for StrongARM 11x0 based boards. 470 471config ARCH_S3C24XX 472 bool "Samsung S3C24XX SoCs" 473 select ATAGS 474 select CLKSRC_SAMSUNG_PWM 475 select GPIO_SAMSUNG 476 select GPIOLIB 477 select GENERIC_IRQ_MULTI_HANDLER 478 select NEED_MACH_IO_H 479 select S3C2410_WATCHDOG 480 select SAMSUNG_ATAGS 481 select USE_OF 482 select WATCHDOG 483 help 484 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 485 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 486 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 487 Samsung SMDK2410 development board (and derivatives). 488 489config ARCH_OMAP1 490 bool "TI OMAP1" 491 depends on MMU 492 select ARCH_OMAP 493 select CLKSRC_MMIO 494 select GENERIC_IRQ_CHIP 495 select GENERIC_IRQ_MULTI_HANDLER 496 select GPIOLIB 497 select HAVE_LEGACY_CLK 498 select IRQ_DOMAIN 499 select NEED_MACH_IO_H if PCCARD 500 select NEED_MACH_MEMORY_H 501 select SPARSE_IRQ 502 help 503 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 504 505endchoice 506 507menu "Multiple platform selection" 508 depends on ARCH_MULTIPLATFORM 509 510comment "CPU Core family selection" 511 512config ARCH_MULTI_V4 513 bool "ARMv4 based platforms (FA526)" 514 depends on !ARCH_MULTI_V6_V7 515 select ARCH_MULTI_V4_V5 516 select CPU_FA526 517 518config ARCH_MULTI_V4T 519 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 520 depends on !ARCH_MULTI_V6_V7 521 select ARCH_MULTI_V4_V5 522 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 523 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 524 CPU_ARM925T || CPU_ARM940T) 525 526config ARCH_MULTI_V5 527 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 528 depends on !ARCH_MULTI_V6_V7 529 select ARCH_MULTI_V4_V5 530 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 531 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 532 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 533 534config ARCH_MULTI_V4_V5 535 bool 536 537config ARCH_MULTI_V6 538 bool "ARMv6 based platforms (ARM11)" 539 select ARCH_MULTI_V6_V7 540 select CPU_V6K 541 542config ARCH_MULTI_V7 543 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 544 default y 545 select ARCH_MULTI_V6_V7 546 select CPU_V7 547 select HAVE_SMP 548 549config ARCH_MULTI_V6_V7 550 bool 551 select MIGHT_HAVE_CACHE_L2X0 552 553config ARCH_MULTI_CPU_AUTO 554 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 555 select ARCH_MULTI_V5 556 557endmenu 558 559config ARCH_VIRT 560 bool "Dummy Virtual Machine" 561 depends on ARCH_MULTI_V7 562 select ARM_AMBA 563 select ARM_GIC 564 select ARM_GIC_V2M if PCI 565 select ARM_GIC_V3 566 select ARM_GIC_V3_ITS if PCI 567 select ARM_PSCI 568 select HAVE_ARM_ARCH_TIMER 569 select ARCH_SUPPORTS_BIG_ENDIAN 570 571# 572# This is sorted alphabetically by mach-* pathname. However, plat-* 573# Kconfigs may be included either alphabetically (according to the 574# plat- suffix) or along side the corresponding mach-* source. 575# 576source "arch/arm/mach-actions/Kconfig" 577 578source "arch/arm/mach-alpine/Kconfig" 579 580source "arch/arm/mach-artpec/Kconfig" 581 582source "arch/arm/mach-asm9260/Kconfig" 583 584source "arch/arm/mach-aspeed/Kconfig" 585 586source "arch/arm/mach-at91/Kconfig" 587 588source "arch/arm/mach-axxia/Kconfig" 589 590source "arch/arm/mach-bcm/Kconfig" 591 592source "arch/arm/mach-berlin/Kconfig" 593 594source "arch/arm/mach-clps711x/Kconfig" 595 596source "arch/arm/mach-cns3xxx/Kconfig" 597 598source "arch/arm/mach-davinci/Kconfig" 599 600source "arch/arm/mach-digicolor/Kconfig" 601 602source "arch/arm/mach-dove/Kconfig" 603 604source "arch/arm/mach-ep93xx/Kconfig" 605 606source "arch/arm/mach-exynos/Kconfig" 607 608source "arch/arm/mach-footbridge/Kconfig" 609 610source "arch/arm/mach-gemini/Kconfig" 611 612source "arch/arm/mach-highbank/Kconfig" 613 614source "arch/arm/mach-hisi/Kconfig" 615 616source "arch/arm/mach-imx/Kconfig" 617 618source "arch/arm/mach-integrator/Kconfig" 619 620source "arch/arm/mach-iop32x/Kconfig" 621 622source "arch/arm/mach-ixp4xx/Kconfig" 623 624source "arch/arm/mach-keystone/Kconfig" 625 626source "arch/arm/mach-lpc32xx/Kconfig" 627 628source "arch/arm/mach-mediatek/Kconfig" 629 630source "arch/arm/mach-meson/Kconfig" 631 632source "arch/arm/mach-milbeaut/Kconfig" 633 634source "arch/arm/mach-mmp/Kconfig" 635 636source "arch/arm/mach-moxart/Kconfig" 637 638source "arch/arm/mach-mstar/Kconfig" 639 640source "arch/arm/mach-mv78xx0/Kconfig" 641 642source "arch/arm/mach-mvebu/Kconfig" 643 644source "arch/arm/mach-mxs/Kconfig" 645 646source "arch/arm/mach-nomadik/Kconfig" 647 648source "arch/arm/mach-npcm/Kconfig" 649 650source "arch/arm/mach-nspire/Kconfig" 651 652source "arch/arm/plat-omap/Kconfig" 653 654source "arch/arm/mach-omap1/Kconfig" 655 656source "arch/arm/mach-omap2/Kconfig" 657 658source "arch/arm/mach-orion5x/Kconfig" 659 660source "arch/arm/mach-oxnas/Kconfig" 661 662source "arch/arm/mach-pxa/Kconfig" 663source "arch/arm/plat-pxa/Kconfig" 664 665source "arch/arm/mach-qcom/Kconfig" 666 667source "arch/arm/mach-rda/Kconfig" 668 669source "arch/arm/mach-realtek/Kconfig" 670 671source "arch/arm/mach-realview/Kconfig" 672 673source "arch/arm/mach-rockchip/Kconfig" 674 675source "arch/arm/mach-s3c/Kconfig" 676 677source "arch/arm/mach-s5pv210/Kconfig" 678 679source "arch/arm/mach-sa1100/Kconfig" 680 681source "arch/arm/mach-shmobile/Kconfig" 682 683source "arch/arm/mach-socfpga/Kconfig" 684 685source "arch/arm/mach-spear/Kconfig" 686 687source "arch/arm/mach-sti/Kconfig" 688 689source "arch/arm/mach-stm32/Kconfig" 690 691source "arch/arm/mach-sunxi/Kconfig" 692 693source "arch/arm/mach-tegra/Kconfig" 694 695source "arch/arm/mach-uniphier/Kconfig" 696 697source "arch/arm/mach-ux500/Kconfig" 698 699source "arch/arm/mach-versatile/Kconfig" 700 701source "arch/arm/mach-vexpress/Kconfig" 702 703source "arch/arm/mach-vt8500/Kconfig" 704 705source "arch/arm/mach-zynq/Kconfig" 706 707# ARMv7-M architecture 708config ARCH_LPC18XX 709 bool "NXP LPC18xx/LPC43xx" 710 depends on ARM_SINGLE_ARMV7M 711 select ARCH_HAS_RESET_CONTROLLER 712 select ARM_AMBA 713 select CLKSRC_LPC32XX 714 select PINCTRL 715 help 716 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 717 high performance microcontrollers. 718 719config ARCH_MPS2 720 bool "ARM MPS2 platform" 721 depends on ARM_SINGLE_ARMV7M 722 select ARM_AMBA 723 select CLKSRC_MPS2 724 help 725 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 726 with a range of available cores like Cortex-M3/M4/M7. 727 728 Please, note that depends which Application Note is used memory map 729 for the platform may vary, so adjustment of RAM base might be needed. 730 731# Definitions to make life easier 732config ARCH_ACORN 733 bool 734 735config PLAT_IOP 736 bool 737 738config PLAT_ORION 739 bool 740 select CLKSRC_MMIO 741 select COMMON_CLK 742 select GENERIC_IRQ_CHIP 743 select IRQ_DOMAIN 744 745config PLAT_ORION_LEGACY 746 bool 747 select PLAT_ORION 748 749config PLAT_PXA 750 bool 751 752config PLAT_VERSATILE 753 bool 754 755source "arch/arm/mm/Kconfig" 756 757config IWMMXT 758 bool "Enable iWMMXt support" 759 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 760 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 761 help 762 Enable support for iWMMXt context switching at run time if 763 running on a CPU that supports it. 764 765if !MMU 766source "arch/arm/Kconfig-nommu" 767endif 768 769config PJ4B_ERRATA_4742 770 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 771 depends on CPU_PJ4B && MACH_ARMADA_370 772 default y 773 help 774 When coming out of either a Wait for Interrupt (WFI) or a Wait for 775 Event (WFE) IDLE states, a specific timing sensitivity exists between 776 the retiring WFI/WFE instructions and the newly issued subsequent 777 instructions. This sensitivity can result in a CPU hang scenario. 778 Workaround: 779 The software must insert either a Data Synchronization Barrier (DSB) 780 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 781 instruction 782 783config ARM_ERRATA_326103 784 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 785 depends on CPU_V6 786 help 787 Executing a SWP instruction to read-only memory does not set bit 11 788 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 789 treat the access as a read, preventing a COW from occurring and 790 causing the faulting task to livelock. 791 792config ARM_ERRATA_411920 793 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 794 depends on CPU_V6 || CPU_V6K 795 help 796 Invalidation of the Instruction Cache operation can 797 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 798 It does not affect the MPCore. This option enables the ARM Ltd. 799 recommended workaround. 800 801config ARM_ERRATA_430973 802 bool "ARM errata: Stale prediction on replaced interworking branch" 803 depends on CPU_V7 804 help 805 This option enables the workaround for the 430973 Cortex-A8 806 r1p* erratum. If a code sequence containing an ARM/Thumb 807 interworking branch is replaced with another code sequence at the 808 same virtual address, whether due to self-modifying code or virtual 809 to physical address re-mapping, Cortex-A8 does not recover from the 810 stale interworking branch prediction. This results in Cortex-A8 811 executing the new code sequence in the incorrect ARM or Thumb state. 812 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 813 and also flushes the branch target cache at every context switch. 814 Note that setting specific bits in the ACTLR register may not be 815 available in non-secure mode. 816 817config ARM_ERRATA_458693 818 bool "ARM errata: Processor deadlock when a false hazard is created" 819 depends on CPU_V7 820 depends on !ARCH_MULTIPLATFORM 821 help 822 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 823 erratum. For very specific sequences of memory operations, it is 824 possible for a hazard condition intended for a cache line to instead 825 be incorrectly associated with a different cache line. This false 826 hazard might then cause a processor deadlock. The workaround enables 827 the L1 caching of the NEON accesses and disables the PLD instruction 828 in the ACTLR register. Note that setting specific bits in the ACTLR 829 register may not be available in non-secure mode. 830 831config ARM_ERRATA_460075 832 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 833 depends on CPU_V7 834 depends on !ARCH_MULTIPLATFORM 835 help 836 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 837 erratum. Any asynchronous access to the L2 cache may encounter a 838 situation in which recent store transactions to the L2 cache are lost 839 and overwritten with stale memory contents from external memory. The 840 workaround disables the write-allocate mode for the L2 cache via the 841 ACTLR register. Note that setting specific bits in the ACTLR register 842 may not be available in non-secure mode. 843 844config ARM_ERRATA_742230 845 bool "ARM errata: DMB operation may be faulty" 846 depends on CPU_V7 && SMP 847 depends on !ARCH_MULTIPLATFORM 848 help 849 This option enables the workaround for the 742230 Cortex-A9 850 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 851 between two write operations may not ensure the correct visibility 852 ordering of the two writes. This workaround sets a specific bit in 853 the diagnostic register of the Cortex-A9 which causes the DMB 854 instruction to behave as a DSB, ensuring the correct behaviour of 855 the two writes. 856 857config ARM_ERRATA_742231 858 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 859 depends on CPU_V7 && SMP 860 depends on !ARCH_MULTIPLATFORM 861 help 862 This option enables the workaround for the 742231 Cortex-A9 863 (r2p0..r2p2) erratum. Under certain conditions, specific to the 864 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 865 accessing some data located in the same cache line, may get corrupted 866 data due to bad handling of the address hazard when the line gets 867 replaced from one of the CPUs at the same time as another CPU is 868 accessing it. This workaround sets specific bits in the diagnostic 869 register of the Cortex-A9 which reduces the linefill issuing 870 capabilities of the processor. 871 872config ARM_ERRATA_643719 873 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 874 depends on CPU_V7 && SMP 875 default y 876 help 877 This option enables the workaround for the 643719 Cortex-A9 (prior to 878 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 879 register returns zero when it should return one. The workaround 880 corrects this value, ensuring cache maintenance operations which use 881 it behave as intended and avoiding data corruption. 882 883config ARM_ERRATA_720789 884 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 885 depends on CPU_V7 886 help 887 This option enables the workaround for the 720789 Cortex-A9 (prior to 888 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 889 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 890 As a consequence of this erratum, some TLB entries which should be 891 invalidated are not, resulting in an incoherency in the system page 892 tables. The workaround changes the TLB flushing routines to invalidate 893 entries regardless of the ASID. 894 895config ARM_ERRATA_743622 896 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 897 depends on CPU_V7 898 depends on !ARCH_MULTIPLATFORM 899 help 900 This option enables the workaround for the 743622 Cortex-A9 901 (r2p*) erratum. Under very rare conditions, a faulty 902 optimisation in the Cortex-A9 Store Buffer may lead to data 903 corruption. This workaround sets a specific bit in the diagnostic 904 register of the Cortex-A9 which disables the Store Buffer 905 optimisation, preventing the defect from occurring. This has no 906 visible impact on the overall performance or power consumption of the 907 processor. 908 909config ARM_ERRATA_751472 910 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 911 depends on CPU_V7 912 depends on !ARCH_MULTIPLATFORM 913 help 914 This option enables the workaround for the 751472 Cortex-A9 (prior 915 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 916 completion of a following broadcasted operation if the second 917 operation is received by a CPU before the ICIALLUIS has completed, 918 potentially leading to corrupted entries in the cache or TLB. 919 920config ARM_ERRATA_754322 921 bool "ARM errata: possible faulty MMU translations following an ASID switch" 922 depends on CPU_V7 923 help 924 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 925 r3p*) erratum. A speculative memory access may cause a page table walk 926 which starts prior to an ASID switch but completes afterwards. This 927 can populate the micro-TLB with a stale entry which may be hit with 928 the new ASID. This workaround places two dsb instructions in the mm 929 switching code so that no page table walks can cross the ASID switch. 930 931config ARM_ERRATA_754327 932 bool "ARM errata: no automatic Store Buffer drain" 933 depends on CPU_V7 && SMP 934 help 935 This option enables the workaround for the 754327 Cortex-A9 (prior to 936 r2p0) erratum. The Store Buffer does not have any automatic draining 937 mechanism and therefore a livelock may occur if an external agent 938 continuously polls a memory location waiting to observe an update. 939 This workaround defines cpu_relax() as smp_mb(), preventing correctly 940 written polling loops from denying visibility of updates to memory. 941 942config ARM_ERRATA_364296 943 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 944 depends on CPU_V6 945 help 946 This options enables the workaround for the 364296 ARM1136 947 r0p2 erratum (possible cache data corruption with 948 hit-under-miss enabled). It sets the undocumented bit 31 in 949 the auxiliary control register and the FI bit in the control 950 register, thus disabling hit-under-miss without putting the 951 processor into full low interrupt latency mode. ARM11MPCore 952 is not affected. 953 954config ARM_ERRATA_764369 955 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 956 depends on CPU_V7 && SMP 957 help 958 This option enables the workaround for erratum 764369 959 affecting Cortex-A9 MPCore with two or more processors (all 960 current revisions). Under certain timing circumstances, a data 961 cache line maintenance operation by MVA targeting an Inner 962 Shareable memory region may fail to proceed up to either the 963 Point of Coherency or to the Point of Unification of the 964 system. This workaround adds a DSB instruction before the 965 relevant cache maintenance functions and sets a specific bit 966 in the diagnostic control register of the SCU. 967 968config ARM_ERRATA_775420 969 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 970 depends on CPU_V7 971 help 972 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 973 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 974 operation aborts with MMU exception, it might cause the processor 975 to deadlock. This workaround puts DSB before executing ISB if 976 an abort may occur on cache maintenance. 977 978config ARM_ERRATA_798181 979 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 980 depends on CPU_V7 && SMP 981 help 982 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 983 adequately shooting down all use of the old entries. This 984 option enables the Linux kernel workaround for this erratum 985 which sends an IPI to the CPUs that are running the same ASID 986 as the one being invalidated. 987 988config ARM_ERRATA_773022 989 bool "ARM errata: incorrect instructions may be executed from loop buffer" 990 depends on CPU_V7 991 help 992 This option enables the workaround for the 773022 Cortex-A15 993 (up to r0p4) erratum. In certain rare sequences of code, the 994 loop buffer may deliver incorrect instructions. This 995 workaround disables the loop buffer to avoid the erratum. 996 997config ARM_ERRATA_818325_852422 998 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 999 depends on CPU_V7 1000 help 1001 This option enables the workaround for: 1002 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1003 instruction might deadlock. Fixed in r0p1. 1004 - Cortex-A12 852422: Execution of a sequence of instructions might 1005 lead to either a data corruption or a CPU deadlock. Not fixed in 1006 any Cortex-A12 cores yet. 1007 This workaround for all both errata involves setting bit[12] of the 1008 Feature Register. This bit disables an optimisation applied to a 1009 sequence of 2 instructions that use opposing condition codes. 1010 1011config ARM_ERRATA_821420 1012 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1013 depends on CPU_V7 1014 help 1015 This option enables the workaround for the 821420 Cortex-A12 1016 (all revs) erratum. In very rare timing conditions, a sequence 1017 of VMOV to Core registers instructions, for which the second 1018 one is in the shadow of a branch or abort, can lead to a 1019 deadlock when the VMOV instructions are issued out-of-order. 1020 1021config ARM_ERRATA_825619 1022 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1023 depends on CPU_V7 1024 help 1025 This option enables the workaround for the 825619 Cortex-A12 1026 (all revs) erratum. Within rare timing constraints, executing a 1027 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1028 and Device/Strongly-Ordered loads and stores might cause deadlock 1029 1030config ARM_ERRATA_857271 1031 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1032 depends on CPU_V7 1033 help 1034 This option enables the workaround for the 857271 Cortex-A12 1035 (all revs) erratum. Under very rare timing conditions, the CPU might 1036 hang. The workaround is expected to have a < 1% performance impact. 1037 1038config ARM_ERRATA_852421 1039 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1040 depends on CPU_V7 1041 help 1042 This option enables the workaround for the 852421 Cortex-A17 1043 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1044 execution of a DMB ST instruction might fail to properly order 1045 stores from GroupA and stores from GroupB. 1046 1047config ARM_ERRATA_852423 1048 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1049 depends on CPU_V7 1050 help 1051 This option enables the workaround for: 1052 - Cortex-A17 852423: Execution of a sequence of instructions might 1053 lead to either a data corruption or a CPU deadlock. Not fixed in 1054 any Cortex-A17 cores yet. 1055 This is identical to Cortex-A12 erratum 852422. It is a separate 1056 config option from the A12 erratum due to the way errata are checked 1057 for and handled. 1058 1059config ARM_ERRATA_857272 1060 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1061 depends on CPU_V7 1062 help 1063 This option enables the workaround for the 857272 Cortex-A17 erratum. 1064 This erratum is not known to be fixed in any A17 revision. 1065 This is identical to Cortex-A12 erratum 857271. It is a separate 1066 config option from the A12 erratum due to the way errata are checked 1067 for and handled. 1068 1069endmenu 1070 1071source "arch/arm/common/Kconfig" 1072 1073menu "Bus support" 1074 1075config ISA 1076 bool 1077 help 1078 Find out whether you have ISA slots on your motherboard. ISA is the 1079 name of a bus system, i.e. the way the CPU talks to the other stuff 1080 inside your box. Other bus systems are PCI, EISA, MicroChannel 1081 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1082 newer boards don't support it. If you have ISA, say Y, otherwise N. 1083 1084# Select ISA DMA controller support 1085config ISA_DMA 1086 bool 1087 select ISA_DMA_API 1088 1089# Select ISA DMA interface 1090config ISA_DMA_API 1091 bool 1092 1093config PCI_NANOENGINE 1094 bool "BSE nanoEngine PCI support" 1095 depends on SA1100_NANOENGINE 1096 help 1097 Enable PCI on the BSE nanoEngine board. 1098 1099config ARM_ERRATA_814220 1100 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1101 depends on CPU_V7 1102 help 1103 The v7 ARM states that all cache and branch predictor maintenance 1104 operations that do not specify an address execute, relative to 1105 each other, in program order. 1106 However, because of this erratum, an L2 set/way cache maintenance 1107 operation can overtake an L1 set/way cache maintenance operation. 1108 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1109 r0p4, r0p5. 1110 1111endmenu 1112 1113menu "Kernel Features" 1114 1115config HAVE_SMP 1116 bool 1117 help 1118 This option should be selected by machines which have an SMP- 1119 capable CPU. 1120 1121 The only effect of this option is to make the SMP-related 1122 options available to the user for configuration. 1123 1124config SMP 1125 bool "Symmetric Multi-Processing" 1126 depends on CPU_V6K || CPU_V7 1127 depends on HAVE_SMP 1128 depends on MMU || ARM_MPU 1129 select IRQ_WORK 1130 help 1131 This enables support for systems with more than one CPU. If you have 1132 a system with only one CPU, say N. If you have a system with more 1133 than one CPU, say Y. 1134 1135 If you say N here, the kernel will run on uni- and multiprocessor 1136 machines, but will use only one CPU of a multiprocessor machine. If 1137 you say Y here, the kernel will run on many, but not all, 1138 uniprocessor machines. On a uniprocessor machine, the kernel 1139 will run faster if you say N here. 1140 1141 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1142 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1143 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1144 1145 If you don't know what to do here, say N. 1146 1147config SMP_ON_UP 1148 bool "Allow booting SMP kernel on uniprocessor systems" 1149 depends on SMP && !XIP_KERNEL && MMU 1150 default y 1151 help 1152 SMP kernels contain instructions which fail on non-SMP processors. 1153 Enabling this option allows the kernel to modify itself to make 1154 these instructions safe. Disabling it allows about 1K of space 1155 savings. 1156 1157 If you don't know what to do here, say Y. 1158 1159 1160config CURRENT_POINTER_IN_TPIDRURO 1161 def_bool y 1162 depends on SMP && CPU_32v6K && !CPU_V6 1163 1164config ARM_CPU_TOPOLOGY 1165 bool "Support cpu topology definition" 1166 depends on SMP && CPU_V7 1167 default y 1168 help 1169 Support ARM cpu topology definition. The MPIDR register defines 1170 affinity between processors which is then used to describe the cpu 1171 topology of an ARM System. 1172 1173config SCHED_MC 1174 bool "Multi-core scheduler support" 1175 depends on ARM_CPU_TOPOLOGY 1176 help 1177 Multi-core scheduler support improves the CPU scheduler's decision 1178 making when dealing with multi-core CPU chips at a cost of slightly 1179 increased overhead in some places. If unsure say N here. 1180 1181config SCHED_SMT 1182 bool "SMT scheduler support" 1183 depends on ARM_CPU_TOPOLOGY 1184 help 1185 Improves the CPU scheduler's decision making when dealing with 1186 MultiThreading at a cost of slightly increased overhead in some 1187 places. If unsure say N here. 1188 1189config HAVE_ARM_SCU 1190 bool 1191 help 1192 This option enables support for the ARM snoop control unit 1193 1194config HAVE_ARM_ARCH_TIMER 1195 bool "Architected timer support" 1196 depends on CPU_V7 1197 select ARM_ARCH_TIMER 1198 help 1199 This option enables support for the ARM architected timer 1200 1201config HAVE_ARM_TWD 1202 bool 1203 help 1204 This options enables support for the ARM timer and watchdog unit 1205 1206config MCPM 1207 bool "Multi-Cluster Power Management" 1208 depends on CPU_V7 && SMP 1209 help 1210 This option provides the common power management infrastructure 1211 for (multi-)cluster based systems, such as big.LITTLE based 1212 systems. 1213 1214config MCPM_QUAD_CLUSTER 1215 bool 1216 depends on MCPM 1217 help 1218 To avoid wasting resources unnecessarily, MCPM only supports up 1219 to 2 clusters by default. 1220 Platforms with 3 or 4 clusters that use MCPM must select this 1221 option to allow the additional clusters to be managed. 1222 1223config BIG_LITTLE 1224 bool "big.LITTLE support (Experimental)" 1225 depends on CPU_V7 && SMP 1226 select MCPM 1227 help 1228 This option enables support selections for the big.LITTLE 1229 system architecture. 1230 1231config BL_SWITCHER 1232 bool "big.LITTLE switcher support" 1233 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1234 select CPU_PM 1235 help 1236 The big.LITTLE "switcher" provides the core functionality to 1237 transparently handle transition between a cluster of A15's 1238 and a cluster of A7's in a big.LITTLE system. 1239 1240config BL_SWITCHER_DUMMY_IF 1241 tristate "Simple big.LITTLE switcher user interface" 1242 depends on BL_SWITCHER && DEBUG_KERNEL 1243 help 1244 This is a simple and dummy char dev interface to control 1245 the big.LITTLE switcher core code. It is meant for 1246 debugging purposes only. 1247 1248choice 1249 prompt "Memory split" 1250 depends on MMU 1251 default VMSPLIT_3G 1252 help 1253 Select the desired split between kernel and user memory. 1254 1255 If you are not absolutely sure what you are doing, leave this 1256 option alone! 1257 1258 config VMSPLIT_3G 1259 bool "3G/1G user/kernel split" 1260 config VMSPLIT_3G_OPT 1261 depends on !ARM_LPAE 1262 bool "3G/1G user/kernel split (for full 1G low memory)" 1263 config VMSPLIT_2G 1264 bool "2G/2G user/kernel split" 1265 config VMSPLIT_1G 1266 bool "1G/3G user/kernel split" 1267endchoice 1268 1269config PAGE_OFFSET 1270 hex 1271 default PHYS_OFFSET if !MMU 1272 default 0x40000000 if VMSPLIT_1G 1273 default 0x80000000 if VMSPLIT_2G 1274 default 0xB0000000 if VMSPLIT_3G_OPT 1275 default 0xC0000000 1276 1277config KASAN_SHADOW_OFFSET 1278 hex 1279 depends on KASAN 1280 default 0x1f000000 if PAGE_OFFSET=0x40000000 1281 default 0x5f000000 if PAGE_OFFSET=0x80000000 1282 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1283 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1284 default 0xffffffff 1285 1286config NR_CPUS 1287 int "Maximum number of CPUs (2-32)" 1288 range 2 16 if DEBUG_KMAP_LOCAL 1289 range 2 32 if !DEBUG_KMAP_LOCAL 1290 depends on SMP 1291 default "4" 1292 help 1293 The maximum number of CPUs that the kernel can support. 1294 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1295 debugging is enabled, which uses half of the per-CPU fixmap 1296 slots as guard regions. 1297 1298config HOTPLUG_CPU 1299 bool "Support for hot-pluggable CPUs" 1300 depends on SMP 1301 select GENERIC_IRQ_MIGRATION 1302 help 1303 Say Y here to experiment with turning CPUs off and on. CPUs 1304 can be controlled through /sys/devices/system/cpu. 1305 1306config ARM_PSCI 1307 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1308 depends on HAVE_ARM_SMCCC 1309 select ARM_PSCI_FW 1310 help 1311 Say Y here if you want Linux to communicate with system firmware 1312 implementing the PSCI specification for CPU-centric power 1313 management operations described in ARM document number ARM DEN 1314 0022A ("Power State Coordination Interface System Software on 1315 ARM processors"). 1316 1317# The GPIO number here must be sorted by descending number. In case of 1318# a multiplatform kernel, we just want the highest value required by the 1319# selected platforms. 1320config ARCH_NR_GPIO 1321 int 1322 default 2048 if ARCH_INTEL_SOCFPGA 1323 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1324 ARCH_ZYNQ || ARCH_ASPEED 1325 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1326 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1327 default 416 if ARCH_SUNXI 1328 default 392 if ARCH_U8500 1329 default 352 if ARCH_VT8500 1330 default 288 if ARCH_ROCKCHIP 1331 default 264 if MACH_H4700 1332 default 0 1333 help 1334 Maximum number of GPIOs in the system. 1335 1336 If unsure, leave the default value. 1337 1338config HZ_FIXED 1339 int 1340 default 128 if SOC_AT91RM9200 1341 default 0 1342 1343choice 1344 depends on HZ_FIXED = 0 1345 prompt "Timer frequency" 1346 1347config HZ_100 1348 bool "100 Hz" 1349 1350config HZ_200 1351 bool "200 Hz" 1352 1353config HZ_250 1354 bool "250 Hz" 1355 1356config HZ_300 1357 bool "300 Hz" 1358 1359config HZ_500 1360 bool "500 Hz" 1361 1362config HZ_1000 1363 bool "1000 Hz" 1364 1365endchoice 1366 1367config HZ 1368 int 1369 default HZ_FIXED if HZ_FIXED != 0 1370 default 100 if HZ_100 1371 default 200 if HZ_200 1372 default 250 if HZ_250 1373 default 300 if HZ_300 1374 default 500 if HZ_500 1375 default 1000 1376 1377config SCHED_HRTICK 1378 def_bool HIGH_RES_TIMERS 1379 1380config THUMB2_KERNEL 1381 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1382 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1383 default y if CPU_THUMBONLY 1384 select ARM_UNWIND 1385 help 1386 By enabling this option, the kernel will be compiled in 1387 Thumb-2 mode. 1388 1389 If unsure, say N. 1390 1391config ARM_PATCH_IDIV 1392 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1393 depends on CPU_32v7 && !XIP_KERNEL 1394 default y 1395 help 1396 The ARM compiler inserts calls to __aeabi_idiv() and 1397 __aeabi_uidiv() when it needs to perform division on signed 1398 and unsigned integers. Some v7 CPUs have support for the sdiv 1399 and udiv instructions that can be used to implement those 1400 functions. 1401 1402 Enabling this option allows the kernel to modify itself to 1403 replace the first two instructions of these library functions 1404 with the sdiv or udiv plus "bx lr" instructions when the CPU 1405 it is running on supports them. Typically this will be faster 1406 and less power intensive than running the original library 1407 code to do integer division. 1408 1409config AEABI 1410 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1411 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1412 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1413 help 1414 This option allows for the kernel to be compiled using the latest 1415 ARM ABI (aka EABI). This is only useful if you are using a user 1416 space environment that is also compiled with EABI. 1417 1418 Since there are major incompatibilities between the legacy ABI and 1419 EABI, especially with regard to structure member alignment, this 1420 option also changes the kernel syscall calling convention to 1421 disambiguate both ABIs and allow for backward compatibility support 1422 (selected with CONFIG_OABI_COMPAT). 1423 1424 To use this you need GCC version 4.0.0 or later. 1425 1426config OABI_COMPAT 1427 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1428 depends on AEABI && !THUMB2_KERNEL 1429 help 1430 This option preserves the old syscall interface along with the 1431 new (ARM EABI) one. It also provides a compatibility layer to 1432 intercept syscalls that have structure arguments which layout 1433 in memory differs between the legacy ABI and the new ARM EABI 1434 (only for non "thumb" binaries). This option adds a tiny 1435 overhead to all syscalls and produces a slightly larger kernel. 1436 1437 The seccomp filter system will not be available when this is 1438 selected, since there is no way yet to sensibly distinguish 1439 between calling conventions during filtering. 1440 1441 If you know you'll be using only pure EABI user space then you 1442 can say N here. If this option is not selected and you attempt 1443 to execute a legacy ABI binary then the result will be 1444 UNPREDICTABLE (in fact it can be predicted that it won't work 1445 at all). If in doubt say N. 1446 1447config ARCH_SELECT_MEMORY_MODEL 1448 bool 1449 1450config ARCH_FLATMEM_ENABLE 1451 bool 1452 1453config ARCH_SPARSEMEM_ENABLE 1454 bool 1455 select SPARSEMEM_STATIC if SPARSEMEM 1456 1457config HIGHMEM 1458 bool "High Memory Support" 1459 depends on MMU 1460 select KMAP_LOCAL 1461 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1462 help 1463 The address space of ARM processors is only 4 Gigabytes large 1464 and it has to accommodate user address space, kernel address 1465 space as well as some memory mapped IO. That means that, if you 1466 have a large amount of physical memory and/or IO, not all of the 1467 memory can be "permanently mapped" by the kernel. The physical 1468 memory that is not permanently mapped is called "high memory". 1469 1470 Depending on the selected kernel/user memory split, minimum 1471 vmalloc space and actual amount of RAM, you may not need this 1472 option which should result in a slightly faster kernel. 1473 1474 If unsure, say n. 1475 1476config HIGHPTE 1477 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1478 depends on HIGHMEM 1479 default y 1480 help 1481 The VM uses one page of physical memory for each page table. 1482 For systems with a lot of processes, this can use a lot of 1483 precious low memory, eventually leading to low memory being 1484 consumed by page tables. Setting this option will allow 1485 user-space 2nd level page tables to reside in high memory. 1486 1487config CPU_SW_DOMAIN_PAN 1488 bool "Enable use of CPU domains to implement privileged no-access" 1489 depends on MMU && !ARM_LPAE 1490 default y 1491 help 1492 Increase kernel security by ensuring that normal kernel accesses 1493 are unable to access userspace addresses. This can help prevent 1494 use-after-free bugs becoming an exploitable privilege escalation 1495 by ensuring that magic values (such as LIST_POISON) will always 1496 fault when dereferenced. 1497 1498 CPUs with low-vector mappings use a best-efforts implementation. 1499 Their lower 1MB needs to remain accessible for the vectors, but 1500 the remainder of userspace will become appropriately inaccessible. 1501 1502config HW_PERF_EVENTS 1503 def_bool y 1504 depends on ARM_PMU 1505 1506config ARCH_WANT_GENERAL_HUGETLB 1507 def_bool y 1508 1509config ARM_MODULE_PLTS 1510 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1511 depends on MODULES 1512 default y 1513 help 1514 Allocate PLTs when loading modules so that jumps and calls whose 1515 targets are too far away for their relative offsets to be encoded 1516 in the instructions themselves can be bounced via veneers in the 1517 module's PLT. This allows modules to be allocated in the generic 1518 vmalloc area after the dedicated module memory area has been 1519 exhausted. The modules will use slightly more memory, but after 1520 rounding up to page size, the actual memory footprint is usually 1521 the same. 1522 1523 Disabling this is usually safe for small single-platform 1524 configurations. If unsure, say y. 1525 1526config FORCE_MAX_ZONEORDER 1527 int "Maximum zone order" 1528 default "12" if SOC_AM33XX 1529 default "9" if SA1111 1530 default "11" 1531 help 1532 The kernel memory allocator divides physically contiguous memory 1533 blocks into "zones", where each zone is a power of two number of 1534 pages. This option selects the largest power of two that the kernel 1535 keeps in the memory allocator. If you need to allocate very large 1536 blocks of physically contiguous memory, then you may need to 1537 increase this value. 1538 1539 This config option is actually maximum order plus one. For example, 1540 a value of 11 means that the largest free memory block is 2^10 pages. 1541 1542config ALIGNMENT_TRAP 1543 def_bool CPU_CP15_MMU 1544 select HAVE_PROC_CPU if PROC_FS 1545 help 1546 ARM processors cannot fetch/store information which is not 1547 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1548 address divisible by 4. On 32-bit ARM processors, these non-aligned 1549 fetch/store instructions will be emulated in software if you say 1550 here, which has a severe performance impact. This is necessary for 1551 correct operation of some network protocols. With an IP-only 1552 configuration it is safe to say N, otherwise say Y. 1553 1554config UACCESS_WITH_MEMCPY 1555 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1556 depends on MMU 1557 default y if CPU_FEROCEON 1558 help 1559 Implement faster copy_to_user and clear_user methods for CPU 1560 cores where a 8-word STM instruction give significantly higher 1561 memory write throughput than a sequence of individual 32bit stores. 1562 1563 A possible side effect is a slight increase in scheduling latency 1564 between threads sharing the same address space if they invoke 1565 such copy operations with large buffers. 1566 1567 However, if the CPU data cache is using a write-allocate mode, 1568 this option is unlikely to provide any performance gain. 1569 1570config PARAVIRT 1571 bool "Enable paravirtualization code" 1572 help 1573 This changes the kernel so it can modify itself when it is run 1574 under a hypervisor, potentially improving performance significantly 1575 over full virtualization. 1576 1577config PARAVIRT_TIME_ACCOUNTING 1578 bool "Paravirtual steal time accounting" 1579 select PARAVIRT 1580 help 1581 Select this option to enable fine granularity task steal time 1582 accounting. Time spent executing other tasks in parallel with 1583 the current vCPU is discounted from the vCPU power. To account for 1584 that, there can be a small performance impact. 1585 1586 If in doubt, say N here. 1587 1588config XEN_DOM0 1589 def_bool y 1590 depends on XEN 1591 1592config XEN 1593 bool "Xen guest support on ARM" 1594 depends on ARM && AEABI && OF 1595 depends on CPU_V7 && !CPU_V6 1596 depends on !GENERIC_ATOMIC64 1597 depends on MMU 1598 select ARCH_DMA_ADDR_T_64BIT 1599 select ARM_PSCI 1600 select SWIOTLB 1601 select SWIOTLB_XEN 1602 select PARAVIRT 1603 help 1604 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1605 1606config STACKPROTECTOR_PER_TASK 1607 bool "Use a unique stack canary value for each task" 1608 depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA 1609 select GCC_PLUGIN_ARM_SSP_PER_TASK 1610 default y 1611 help 1612 Due to the fact that GCC uses an ordinary symbol reference from 1613 which to load the value of the stack canary, this value can only 1614 change at reboot time on SMP systems, and all tasks running in the 1615 kernel's address space are forced to use the same canary value for 1616 the entire duration that the system is up. 1617 1618 Enable this option to switch to a different method that uses a 1619 different canary value for each task. 1620 1621endmenu 1622 1623menu "Boot options" 1624 1625config USE_OF 1626 bool "Flattened Device Tree support" 1627 select IRQ_DOMAIN 1628 select OF 1629 help 1630 Include support for flattened device tree machine descriptions. 1631 1632config ATAGS 1633 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1634 default y 1635 help 1636 This is the traditional way of passing data to the kernel at boot 1637 time. If you are solely relying on the flattened device tree (or 1638 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1639 to remove ATAGS support from your kernel binary. If unsure, 1640 leave this to y. 1641 1642config DEPRECATED_PARAM_STRUCT 1643 bool "Provide old way to pass kernel parameters" 1644 depends on ATAGS 1645 help 1646 This was deprecated in 2001 and announced to live on for 5 years. 1647 Some old boot loaders still use this way. 1648 1649# Compressed boot loader in ROM. Yes, we really want to ask about 1650# TEXT and BSS so we preserve their values in the config files. 1651config ZBOOT_ROM_TEXT 1652 hex "Compressed ROM boot loader base address" 1653 default 0x0 1654 help 1655 The physical address at which the ROM-able zImage is to be 1656 placed in the target. Platforms which normally make use of 1657 ROM-able zImage formats normally set this to a suitable 1658 value in their defconfig file. 1659 1660 If ZBOOT_ROM is not enabled, this has no effect. 1661 1662config ZBOOT_ROM_BSS 1663 hex "Compressed ROM boot loader BSS address" 1664 default 0x0 1665 help 1666 The base address of an area of read/write memory in the target 1667 for the ROM-able zImage which must be available while the 1668 decompressor is running. It must be large enough to hold the 1669 entire decompressed kernel plus an additional 128 KiB. 1670 Platforms which normally make use of ROM-able zImage formats 1671 normally set this to a suitable value in their defconfig file. 1672 1673 If ZBOOT_ROM is not enabled, this has no effect. 1674 1675config ZBOOT_ROM 1676 bool "Compressed boot loader in ROM/flash" 1677 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1678 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1679 help 1680 Say Y here if you intend to execute your compressed kernel image 1681 (zImage) directly from ROM or flash. If unsure, say N. 1682 1683config ARM_APPENDED_DTB 1684 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1685 depends on OF 1686 help 1687 With this option, the boot code will look for a device tree binary 1688 (DTB) appended to zImage 1689 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1690 1691 This is meant as a backward compatibility convenience for those 1692 systems with a bootloader that can't be upgraded to accommodate 1693 the documented boot protocol using a device tree. 1694 1695 Beware that there is very little in terms of protection against 1696 this option being confused by leftover garbage in memory that might 1697 look like a DTB header after a reboot if no actual DTB is appended 1698 to zImage. Do not leave this option active in a production kernel 1699 if you don't intend to always append a DTB. Proper passing of the 1700 location into r2 of a bootloader provided DTB is always preferable 1701 to this option. 1702 1703config ARM_ATAG_DTB_COMPAT 1704 bool "Supplement the appended DTB with traditional ATAG information" 1705 depends on ARM_APPENDED_DTB 1706 help 1707 Some old bootloaders can't be updated to a DTB capable one, yet 1708 they provide ATAGs with memory configuration, the ramdisk address, 1709 the kernel cmdline string, etc. Such information is dynamically 1710 provided by the bootloader and can't always be stored in a static 1711 DTB. To allow a device tree enabled kernel to be used with such 1712 bootloaders, this option allows zImage to extract the information 1713 from the ATAG list and store it at run time into the appended DTB. 1714 1715choice 1716 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1717 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1718 1719config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1720 bool "Use bootloader kernel arguments if available" 1721 help 1722 Uses the command-line options passed by the boot loader instead of 1723 the device tree bootargs property. If the boot loader doesn't provide 1724 any, the device tree bootargs property will be used. 1725 1726config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1727 bool "Extend with bootloader kernel arguments" 1728 help 1729 The command-line arguments provided by the boot loader will be 1730 appended to the the device tree bootargs property. 1731 1732endchoice 1733 1734config CMDLINE 1735 string "Default kernel command string" 1736 default "" 1737 help 1738 On some architectures (e.g. CATS), there is currently no way 1739 for the boot loader to pass arguments to the kernel. For these 1740 architectures, you should supply some command-line options at build 1741 time by entering them here. As a minimum, you should specify the 1742 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1743 1744choice 1745 prompt "Kernel command line type" if CMDLINE != "" 1746 default CMDLINE_FROM_BOOTLOADER 1747 depends on ATAGS 1748 1749config CMDLINE_FROM_BOOTLOADER 1750 bool "Use bootloader kernel arguments if available" 1751 help 1752 Uses the command-line options passed by the boot loader. If 1753 the boot loader doesn't provide any, the default kernel command 1754 string provided in CMDLINE will be used. 1755 1756config CMDLINE_EXTEND 1757 bool "Extend bootloader kernel arguments" 1758 help 1759 The command-line arguments provided by the boot loader will be 1760 appended to the default kernel command string. 1761 1762config CMDLINE_FORCE 1763 bool "Always use the default kernel command string" 1764 help 1765 Always use the default kernel command string, even if the boot 1766 loader passes other arguments to the kernel. 1767 This is useful if you cannot or don't want to change the 1768 command-line options your boot loader passes to the kernel. 1769endchoice 1770 1771config XIP_KERNEL 1772 bool "Kernel Execute-In-Place from ROM" 1773 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1774 help 1775 Execute-In-Place allows the kernel to run from non-volatile storage 1776 directly addressable by the CPU, such as NOR flash. This saves RAM 1777 space since the text section of the kernel is not loaded from flash 1778 to RAM. Read-write sections, such as the data section and stack, 1779 are still copied to RAM. The XIP kernel is not compressed since 1780 it has to run directly from flash, so it will take more space to 1781 store it. The flash address used to link the kernel object files, 1782 and for storing it, is configuration dependent. Therefore, if you 1783 say Y here, you must know the proper physical address where to 1784 store the kernel image depending on your own flash memory usage. 1785 1786 Also note that the make target becomes "make xipImage" rather than 1787 "make zImage" or "make Image". The final kernel binary to put in 1788 ROM memory will be arch/arm/boot/xipImage. 1789 1790 If unsure, say N. 1791 1792config XIP_PHYS_ADDR 1793 hex "XIP Kernel Physical Location" 1794 depends on XIP_KERNEL 1795 default "0x00080000" 1796 help 1797 This is the physical address in your flash memory the kernel will 1798 be linked for and stored to. This address is dependent on your 1799 own flash usage. 1800 1801config XIP_DEFLATED_DATA 1802 bool "Store kernel .data section compressed in ROM" 1803 depends on XIP_KERNEL 1804 select ZLIB_INFLATE 1805 help 1806 Before the kernel is actually executed, its .data section has to be 1807 copied to RAM from ROM. This option allows for storing that data 1808 in compressed form and decompressed to RAM rather than merely being 1809 copied, saving some precious ROM space. A possible drawback is a 1810 slightly longer boot delay. 1811 1812config KEXEC 1813 bool "Kexec system call (EXPERIMENTAL)" 1814 depends on (!SMP || PM_SLEEP_SMP) 1815 depends on MMU 1816 select KEXEC_CORE 1817 help 1818 kexec is a system call that implements the ability to shutdown your 1819 current kernel, and to start another kernel. It is like a reboot 1820 but it is independent of the system firmware. And like a reboot 1821 you can start any kernel with it, not just Linux. 1822 1823 It is an ongoing process to be certain the hardware in a machine 1824 is properly shutdown, so do not be surprised if this code does not 1825 initially work for you. 1826 1827config ATAGS_PROC 1828 bool "Export atags in procfs" 1829 depends on ATAGS && KEXEC 1830 default y 1831 help 1832 Should the atags used to boot the kernel be exported in an "atags" 1833 file in procfs. Useful with kexec. 1834 1835config CRASH_DUMP 1836 bool "Build kdump crash kernel (EXPERIMENTAL)" 1837 help 1838 Generate crash dump after being started by kexec. This should 1839 be normally only set in special crash dump kernels which are 1840 loaded in the main kernel with kexec-tools into a specially 1841 reserved region and then later executed after a crash by 1842 kdump/kexec. The crash dump kernel must be compiled to a 1843 memory address not used by the main kernel 1844 1845 For more details see Documentation/admin-guide/kdump/kdump.rst 1846 1847config AUTO_ZRELADDR 1848 bool "Auto calculation of the decompressed kernel image address" 1849 help 1850 ZRELADDR is the physical address where the decompressed kernel 1851 image will be placed. If AUTO_ZRELADDR is selected, the address 1852 will be determined at run-time, either by masking the current IP 1853 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1854 This assumes the zImage being placed in the first 128MB from 1855 start of memory. 1856 1857config EFI_STUB 1858 bool 1859 1860config EFI 1861 bool "UEFI runtime support" 1862 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1863 select UCS2_STRING 1864 select EFI_PARAMS_FROM_FDT 1865 select EFI_STUB 1866 select EFI_GENERIC_STUB 1867 select EFI_RUNTIME_WRAPPERS 1868 help 1869 This option provides support for runtime services provided 1870 by UEFI firmware (such as non-volatile variables, realtime 1871 clock, and platform reset). A UEFI stub is also provided to 1872 allow the kernel to be booted as an EFI application. This 1873 is only useful for kernels that may run on systems that have 1874 UEFI firmware. 1875 1876config DMI 1877 bool "Enable support for SMBIOS (DMI) tables" 1878 depends on EFI 1879 default y 1880 help 1881 This enables SMBIOS/DMI feature for systems. 1882 1883 This option is only useful on systems that have UEFI firmware. 1884 However, even with this option, the resultant kernel should 1885 continue to boot on existing non-UEFI platforms. 1886 1887 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1888 i.e., the the practice of identifying the platform via DMI to 1889 decide whether certain workarounds for buggy hardware and/or 1890 firmware need to be enabled. This would require the DMI subsystem 1891 to be enabled much earlier than we do on ARM, which is non-trivial. 1892 1893endmenu 1894 1895menu "CPU Power Management" 1896 1897source "drivers/cpufreq/Kconfig" 1898 1899source "drivers/cpuidle/Kconfig" 1900 1901endmenu 1902 1903menu "Floating point emulation" 1904 1905comment "At least one emulation must be selected" 1906 1907config FPE_NWFPE 1908 bool "NWFPE math emulation" 1909 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1910 help 1911 Say Y to include the NWFPE floating point emulator in the kernel. 1912 This is necessary to run most binaries. Linux does not currently 1913 support floating point hardware so you need to say Y here even if 1914 your machine has an FPA or floating point co-processor podule. 1915 1916 You may say N here if you are going to load the Acorn FPEmulator 1917 early in the bootup. 1918 1919config FPE_NWFPE_XP 1920 bool "Support extended precision" 1921 depends on FPE_NWFPE 1922 help 1923 Say Y to include 80-bit support in the kernel floating-point 1924 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1925 Note that gcc does not generate 80-bit operations by default, 1926 so in most cases this option only enlarges the size of the 1927 floating point emulator without any good reason. 1928 1929 You almost surely want to say N here. 1930 1931config FPE_FASTFPE 1932 bool "FastFPE math emulation (EXPERIMENTAL)" 1933 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1934 help 1935 Say Y here to include the FAST floating point emulator in the kernel. 1936 This is an experimental much faster emulator which now also has full 1937 precision for the mantissa. It does not support any exceptions. 1938 It is very simple, and approximately 3-6 times faster than NWFPE. 1939 1940 It should be sufficient for most programs. It may be not suitable 1941 for scientific calculations, but you have to check this for yourself. 1942 If you do not feel you need a faster FP emulation you should better 1943 choose NWFPE. 1944 1945config VFP 1946 bool "VFP-format floating point maths" 1947 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1948 help 1949 Say Y to include VFP support code in the kernel. This is needed 1950 if your hardware includes a VFP unit. 1951 1952 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1953 release notes and additional status information. 1954 1955 Say N if your target does not have VFP hardware. 1956 1957config VFPv3 1958 bool 1959 depends on VFP 1960 default y if CPU_V7 1961 1962config NEON 1963 bool "Advanced SIMD (NEON) Extension support" 1964 depends on VFPv3 && CPU_V7 1965 help 1966 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1967 Extension. 1968 1969config KERNEL_MODE_NEON 1970 bool "Support for NEON in kernel mode" 1971 depends on NEON && AEABI 1972 help 1973 Say Y to include support for NEON in kernel mode. 1974 1975endmenu 1976 1977menu "Power management options" 1978 1979source "kernel/power/Kconfig" 1980 1981config ARCH_SUSPEND_POSSIBLE 1982 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1983 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1984 def_bool y 1985 1986config ARM_CPU_SUSPEND 1987 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1988 depends on ARCH_SUSPEND_POSSIBLE 1989 1990config ARCH_HIBERNATION_POSSIBLE 1991 bool 1992 depends on MMU 1993 default y if ARCH_SUSPEND_POSSIBLE 1994 1995endmenu 1996 1997if CRYPTO 1998source "arch/arm/crypto/Kconfig" 1999endif 2000 2001source "arch/arm/Kconfig.assembler" 2002