1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 13 select HAVE_ARCH_KGDB 14 select HAVE_KPROBES if !XIP_KERNEL 15 select HAVE_KRETPROBES if (HAVE_KPROBES) 16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 21 select HAVE_GENERIC_DMA_COHERENT 22 select HAVE_KERNEL_GZIP 23 select HAVE_KERNEL_LZO 24 select HAVE_KERNEL_LZMA 25 select HAVE_KERNEL_XZ 26 select HAVE_IRQ_WORK 27 select HAVE_PERF_EVENTS 28 select PERF_USE_VMALLOC 29 select HAVE_REGS_AND_STACK_ACCESS_API 30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 31 select HAVE_C_RECORDMCOUNT 32 select HAVE_GENERIC_HARDIRQS 33 select HAVE_SPARSE_IRQ 34 select GENERIC_IRQ_SHOW 35 select CPU_PM if (SUSPEND || CPU_IDLE) 36 select GENERIC_PCI_IOMAP 37 help 38 The ARM series is a line of low-power-consumption RISC chip designs 39 licensed by ARM Ltd and targeted at embedded applications and 40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 41 manufactured, but legacy ARM-based PC hardware remains popular in 42 Europe. There is an ARM Linux project with a web page at 43 <http://www.arm.linux.org.uk/>. 44 45config ARM_HAS_SG_CHAIN 46 bool 47 48config HAVE_PWM 49 bool 50 51config MIGHT_HAVE_PCI 52 bool 53 54config SYS_SUPPORTS_APM_EMULATION 55 bool 56 57config HAVE_SCHED_CLOCK 58 bool 59 60config GENERIC_GPIO 61 bool 62 63config ARCH_USES_GETTIMEOFFSET 64 bool 65 default n 66 67config GENERIC_CLOCKEVENTS 68 bool 69 70config GENERIC_CLOCKEVENTS_BROADCAST 71 bool 72 depends on GENERIC_CLOCKEVENTS 73 default y if SMP 74 75config KTIME_SCALAR 76 bool 77 default y 78 79config HAVE_TCM 80 bool 81 select GENERIC_ALLOCATOR 82 83config HAVE_PROC_CPU 84 bool 85 86config NO_IOPORT 87 bool 88 89config EISA 90 bool 91 ---help--- 92 The Extended Industry Standard Architecture (EISA) bus was 93 developed as an open alternative to the IBM MicroChannel bus. 94 95 The EISA bus provided some of the features of the IBM MicroChannel 96 bus while maintaining backward compatibility with cards made for 97 the older ISA bus. The EISA bus saw limited use between 1988 and 98 1995 when it was made obsolete by the PCI bus. 99 100 Say Y here if you are building a kernel for an EISA-based machine. 101 102 Otherwise, say N. 103 104config SBUS 105 bool 106 107config MCA 108 bool 109 help 110 MicroChannel Architecture is found in some IBM PS/2 machines and 111 laptops. It is a bus system similar to PCI or ISA. See 112 <file:Documentation/mca.txt> (and especially the web page given 113 there) before attempting to build an MCA bus kernel. 114 115config STACKTRACE_SUPPORT 116 bool 117 default y 118 119config HAVE_LATENCYTOP_SUPPORT 120 bool 121 depends on !SMP 122 default y 123 124config LOCKDEP_SUPPORT 125 bool 126 default y 127 128config TRACE_IRQFLAGS_SUPPORT 129 bool 130 default y 131 132config HARDIRQS_SW_RESEND 133 bool 134 default y 135 136config GENERIC_IRQ_PROBE 137 bool 138 default y 139 140config GENERIC_LOCKBREAK 141 bool 142 default y 143 depends on SMP && PREEMPT 144 145config RWSEM_GENERIC_SPINLOCK 146 bool 147 default y 148 149config RWSEM_XCHGADD_ALGORITHM 150 bool 151 152config ARCH_HAS_ILOG2_U32 153 bool 154 155config ARCH_HAS_ILOG2_U64 156 bool 157 158config ARCH_HAS_CPUFREQ 159 bool 160 help 161 Internal node to signify that the ARCH has CPUFREQ support 162 and that the relevant menu configurations are displayed for 163 it. 164 165config ARCH_HAS_CPU_IDLE_WAIT 166 def_bool y 167 168config GENERIC_HWEIGHT 169 bool 170 default y 171 172config GENERIC_CALIBRATE_DELAY 173 bool 174 default y 175 176config ARCH_MAY_HAVE_PC_FDC 177 bool 178 179config ZONE_DMA 180 bool 181 182config NEED_DMA_MAP_STATE 183 def_bool y 184 185config GENERIC_ISA_DMA 186 bool 187 188config FIQ 189 bool 190 191config ARCH_MTD_XIP 192 bool 193 194config VECTORS_BASE 195 hex 196 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 197 default DRAM_BASE if REMAP_VECTORS_TO_RAM 198 default 0x00000000 199 help 200 The base address of exception vectors. 201 202config ARM_PATCH_PHYS_VIRT 203 bool "Patch physical to virtual translations at runtime" if EMBEDDED 204 default y 205 depends on !XIP_KERNEL && MMU 206 depends on !ARCH_REALVIEW || !SPARSEMEM 207 help 208 Patch phys-to-virt and virt-to-phys translation functions at 209 boot and module load time according to the position of the 210 kernel in system memory. 211 212 This can only be used with non-XIP MMU kernels where the base 213 of physical memory is at a 16MB boundary. 214 215 Only disable this option if you know that you do not require 216 this feature (eg, building a kernel for a single machine) and 217 you need to shrink the kernel to the minimal size. 218 219config NEED_MACH_MEMORY_H 220 bool 221 help 222 Select this when mach/memory.h is required to provide special 223 definitions for this platform. The need for mach/memory.h should 224 be avoided when possible. 225 226config PHYS_OFFSET 227 hex "Physical address of main memory" if MMU 228 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 229 default DRAM_BASE if !MMU 230 help 231 Please provide the physical address corresponding to the 232 location of main memory in your system. 233 234config GENERIC_BUG 235 def_bool y 236 depends on BUG 237 238source "init/Kconfig" 239 240source "kernel/Kconfig.freezer" 241 242menu "System Type" 243 244config MMU 245 bool "MMU-based Paged Memory Management Support" 246 default y 247 help 248 Select if you want MMU-based virtualised addressing space 249 support by paged memory management. If unsure, say 'Y'. 250 251# 252# The "ARM system type" choice list is ordered alphabetically by option 253# text. Please add new entries in the option alphabetic order. 254# 255choice 256 prompt "ARM system type" 257 default ARCH_VERSATILE 258 259config ARCH_INTEGRATOR 260 bool "ARM Ltd. Integrator family" 261 select ARM_AMBA 262 select ARCH_HAS_CPUFREQ 263 select CLKDEV_LOOKUP 264 select HAVE_MACH_CLKDEV 265 select HAVE_TCM 266 select ICST 267 select GENERIC_CLOCKEVENTS 268 select PLAT_VERSATILE 269 select PLAT_VERSATILE_FPGA_IRQ 270 select NEED_MACH_MEMORY_H 271 help 272 Support for ARM's Integrator platform. 273 274config ARCH_REALVIEW 275 bool "ARM Ltd. RealView family" 276 select ARM_AMBA 277 select CLKDEV_LOOKUP 278 select HAVE_MACH_CLKDEV 279 select ICST 280 select GENERIC_CLOCKEVENTS 281 select ARCH_WANT_OPTIONAL_GPIOLIB 282 select PLAT_VERSATILE 283 select PLAT_VERSATILE_CLCD 284 select ARM_TIMER_SP804 285 select GPIO_PL061 if GPIOLIB 286 select NEED_MACH_MEMORY_H 287 help 288 This enables support for ARM Ltd RealView boards. 289 290config ARCH_VERSATILE 291 bool "ARM Ltd. Versatile family" 292 select ARM_AMBA 293 select ARM_VIC 294 select CLKDEV_LOOKUP 295 select HAVE_MACH_CLKDEV 296 select ICST 297 select GENERIC_CLOCKEVENTS 298 select ARCH_WANT_OPTIONAL_GPIOLIB 299 select PLAT_VERSATILE 300 select PLAT_VERSATILE_CLCD 301 select PLAT_VERSATILE_FPGA_IRQ 302 select ARM_TIMER_SP804 303 help 304 This enables support for ARM Ltd Versatile board. 305 306config ARCH_VEXPRESS 307 bool "ARM Ltd. Versatile Express family" 308 select ARCH_WANT_OPTIONAL_GPIOLIB 309 select ARM_AMBA 310 select ARM_TIMER_SP804 311 select CLKDEV_LOOKUP 312 select HAVE_MACH_CLKDEV 313 select GENERIC_CLOCKEVENTS 314 select HAVE_CLK 315 select HAVE_PATA_PLATFORM 316 select ICST 317 select NO_IOPORT 318 select PLAT_VERSATILE 319 select PLAT_VERSATILE_CLCD 320 help 321 This enables support for the ARM Ltd Versatile Express boards. 322 323config ARCH_AT91 324 bool "Atmel AT91" 325 select ARCH_REQUIRE_GPIOLIB 326 select HAVE_CLK 327 select CLKDEV_LOOKUP 328 help 329 This enables support for systems based on the Atmel AT91RM9200, 330 AT91SAM9 and AT91CAP9 processors. 331 332config ARCH_BCMRING 333 bool "Broadcom BCMRING" 334 depends on MMU 335 select CPU_V6 336 select ARM_AMBA 337 select ARM_TIMER_SP804 338 select CLKDEV_LOOKUP 339 select GENERIC_CLOCKEVENTS 340 select ARCH_WANT_OPTIONAL_GPIOLIB 341 help 342 Support for Broadcom's BCMRing platform. 343 344config ARCH_HIGHBANK 345 bool "Calxeda Highbank-based" 346 select ARCH_WANT_OPTIONAL_GPIOLIB 347 select ARM_AMBA 348 select ARM_GIC 349 select ARM_TIMER_SP804 350 select CACHE_L2X0 351 select CLKDEV_LOOKUP 352 select CPU_V7 353 select GENERIC_CLOCKEVENTS 354 select HAVE_ARM_SCU 355 select HAVE_SMP 356 select USE_OF 357 help 358 Support for the Calxeda Highbank SoC based boards. 359 360config ARCH_CLPS711X 361 bool "Cirrus Logic CLPS711x/EP721x-based" 362 select CPU_ARM720T 363 select ARCH_USES_GETTIMEOFFSET 364 select NEED_MACH_MEMORY_H 365 help 366 Support for Cirrus Logic 711x/721x based boards. 367 368config ARCH_CNS3XXX 369 bool "Cavium Networks CNS3XXX family" 370 select CPU_V6K 371 select GENERIC_CLOCKEVENTS 372 select ARM_GIC 373 select MIGHT_HAVE_CACHE_L2X0 374 select MIGHT_HAVE_PCI 375 select PCI_DOMAINS if PCI 376 help 377 Support for Cavium Networks CNS3XXX platform. 378 379config ARCH_GEMINI 380 bool "Cortina Systems Gemini" 381 select CPU_FA526 382 select ARCH_REQUIRE_GPIOLIB 383 select ARCH_USES_GETTIMEOFFSET 384 help 385 Support for the Cortina Systems Gemini family SoCs 386 387config ARCH_PRIMA2 388 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 389 select CPU_V7 390 select NO_IOPORT 391 select GENERIC_CLOCKEVENTS 392 select CLKDEV_LOOKUP 393 select GENERIC_IRQ_CHIP 394 select MIGHT_HAVE_CACHE_L2X0 395 select USE_OF 396 select ZONE_DMA 397 help 398 Support for CSR SiRFSoC ARM Cortex A9 Platform 399 400config ARCH_EBSA110 401 bool "EBSA-110" 402 select CPU_SA110 403 select ISA 404 select NO_IOPORT 405 select ARCH_USES_GETTIMEOFFSET 406 select NEED_MACH_MEMORY_H 407 help 408 This is an evaluation board for the StrongARM processor available 409 from Digital. It has limited hardware on-board, including an 410 Ethernet interface, two PCMCIA sockets, two serial ports and a 411 parallel port. 412 413config ARCH_EP93XX 414 bool "EP93xx-based" 415 select CPU_ARM920T 416 select ARM_AMBA 417 select ARM_VIC 418 select CLKDEV_LOOKUP 419 select ARCH_REQUIRE_GPIOLIB 420 select ARCH_HAS_HOLES_MEMORYMODEL 421 select ARCH_USES_GETTIMEOFFSET 422 select NEED_MACH_MEMORY_H 423 help 424 This enables support for the Cirrus EP93xx series of CPUs. 425 426config ARCH_FOOTBRIDGE 427 bool "FootBridge" 428 select CPU_SA110 429 select FOOTBRIDGE 430 select GENERIC_CLOCKEVENTS 431 select HAVE_IDE 432 select NEED_MACH_MEMORY_H 433 help 434 Support for systems based on the DC21285 companion chip 435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 436 437config ARCH_MXC 438 bool "Freescale MXC/iMX-based" 439 select GENERIC_CLOCKEVENTS 440 select ARCH_REQUIRE_GPIOLIB 441 select CLKDEV_LOOKUP 442 select CLKSRC_MMIO 443 select GENERIC_IRQ_CHIP 444 select HAVE_SCHED_CLOCK 445 select MULTI_IRQ_HANDLER 446 help 447 Support for Freescale MXC/iMX-based family of processors 448 449config ARCH_MXS 450 bool "Freescale MXS-based" 451 select GENERIC_CLOCKEVENTS 452 select ARCH_REQUIRE_GPIOLIB 453 select CLKDEV_LOOKUP 454 select CLKSRC_MMIO 455 select HAVE_CLK_PREPARE 456 help 457 Support for Freescale MXS-based family of processors 458 459config ARCH_NETX 460 bool "Hilscher NetX based" 461 select CLKSRC_MMIO 462 select CPU_ARM926T 463 select ARM_VIC 464 select GENERIC_CLOCKEVENTS 465 help 466 This enables support for systems based on the Hilscher NetX Soc 467 468config ARCH_H720X 469 bool "Hynix HMS720x-based" 470 select CPU_ARM720T 471 select ISA_DMA_API 472 select ARCH_USES_GETTIMEOFFSET 473 help 474 This enables support for systems based on the Hynix HMS720x 475 476config ARCH_IOP13XX 477 bool "IOP13xx-based" 478 depends on MMU 479 select CPU_XSC3 480 select PLAT_IOP 481 select PCI 482 select ARCH_SUPPORTS_MSI 483 select VMSPLIT_1G 484 select NEED_MACH_MEMORY_H 485 help 486 Support for Intel's IOP13XX (XScale) family of processors. 487 488config ARCH_IOP32X 489 bool "IOP32x-based" 490 depends on MMU 491 select CPU_XSCALE 492 select PLAT_IOP 493 select PCI 494 select ARCH_REQUIRE_GPIOLIB 495 help 496 Support for Intel's 80219 and IOP32X (XScale) family of 497 processors. 498 499config ARCH_IOP33X 500 bool "IOP33x-based" 501 depends on MMU 502 select CPU_XSCALE 503 select PLAT_IOP 504 select PCI 505 select ARCH_REQUIRE_GPIOLIB 506 help 507 Support for Intel's IOP33X (XScale) family of processors. 508 509config ARCH_IXP23XX 510 bool "IXP23XX-based" 511 depends on MMU 512 select CPU_XSC3 513 select PCI 514 select ARCH_USES_GETTIMEOFFSET 515 select NEED_MACH_MEMORY_H 516 help 517 Support for Intel's IXP23xx (XScale) family of processors. 518 519config ARCH_IXP2000 520 bool "IXP2400/2800-based" 521 depends on MMU 522 select CPU_XSCALE 523 select PCI 524 select ARCH_USES_GETTIMEOFFSET 525 select NEED_MACH_MEMORY_H 526 help 527 Support for Intel's IXP2400/2800 (XScale) family of processors. 528 529config ARCH_IXP4XX 530 bool "IXP4xx-based" 531 depends on MMU 532 select CLKSRC_MMIO 533 select CPU_XSCALE 534 select GENERIC_GPIO 535 select GENERIC_CLOCKEVENTS 536 select HAVE_SCHED_CLOCK 537 select MIGHT_HAVE_PCI 538 select DMABOUNCE if PCI 539 help 540 Support for Intel's IXP4XX (XScale) family of processors. 541 542config ARCH_DOVE 543 bool "Marvell Dove" 544 select CPU_V7 545 select PCI 546 select ARCH_REQUIRE_GPIOLIB 547 select GENERIC_CLOCKEVENTS 548 select PLAT_ORION 549 help 550 Support for the Marvell Dove SoC 88AP510 551 552config ARCH_KIRKWOOD 553 bool "Marvell Kirkwood" 554 select CPU_FEROCEON 555 select PCI 556 select ARCH_REQUIRE_GPIOLIB 557 select GENERIC_CLOCKEVENTS 558 select PLAT_ORION 559 help 560 Support for the following Marvell Kirkwood series SoCs: 561 88F6180, 88F6192 and 88F6281. 562 563config ARCH_LPC32XX 564 bool "NXP LPC32XX" 565 select CLKSRC_MMIO 566 select CPU_ARM926T 567 select ARCH_REQUIRE_GPIOLIB 568 select HAVE_IDE 569 select ARM_AMBA 570 select USB_ARCH_HAS_OHCI 571 select CLKDEV_LOOKUP 572 select GENERIC_CLOCKEVENTS 573 help 574 Support for the NXP LPC32XX family of processors 575 576config ARCH_MV78XX0 577 bool "Marvell MV78xx0" 578 select CPU_FEROCEON 579 select PCI 580 select ARCH_REQUIRE_GPIOLIB 581 select GENERIC_CLOCKEVENTS 582 select PLAT_ORION 583 help 584 Support for the following Marvell MV78xx0 series SoCs: 585 MV781x0, MV782x0. 586 587config ARCH_ORION5X 588 bool "Marvell Orion" 589 depends on MMU 590 select CPU_FEROCEON 591 select PCI 592 select ARCH_REQUIRE_GPIOLIB 593 select GENERIC_CLOCKEVENTS 594 select PLAT_ORION 595 help 596 Support for the following Marvell Orion 5x series SoCs: 597 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 598 Orion-2 (5281), Orion-1-90 (6183). 599 600config ARCH_MMP 601 bool "Marvell PXA168/910/MMP2" 602 depends on MMU 603 select ARCH_REQUIRE_GPIOLIB 604 select CLKDEV_LOOKUP 605 select GENERIC_CLOCKEVENTS 606 select GPIO_PXA 607 select HAVE_SCHED_CLOCK 608 select TICK_ONESHOT 609 select PLAT_PXA 610 select SPARSE_IRQ 611 select GENERIC_ALLOCATOR 612 help 613 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 614 615config ARCH_KS8695 616 bool "Micrel/Kendin KS8695" 617 select CPU_ARM922T 618 select ARCH_REQUIRE_GPIOLIB 619 select ARCH_USES_GETTIMEOFFSET 620 select NEED_MACH_MEMORY_H 621 help 622 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 623 System-on-Chip devices. 624 625config ARCH_W90X900 626 bool "Nuvoton W90X900 CPU" 627 select CPU_ARM926T 628 select ARCH_REQUIRE_GPIOLIB 629 select CLKDEV_LOOKUP 630 select CLKSRC_MMIO 631 select GENERIC_CLOCKEVENTS 632 help 633 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 634 At present, the w90x900 has been renamed nuc900, regarding 635 the ARM series product line, you can login the following 636 link address to know more. 637 638 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 639 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 640 641config ARCH_TEGRA 642 bool "NVIDIA Tegra" 643 select CLKDEV_LOOKUP 644 select CLKSRC_MMIO 645 select GENERIC_CLOCKEVENTS 646 select GENERIC_GPIO 647 select HAVE_CLK 648 select HAVE_SCHED_CLOCK 649 select HAVE_SMP 650 select MIGHT_HAVE_CACHE_L2X0 651 select ARCH_HAS_CPUFREQ 652 help 653 This enables support for NVIDIA Tegra based systems (Tegra APX, 654 Tegra 6xx and Tegra 2 series). 655 656config ARCH_PICOXCELL 657 bool "Picochip picoXcell" 658 select ARCH_REQUIRE_GPIOLIB 659 select ARM_PATCH_PHYS_VIRT 660 select ARM_VIC 661 select CPU_V6K 662 select DW_APB_TIMER 663 select GENERIC_CLOCKEVENTS 664 select GENERIC_GPIO 665 select HAVE_SCHED_CLOCK 666 select HAVE_TCM 667 select NO_IOPORT 668 select SPARSE_IRQ 669 select USE_OF 670 help 671 This enables support for systems based on the Picochip picoXcell 672 family of Femtocell devices. The picoxcell support requires device tree 673 for all boards. 674 675config ARCH_PNX4008 676 bool "Philips Nexperia PNX4008 Mobile" 677 select CPU_ARM926T 678 select CLKDEV_LOOKUP 679 select ARCH_USES_GETTIMEOFFSET 680 help 681 This enables support for Philips PNX4008 mobile platform. 682 683config ARCH_PXA 684 bool "PXA2xx/PXA3xx-based" 685 depends on MMU 686 select ARCH_MTD_XIP 687 select ARCH_HAS_CPUFREQ 688 select CLKDEV_LOOKUP 689 select CLKSRC_MMIO 690 select ARCH_REQUIRE_GPIOLIB 691 select GENERIC_CLOCKEVENTS 692 select GPIO_PXA 693 select HAVE_SCHED_CLOCK 694 select TICK_ONESHOT 695 select PLAT_PXA 696 select SPARSE_IRQ 697 select AUTO_ZRELADDR 698 select MULTI_IRQ_HANDLER 699 select ARM_CPU_SUSPEND if PM 700 select HAVE_IDE 701 help 702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 703 704config ARCH_MSM 705 bool "Qualcomm MSM" 706 select HAVE_CLK 707 select GENERIC_CLOCKEVENTS 708 select ARCH_REQUIRE_GPIOLIB 709 select CLKDEV_LOOKUP 710 help 711 Support for Qualcomm MSM/QSD based systems. This runs on the 712 apps processor of the MSM/QSD and depends on a shared memory 713 interface to the modem processor which runs the baseband 714 stack and controls some vital subsystems 715 (clock and power control, etc). 716 717config ARCH_SHMOBILE 718 bool "Renesas SH-Mobile / R-Mobile" 719 select HAVE_CLK 720 select CLKDEV_LOOKUP 721 select HAVE_MACH_CLKDEV 722 select HAVE_SMP 723 select GENERIC_CLOCKEVENTS 724 select MIGHT_HAVE_CACHE_L2X0 725 select NO_IOPORT 726 select SPARSE_IRQ 727 select MULTI_IRQ_HANDLER 728 select PM_GENERIC_DOMAINS if PM 729 select NEED_MACH_MEMORY_H 730 help 731 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 732 733config ARCH_RPC 734 bool "RiscPC" 735 select ARCH_ACORN 736 select FIQ 737 select TIMER_ACORN 738 select ARCH_MAY_HAVE_PC_FDC 739 select HAVE_PATA_PLATFORM 740 select ISA_DMA_API 741 select NO_IOPORT 742 select ARCH_SPARSEMEM_ENABLE 743 select ARCH_USES_GETTIMEOFFSET 744 select HAVE_IDE 745 select NEED_MACH_MEMORY_H 746 help 747 On the Acorn Risc-PC, Linux can support the internal IDE disk and 748 CD-ROM interface, serial and parallel port, and the floppy drive. 749 750config ARCH_SA1100 751 bool "SA1100-based" 752 select CLKSRC_MMIO 753 select CPU_SA1100 754 select ISA 755 select ARCH_SPARSEMEM_ENABLE 756 select ARCH_MTD_XIP 757 select ARCH_HAS_CPUFREQ 758 select CPU_FREQ 759 select GENERIC_CLOCKEVENTS 760 select CLKDEV_LOOKUP 761 select HAVE_SCHED_CLOCK 762 select TICK_ONESHOT 763 select ARCH_REQUIRE_GPIOLIB 764 select HAVE_IDE 765 select NEED_MACH_MEMORY_H 766 help 767 Support for StrongARM 11x0 based boards. 768 769config ARCH_S3C2410 770 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 771 select GENERIC_GPIO 772 select ARCH_HAS_CPUFREQ 773 select HAVE_CLK 774 select CLKDEV_LOOKUP 775 select ARCH_USES_GETTIMEOFFSET 776 select HAVE_S3C2410_I2C if I2C 777 help 778 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 779 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 780 the Samsung SMDK2410 development board (and derivatives). 781 782 Note, the S3C2416 and the S3C2450 are so close that they even share 783 the same SoC ID code. This means that there is no separate machine 784 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 785 786config ARCH_S3C64XX 787 bool "Samsung S3C64XX" 788 select PLAT_SAMSUNG 789 select CPU_V6 790 select ARM_VIC 791 select HAVE_CLK 792 select HAVE_TCM 793 select CLKDEV_LOOKUP 794 select NO_IOPORT 795 select ARCH_USES_GETTIMEOFFSET 796 select ARCH_HAS_CPUFREQ 797 select ARCH_REQUIRE_GPIOLIB 798 select SAMSUNG_CLKSRC 799 select SAMSUNG_IRQ_VIC_TIMER 800 select S3C_GPIO_TRACK 801 select S3C_DEV_NAND 802 select USB_ARCH_HAS_OHCI 803 select SAMSUNG_GPIOLIB_4BIT 804 select HAVE_S3C2410_I2C if I2C 805 select HAVE_S3C2410_WATCHDOG if WATCHDOG 806 help 807 Samsung S3C64XX series based systems 808 809config ARCH_S5P64X0 810 bool "Samsung S5P6440 S5P6450" 811 select CPU_V6 812 select GENERIC_GPIO 813 select HAVE_CLK 814 select CLKDEV_LOOKUP 815 select CLKSRC_MMIO 816 select HAVE_S3C2410_WATCHDOG if WATCHDOG 817 select GENERIC_CLOCKEVENTS 818 select HAVE_SCHED_CLOCK 819 select HAVE_S3C2410_I2C if I2C 820 select HAVE_S3C_RTC if RTC_CLASS 821 help 822 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 823 SMDK6450. 824 825config ARCH_S5PC100 826 bool "Samsung S5PC100" 827 select GENERIC_GPIO 828 select HAVE_CLK 829 select CLKDEV_LOOKUP 830 select CPU_V7 831 select ARM_L1_CACHE_SHIFT_6 832 select ARCH_USES_GETTIMEOFFSET 833 select HAVE_S3C2410_I2C if I2C 834 select HAVE_S3C_RTC if RTC_CLASS 835 select HAVE_S3C2410_WATCHDOG if WATCHDOG 836 help 837 Samsung S5PC100 series based systems 838 839config ARCH_S5PV210 840 bool "Samsung S5PV210/S5PC110" 841 select CPU_V7 842 select ARCH_SPARSEMEM_ENABLE 843 select ARCH_HAS_HOLES_MEMORYMODEL 844 select GENERIC_GPIO 845 select HAVE_CLK 846 select CLKDEV_LOOKUP 847 select CLKSRC_MMIO 848 select ARM_L1_CACHE_SHIFT_6 849 select ARCH_HAS_CPUFREQ 850 select GENERIC_CLOCKEVENTS 851 select HAVE_SCHED_CLOCK 852 select HAVE_S3C2410_I2C if I2C 853 select HAVE_S3C_RTC if RTC_CLASS 854 select HAVE_S3C2410_WATCHDOG if WATCHDOG 855 select NEED_MACH_MEMORY_H 856 help 857 Samsung S5PV210/S5PC110 series based systems 858 859config ARCH_EXYNOS 860 bool "SAMSUNG EXYNOS" 861 select CPU_V7 862 select ARCH_SPARSEMEM_ENABLE 863 select ARCH_HAS_HOLES_MEMORYMODEL 864 select GENERIC_GPIO 865 select HAVE_CLK 866 select CLKDEV_LOOKUP 867 select ARCH_HAS_CPUFREQ 868 select GENERIC_CLOCKEVENTS 869 select HAVE_S3C_RTC if RTC_CLASS 870 select HAVE_S3C2410_I2C if I2C 871 select HAVE_S3C2410_WATCHDOG if WATCHDOG 872 select NEED_MACH_MEMORY_H 873 help 874 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 875 876config ARCH_SHARK 877 bool "Shark" 878 select CPU_SA110 879 select ISA 880 select ISA_DMA 881 select ZONE_DMA 882 select PCI 883 select ARCH_USES_GETTIMEOFFSET 884 select NEED_MACH_MEMORY_H 885 help 886 Support for the StrongARM based Digital DNARD machine, also known 887 as "Shark" (<http://www.shark-linux.de/shark.html>). 888 889config ARCH_U300 890 bool "ST-Ericsson U300 Series" 891 depends on MMU 892 select CLKSRC_MMIO 893 select CPU_ARM926T 894 select HAVE_SCHED_CLOCK 895 select HAVE_TCM 896 select ARM_AMBA 897 select ARM_PATCH_PHYS_VIRT 898 select ARM_VIC 899 select GENERIC_CLOCKEVENTS 900 select CLKDEV_LOOKUP 901 select HAVE_MACH_CLKDEV 902 select GENERIC_GPIO 903 select ARCH_REQUIRE_GPIOLIB 904 help 905 Support for ST-Ericsson U300 series mobile platforms. 906 907config ARCH_U8500 908 bool "ST-Ericsson U8500 Series" 909 select CPU_V7 910 select ARM_AMBA 911 select GENERIC_CLOCKEVENTS 912 select CLKDEV_LOOKUP 913 select ARCH_REQUIRE_GPIOLIB 914 select ARCH_HAS_CPUFREQ 915 select HAVE_SMP 916 select MIGHT_HAVE_CACHE_L2X0 917 help 918 Support for ST-Ericsson's Ux500 architecture 919 920config ARCH_NOMADIK 921 bool "STMicroelectronics Nomadik" 922 select ARM_AMBA 923 select ARM_VIC 924 select CPU_ARM926T 925 select CLKDEV_LOOKUP 926 select GENERIC_CLOCKEVENTS 927 select MIGHT_HAVE_CACHE_L2X0 928 select ARCH_REQUIRE_GPIOLIB 929 help 930 Support for the Nomadik platform by ST-Ericsson 931 932config ARCH_DAVINCI 933 bool "TI DaVinci" 934 select GENERIC_CLOCKEVENTS 935 select ARCH_REQUIRE_GPIOLIB 936 select ZONE_DMA 937 select HAVE_IDE 938 select CLKDEV_LOOKUP 939 select GENERIC_ALLOCATOR 940 select GENERIC_IRQ_CHIP 941 select ARCH_HAS_HOLES_MEMORYMODEL 942 help 943 Support for TI's DaVinci platform. 944 945config ARCH_OMAP 946 bool "TI OMAP" 947 select HAVE_CLK 948 select ARCH_REQUIRE_GPIOLIB 949 select ARCH_HAS_CPUFREQ 950 select CLKSRC_MMIO 951 select GENERIC_CLOCKEVENTS 952 select HAVE_SCHED_CLOCK 953 select ARCH_HAS_HOLES_MEMORYMODEL 954 help 955 Support for TI's OMAP platform (OMAP1/2/3/4). 956 957config PLAT_SPEAR 958 bool "ST SPEAr" 959 select ARM_AMBA 960 select ARCH_REQUIRE_GPIOLIB 961 select CLKDEV_LOOKUP 962 select CLKSRC_MMIO 963 select GENERIC_CLOCKEVENTS 964 select HAVE_CLK 965 help 966 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 967 968config ARCH_VT8500 969 bool "VIA/WonderMedia 85xx" 970 select CPU_ARM926T 971 select GENERIC_GPIO 972 select ARCH_HAS_CPUFREQ 973 select GENERIC_CLOCKEVENTS 974 select ARCH_REQUIRE_GPIOLIB 975 select HAVE_PWM 976 help 977 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 978 979config ARCH_ZYNQ 980 bool "Xilinx Zynq ARM Cortex A9 Platform" 981 select CPU_V7 982 select GENERIC_CLOCKEVENTS 983 select CLKDEV_LOOKUP 984 select ARM_GIC 985 select ARM_AMBA 986 select ICST 987 select MIGHT_HAVE_CACHE_L2X0 988 select USE_OF 989 help 990 Support for Xilinx Zynq ARM Cortex A9 Platform 991endchoice 992 993# 994# This is sorted alphabetically by mach-* pathname. However, plat-* 995# Kconfigs may be included either alphabetically (according to the 996# plat- suffix) or along side the corresponding mach-* source. 997# 998source "arch/arm/mach-at91/Kconfig" 999 1000source "arch/arm/mach-bcmring/Kconfig" 1001 1002source "arch/arm/mach-clps711x/Kconfig" 1003 1004source "arch/arm/mach-cns3xxx/Kconfig" 1005 1006source "arch/arm/mach-davinci/Kconfig" 1007 1008source "arch/arm/mach-dove/Kconfig" 1009 1010source "arch/arm/mach-ep93xx/Kconfig" 1011 1012source "arch/arm/mach-footbridge/Kconfig" 1013 1014source "arch/arm/mach-gemini/Kconfig" 1015 1016source "arch/arm/mach-h720x/Kconfig" 1017 1018source "arch/arm/mach-integrator/Kconfig" 1019 1020source "arch/arm/mach-iop32x/Kconfig" 1021 1022source "arch/arm/mach-iop33x/Kconfig" 1023 1024source "arch/arm/mach-iop13xx/Kconfig" 1025 1026source "arch/arm/mach-ixp4xx/Kconfig" 1027 1028source "arch/arm/mach-ixp2000/Kconfig" 1029 1030source "arch/arm/mach-ixp23xx/Kconfig" 1031 1032source "arch/arm/mach-kirkwood/Kconfig" 1033 1034source "arch/arm/mach-ks8695/Kconfig" 1035 1036source "arch/arm/mach-lpc32xx/Kconfig" 1037 1038source "arch/arm/mach-msm/Kconfig" 1039 1040source "arch/arm/mach-mv78xx0/Kconfig" 1041 1042source "arch/arm/plat-mxc/Kconfig" 1043 1044source "arch/arm/mach-mxs/Kconfig" 1045 1046source "arch/arm/mach-netx/Kconfig" 1047 1048source "arch/arm/mach-nomadik/Kconfig" 1049source "arch/arm/plat-nomadik/Kconfig" 1050 1051source "arch/arm/plat-omap/Kconfig" 1052 1053source "arch/arm/mach-omap1/Kconfig" 1054 1055source "arch/arm/mach-omap2/Kconfig" 1056 1057source "arch/arm/mach-orion5x/Kconfig" 1058 1059source "arch/arm/mach-pxa/Kconfig" 1060source "arch/arm/plat-pxa/Kconfig" 1061 1062source "arch/arm/mach-mmp/Kconfig" 1063 1064source "arch/arm/mach-realview/Kconfig" 1065 1066source "arch/arm/mach-sa1100/Kconfig" 1067 1068source "arch/arm/plat-samsung/Kconfig" 1069source "arch/arm/plat-s3c24xx/Kconfig" 1070source "arch/arm/plat-s5p/Kconfig" 1071 1072source "arch/arm/plat-spear/Kconfig" 1073 1074if ARCH_S3C2410 1075source "arch/arm/mach-s3c2410/Kconfig" 1076source "arch/arm/mach-s3c2412/Kconfig" 1077source "arch/arm/mach-s3c2416/Kconfig" 1078source "arch/arm/mach-s3c2440/Kconfig" 1079source "arch/arm/mach-s3c2443/Kconfig" 1080endif 1081 1082if ARCH_S3C64XX 1083source "arch/arm/mach-s3c64xx/Kconfig" 1084endif 1085 1086source "arch/arm/mach-s5p64x0/Kconfig" 1087 1088source "arch/arm/mach-s5pc100/Kconfig" 1089 1090source "arch/arm/mach-s5pv210/Kconfig" 1091 1092source "arch/arm/mach-exynos/Kconfig" 1093 1094source "arch/arm/mach-shmobile/Kconfig" 1095 1096source "arch/arm/mach-tegra/Kconfig" 1097 1098source "arch/arm/mach-u300/Kconfig" 1099 1100source "arch/arm/mach-ux500/Kconfig" 1101 1102source "arch/arm/mach-versatile/Kconfig" 1103 1104source "arch/arm/mach-vexpress/Kconfig" 1105source "arch/arm/plat-versatile/Kconfig" 1106 1107source "arch/arm/mach-vt8500/Kconfig" 1108 1109source "arch/arm/mach-w90x900/Kconfig" 1110 1111# Definitions to make life easier 1112config ARCH_ACORN 1113 bool 1114 1115config PLAT_IOP 1116 bool 1117 select GENERIC_CLOCKEVENTS 1118 select HAVE_SCHED_CLOCK 1119 1120config PLAT_ORION 1121 bool 1122 select CLKSRC_MMIO 1123 select GENERIC_IRQ_CHIP 1124 select HAVE_SCHED_CLOCK 1125 1126config PLAT_PXA 1127 bool 1128 1129config PLAT_VERSATILE 1130 bool 1131 1132config ARM_TIMER_SP804 1133 bool 1134 select CLKSRC_MMIO 1135 1136source arch/arm/mm/Kconfig 1137 1138config ARM_NR_BANKS 1139 int 1140 default 16 if ARCH_EP93XX 1141 default 8 1142 1143config IWMMXT 1144 bool "Enable iWMMXt support" 1145 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1146 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1147 help 1148 Enable support for iWMMXt context switching at run time if 1149 running on a CPU that supports it. 1150 1151config XSCALE_PMU 1152 bool 1153 depends on CPU_XSCALE 1154 default y 1155 1156config CPU_HAS_PMU 1157 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1158 (!ARCH_OMAP3 || OMAP3_EMU) 1159 default y 1160 bool 1161 1162config MULTI_IRQ_HANDLER 1163 bool 1164 help 1165 Allow each machine to specify it's own IRQ handler at run time. 1166 1167if !MMU 1168source "arch/arm/Kconfig-nommu" 1169endif 1170 1171config ARM_ERRATA_411920 1172 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1173 depends on CPU_V6 || CPU_V6K 1174 help 1175 Invalidation of the Instruction Cache operation can 1176 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1177 It does not affect the MPCore. This option enables the ARM Ltd. 1178 recommended workaround. 1179 1180config ARM_ERRATA_430973 1181 bool "ARM errata: Stale prediction on replaced interworking branch" 1182 depends on CPU_V7 1183 help 1184 This option enables the workaround for the 430973 Cortex-A8 1185 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1186 interworking branch is replaced with another code sequence at the 1187 same virtual address, whether due to self-modifying code or virtual 1188 to physical address re-mapping, Cortex-A8 does not recover from the 1189 stale interworking branch prediction. This results in Cortex-A8 1190 executing the new code sequence in the incorrect ARM or Thumb state. 1191 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1192 and also flushes the branch target cache at every context switch. 1193 Note that setting specific bits in the ACTLR register may not be 1194 available in non-secure mode. 1195 1196config ARM_ERRATA_458693 1197 bool "ARM errata: Processor deadlock when a false hazard is created" 1198 depends on CPU_V7 1199 help 1200 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1201 erratum. For very specific sequences of memory operations, it is 1202 possible for a hazard condition intended for a cache line to instead 1203 be incorrectly associated with a different cache line. This false 1204 hazard might then cause a processor deadlock. The workaround enables 1205 the L1 caching of the NEON accesses and disables the PLD instruction 1206 in the ACTLR register. Note that setting specific bits in the ACTLR 1207 register may not be available in non-secure mode. 1208 1209config ARM_ERRATA_460075 1210 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1211 depends on CPU_V7 1212 help 1213 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1214 erratum. Any asynchronous access to the L2 cache may encounter a 1215 situation in which recent store transactions to the L2 cache are lost 1216 and overwritten with stale memory contents from external memory. The 1217 workaround disables the write-allocate mode for the L2 cache via the 1218 ACTLR register. Note that setting specific bits in the ACTLR register 1219 may not be available in non-secure mode. 1220 1221config ARM_ERRATA_742230 1222 bool "ARM errata: DMB operation may be faulty" 1223 depends on CPU_V7 && SMP 1224 help 1225 This option enables the workaround for the 742230 Cortex-A9 1226 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1227 between two write operations may not ensure the correct visibility 1228 ordering of the two writes. This workaround sets a specific bit in 1229 the diagnostic register of the Cortex-A9 which causes the DMB 1230 instruction to behave as a DSB, ensuring the correct behaviour of 1231 the two writes. 1232 1233config ARM_ERRATA_742231 1234 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1235 depends on CPU_V7 && SMP 1236 help 1237 This option enables the workaround for the 742231 Cortex-A9 1238 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1239 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1240 accessing some data located in the same cache line, may get corrupted 1241 data due to bad handling of the address hazard when the line gets 1242 replaced from one of the CPUs at the same time as another CPU is 1243 accessing it. This workaround sets specific bits in the diagnostic 1244 register of the Cortex-A9 which reduces the linefill issuing 1245 capabilities of the processor. 1246 1247config PL310_ERRATA_588369 1248 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1249 depends on CACHE_L2X0 1250 help 1251 The PL310 L2 cache controller implements three types of Clean & 1252 Invalidate maintenance operations: by Physical Address 1253 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1254 They are architecturally defined to behave as the execution of a 1255 clean operation followed immediately by an invalidate operation, 1256 both performing to the same memory location. This functionality 1257 is not correctly implemented in PL310 as clean lines are not 1258 invalidated as a result of these operations. 1259 1260config ARM_ERRATA_720789 1261 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1262 depends on CPU_V7 1263 help 1264 This option enables the workaround for the 720789 Cortex-A9 (prior to 1265 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1266 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1267 As a consequence of this erratum, some TLB entries which should be 1268 invalidated are not, resulting in an incoherency in the system page 1269 tables. The workaround changes the TLB flushing routines to invalidate 1270 entries regardless of the ASID. 1271 1272config PL310_ERRATA_727915 1273 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1274 depends on CACHE_L2X0 1275 help 1276 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1277 operation (offset 0x7FC). This operation runs in background so that 1278 PL310 can handle normal accesses while it is in progress. Under very 1279 rare circumstances, due to this erratum, write data can be lost when 1280 PL310 treats a cacheable write transaction during a Clean & 1281 Invalidate by Way operation. 1282 1283config ARM_ERRATA_743622 1284 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1285 depends on CPU_V7 1286 help 1287 This option enables the workaround for the 743622 Cortex-A9 1288 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1289 optimisation in the Cortex-A9 Store Buffer may lead to data 1290 corruption. This workaround sets a specific bit in the diagnostic 1291 register of the Cortex-A9 which disables the Store Buffer 1292 optimisation, preventing the defect from occurring. This has no 1293 visible impact on the overall performance or power consumption of the 1294 processor. 1295 1296config ARM_ERRATA_751472 1297 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1298 depends on CPU_V7 1299 help 1300 This option enables the workaround for the 751472 Cortex-A9 (prior 1301 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1302 completion of a following broadcasted operation if the second 1303 operation is received by a CPU before the ICIALLUIS has completed, 1304 potentially leading to corrupted entries in the cache or TLB. 1305 1306config PL310_ERRATA_753970 1307 bool "PL310 errata: cache sync operation may be faulty" 1308 depends on CACHE_PL310 1309 help 1310 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1311 1312 Under some condition the effect of cache sync operation on 1313 the store buffer still remains when the operation completes. 1314 This means that the store buffer is always asked to drain and 1315 this prevents it from merging any further writes. The workaround 1316 is to replace the normal offset of cache sync operation (0x730) 1317 by another offset targeting an unmapped PL310 register 0x740. 1318 This has the same effect as the cache sync operation: store buffer 1319 drain and waiting for all buffers empty. 1320 1321config ARM_ERRATA_754322 1322 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1323 depends on CPU_V7 1324 help 1325 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1326 r3p*) erratum. A speculative memory access may cause a page table walk 1327 which starts prior to an ASID switch but completes afterwards. This 1328 can populate the micro-TLB with a stale entry which may be hit with 1329 the new ASID. This workaround places two dsb instructions in the mm 1330 switching code so that no page table walks can cross the ASID switch. 1331 1332config ARM_ERRATA_754327 1333 bool "ARM errata: no automatic Store Buffer drain" 1334 depends on CPU_V7 && SMP 1335 help 1336 This option enables the workaround for the 754327 Cortex-A9 (prior to 1337 r2p0) erratum. The Store Buffer does not have any automatic draining 1338 mechanism and therefore a livelock may occur if an external agent 1339 continuously polls a memory location waiting to observe an update. 1340 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1341 written polling loops from denying visibility of updates to memory. 1342 1343config ARM_ERRATA_364296 1344 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1345 depends on CPU_V6 && !SMP 1346 help 1347 This options enables the workaround for the 364296 ARM1136 1348 r0p2 erratum (possible cache data corruption with 1349 hit-under-miss enabled). It sets the undocumented bit 31 in 1350 the auxiliary control register and the FI bit in the control 1351 register, thus disabling hit-under-miss without putting the 1352 processor into full low interrupt latency mode. ARM11MPCore 1353 is not affected. 1354 1355config ARM_ERRATA_764369 1356 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1357 depends on CPU_V7 && SMP 1358 help 1359 This option enables the workaround for erratum 764369 1360 affecting Cortex-A9 MPCore with two or more processors (all 1361 current revisions). Under certain timing circumstances, a data 1362 cache line maintenance operation by MVA targeting an Inner 1363 Shareable memory region may fail to proceed up to either the 1364 Point of Coherency or to the Point of Unification of the 1365 system. This workaround adds a DSB instruction before the 1366 relevant cache maintenance functions and sets a specific bit 1367 in the diagnostic control register of the SCU. 1368 1369config PL310_ERRATA_769419 1370 bool "PL310 errata: no automatic Store Buffer drain" 1371 depends on CACHE_L2X0 1372 help 1373 On revisions of the PL310 prior to r3p2, the Store Buffer does 1374 not automatically drain. This can cause normal, non-cacheable 1375 writes to be retained when the memory system is idle, leading 1376 to suboptimal I/O performance for drivers using coherent DMA. 1377 This option adds a write barrier to the cpu_idle loop so that, 1378 on systems with an outer cache, the store buffer is drained 1379 explicitly. 1380 1381endmenu 1382 1383source "arch/arm/common/Kconfig" 1384 1385menu "Bus support" 1386 1387config ARM_AMBA 1388 bool 1389 1390config ISA 1391 bool 1392 help 1393 Find out whether you have ISA slots on your motherboard. ISA is the 1394 name of a bus system, i.e. the way the CPU talks to the other stuff 1395 inside your box. Other bus systems are PCI, EISA, MicroChannel 1396 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1397 newer boards don't support it. If you have ISA, say Y, otherwise N. 1398 1399# Select ISA DMA controller support 1400config ISA_DMA 1401 bool 1402 select ISA_DMA_API 1403 1404# Select ISA DMA interface 1405config ISA_DMA_API 1406 bool 1407 1408config PCI 1409 bool "PCI support" if MIGHT_HAVE_PCI 1410 help 1411 Find out whether you have a PCI motherboard. PCI is the name of a 1412 bus system, i.e. the way the CPU talks to the other stuff inside 1413 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1414 VESA. If you have PCI, say Y, otherwise N. 1415 1416config PCI_DOMAINS 1417 bool 1418 depends on PCI 1419 1420config PCI_NANOENGINE 1421 bool "BSE nanoEngine PCI support" 1422 depends on SA1100_NANOENGINE 1423 help 1424 Enable PCI on the BSE nanoEngine board. 1425 1426config PCI_SYSCALL 1427 def_bool PCI 1428 1429# Select the host bridge type 1430config PCI_HOST_VIA82C505 1431 bool 1432 depends on PCI && ARCH_SHARK 1433 default y 1434 1435config PCI_HOST_ITE8152 1436 bool 1437 depends on PCI && MACH_ARMCORE 1438 default y 1439 select DMABOUNCE 1440 1441source "drivers/pci/Kconfig" 1442 1443source "drivers/pcmcia/Kconfig" 1444 1445endmenu 1446 1447menu "Kernel Features" 1448 1449source "kernel/time/Kconfig" 1450 1451config HAVE_SMP 1452 bool 1453 help 1454 This option should be selected by machines which have an SMP- 1455 capable CPU. 1456 1457 The only effect of this option is to make the SMP-related 1458 options available to the user for configuration. 1459 1460config SMP 1461 bool "Symmetric Multi-Processing" 1462 depends on CPU_V6K || CPU_V7 1463 depends on GENERIC_CLOCKEVENTS 1464 depends on HAVE_SMP 1465 depends on MMU 1466 select USE_GENERIC_SMP_HELPERS 1467 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1468 help 1469 This enables support for systems with more than one CPU. If you have 1470 a system with only one CPU, like most personal computers, say N. If 1471 you have a system with more than one CPU, say Y. 1472 1473 If you say N here, the kernel will run on single and multiprocessor 1474 machines, but will use only one CPU of a multiprocessor machine. If 1475 you say Y here, the kernel will run on many, but not all, single 1476 processor machines. On a single processor machine, the kernel will 1477 run faster if you say N here. 1478 1479 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1480 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1481 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1482 1483 If you don't know what to do here, say N. 1484 1485config SMP_ON_UP 1486 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1487 depends on EXPERIMENTAL 1488 depends on SMP && !XIP_KERNEL 1489 default y 1490 help 1491 SMP kernels contain instructions which fail on non-SMP processors. 1492 Enabling this option allows the kernel to modify itself to make 1493 these instructions safe. Disabling it allows about 1K of space 1494 savings. 1495 1496 If you don't know what to do here, say Y. 1497 1498config ARM_CPU_TOPOLOGY 1499 bool "Support cpu topology definition" 1500 depends on SMP && CPU_V7 1501 default y 1502 help 1503 Support ARM cpu topology definition. The MPIDR register defines 1504 affinity between processors which is then used to describe the cpu 1505 topology of an ARM System. 1506 1507config SCHED_MC 1508 bool "Multi-core scheduler support" 1509 depends on ARM_CPU_TOPOLOGY 1510 help 1511 Multi-core scheduler support improves the CPU scheduler's decision 1512 making when dealing with multi-core CPU chips at a cost of slightly 1513 increased overhead in some places. If unsure say N here. 1514 1515config SCHED_SMT 1516 bool "SMT scheduler support" 1517 depends on ARM_CPU_TOPOLOGY 1518 help 1519 Improves the CPU scheduler's decision making when dealing with 1520 MultiThreading at a cost of slightly increased overhead in some 1521 places. If unsure say N here. 1522 1523config HAVE_ARM_SCU 1524 bool 1525 help 1526 This option enables support for the ARM system coherency unit 1527 1528config HAVE_ARM_TWD 1529 bool 1530 depends on SMP 1531 select TICK_ONESHOT 1532 help 1533 This options enables support for the ARM timer and watchdog unit 1534 1535choice 1536 prompt "Memory split" 1537 default VMSPLIT_3G 1538 help 1539 Select the desired split between kernel and user memory. 1540 1541 If you are not absolutely sure what you are doing, leave this 1542 option alone! 1543 1544 config VMSPLIT_3G 1545 bool "3G/1G user/kernel split" 1546 config VMSPLIT_2G 1547 bool "2G/2G user/kernel split" 1548 config VMSPLIT_1G 1549 bool "1G/3G user/kernel split" 1550endchoice 1551 1552config PAGE_OFFSET 1553 hex 1554 default 0x40000000 if VMSPLIT_1G 1555 default 0x80000000 if VMSPLIT_2G 1556 default 0xC0000000 1557 1558config NR_CPUS 1559 int "Maximum number of CPUs (2-32)" 1560 range 2 32 1561 depends on SMP 1562 default "4" 1563 1564config HOTPLUG_CPU 1565 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1566 depends on SMP && HOTPLUG && EXPERIMENTAL 1567 help 1568 Say Y here to experiment with turning CPUs off and on. CPUs 1569 can be controlled through /sys/devices/system/cpu. 1570 1571config LOCAL_TIMERS 1572 bool "Use local timer interrupts" 1573 depends on SMP 1574 default y 1575 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1576 help 1577 Enable support for local timers on SMP platforms, rather then the 1578 legacy IPI broadcast method. Local timers allows the system 1579 accounting to be spread across the timer interval, preventing a 1580 "thundering herd" at every timer tick. 1581 1582config ARCH_NR_GPIO 1583 int 1584 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1585 default 350 if ARCH_U8500 1586 default 0 1587 help 1588 Maximum number of GPIOs in the system. 1589 1590 If unsure, leave the default value. 1591 1592source kernel/Kconfig.preempt 1593 1594config HZ 1595 int 1596 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1597 ARCH_S5PV210 || ARCH_EXYNOS4 1598 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1599 default AT91_TIMER_HZ if ARCH_AT91 1600 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1601 default 100 1602 1603config THUMB2_KERNEL 1604 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1605 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1606 select AEABI 1607 select ARM_ASM_UNIFIED 1608 select ARM_UNWIND 1609 help 1610 By enabling this option, the kernel will be compiled in 1611 Thumb-2 mode. A compiler/assembler that understand the unified 1612 ARM-Thumb syntax is needed. 1613 1614 If unsure, say N. 1615 1616config THUMB2_AVOID_R_ARM_THM_JUMP11 1617 bool "Work around buggy Thumb-2 short branch relocations in gas" 1618 depends on THUMB2_KERNEL && MODULES 1619 default y 1620 help 1621 Various binutils versions can resolve Thumb-2 branches to 1622 locally-defined, preemptible global symbols as short-range "b.n" 1623 branch instructions. 1624 1625 This is a problem, because there's no guarantee the final 1626 destination of the symbol, or any candidate locations for a 1627 trampoline, are within range of the branch. For this reason, the 1628 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1629 relocation in modules at all, and it makes little sense to add 1630 support. 1631 1632 The symptom is that the kernel fails with an "unsupported 1633 relocation" error when loading some modules. 1634 1635 Until fixed tools are available, passing 1636 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1637 code which hits this problem, at the cost of a bit of extra runtime 1638 stack usage in some cases. 1639 1640 The problem is described in more detail at: 1641 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1642 1643 Only Thumb-2 kernels are affected. 1644 1645 Unless you are sure your tools don't have this problem, say Y. 1646 1647config ARM_ASM_UNIFIED 1648 bool 1649 1650config AEABI 1651 bool "Use the ARM EABI to compile the kernel" 1652 help 1653 This option allows for the kernel to be compiled using the latest 1654 ARM ABI (aka EABI). This is only useful if you are using a user 1655 space environment that is also compiled with EABI. 1656 1657 Since there are major incompatibilities between the legacy ABI and 1658 EABI, especially with regard to structure member alignment, this 1659 option also changes the kernel syscall calling convention to 1660 disambiguate both ABIs and allow for backward compatibility support 1661 (selected with CONFIG_OABI_COMPAT). 1662 1663 To use this you need GCC version 4.0.0 or later. 1664 1665config OABI_COMPAT 1666 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1667 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1668 default y 1669 help 1670 This option preserves the old syscall interface along with the 1671 new (ARM EABI) one. It also provides a compatibility layer to 1672 intercept syscalls that have structure arguments which layout 1673 in memory differs between the legacy ABI and the new ARM EABI 1674 (only for non "thumb" binaries). This option adds a tiny 1675 overhead to all syscalls and produces a slightly larger kernel. 1676 If you know you'll be using only pure EABI user space then you 1677 can say N here. If this option is not selected and you attempt 1678 to execute a legacy ABI binary then the result will be 1679 UNPREDICTABLE (in fact it can be predicted that it won't work 1680 at all). If in doubt say Y. 1681 1682config ARCH_HAS_HOLES_MEMORYMODEL 1683 bool 1684 1685config ARCH_SPARSEMEM_ENABLE 1686 bool 1687 1688config ARCH_SPARSEMEM_DEFAULT 1689 def_bool ARCH_SPARSEMEM_ENABLE 1690 1691config ARCH_SELECT_MEMORY_MODEL 1692 def_bool ARCH_SPARSEMEM_ENABLE 1693 1694config HAVE_ARCH_PFN_VALID 1695 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1696 1697config HIGHMEM 1698 bool "High Memory Support" 1699 depends on MMU 1700 help 1701 The address space of ARM processors is only 4 Gigabytes large 1702 and it has to accommodate user address space, kernel address 1703 space as well as some memory mapped IO. That means that, if you 1704 have a large amount of physical memory and/or IO, not all of the 1705 memory can be "permanently mapped" by the kernel. The physical 1706 memory that is not permanently mapped is called "high memory". 1707 1708 Depending on the selected kernel/user memory split, minimum 1709 vmalloc space and actual amount of RAM, you may not need this 1710 option which should result in a slightly faster kernel. 1711 1712 If unsure, say n. 1713 1714config HIGHPTE 1715 bool "Allocate 2nd-level pagetables from highmem" 1716 depends on HIGHMEM 1717 1718config HW_PERF_EVENTS 1719 bool "Enable hardware performance counter support for perf events" 1720 depends on PERF_EVENTS && CPU_HAS_PMU 1721 default y 1722 help 1723 Enable hardware performance counter support for perf events. If 1724 disabled, perf events will use software events only. 1725 1726source "mm/Kconfig" 1727 1728config FORCE_MAX_ZONEORDER 1729 int "Maximum zone order" if ARCH_SHMOBILE 1730 range 11 64 if ARCH_SHMOBILE 1731 default "9" if SA1111 1732 default "11" 1733 help 1734 The kernel memory allocator divides physically contiguous memory 1735 blocks into "zones", where each zone is a power of two number of 1736 pages. This option selects the largest power of two that the kernel 1737 keeps in the memory allocator. If you need to allocate very large 1738 blocks of physically contiguous memory, then you may need to 1739 increase this value. 1740 1741 This config option is actually maximum order plus one. For example, 1742 a value of 11 means that the largest free memory block is 2^10 pages. 1743 1744config LEDS 1745 bool "Timer and CPU usage LEDs" 1746 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1747 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1748 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1749 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1750 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1751 ARCH_AT91 || ARCH_DAVINCI || \ 1752 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1753 help 1754 If you say Y here, the LEDs on your machine will be used 1755 to provide useful information about your current system status. 1756 1757 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1758 be able to select which LEDs are active using the options below. If 1759 you are compiling a kernel for the EBSA-110 or the LART however, the 1760 red LED will simply flash regularly to indicate that the system is 1761 still functional. It is safe to say Y here if you have a CATS 1762 system, but the driver will do nothing. 1763 1764config LEDS_TIMER 1765 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1766 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1767 || MACH_OMAP_PERSEUS2 1768 depends on LEDS 1769 depends on !GENERIC_CLOCKEVENTS 1770 default y if ARCH_EBSA110 1771 help 1772 If you say Y here, one of the system LEDs (the green one on the 1773 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1774 will flash regularly to indicate that the system is still 1775 operational. This is mainly useful to kernel hackers who are 1776 debugging unstable kernels. 1777 1778 The LART uses the same LED for both Timer LED and CPU usage LED 1779 functions. You may choose to use both, but the Timer LED function 1780 will overrule the CPU usage LED. 1781 1782config LEDS_CPU 1783 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1784 !ARCH_OMAP) \ 1785 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1786 || MACH_OMAP_PERSEUS2 1787 depends on LEDS 1788 help 1789 If you say Y here, the red LED will be used to give a good real 1790 time indication of CPU usage, by lighting whenever the idle task 1791 is not currently executing. 1792 1793 The LART uses the same LED for both Timer LED and CPU usage LED 1794 functions. You may choose to use both, but the Timer LED function 1795 will overrule the CPU usage LED. 1796 1797config ALIGNMENT_TRAP 1798 bool 1799 depends on CPU_CP15_MMU 1800 default y if !ARCH_EBSA110 1801 select HAVE_PROC_CPU if PROC_FS 1802 help 1803 ARM processors cannot fetch/store information which is not 1804 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1805 address divisible by 4. On 32-bit ARM processors, these non-aligned 1806 fetch/store instructions will be emulated in software if you say 1807 here, which has a severe performance impact. This is necessary for 1808 correct operation of some network protocols. With an IP-only 1809 configuration it is safe to say N, otherwise say Y. 1810 1811config UACCESS_WITH_MEMCPY 1812 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1813 depends on MMU && EXPERIMENTAL 1814 default y if CPU_FEROCEON 1815 help 1816 Implement faster copy_to_user and clear_user methods for CPU 1817 cores where a 8-word STM instruction give significantly higher 1818 memory write throughput than a sequence of individual 32bit stores. 1819 1820 A possible side effect is a slight increase in scheduling latency 1821 between threads sharing the same address space if they invoke 1822 such copy operations with large buffers. 1823 1824 However, if the CPU data cache is using a write-allocate mode, 1825 this option is unlikely to provide any performance gain. 1826 1827config SECCOMP 1828 bool 1829 prompt "Enable seccomp to safely compute untrusted bytecode" 1830 ---help--- 1831 This kernel feature is useful for number crunching applications 1832 that may need to compute untrusted bytecode during their 1833 execution. By using pipes or other transports made available to 1834 the process as file descriptors supporting the read/write 1835 syscalls, it's possible to isolate those applications in 1836 their own address space using seccomp. Once seccomp is 1837 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1838 and the task is only allowed to execute a few safe syscalls 1839 defined by each seccomp mode. 1840 1841config CC_STACKPROTECTOR 1842 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1843 depends on EXPERIMENTAL 1844 help 1845 This option turns on the -fstack-protector GCC feature. This 1846 feature puts, at the beginning of functions, a canary value on 1847 the stack just before the return address, and validates 1848 the value just before actually returning. Stack based buffer 1849 overflows (that need to overwrite this return address) now also 1850 overwrite the canary, which gets detected and the attack is then 1851 neutralized via a kernel panic. 1852 This feature requires gcc version 4.2 or above. 1853 1854config DEPRECATED_PARAM_STRUCT 1855 bool "Provide old way to pass kernel parameters" 1856 help 1857 This was deprecated in 2001 and announced to live on for 5 years. 1858 Some old boot loaders still use this way. 1859 1860endmenu 1861 1862menu "Boot options" 1863 1864config USE_OF 1865 bool "Flattened Device Tree support" 1866 select OF 1867 select OF_EARLY_FLATTREE 1868 select IRQ_DOMAIN 1869 help 1870 Include support for flattened device tree machine descriptions. 1871 1872# Compressed boot loader in ROM. Yes, we really want to ask about 1873# TEXT and BSS so we preserve their values in the config files. 1874config ZBOOT_ROM_TEXT 1875 hex "Compressed ROM boot loader base address" 1876 default "0" 1877 help 1878 The physical address at which the ROM-able zImage is to be 1879 placed in the target. Platforms which normally make use of 1880 ROM-able zImage formats normally set this to a suitable 1881 value in their defconfig file. 1882 1883 If ZBOOT_ROM is not enabled, this has no effect. 1884 1885config ZBOOT_ROM_BSS 1886 hex "Compressed ROM boot loader BSS address" 1887 default "0" 1888 help 1889 The base address of an area of read/write memory in the target 1890 for the ROM-able zImage which must be available while the 1891 decompressor is running. It must be large enough to hold the 1892 entire decompressed kernel plus an additional 128 KiB. 1893 Platforms which normally make use of ROM-able zImage formats 1894 normally set this to a suitable value in their defconfig file. 1895 1896 If ZBOOT_ROM is not enabled, this has no effect. 1897 1898config ZBOOT_ROM 1899 bool "Compressed boot loader in ROM/flash" 1900 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1901 help 1902 Say Y here if you intend to execute your compressed kernel image 1903 (zImage) directly from ROM or flash. If unsure, say N. 1904 1905choice 1906 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1907 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1908 default ZBOOT_ROM_NONE 1909 help 1910 Include experimental SD/MMC loading code in the ROM-able zImage. 1911 With this enabled it is possible to write the the ROM-able zImage 1912 kernel image to an MMC or SD card and boot the kernel straight 1913 from the reset vector. At reset the processor Mask ROM will load 1914 the first part of the the ROM-able zImage which in turn loads the 1915 rest the kernel image to RAM. 1916 1917config ZBOOT_ROM_NONE 1918 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1919 help 1920 Do not load image from SD or MMC 1921 1922config ZBOOT_ROM_MMCIF 1923 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1924 help 1925 Load image from MMCIF hardware block. 1926 1927config ZBOOT_ROM_SH_MOBILE_SDHI 1928 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1929 help 1930 Load image from SDHI hardware block 1931 1932endchoice 1933 1934config ARM_APPENDED_DTB 1935 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1936 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1937 help 1938 With this option, the boot code will look for a device tree binary 1939 (DTB) appended to zImage 1940 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1941 1942 This is meant as a backward compatibility convenience for those 1943 systems with a bootloader that can't be upgraded to accommodate 1944 the documented boot protocol using a device tree. 1945 1946 Beware that there is very little in terms of protection against 1947 this option being confused by leftover garbage in memory that might 1948 look like a DTB header after a reboot if no actual DTB is appended 1949 to zImage. Do not leave this option active in a production kernel 1950 if you don't intend to always append a DTB. Proper passing of the 1951 location into r2 of a bootloader provided DTB is always preferable 1952 to this option. 1953 1954config ARM_ATAG_DTB_COMPAT 1955 bool "Supplement the appended DTB with traditional ATAG information" 1956 depends on ARM_APPENDED_DTB 1957 help 1958 Some old bootloaders can't be updated to a DTB capable one, yet 1959 they provide ATAGs with memory configuration, the ramdisk address, 1960 the kernel cmdline string, etc. Such information is dynamically 1961 provided by the bootloader and can't always be stored in a static 1962 DTB. To allow a device tree enabled kernel to be used with such 1963 bootloaders, this option allows zImage to extract the information 1964 from the ATAG list and store it at run time into the appended DTB. 1965 1966config CMDLINE 1967 string "Default kernel command string" 1968 default "" 1969 help 1970 On some architectures (EBSA110 and CATS), there is currently no way 1971 for the boot loader to pass arguments to the kernel. For these 1972 architectures, you should supply some command-line options at build 1973 time by entering them here. As a minimum, you should specify the 1974 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1975 1976choice 1977 prompt "Kernel command line type" if CMDLINE != "" 1978 default CMDLINE_FROM_BOOTLOADER 1979 1980config CMDLINE_FROM_BOOTLOADER 1981 bool "Use bootloader kernel arguments if available" 1982 help 1983 Uses the command-line options passed by the boot loader. If 1984 the boot loader doesn't provide any, the default kernel command 1985 string provided in CMDLINE will be used. 1986 1987config CMDLINE_EXTEND 1988 bool "Extend bootloader kernel arguments" 1989 help 1990 The command-line arguments provided by the boot loader will be 1991 appended to the default kernel command string. 1992 1993config CMDLINE_FORCE 1994 bool "Always use the default kernel command string" 1995 help 1996 Always use the default kernel command string, even if the boot 1997 loader passes other arguments to the kernel. 1998 This is useful if you cannot or don't want to change the 1999 command-line options your boot loader passes to the kernel. 2000endchoice 2001 2002config XIP_KERNEL 2003 bool "Kernel Execute-In-Place from ROM" 2004 depends on !ZBOOT_ROM && !ARM_LPAE 2005 help 2006 Execute-In-Place allows the kernel to run from non-volatile storage 2007 directly addressable by the CPU, such as NOR flash. This saves RAM 2008 space since the text section of the kernel is not loaded from flash 2009 to RAM. Read-write sections, such as the data section and stack, 2010 are still copied to RAM. The XIP kernel is not compressed since 2011 it has to run directly from flash, so it will take more space to 2012 store it. The flash address used to link the kernel object files, 2013 and for storing it, is configuration dependent. Therefore, if you 2014 say Y here, you must know the proper physical address where to 2015 store the kernel image depending on your own flash memory usage. 2016 2017 Also note that the make target becomes "make xipImage" rather than 2018 "make zImage" or "make Image". The final kernel binary to put in 2019 ROM memory will be arch/arm/boot/xipImage. 2020 2021 If unsure, say N. 2022 2023config XIP_PHYS_ADDR 2024 hex "XIP Kernel Physical Location" 2025 depends on XIP_KERNEL 2026 default "0x00080000" 2027 help 2028 This is the physical address in your flash memory the kernel will 2029 be linked for and stored to. This address is dependent on your 2030 own flash usage. 2031 2032config KEXEC 2033 bool "Kexec system call (EXPERIMENTAL)" 2034 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2035 help 2036 kexec is a system call that implements the ability to shutdown your 2037 current kernel, and to start another kernel. It is like a reboot 2038 but it is independent of the system firmware. And like a reboot 2039 you can start any kernel with it, not just Linux. 2040 2041 It is an ongoing process to be certain the hardware in a machine 2042 is properly shutdown, so do not be surprised if this code does not 2043 initially work for you. It may help to enable device hotplugging 2044 support. 2045 2046config ATAGS_PROC 2047 bool "Export atags in procfs" 2048 depends on KEXEC 2049 default y 2050 help 2051 Should the atags used to boot the kernel be exported in an "atags" 2052 file in procfs. Useful with kexec. 2053 2054config CRASH_DUMP 2055 bool "Build kdump crash kernel (EXPERIMENTAL)" 2056 depends on EXPERIMENTAL 2057 help 2058 Generate crash dump after being started by kexec. This should 2059 be normally only set in special crash dump kernels which are 2060 loaded in the main kernel with kexec-tools into a specially 2061 reserved region and then later executed after a crash by 2062 kdump/kexec. The crash dump kernel must be compiled to a 2063 memory address not used by the main kernel 2064 2065 For more details see Documentation/kdump/kdump.txt 2066 2067config AUTO_ZRELADDR 2068 bool "Auto calculation of the decompressed kernel image address" 2069 depends on !ZBOOT_ROM && !ARCH_U300 2070 help 2071 ZRELADDR is the physical address where the decompressed kernel 2072 image will be placed. If AUTO_ZRELADDR is selected, the address 2073 will be determined at run-time by masking the current IP with 2074 0xf8000000. This assumes the zImage being placed in the first 128MB 2075 from start of memory. 2076 2077endmenu 2078 2079menu "CPU Power Management" 2080 2081if ARCH_HAS_CPUFREQ 2082 2083source "drivers/cpufreq/Kconfig" 2084 2085config CPU_FREQ_IMX 2086 tristate "CPUfreq driver for i.MX CPUs" 2087 depends on ARCH_MXC && CPU_FREQ 2088 help 2089 This enables the CPUfreq driver for i.MX CPUs. 2090 2091config CPU_FREQ_SA1100 2092 bool 2093 2094config CPU_FREQ_SA1110 2095 bool 2096 2097config CPU_FREQ_INTEGRATOR 2098 tristate "CPUfreq driver for ARM Integrator CPUs" 2099 depends on ARCH_INTEGRATOR && CPU_FREQ 2100 default y 2101 help 2102 This enables the CPUfreq driver for ARM Integrator CPUs. 2103 2104 For details, take a look at <file:Documentation/cpu-freq>. 2105 2106 If in doubt, say Y. 2107 2108config CPU_FREQ_PXA 2109 bool 2110 depends on CPU_FREQ && ARCH_PXA && PXA25x 2111 default y 2112 select CPU_FREQ_TABLE 2113 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2114 2115config CPU_FREQ_S3C 2116 bool 2117 help 2118 Internal configuration node for common cpufreq on Samsung SoC 2119 2120config CPU_FREQ_S3C24XX 2121 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2122 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 2123 select CPU_FREQ_S3C 2124 help 2125 This enables the CPUfreq driver for the Samsung S3C24XX family 2126 of CPUs. 2127 2128 For details, take a look at <file:Documentation/cpu-freq>. 2129 2130 If in doubt, say N. 2131 2132config CPU_FREQ_S3C24XX_PLL 2133 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2134 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2135 help 2136 Compile in support for changing the PLL frequency from the 2137 S3C24XX series CPUfreq driver. The PLL takes time to settle 2138 after a frequency change, so by default it is not enabled. 2139 2140 This also means that the PLL tables for the selected CPU(s) will 2141 be built which may increase the size of the kernel image. 2142 2143config CPU_FREQ_S3C24XX_DEBUG 2144 bool "Debug CPUfreq Samsung driver core" 2145 depends on CPU_FREQ_S3C24XX 2146 help 2147 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2148 2149config CPU_FREQ_S3C24XX_IODEBUG 2150 bool "Debug CPUfreq Samsung driver IO timing" 2151 depends on CPU_FREQ_S3C24XX 2152 help 2153 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2154 2155config CPU_FREQ_S3C24XX_DEBUGFS 2156 bool "Export debugfs for CPUFreq" 2157 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2158 help 2159 Export status information via debugfs. 2160 2161endif 2162 2163source "drivers/cpuidle/Kconfig" 2164 2165endmenu 2166 2167menu "Floating point emulation" 2168 2169comment "At least one emulation must be selected" 2170 2171config FPE_NWFPE 2172 bool "NWFPE math emulation" 2173 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2174 ---help--- 2175 Say Y to include the NWFPE floating point emulator in the kernel. 2176 This is necessary to run most binaries. Linux does not currently 2177 support floating point hardware so you need to say Y here even if 2178 your machine has an FPA or floating point co-processor podule. 2179 2180 You may say N here if you are going to load the Acorn FPEmulator 2181 early in the bootup. 2182 2183config FPE_NWFPE_XP 2184 bool "Support extended precision" 2185 depends on FPE_NWFPE 2186 help 2187 Say Y to include 80-bit support in the kernel floating-point 2188 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2189 Note that gcc does not generate 80-bit operations by default, 2190 so in most cases this option only enlarges the size of the 2191 floating point emulator without any good reason. 2192 2193 You almost surely want to say N here. 2194 2195config FPE_FASTFPE 2196 bool "FastFPE math emulation (EXPERIMENTAL)" 2197 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2198 ---help--- 2199 Say Y here to include the FAST floating point emulator in the kernel. 2200 This is an experimental much faster emulator which now also has full 2201 precision for the mantissa. It does not support any exceptions. 2202 It is very simple, and approximately 3-6 times faster than NWFPE. 2203 2204 It should be sufficient for most programs. It may be not suitable 2205 for scientific calculations, but you have to check this for yourself. 2206 If you do not feel you need a faster FP emulation you should better 2207 choose NWFPE. 2208 2209config VFP 2210 bool "VFP-format floating point maths" 2211 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2212 help 2213 Say Y to include VFP support code in the kernel. This is needed 2214 if your hardware includes a VFP unit. 2215 2216 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2217 release notes and additional status information. 2218 2219 Say N if your target does not have VFP hardware. 2220 2221config VFPv3 2222 bool 2223 depends on VFP 2224 default y if CPU_V7 2225 2226config NEON 2227 bool "Advanced SIMD (NEON) Extension support" 2228 depends on VFPv3 && CPU_V7 2229 help 2230 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2231 Extension. 2232 2233endmenu 2234 2235menu "Userspace binary formats" 2236 2237source "fs/Kconfig.binfmt" 2238 2239config ARTHUR 2240 tristate "RISC OS personality" 2241 depends on !AEABI 2242 help 2243 Say Y here to include the kernel code necessary if you want to run 2244 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2245 experimental; if this sounds frightening, say N and sleep in peace. 2246 You can also say M here to compile this support as a module (which 2247 will be called arthur). 2248 2249endmenu 2250 2251menu "Power management options" 2252 2253source "kernel/power/Kconfig" 2254 2255config ARCH_SUSPEND_POSSIBLE 2256 depends on !ARCH_S5PC100 2257 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2258 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2259 def_bool y 2260 2261config ARM_CPU_SUSPEND 2262 def_bool PM_SLEEP 2263 2264endmenu 2265 2266source "net/Kconfig" 2267 2268source "drivers/Kconfig" 2269 2270source "fs/Kconfig" 2271 2272source "arch/arm/Kconfig.debug" 2273 2274source "security/Kconfig" 2275 2276source "crypto/Kconfig" 2277 2278source "lib/Kconfig" 2279