1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_STACKWALK 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 24 select ARCH_HAS_SYNC_DMA_FOR_CPU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 80 select HAVE_ARCH_MMAP_RND_BITS if MMU 81 select HAVE_ARCH_PFN_VALID 82 select HAVE_ARCH_SECCOMP 83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 85 select HAVE_ARCH_TRACEHOOK 86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 87 select HAVE_ARM_SMCCC if CPU_V7 88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 89 select HAVE_CONTEXT_TRACKING_USER 90 select HAVE_C_RECORDMCOUNT 91 select HAVE_BUILDTIME_MCOUNT_SORT 92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 93 select HAVE_DMA_CONTIGUOUS if MMU 94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 97 select HAVE_EXIT_THREAD 98 select HAVE_FAST_GUP if ARM_LPAE 99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 100 select HAVE_FUNCTION_ERROR_INJECTION 101 select HAVE_FUNCTION_GRAPH_TRACER 102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 103 select HAVE_GCC_PLUGINS 104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 105 select HAVE_IRQ_TIME_ACCOUNTING 106 select HAVE_KERNEL_GZIP 107 select HAVE_KERNEL_LZ4 108 select HAVE_KERNEL_LZMA 109 select HAVE_KERNEL_LZO 110 select HAVE_KERNEL_XZ 111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 112 select HAVE_KRETPROBES if HAVE_KPROBES 113 select HAVE_MOD_ARCH_SPECIFIC 114 select HAVE_NMI 115 select HAVE_OPTPROBES if !THUMB2_KERNEL 116 select HAVE_PCI if MMU 117 select HAVE_PERF_EVENTS 118 select HAVE_PERF_REGS 119 select HAVE_PERF_USER_STACK_DUMP 120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 121 select HAVE_REGS_AND_STACK_ACCESS_API 122 select HAVE_RSEQ 123 select HAVE_STACKPROTECTOR 124 select HAVE_SYSCALL_TRACEPOINTS 125 select HAVE_UID16 126 select HAVE_VIRT_CPU_ACCOUNTING_GEN 127 select IRQ_FORCED_THREADING 128 select MODULES_USE_ELF_REL 129 select NEED_DMA_MAP_STATE 130 select OF_EARLY_FLATTREE if OF 131 select OLD_SIGACTION 132 select OLD_SIGSUSPEND3 133 select PCI_DOMAINS_GENERIC if PCI 134 select PCI_SYSCALL if PCI 135 select PERF_USE_VMALLOC 136 select RTC_LIB 137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 138 select SYS_SUPPORTS_APM_EMULATION 139 select THREAD_INFO_IN_TASK 140 select TIMER_OF if OF 141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 144 # Above selects are sorted alphabetically; please add new ones 145 # according to that. Thanks. 146 help 147 The ARM series is a line of low-power-consumption RISC chip designs 148 licensed by ARM Ltd and targeted at embedded applications and 149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 150 manufactured, but legacy ARM-based PC hardware remains popular in 151 Europe. There is an ARM Linux project with a web page at 152 <http://www.arm.linux.org.uk/>. 153 154config ARM_HAS_GROUP_RELOCS 155 def_bool y 156 depends on !LD_IS_LLD || LLD_VERSION >= 140000 157 depends on !COMPILE_TEST 158 help 159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 160 relocations, which have been around for a long time, but were not 161 supported in LLD until version 14. The combined range is -/+ 256 MiB, 162 which is usually sufficient, but not for allyesconfig, so we disable 163 this feature when doing compile testing. 164 165config ARM_DMA_USE_IOMMU 166 bool 167 select NEED_SG_DMA_LENGTH 168 169if ARM_DMA_USE_IOMMU 170 171config ARM_DMA_IOMMU_ALIGNMENT 172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 173 range 4 9 174 default 8 175 help 176 DMA mapping framework by default aligns all buffers to the smallest 177 PAGE_SIZE order which is greater than or equal to the requested buffer 178 size. This works well for buffers up to a few hundreds kilobytes, but 179 for larger buffers it just a waste of address space. Drivers which has 180 relatively small addressing window (like 64Mib) might run out of 181 virtual space with just a few allocations. 182 183 With this parameter you can specify the maximum PAGE_SIZE order for 184 DMA IOMMU buffers. Larger buffers will be aligned only to this 185 specified order. The order is expressed as a power of two multiplied 186 by the PAGE_SIZE. 187 188endif 189 190config SYS_SUPPORTS_APM_EMULATION 191 bool 192 193config HAVE_TCM 194 bool 195 select GENERIC_ALLOCATOR 196 197config HAVE_PROC_CPU 198 bool 199 200config NO_IOPORT_MAP 201 bool 202 203config SBUS 204 bool 205 206config STACKTRACE_SUPPORT 207 bool 208 default y 209 210config LOCKDEP_SUPPORT 211 bool 212 default y 213 214config ARCH_HAS_ILOG2_U32 215 bool 216 217config ARCH_HAS_ILOG2_U64 218 bool 219 220config ARCH_HAS_BANDGAP 221 bool 222 223config FIX_EARLYCON_MEM 224 def_bool y if MMU 225 226config GENERIC_HWEIGHT 227 bool 228 default y 229 230config GENERIC_CALIBRATE_DELAY 231 bool 232 default y 233 234config ARCH_MAY_HAVE_PC_FDC 235 bool 236 237config ARCH_SUPPORTS_UPROBES 238 def_bool y 239 240config GENERIC_ISA_DMA 241 bool 242 243config FIQ 244 bool 245 246config ARCH_MTD_XIP 247 bool 248 249config ARM_PATCH_PHYS_VIRT 250 bool "Patch physical to virtual translations at runtime" if EMBEDDED 251 default y 252 depends on MMU 253 help 254 Patch phys-to-virt and virt-to-phys translation functions at 255 boot and module load time according to the position of the 256 kernel in system memory. 257 258 This can only be used with non-XIP MMU kernels where the base 259 of physical memory is at a 2 MiB boundary. 260 261 Only disable this option if you know that you do not require 262 this feature (eg, building a kernel for a single machine) and 263 you need to shrink the kernel to the minimal size. 264 265config NEED_MACH_IO_H 266 bool 267 help 268 Select this when mach/io.h is required to provide special 269 definitions for this platform. The need for mach/io.h should 270 be avoided when possible. 271 272config NEED_MACH_MEMORY_H 273 bool 274 help 275 Select this when mach/memory.h is required to provide special 276 definitions for this platform. The need for mach/memory.h should 277 be avoided when possible. 278 279config PHYS_OFFSET 280 hex "Physical address of main memory" if MMU 281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 282 default DRAM_BASE if !MMU 283 default 0x00000000 if ARCH_FOOTBRIDGE 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0x30000000 if ARCH_S3C24XX 286 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 287 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 288 default 0 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARM_SINGLE_ARMV7M 312 def_bool !MMU 313 select ARM_NVIC 314 select CPU_V7M 315 select NO_IOPORT_MAP 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 8 319 320config ARCH_MMAP_RND_BITS_MAX 321 default 14 if PAGE_OFFSET=0x40000000 322 default 15 if PAGE_OFFSET=0x80000000 323 default 16 324 325config ARCH_MULTIPLATFORM 326 bool "Require kernel to be portable to multiple machines" if EXPERT 327 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 328 default y 329 help 330 In general, all Arm machines can be supported in a single 331 kernel image, covering either Armv4/v5 or Armv6/v7. 332 333 However, some configuration options require hardcoding machine 334 specific physical addresses or enable errata workarounds that may 335 break other machines. 336 337 Selecting N here allows using those options, including 338 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 339 340menu "Platform selection" 341 depends on MMU 342 343comment "CPU Core family selection" 344 345config ARCH_MULTI_V4 346 bool "ARMv4 based platforms (FA526, StrongARM)" 347 depends on !ARCH_MULTI_V6_V7 348 depends on !LD_IS_LLD 349 select ARCH_MULTI_V4_V5 350 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 351 352config ARCH_MULTI_V4T 353 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 354 depends on !ARCH_MULTI_V6_V7 355 depends on !LD_IS_LLD 356 select ARCH_MULTI_V4_V5 357 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 358 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 359 CPU_ARM925T || CPU_ARM940T) 360 361config ARCH_MULTI_V5 362 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 363 depends on !ARCH_MULTI_V6_V7 364 select ARCH_MULTI_V4_V5 365 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 366 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 367 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 368 369config ARCH_MULTI_V4_V5 370 bool 371 372config ARCH_MULTI_V6 373 bool "ARMv6 based platforms (ARM11)" 374 select ARCH_MULTI_V6_V7 375 select CPU_V6K 376 377config ARCH_MULTI_V7 378 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 379 default y 380 select ARCH_MULTI_V6_V7 381 select CPU_V7 382 select HAVE_SMP 383 384config ARCH_MULTI_V6_V7 385 bool 386 select MIGHT_HAVE_CACHE_L2X0 387 388config ARCH_MULTI_CPU_AUTO 389 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 390 select ARCH_MULTI_V5 391 392endmenu 393 394config ARCH_VIRT 395 bool "Dummy Virtual Machine" 396 depends on ARCH_MULTI_V7 397 select ARM_AMBA 398 select ARM_GIC 399 select ARM_GIC_V2M if PCI 400 select ARM_GIC_V3 401 select ARM_GIC_V3_ITS if PCI 402 select ARM_PSCI 403 select HAVE_ARM_ARCH_TIMER 404 405config ARCH_AIROHA 406 bool "Airoha SoC Support" 407 depends on ARCH_MULTI_V7 408 select ARM_AMBA 409 select ARM_GIC 410 select ARM_GIC_V3 411 select ARM_PSCI 412 select HAVE_ARM_ARCH_TIMER 413 help 414 Support for Airoha EN7523 SoCs 415 416# 417# This is sorted alphabetically by mach-* pathname. However, plat-* 418# Kconfigs may be included either alphabetically (according to the 419# plat- suffix) or along side the corresponding mach-* source. 420# 421source "arch/arm/mach-actions/Kconfig" 422 423source "arch/arm/mach-alpine/Kconfig" 424 425source "arch/arm/mach-artpec/Kconfig" 426 427source "arch/arm/mach-asm9260/Kconfig" 428 429source "arch/arm/mach-aspeed/Kconfig" 430 431source "arch/arm/mach-at91/Kconfig" 432 433source "arch/arm/mach-axxia/Kconfig" 434 435source "arch/arm/mach-bcm/Kconfig" 436 437source "arch/arm/mach-berlin/Kconfig" 438 439source "arch/arm/mach-clps711x/Kconfig" 440 441source "arch/arm/mach-cns3xxx/Kconfig" 442 443source "arch/arm/mach-davinci/Kconfig" 444 445source "arch/arm/mach-digicolor/Kconfig" 446 447source "arch/arm/mach-dove/Kconfig" 448 449source "arch/arm/mach-ep93xx/Kconfig" 450 451source "arch/arm/mach-exynos/Kconfig" 452 453source "arch/arm/mach-footbridge/Kconfig" 454 455source "arch/arm/mach-gemini/Kconfig" 456 457source "arch/arm/mach-highbank/Kconfig" 458 459source "arch/arm/mach-hisi/Kconfig" 460 461source "arch/arm/mach-hpe/Kconfig" 462 463source "arch/arm/mach-imx/Kconfig" 464 465source "arch/arm/mach-iop32x/Kconfig" 466 467source "arch/arm/mach-ixp4xx/Kconfig" 468 469source "arch/arm/mach-keystone/Kconfig" 470 471source "arch/arm/mach-lpc32xx/Kconfig" 472 473source "arch/arm/mach-mediatek/Kconfig" 474 475source "arch/arm/mach-meson/Kconfig" 476 477source "arch/arm/mach-milbeaut/Kconfig" 478 479source "arch/arm/mach-mmp/Kconfig" 480 481source "arch/arm/mach-moxart/Kconfig" 482 483source "arch/arm/mach-mstar/Kconfig" 484 485source "arch/arm/mach-mv78xx0/Kconfig" 486 487source "arch/arm/mach-mvebu/Kconfig" 488 489source "arch/arm/mach-mxs/Kconfig" 490 491source "arch/arm/mach-nomadik/Kconfig" 492 493source "arch/arm/mach-npcm/Kconfig" 494 495source "arch/arm/mach-nspire/Kconfig" 496 497source "arch/arm/mach-omap1/Kconfig" 498 499source "arch/arm/mach-omap2/Kconfig" 500 501source "arch/arm/mach-orion5x/Kconfig" 502 503source "arch/arm/mach-oxnas/Kconfig" 504 505source "arch/arm/mach-pxa/Kconfig" 506 507source "arch/arm/mach-qcom/Kconfig" 508 509source "arch/arm/mach-rda/Kconfig" 510 511source "arch/arm/mach-realtek/Kconfig" 512 513source "arch/arm/mach-rpc/Kconfig" 514 515source "arch/arm/mach-rockchip/Kconfig" 516 517source "arch/arm/mach-s3c/Kconfig" 518 519source "arch/arm/mach-s5pv210/Kconfig" 520 521source "arch/arm/mach-sa1100/Kconfig" 522 523source "arch/arm/mach-shmobile/Kconfig" 524 525source "arch/arm/mach-socfpga/Kconfig" 526 527source "arch/arm/mach-spear/Kconfig" 528 529source "arch/arm/mach-sti/Kconfig" 530 531source "arch/arm/mach-stm32/Kconfig" 532 533source "arch/arm/mach-sunplus/Kconfig" 534 535source "arch/arm/mach-sunxi/Kconfig" 536 537source "arch/arm/mach-tegra/Kconfig" 538 539source "arch/arm/mach-uniphier/Kconfig" 540 541source "arch/arm/mach-ux500/Kconfig" 542 543source "arch/arm/mach-versatile/Kconfig" 544 545source "arch/arm/mach-vt8500/Kconfig" 546 547source "arch/arm/mach-zynq/Kconfig" 548 549# ARMv7-M architecture 550config ARCH_LPC18XX 551 bool "NXP LPC18xx/LPC43xx" 552 depends on ARM_SINGLE_ARMV7M 553 select ARCH_HAS_RESET_CONTROLLER 554 select ARM_AMBA 555 select CLKSRC_LPC32XX 556 select PINCTRL 557 help 558 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 559 high performance microcontrollers. 560 561config ARCH_MPS2 562 bool "ARM MPS2 platform" 563 depends on ARM_SINGLE_ARMV7M 564 select ARM_AMBA 565 select CLKSRC_MPS2 566 help 567 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 568 with a range of available cores like Cortex-M3/M4/M7. 569 570 Please, note that depends which Application Note is used memory map 571 for the platform may vary, so adjustment of RAM base might be needed. 572 573# Definitions to make life easier 574config ARCH_ACORN 575 bool 576 577config PLAT_ORION 578 bool 579 select CLKSRC_MMIO 580 select GENERIC_IRQ_CHIP 581 select IRQ_DOMAIN 582 583config PLAT_ORION_LEGACY 584 bool 585 select PLAT_ORION 586 587config PLAT_VERSATILE 588 bool 589 590source "arch/arm/mm/Kconfig" 591 592config IWMMXT 593 bool "Enable iWMMXt support" 594 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 595 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 596 help 597 Enable support for iWMMXt context switching at run time if 598 running on a CPU that supports it. 599 600if !MMU 601source "arch/arm/Kconfig-nommu" 602endif 603 604config PJ4B_ERRATA_4742 605 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 606 depends on CPU_PJ4B && MACH_ARMADA_370 607 default y 608 help 609 When coming out of either a Wait for Interrupt (WFI) or a Wait for 610 Event (WFE) IDLE states, a specific timing sensitivity exists between 611 the retiring WFI/WFE instructions and the newly issued subsequent 612 instructions. This sensitivity can result in a CPU hang scenario. 613 Workaround: 614 The software must insert either a Data Synchronization Barrier (DSB) 615 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 616 instruction 617 618config ARM_ERRATA_326103 619 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 620 depends on CPU_V6 621 help 622 Executing a SWP instruction to read-only memory does not set bit 11 623 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 624 treat the access as a read, preventing a COW from occurring and 625 causing the faulting task to livelock. 626 627config ARM_ERRATA_411920 628 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 629 depends on CPU_V6 || CPU_V6K 630 help 631 Invalidation of the Instruction Cache operation can 632 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 633 It does not affect the MPCore. This option enables the ARM Ltd. 634 recommended workaround. 635 636config ARM_ERRATA_430973 637 bool "ARM errata: Stale prediction on replaced interworking branch" 638 depends on CPU_V7 639 help 640 This option enables the workaround for the 430973 Cortex-A8 641 r1p* erratum. If a code sequence containing an ARM/Thumb 642 interworking branch is replaced with another code sequence at the 643 same virtual address, whether due to self-modifying code or virtual 644 to physical address re-mapping, Cortex-A8 does not recover from the 645 stale interworking branch prediction. This results in Cortex-A8 646 executing the new code sequence in the incorrect ARM or Thumb state. 647 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 648 and also flushes the branch target cache at every context switch. 649 Note that setting specific bits in the ACTLR register may not be 650 available in non-secure mode. 651 652config ARM_ERRATA_458693 653 bool "ARM errata: Processor deadlock when a false hazard is created" 654 depends on CPU_V7 655 depends on !ARCH_MULTIPLATFORM 656 help 657 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 658 erratum. For very specific sequences of memory operations, it is 659 possible for a hazard condition intended for a cache line to instead 660 be incorrectly associated with a different cache line. This false 661 hazard might then cause a processor deadlock. The workaround enables 662 the L1 caching of the NEON accesses and disables the PLD instruction 663 in the ACTLR register. Note that setting specific bits in the ACTLR 664 register may not be available in non-secure mode. 665 666config ARM_ERRATA_460075 667 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 668 depends on CPU_V7 669 depends on !ARCH_MULTIPLATFORM 670 help 671 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 672 erratum. Any asynchronous access to the L2 cache may encounter a 673 situation in which recent store transactions to the L2 cache are lost 674 and overwritten with stale memory contents from external memory. The 675 workaround disables the write-allocate mode for the L2 cache via the 676 ACTLR register. Note that setting specific bits in the ACTLR register 677 may not be available in non-secure mode. 678 679config ARM_ERRATA_742230 680 bool "ARM errata: DMB operation may be faulty" 681 depends on CPU_V7 && SMP 682 depends on !ARCH_MULTIPLATFORM 683 help 684 This option enables the workaround for the 742230 Cortex-A9 685 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 686 between two write operations may not ensure the correct visibility 687 ordering of the two writes. This workaround sets a specific bit in 688 the diagnostic register of the Cortex-A9 which causes the DMB 689 instruction to behave as a DSB, ensuring the correct behaviour of 690 the two writes. 691 692config ARM_ERRATA_742231 693 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 694 depends on CPU_V7 && SMP 695 depends on !ARCH_MULTIPLATFORM 696 help 697 This option enables the workaround for the 742231 Cortex-A9 698 (r2p0..r2p2) erratum. Under certain conditions, specific to the 699 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 700 accessing some data located in the same cache line, may get corrupted 701 data due to bad handling of the address hazard when the line gets 702 replaced from one of the CPUs at the same time as another CPU is 703 accessing it. This workaround sets specific bits in the diagnostic 704 register of the Cortex-A9 which reduces the linefill issuing 705 capabilities of the processor. 706 707config ARM_ERRATA_643719 708 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 709 depends on CPU_V7 && SMP 710 default y 711 help 712 This option enables the workaround for the 643719 Cortex-A9 (prior to 713 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 714 register returns zero when it should return one. The workaround 715 corrects this value, ensuring cache maintenance operations which use 716 it behave as intended and avoiding data corruption. 717 718config ARM_ERRATA_720789 719 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 720 depends on CPU_V7 721 help 722 This option enables the workaround for the 720789 Cortex-A9 (prior to 723 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 724 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 725 As a consequence of this erratum, some TLB entries which should be 726 invalidated are not, resulting in an incoherency in the system page 727 tables. The workaround changes the TLB flushing routines to invalidate 728 entries regardless of the ASID. 729 730config ARM_ERRATA_743622 731 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 732 depends on CPU_V7 733 depends on !ARCH_MULTIPLATFORM 734 help 735 This option enables the workaround for the 743622 Cortex-A9 736 (r2p*) erratum. Under very rare conditions, a faulty 737 optimisation in the Cortex-A9 Store Buffer may lead to data 738 corruption. This workaround sets a specific bit in the diagnostic 739 register of the Cortex-A9 which disables the Store Buffer 740 optimisation, preventing the defect from occurring. This has no 741 visible impact on the overall performance or power consumption of the 742 processor. 743 744config ARM_ERRATA_751472 745 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 746 depends on CPU_V7 747 depends on !ARCH_MULTIPLATFORM 748 help 749 This option enables the workaround for the 751472 Cortex-A9 (prior 750 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 751 completion of a following broadcasted operation if the second 752 operation is received by a CPU before the ICIALLUIS has completed, 753 potentially leading to corrupted entries in the cache or TLB. 754 755config ARM_ERRATA_754322 756 bool "ARM errata: possible faulty MMU translations following an ASID switch" 757 depends on CPU_V7 758 help 759 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 760 r3p*) erratum. A speculative memory access may cause a page table walk 761 which starts prior to an ASID switch but completes afterwards. This 762 can populate the micro-TLB with a stale entry which may be hit with 763 the new ASID. This workaround places two dsb instructions in the mm 764 switching code so that no page table walks can cross the ASID switch. 765 766config ARM_ERRATA_754327 767 bool "ARM errata: no automatic Store Buffer drain" 768 depends on CPU_V7 && SMP 769 help 770 This option enables the workaround for the 754327 Cortex-A9 (prior to 771 r2p0) erratum. The Store Buffer does not have any automatic draining 772 mechanism and therefore a livelock may occur if an external agent 773 continuously polls a memory location waiting to observe an update. 774 This workaround defines cpu_relax() as smp_mb(), preventing correctly 775 written polling loops from denying visibility of updates to memory. 776 777config ARM_ERRATA_364296 778 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 779 depends on CPU_V6 780 help 781 This options enables the workaround for the 364296 ARM1136 782 r0p2 erratum (possible cache data corruption with 783 hit-under-miss enabled). It sets the undocumented bit 31 in 784 the auxiliary control register and the FI bit in the control 785 register, thus disabling hit-under-miss without putting the 786 processor into full low interrupt latency mode. ARM11MPCore 787 is not affected. 788 789config ARM_ERRATA_764369 790 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 791 depends on CPU_V7 && SMP 792 help 793 This option enables the workaround for erratum 764369 794 affecting Cortex-A9 MPCore with two or more processors (all 795 current revisions). Under certain timing circumstances, a data 796 cache line maintenance operation by MVA targeting an Inner 797 Shareable memory region may fail to proceed up to either the 798 Point of Coherency or to the Point of Unification of the 799 system. This workaround adds a DSB instruction before the 800 relevant cache maintenance functions and sets a specific bit 801 in the diagnostic control register of the SCU. 802 803config ARM_ERRATA_764319 804 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 805 depends on CPU_V7 806 help 807 This option enables the workaround for the 764319 Cortex A-9 erratum. 808 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 809 unexpected Undefined Instruction exception when the DBGSWENABLE 810 external pin is set to 0, even when the CP14 accesses are performed 811 from a privileged mode. This work around catches the exception in a 812 way the kernel does not stop execution. 813 814config ARM_ERRATA_775420 815 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 816 depends on CPU_V7 817 help 818 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 819 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 820 operation aborts with MMU exception, it might cause the processor 821 to deadlock. This workaround puts DSB before executing ISB if 822 an abort may occur on cache maintenance. 823 824config ARM_ERRATA_798181 825 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 826 depends on CPU_V7 && SMP 827 help 828 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 829 adequately shooting down all use of the old entries. This 830 option enables the Linux kernel workaround for this erratum 831 which sends an IPI to the CPUs that are running the same ASID 832 as the one being invalidated. 833 834config ARM_ERRATA_773022 835 bool "ARM errata: incorrect instructions may be executed from loop buffer" 836 depends on CPU_V7 837 help 838 This option enables the workaround for the 773022 Cortex-A15 839 (up to r0p4) erratum. In certain rare sequences of code, the 840 loop buffer may deliver incorrect instructions. This 841 workaround disables the loop buffer to avoid the erratum. 842 843config ARM_ERRATA_818325_852422 844 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 845 depends on CPU_V7 846 help 847 This option enables the workaround for: 848 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 849 instruction might deadlock. Fixed in r0p1. 850 - Cortex-A12 852422: Execution of a sequence of instructions might 851 lead to either a data corruption or a CPU deadlock. Not fixed in 852 any Cortex-A12 cores yet. 853 This workaround for all both errata involves setting bit[12] of the 854 Feature Register. This bit disables an optimisation applied to a 855 sequence of 2 instructions that use opposing condition codes. 856 857config ARM_ERRATA_821420 858 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 859 depends on CPU_V7 860 help 861 This option enables the workaround for the 821420 Cortex-A12 862 (all revs) erratum. In very rare timing conditions, a sequence 863 of VMOV to Core registers instructions, for which the second 864 one is in the shadow of a branch or abort, can lead to a 865 deadlock when the VMOV instructions are issued out-of-order. 866 867config ARM_ERRATA_825619 868 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 869 depends on CPU_V7 870 help 871 This option enables the workaround for the 825619 Cortex-A12 872 (all revs) erratum. Within rare timing constraints, executing a 873 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 874 and Device/Strongly-Ordered loads and stores might cause deadlock 875 876config ARM_ERRATA_857271 877 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 878 depends on CPU_V7 879 help 880 This option enables the workaround for the 857271 Cortex-A12 881 (all revs) erratum. Under very rare timing conditions, the CPU might 882 hang. The workaround is expected to have a < 1% performance impact. 883 884config ARM_ERRATA_852421 885 bool "ARM errata: A17: DMB ST might fail to create order between stores" 886 depends on CPU_V7 887 help 888 This option enables the workaround for the 852421 Cortex-A17 889 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 890 execution of a DMB ST instruction might fail to properly order 891 stores from GroupA and stores from GroupB. 892 893config ARM_ERRATA_852423 894 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 895 depends on CPU_V7 896 help 897 This option enables the workaround for: 898 - Cortex-A17 852423: Execution of a sequence of instructions might 899 lead to either a data corruption or a CPU deadlock. Not fixed in 900 any Cortex-A17 cores yet. 901 This is identical to Cortex-A12 erratum 852422. It is a separate 902 config option from the A12 erratum due to the way errata are checked 903 for and handled. 904 905config ARM_ERRATA_857272 906 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 907 depends on CPU_V7 908 help 909 This option enables the workaround for the 857272 Cortex-A17 erratum. 910 This erratum is not known to be fixed in any A17 revision. 911 This is identical to Cortex-A12 erratum 857271. It is a separate 912 config option from the A12 erratum due to the way errata are checked 913 for and handled. 914 915endmenu 916 917source "arch/arm/common/Kconfig" 918 919menu "Bus support" 920 921config ISA 922 bool 923 help 924 Find out whether you have ISA slots on your motherboard. ISA is the 925 name of a bus system, i.e. the way the CPU talks to the other stuff 926 inside your box. Other bus systems are PCI, EISA, MicroChannel 927 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 928 newer boards don't support it. If you have ISA, say Y, otherwise N. 929 930# Select ISA DMA interface 931config ISA_DMA_API 932 bool 933 934config PCI_NANOENGINE 935 bool "BSE nanoEngine PCI support" 936 depends on SA1100_NANOENGINE 937 help 938 Enable PCI on the BSE nanoEngine board. 939 940config ARM_ERRATA_814220 941 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 942 depends on CPU_V7 943 help 944 The v7 ARM states that all cache and branch predictor maintenance 945 operations that do not specify an address execute, relative to 946 each other, in program order. 947 However, because of this erratum, an L2 set/way cache maintenance 948 operation can overtake an L1 set/way cache maintenance operation. 949 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 950 r0p4, r0p5. 951 952endmenu 953 954menu "Kernel Features" 955 956config HAVE_SMP 957 bool 958 help 959 This option should be selected by machines which have an SMP- 960 capable CPU. 961 962 The only effect of this option is to make the SMP-related 963 options available to the user for configuration. 964 965config SMP 966 bool "Symmetric Multi-Processing" 967 depends on CPU_V6K || CPU_V7 968 depends on HAVE_SMP 969 depends on MMU || ARM_MPU 970 select IRQ_WORK 971 help 972 This enables support for systems with more than one CPU. If you have 973 a system with only one CPU, say N. If you have a system with more 974 than one CPU, say Y. 975 976 If you say N here, the kernel will run on uni- and multiprocessor 977 machines, but will use only one CPU of a multiprocessor machine. If 978 you say Y here, the kernel will run on many, but not all, 979 uniprocessor machines. On a uniprocessor machine, the kernel 980 will run faster if you say N here. 981 982 See also <file:Documentation/x86/i386/IO-APIC.rst>, 983 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 984 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 985 986 If you don't know what to do here, say N. 987 988config SMP_ON_UP 989 bool "Allow booting SMP kernel on uniprocessor systems" 990 depends on SMP && MMU 991 default y 992 help 993 SMP kernels contain instructions which fail on non-SMP processors. 994 Enabling this option allows the kernel to modify itself to make 995 these instructions safe. Disabling it allows about 1K of space 996 savings. 997 998 If you don't know what to do here, say Y. 999 1000 1001config CURRENT_POINTER_IN_TPIDRURO 1002 def_bool y 1003 depends on CPU_32v6K && !CPU_V6 1004 1005config IRQSTACKS 1006 def_bool y 1007 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1008 select HAVE_SOFTIRQ_ON_OWN_STACK 1009 1010config ARM_CPU_TOPOLOGY 1011 bool "Support cpu topology definition" 1012 depends on SMP && CPU_V7 1013 default y 1014 help 1015 Support ARM cpu topology definition. The MPIDR register defines 1016 affinity between processors which is then used to describe the cpu 1017 topology of an ARM System. 1018 1019config SCHED_MC 1020 bool "Multi-core scheduler support" 1021 depends on ARM_CPU_TOPOLOGY 1022 help 1023 Multi-core scheduler support improves the CPU scheduler's decision 1024 making when dealing with multi-core CPU chips at a cost of slightly 1025 increased overhead in some places. If unsure say N here. 1026 1027config SCHED_SMT 1028 bool "SMT scheduler support" 1029 depends on ARM_CPU_TOPOLOGY 1030 help 1031 Improves the CPU scheduler's decision making when dealing with 1032 MultiThreading at a cost of slightly increased overhead in some 1033 places. If unsure say N here. 1034 1035config HAVE_ARM_SCU 1036 bool 1037 help 1038 This option enables support for the ARM snoop control unit 1039 1040config HAVE_ARM_ARCH_TIMER 1041 bool "Architected timer support" 1042 depends on CPU_V7 1043 select ARM_ARCH_TIMER 1044 help 1045 This option enables support for the ARM architected timer 1046 1047config HAVE_ARM_TWD 1048 bool 1049 help 1050 This options enables support for the ARM timer and watchdog unit 1051 1052config MCPM 1053 bool "Multi-Cluster Power Management" 1054 depends on CPU_V7 && SMP 1055 help 1056 This option provides the common power management infrastructure 1057 for (multi-)cluster based systems, such as big.LITTLE based 1058 systems. 1059 1060config MCPM_QUAD_CLUSTER 1061 bool 1062 depends on MCPM 1063 help 1064 To avoid wasting resources unnecessarily, MCPM only supports up 1065 to 2 clusters by default. 1066 Platforms with 3 or 4 clusters that use MCPM must select this 1067 option to allow the additional clusters to be managed. 1068 1069config BIG_LITTLE 1070 bool "big.LITTLE support (Experimental)" 1071 depends on CPU_V7 && SMP 1072 select MCPM 1073 help 1074 This option enables support selections for the big.LITTLE 1075 system architecture. 1076 1077config BL_SWITCHER 1078 bool "big.LITTLE switcher support" 1079 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1080 select CPU_PM 1081 help 1082 The big.LITTLE "switcher" provides the core functionality to 1083 transparently handle transition between a cluster of A15's 1084 and a cluster of A7's in a big.LITTLE system. 1085 1086config BL_SWITCHER_DUMMY_IF 1087 tristate "Simple big.LITTLE switcher user interface" 1088 depends on BL_SWITCHER && DEBUG_KERNEL 1089 help 1090 This is a simple and dummy char dev interface to control 1091 the big.LITTLE switcher core code. It is meant for 1092 debugging purposes only. 1093 1094choice 1095 prompt "Memory split" 1096 depends on MMU 1097 default VMSPLIT_3G 1098 help 1099 Select the desired split between kernel and user memory. 1100 1101 If you are not absolutely sure what you are doing, leave this 1102 option alone! 1103 1104 config VMSPLIT_3G 1105 bool "3G/1G user/kernel split" 1106 config VMSPLIT_3G_OPT 1107 depends on !ARM_LPAE 1108 bool "3G/1G user/kernel split (for full 1G low memory)" 1109 config VMSPLIT_2G 1110 bool "2G/2G user/kernel split" 1111 config VMSPLIT_1G 1112 bool "1G/3G user/kernel split" 1113endchoice 1114 1115config PAGE_OFFSET 1116 hex 1117 default PHYS_OFFSET if !MMU 1118 default 0x40000000 if VMSPLIT_1G 1119 default 0x80000000 if VMSPLIT_2G 1120 default 0xB0000000 if VMSPLIT_3G_OPT 1121 default 0xC0000000 1122 1123config KASAN_SHADOW_OFFSET 1124 hex 1125 depends on KASAN 1126 default 0x1f000000 if PAGE_OFFSET=0x40000000 1127 default 0x5f000000 if PAGE_OFFSET=0x80000000 1128 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1129 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1130 default 0xffffffff 1131 1132config NR_CPUS 1133 int "Maximum number of CPUs (2-32)" 1134 range 2 16 if DEBUG_KMAP_LOCAL 1135 range 2 32 if !DEBUG_KMAP_LOCAL 1136 depends on SMP 1137 default "4" 1138 help 1139 The maximum number of CPUs that the kernel can support. 1140 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1141 debugging is enabled, which uses half of the per-CPU fixmap 1142 slots as guard regions. 1143 1144config HOTPLUG_CPU 1145 bool "Support for hot-pluggable CPUs" 1146 depends on SMP 1147 select GENERIC_IRQ_MIGRATION 1148 help 1149 Say Y here to experiment with turning CPUs off and on. CPUs 1150 can be controlled through /sys/devices/system/cpu. 1151 1152config ARM_PSCI 1153 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1154 depends on HAVE_ARM_SMCCC 1155 select ARM_PSCI_FW 1156 help 1157 Say Y here if you want Linux to communicate with system firmware 1158 implementing the PSCI specification for CPU-centric power 1159 management operations described in ARM document number ARM DEN 1160 0022A ("Power State Coordination Interface System Software on 1161 ARM processors"). 1162 1163config HZ_FIXED 1164 int 1165 default 128 if SOC_AT91RM9200 1166 default 0 1167 1168choice 1169 depends on HZ_FIXED = 0 1170 prompt "Timer frequency" 1171 1172config HZ_100 1173 bool "100 Hz" 1174 1175config HZ_200 1176 bool "200 Hz" 1177 1178config HZ_250 1179 bool "250 Hz" 1180 1181config HZ_300 1182 bool "300 Hz" 1183 1184config HZ_500 1185 bool "500 Hz" 1186 1187config HZ_1000 1188 bool "1000 Hz" 1189 1190endchoice 1191 1192config HZ 1193 int 1194 default HZ_FIXED if HZ_FIXED != 0 1195 default 100 if HZ_100 1196 default 200 if HZ_200 1197 default 250 if HZ_250 1198 default 300 if HZ_300 1199 default 500 if HZ_500 1200 default 1000 1201 1202config SCHED_HRTICK 1203 def_bool HIGH_RES_TIMERS 1204 1205config THUMB2_KERNEL 1206 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1207 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1208 default y if CPU_THUMBONLY 1209 select ARM_UNWIND 1210 help 1211 By enabling this option, the kernel will be compiled in 1212 Thumb-2 mode. 1213 1214 If unsure, say N. 1215 1216config ARM_PATCH_IDIV 1217 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1218 depends on CPU_32v7 1219 default y 1220 help 1221 The ARM compiler inserts calls to __aeabi_idiv() and 1222 __aeabi_uidiv() when it needs to perform division on signed 1223 and unsigned integers. Some v7 CPUs have support for the sdiv 1224 and udiv instructions that can be used to implement those 1225 functions. 1226 1227 Enabling this option allows the kernel to modify itself to 1228 replace the first two instructions of these library functions 1229 with the sdiv or udiv plus "bx lr" instructions when the CPU 1230 it is running on supports them. Typically this will be faster 1231 and less power intensive than running the original library 1232 code to do integer division. 1233 1234config AEABI 1235 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1236 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1237 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1238 help 1239 This option allows for the kernel to be compiled using the latest 1240 ARM ABI (aka EABI). This is only useful if you are using a user 1241 space environment that is also compiled with EABI. 1242 1243 Since there are major incompatibilities between the legacy ABI and 1244 EABI, especially with regard to structure member alignment, this 1245 option also changes the kernel syscall calling convention to 1246 disambiguate both ABIs and allow for backward compatibility support 1247 (selected with CONFIG_OABI_COMPAT). 1248 1249 To use this you need GCC version 4.0.0 or later. 1250 1251config OABI_COMPAT 1252 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1253 depends on AEABI && !THUMB2_KERNEL 1254 help 1255 This option preserves the old syscall interface along with the 1256 new (ARM EABI) one. It also provides a compatibility layer to 1257 intercept syscalls that have structure arguments which layout 1258 in memory differs between the legacy ABI and the new ARM EABI 1259 (only for non "thumb" binaries). This option adds a tiny 1260 overhead to all syscalls and produces a slightly larger kernel. 1261 1262 The seccomp filter system will not be available when this is 1263 selected, since there is no way yet to sensibly distinguish 1264 between calling conventions during filtering. 1265 1266 If you know you'll be using only pure EABI user space then you 1267 can say N here. If this option is not selected and you attempt 1268 to execute a legacy ABI binary then the result will be 1269 UNPREDICTABLE (in fact it can be predicted that it won't work 1270 at all). If in doubt say N. 1271 1272config ARCH_SELECT_MEMORY_MODEL 1273 def_bool y 1274 1275config ARCH_FLATMEM_ENABLE 1276 def_bool !(ARCH_RPC || ARCH_SA1100) 1277 1278config ARCH_SPARSEMEM_ENABLE 1279 def_bool !ARCH_FOOTBRIDGE 1280 select SPARSEMEM_STATIC if SPARSEMEM 1281 1282config HIGHMEM 1283 bool "High Memory Support" 1284 depends on MMU 1285 select KMAP_LOCAL 1286 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1287 help 1288 The address space of ARM processors is only 4 Gigabytes large 1289 and it has to accommodate user address space, kernel address 1290 space as well as some memory mapped IO. That means that, if you 1291 have a large amount of physical memory and/or IO, not all of the 1292 memory can be "permanently mapped" by the kernel. The physical 1293 memory that is not permanently mapped is called "high memory". 1294 1295 Depending on the selected kernel/user memory split, minimum 1296 vmalloc space and actual amount of RAM, you may not need this 1297 option which should result in a slightly faster kernel. 1298 1299 If unsure, say n. 1300 1301config HIGHPTE 1302 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1303 depends on HIGHMEM 1304 default y 1305 help 1306 The VM uses one page of physical memory for each page table. 1307 For systems with a lot of processes, this can use a lot of 1308 precious low memory, eventually leading to low memory being 1309 consumed by page tables. Setting this option will allow 1310 user-space 2nd level page tables to reside in high memory. 1311 1312config CPU_SW_DOMAIN_PAN 1313 bool "Enable use of CPU domains to implement privileged no-access" 1314 depends on MMU && !ARM_LPAE 1315 default y 1316 help 1317 Increase kernel security by ensuring that normal kernel accesses 1318 are unable to access userspace addresses. This can help prevent 1319 use-after-free bugs becoming an exploitable privilege escalation 1320 by ensuring that magic values (such as LIST_POISON) will always 1321 fault when dereferenced. 1322 1323 CPUs with low-vector mappings use a best-efforts implementation. 1324 Their lower 1MB needs to remain accessible for the vectors, but 1325 the remainder of userspace will become appropriately inaccessible. 1326 1327config HW_PERF_EVENTS 1328 def_bool y 1329 depends on ARM_PMU 1330 1331config ARM_MODULE_PLTS 1332 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1333 depends on MODULES 1334 select KASAN_VMALLOC if KASAN 1335 default y 1336 help 1337 Allocate PLTs when loading modules so that jumps and calls whose 1338 targets are too far away for their relative offsets to be encoded 1339 in the instructions themselves can be bounced via veneers in the 1340 module's PLT. This allows modules to be allocated in the generic 1341 vmalloc area after the dedicated module memory area has been 1342 exhausted. The modules will use slightly more memory, but after 1343 rounding up to page size, the actual memory footprint is usually 1344 the same. 1345 1346 Disabling this is usually safe for small single-platform 1347 configurations. If unsure, say y. 1348 1349config ARCH_FORCE_MAX_ORDER 1350 int "Maximum zone order" 1351 default "12" if SOC_AM33XX 1352 default "9" if SA1111 1353 default "11" 1354 help 1355 The kernel memory allocator divides physically contiguous memory 1356 blocks into "zones", where each zone is a power of two number of 1357 pages. This option selects the largest power of two that the kernel 1358 keeps in the memory allocator. If you need to allocate very large 1359 blocks of physically contiguous memory, then you may need to 1360 increase this value. 1361 1362 This config option is actually maximum order plus one. For example, 1363 a value of 11 means that the largest free memory block is 2^10 pages. 1364 1365config ALIGNMENT_TRAP 1366 def_bool CPU_CP15_MMU 1367 select HAVE_PROC_CPU if PROC_FS 1368 help 1369 ARM processors cannot fetch/store information which is not 1370 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1371 address divisible by 4. On 32-bit ARM processors, these non-aligned 1372 fetch/store instructions will be emulated in software if you say 1373 here, which has a severe performance impact. This is necessary for 1374 correct operation of some network protocols. With an IP-only 1375 configuration it is safe to say N, otherwise say Y. 1376 1377config UACCESS_WITH_MEMCPY 1378 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1379 depends on MMU 1380 default y if CPU_FEROCEON 1381 help 1382 Implement faster copy_to_user and clear_user methods for CPU 1383 cores where a 8-word STM instruction give significantly higher 1384 memory write throughput than a sequence of individual 32bit stores. 1385 1386 A possible side effect is a slight increase in scheduling latency 1387 between threads sharing the same address space if they invoke 1388 such copy operations with large buffers. 1389 1390 However, if the CPU data cache is using a write-allocate mode, 1391 this option is unlikely to provide any performance gain. 1392 1393config PARAVIRT 1394 bool "Enable paravirtualization code" 1395 help 1396 This changes the kernel so it can modify itself when it is run 1397 under a hypervisor, potentially improving performance significantly 1398 over full virtualization. 1399 1400config PARAVIRT_TIME_ACCOUNTING 1401 bool "Paravirtual steal time accounting" 1402 select PARAVIRT 1403 help 1404 Select this option to enable fine granularity task steal time 1405 accounting. Time spent executing other tasks in parallel with 1406 the current vCPU is discounted from the vCPU power. To account for 1407 that, there can be a small performance impact. 1408 1409 If in doubt, say N here. 1410 1411config XEN_DOM0 1412 def_bool y 1413 depends on XEN 1414 1415config XEN 1416 bool "Xen guest support on ARM" 1417 depends on ARM && AEABI && OF 1418 depends on CPU_V7 && !CPU_V6 1419 depends on !GENERIC_ATOMIC64 1420 depends on MMU 1421 select ARCH_DMA_ADDR_T_64BIT 1422 select ARM_PSCI 1423 select SWIOTLB 1424 select SWIOTLB_XEN 1425 select PARAVIRT 1426 help 1427 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1428 1429config CC_HAVE_STACKPROTECTOR_TLS 1430 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1431 1432config STACKPROTECTOR_PER_TASK 1433 bool "Use a unique stack canary value for each task" 1434 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1435 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1436 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1437 default y 1438 help 1439 Due to the fact that GCC uses an ordinary symbol reference from 1440 which to load the value of the stack canary, this value can only 1441 change at reboot time on SMP systems, and all tasks running in the 1442 kernel's address space are forced to use the same canary value for 1443 the entire duration that the system is up. 1444 1445 Enable this option to switch to a different method that uses a 1446 different canary value for each task. 1447 1448endmenu 1449 1450menu "Boot options" 1451 1452config USE_OF 1453 bool "Flattened Device Tree support" 1454 select IRQ_DOMAIN 1455 select OF 1456 help 1457 Include support for flattened device tree machine descriptions. 1458 1459config ATAGS 1460 bool "Support for the traditional ATAGS boot data passing" 1461 default y 1462 help 1463 This is the traditional way of passing data to the kernel at boot 1464 time. If you are solely relying on the flattened device tree (or 1465 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1466 to remove ATAGS support from your kernel binary. 1467 1468config UNUSED_BOARD_FILES 1469 bool "Board support for machines without known users" 1470 depends on ATAGS 1471 help 1472 Most ATAGS based board files are completely unused and are 1473 scheduled for removal in early 2023, and left out of kernels 1474 by default now. If you are using a board file that is marked 1475 as unused, turn on this option to build support into the kernel. 1476 1477 To keep support for your individual board from being removed, 1478 send a reply to the email discussion at 1479 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1480 1481config DEPRECATED_PARAM_STRUCT 1482 bool "Provide old way to pass kernel parameters" 1483 depends on ATAGS 1484 help 1485 This was deprecated in 2001 and announced to live on for 5 years. 1486 Some old boot loaders still use this way. 1487 1488# Compressed boot loader in ROM. Yes, we really want to ask about 1489# TEXT and BSS so we preserve their values in the config files. 1490config ZBOOT_ROM_TEXT 1491 hex "Compressed ROM boot loader base address" 1492 default 0x0 1493 help 1494 The physical address at which the ROM-able zImage is to be 1495 placed in the target. Platforms which normally make use of 1496 ROM-able zImage formats normally set this to a suitable 1497 value in their defconfig file. 1498 1499 If ZBOOT_ROM is not enabled, this has no effect. 1500 1501config ZBOOT_ROM_BSS 1502 hex "Compressed ROM boot loader BSS address" 1503 default 0x0 1504 help 1505 The base address of an area of read/write memory in the target 1506 for the ROM-able zImage which must be available while the 1507 decompressor is running. It must be large enough to hold the 1508 entire decompressed kernel plus an additional 128 KiB. 1509 Platforms which normally make use of ROM-able zImage formats 1510 normally set this to a suitable value in their defconfig file. 1511 1512 If ZBOOT_ROM is not enabled, this has no effect. 1513 1514config ZBOOT_ROM 1515 bool "Compressed boot loader in ROM/flash" 1516 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1517 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1518 help 1519 Say Y here if you intend to execute your compressed kernel image 1520 (zImage) directly from ROM or flash. If unsure, say N. 1521 1522config ARM_APPENDED_DTB 1523 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1524 depends on OF 1525 help 1526 With this option, the boot code will look for a device tree binary 1527 (DTB) appended to zImage 1528 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1529 1530 This is meant as a backward compatibility convenience for those 1531 systems with a bootloader that can't be upgraded to accommodate 1532 the documented boot protocol using a device tree. 1533 1534 Beware that there is very little in terms of protection against 1535 this option being confused by leftover garbage in memory that might 1536 look like a DTB header after a reboot if no actual DTB is appended 1537 to zImage. Do not leave this option active in a production kernel 1538 if you don't intend to always append a DTB. Proper passing of the 1539 location into r2 of a bootloader provided DTB is always preferable 1540 to this option. 1541 1542config ARM_ATAG_DTB_COMPAT 1543 bool "Supplement the appended DTB with traditional ATAG information" 1544 depends on ARM_APPENDED_DTB 1545 help 1546 Some old bootloaders can't be updated to a DTB capable one, yet 1547 they provide ATAGs with memory configuration, the ramdisk address, 1548 the kernel cmdline string, etc. Such information is dynamically 1549 provided by the bootloader and can't always be stored in a static 1550 DTB. To allow a device tree enabled kernel to be used with such 1551 bootloaders, this option allows zImage to extract the information 1552 from the ATAG list and store it at run time into the appended DTB. 1553 1554choice 1555 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1556 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1557 1558config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1559 bool "Use bootloader kernel arguments if available" 1560 help 1561 Uses the command-line options passed by the boot loader instead of 1562 the device tree bootargs property. If the boot loader doesn't provide 1563 any, the device tree bootargs property will be used. 1564 1565config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1566 bool "Extend with bootloader kernel arguments" 1567 help 1568 The command-line arguments provided by the boot loader will be 1569 appended to the the device tree bootargs property. 1570 1571endchoice 1572 1573config CMDLINE 1574 string "Default kernel command string" 1575 default "" 1576 help 1577 On some architectures (e.g. CATS), there is currently no way 1578 for the boot loader to pass arguments to the kernel. For these 1579 architectures, you should supply some command-line options at build 1580 time by entering them here. As a minimum, you should specify the 1581 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1582 1583choice 1584 prompt "Kernel command line type" if CMDLINE != "" 1585 default CMDLINE_FROM_BOOTLOADER 1586 1587config CMDLINE_FROM_BOOTLOADER 1588 bool "Use bootloader kernel arguments if available" 1589 help 1590 Uses the command-line options passed by the boot loader. If 1591 the boot loader doesn't provide any, the default kernel command 1592 string provided in CMDLINE will be used. 1593 1594config CMDLINE_EXTEND 1595 bool "Extend bootloader kernel arguments" 1596 help 1597 The command-line arguments provided by the boot loader will be 1598 appended to the default kernel command string. 1599 1600config CMDLINE_FORCE 1601 bool "Always use the default kernel command string" 1602 help 1603 Always use the default kernel command string, even if the boot 1604 loader passes other arguments to the kernel. 1605 This is useful if you cannot or don't want to change the 1606 command-line options your boot loader passes to the kernel. 1607endchoice 1608 1609config XIP_KERNEL 1610 bool "Kernel Execute-In-Place from ROM" 1611 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1612 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1613 help 1614 Execute-In-Place allows the kernel to run from non-volatile storage 1615 directly addressable by the CPU, such as NOR flash. This saves RAM 1616 space since the text section of the kernel is not loaded from flash 1617 to RAM. Read-write sections, such as the data section and stack, 1618 are still copied to RAM. The XIP kernel is not compressed since 1619 it has to run directly from flash, so it will take more space to 1620 store it. The flash address used to link the kernel object files, 1621 and for storing it, is configuration dependent. Therefore, if you 1622 say Y here, you must know the proper physical address where to 1623 store the kernel image depending on your own flash memory usage. 1624 1625 Also note that the make target becomes "make xipImage" rather than 1626 "make zImage" or "make Image". The final kernel binary to put in 1627 ROM memory will be arch/arm/boot/xipImage. 1628 1629 If unsure, say N. 1630 1631config XIP_PHYS_ADDR 1632 hex "XIP Kernel Physical Location" 1633 depends on XIP_KERNEL 1634 default "0x00080000" 1635 help 1636 This is the physical address in your flash memory the kernel will 1637 be linked for and stored to. This address is dependent on your 1638 own flash usage. 1639 1640config XIP_DEFLATED_DATA 1641 bool "Store kernel .data section compressed in ROM" 1642 depends on XIP_KERNEL 1643 select ZLIB_INFLATE 1644 help 1645 Before the kernel is actually executed, its .data section has to be 1646 copied to RAM from ROM. This option allows for storing that data 1647 in compressed form and decompressed to RAM rather than merely being 1648 copied, saving some precious ROM space. A possible drawback is a 1649 slightly longer boot delay. 1650 1651config KEXEC 1652 bool "Kexec system call (EXPERIMENTAL)" 1653 depends on (!SMP || PM_SLEEP_SMP) 1654 depends on MMU 1655 select KEXEC_CORE 1656 help 1657 kexec is a system call that implements the ability to shutdown your 1658 current kernel, and to start another kernel. It is like a reboot 1659 but it is independent of the system firmware. And like a reboot 1660 you can start any kernel with it, not just Linux. 1661 1662 It is an ongoing process to be certain the hardware in a machine 1663 is properly shutdown, so do not be surprised if this code does not 1664 initially work for you. 1665 1666config ATAGS_PROC 1667 bool "Export atags in procfs" 1668 depends on ATAGS && KEXEC 1669 default y 1670 help 1671 Should the atags used to boot the kernel be exported in an "atags" 1672 file in procfs. Useful with kexec. 1673 1674config CRASH_DUMP 1675 bool "Build kdump crash kernel (EXPERIMENTAL)" 1676 help 1677 Generate crash dump after being started by kexec. This should 1678 be normally only set in special crash dump kernels which are 1679 loaded in the main kernel with kexec-tools into a specially 1680 reserved region and then later executed after a crash by 1681 kdump/kexec. The crash dump kernel must be compiled to a 1682 memory address not used by the main kernel 1683 1684 For more details see Documentation/admin-guide/kdump/kdump.rst 1685 1686config AUTO_ZRELADDR 1687 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1688 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1689 help 1690 ZRELADDR is the physical address where the decompressed kernel 1691 image will be placed. If AUTO_ZRELADDR is selected, the address 1692 will be determined at run-time, either by masking the current IP 1693 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1694 This assumes the zImage being placed in the first 128MB from 1695 start of memory. 1696 1697config EFI_STUB 1698 bool 1699 1700config EFI 1701 bool "UEFI runtime support" 1702 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1703 select UCS2_STRING 1704 select EFI_PARAMS_FROM_FDT 1705 select EFI_STUB 1706 select EFI_GENERIC_STUB 1707 select EFI_RUNTIME_WRAPPERS 1708 help 1709 This option provides support for runtime services provided 1710 by UEFI firmware (such as non-volatile variables, realtime 1711 clock, and platform reset). A UEFI stub is also provided to 1712 allow the kernel to be booted as an EFI application. This 1713 is only useful for kernels that may run on systems that have 1714 UEFI firmware. 1715 1716config DMI 1717 bool "Enable support for SMBIOS (DMI) tables" 1718 depends on EFI 1719 default y 1720 help 1721 This enables SMBIOS/DMI feature for systems. 1722 1723 This option is only useful on systems that have UEFI firmware. 1724 However, even with this option, the resultant kernel should 1725 continue to boot on existing non-UEFI platforms. 1726 1727 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1728 i.e., the the practice of identifying the platform via DMI to 1729 decide whether certain workarounds for buggy hardware and/or 1730 firmware need to be enabled. This would require the DMI subsystem 1731 to be enabled much earlier than we do on ARM, which is non-trivial. 1732 1733endmenu 1734 1735menu "CPU Power Management" 1736 1737source "drivers/cpufreq/Kconfig" 1738 1739source "drivers/cpuidle/Kconfig" 1740 1741endmenu 1742 1743menu "Floating point emulation" 1744 1745comment "At least one emulation must be selected" 1746 1747config FPE_NWFPE 1748 bool "NWFPE math emulation" 1749 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1750 help 1751 Say Y to include the NWFPE floating point emulator in the kernel. 1752 This is necessary to run most binaries. Linux does not currently 1753 support floating point hardware so you need to say Y here even if 1754 your machine has an FPA or floating point co-processor podule. 1755 1756 You may say N here if you are going to load the Acorn FPEmulator 1757 early in the bootup. 1758 1759config FPE_NWFPE_XP 1760 bool "Support extended precision" 1761 depends on FPE_NWFPE 1762 help 1763 Say Y to include 80-bit support in the kernel floating-point 1764 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1765 Note that gcc does not generate 80-bit operations by default, 1766 so in most cases this option only enlarges the size of the 1767 floating point emulator without any good reason. 1768 1769 You almost surely want to say N here. 1770 1771config FPE_FASTFPE 1772 bool "FastFPE math emulation (EXPERIMENTAL)" 1773 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1774 help 1775 Say Y here to include the FAST floating point emulator in the kernel. 1776 This is an experimental much faster emulator which now also has full 1777 precision for the mantissa. It does not support any exceptions. 1778 It is very simple, and approximately 3-6 times faster than NWFPE. 1779 1780 It should be sufficient for most programs. It may be not suitable 1781 for scientific calculations, but you have to check this for yourself. 1782 If you do not feel you need a faster FP emulation you should better 1783 choose NWFPE. 1784 1785config VFP 1786 bool "VFP-format floating point maths" 1787 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1788 help 1789 Say Y to include VFP support code in the kernel. This is needed 1790 if your hardware includes a VFP unit. 1791 1792 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1793 release notes and additional status information. 1794 1795 Say N if your target does not have VFP hardware. 1796 1797config VFPv3 1798 bool 1799 depends on VFP 1800 default y if CPU_V7 1801 1802config NEON 1803 bool "Advanced SIMD (NEON) Extension support" 1804 depends on VFPv3 && CPU_V7 1805 help 1806 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1807 Extension. 1808 1809config KERNEL_MODE_NEON 1810 bool "Support for NEON in kernel mode" 1811 depends on NEON && AEABI 1812 help 1813 Say Y to include support for NEON in kernel mode. 1814 1815endmenu 1816 1817menu "Power management options" 1818 1819source "kernel/power/Kconfig" 1820 1821config ARCH_SUSPEND_POSSIBLE 1822 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1823 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1824 def_bool y 1825 1826config ARM_CPU_SUSPEND 1827 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1828 depends on ARCH_SUSPEND_POSSIBLE 1829 1830config ARCH_HIBERNATION_POSSIBLE 1831 bool 1832 depends on MMU 1833 default y if ARCH_SUSPEND_POSSIBLE 1834 1835endmenu 1836 1837source "arch/arm/Kconfig.assembler" 1838