1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP 72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 74 select HAVE_ARCH_TRACEHOOK 75 select HAVE_ARM_SMCCC if CPU_V7 76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 77 select HAVE_CONTEXT_TRACKING 78 select HAVE_C_RECORDMCOUNT 79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 80 select HAVE_DMA_CONTIGUOUS if MMU 81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 84 select HAVE_EXIT_THREAD 85 select HAVE_FAST_GUP if ARM_LPAE 86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 89 select HAVE_GCC_PLUGINS 90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 91 select HAVE_IDE if PCI || ISA || PCMCIA 92 select HAVE_IRQ_TIME_ACCOUNTING 93 select HAVE_KERNEL_GZIP 94 select HAVE_KERNEL_LZ4 95 select HAVE_KERNEL_LZMA 96 select HAVE_KERNEL_LZO 97 select HAVE_KERNEL_XZ 98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 99 select HAVE_KRETPROBES if HAVE_KPROBES 100 select HAVE_MOD_ARCH_SPECIFIC 101 select HAVE_NMI 102 select HAVE_OPROFILE if HAVE_PERF_EVENTS 103 select HAVE_OPTPROBES if !THUMB2_KERNEL 104 select HAVE_PERF_EVENTS 105 select HAVE_PERF_REGS 106 select HAVE_PERF_USER_STACK_DUMP 107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 108 select HAVE_REGS_AND_STACK_ACCESS_API 109 select HAVE_RSEQ 110 select HAVE_STACKPROTECTOR 111 select HAVE_SYSCALL_TRACEPOINTS 112 select HAVE_UID16 113 select HAVE_VIRT_CPU_ACCOUNTING_GEN 114 select IRQ_FORCED_THREADING 115 select MODULES_USE_ELF_REL 116 select NEED_DMA_MAP_STATE 117 select OF_EARLY_FLATTREE if OF 118 select OLD_SIGACTION 119 select OLD_SIGSUSPEND3 120 select PCI_SYSCALL if PCI 121 select PERF_USE_VMALLOC 122 select RTC_LIB 123 select SET_FS 124 select SYS_SUPPORTS_APM_EMULATION 125 # Above selects are sorted alphabetically; please add new ones 126 # according to that. Thanks. 127 help 128 The ARM series is a line of low-power-consumption RISC chip designs 129 licensed by ARM Ltd and targeted at embedded applications and 130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 131 manufactured, but legacy ARM-based PC hardware remains popular in 132 Europe. There is an ARM Linux project with a web page at 133 <http://www.arm.linux.org.uk/>. 134 135config ARM_HAS_SG_CHAIN 136 bool 137 138config ARM_DMA_USE_IOMMU 139 bool 140 select ARM_HAS_SG_CHAIN 141 select NEED_SG_DMA_LENGTH 142 143if ARM_DMA_USE_IOMMU 144 145config ARM_DMA_IOMMU_ALIGNMENT 146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 147 range 4 9 148 default 8 149 help 150 DMA mapping framework by default aligns all buffers to the smallest 151 PAGE_SIZE order which is greater than or equal to the requested buffer 152 size. This works well for buffers up to a few hundreds kilobytes, but 153 for larger buffers it just a waste of address space. Drivers which has 154 relatively small addressing window (like 64Mib) might run out of 155 virtual space with just a few allocations. 156 157 With this parameter you can specify the maximum PAGE_SIZE order for 158 DMA IOMMU buffers. Larger buffers will be aligned only to this 159 specified order. The order is expressed as a power of two multiplied 160 by the PAGE_SIZE. 161 162endif 163 164config SYS_SUPPORTS_APM_EMULATION 165 bool 166 167config HAVE_TCM 168 bool 169 select GENERIC_ALLOCATOR 170 171config HAVE_PROC_CPU 172 bool 173 174config NO_IOPORT_MAP 175 bool 176 177config SBUS 178 bool 179 180config STACKTRACE_SUPPORT 181 bool 182 default y 183 184config LOCKDEP_SUPPORT 185 bool 186 default y 187 188config TRACE_IRQFLAGS_SUPPORT 189 bool 190 default !CPU_V7M 191 192config ARCH_HAS_ILOG2_U32 193 bool 194 195config ARCH_HAS_ILOG2_U64 196 bool 197 198config ARCH_HAS_BANDGAP 199 bool 200 201config FIX_EARLYCON_MEM 202 def_bool y if MMU 203 204config GENERIC_HWEIGHT 205 bool 206 default y 207 208config GENERIC_CALIBRATE_DELAY 209 bool 210 default y 211 212config ARCH_MAY_HAVE_PC_FDC 213 bool 214 215config ZONE_DMA 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config ARM_PATCH_PHYS_VIRT 237 bool "Patch physical to virtual translations at runtime" if EMBEDDED 238 default y 239 depends on !XIP_KERNEL && MMU 240 help 241 Patch phys-to-virt and virt-to-phys translation functions at 242 boot and module load time according to the position of the 243 kernel in system memory. 244 245 This can only be used with non-XIP MMU kernels where the base 246 of physical memory is at a 16MB boundary. 247 248 Only disable this option if you know that you do not require 249 this feature (eg, building a kernel for a single machine) and 250 you need to shrink the kernel to the minimal size. 251 252config NEED_MACH_IO_H 253 bool 254 help 255 Select this when mach/io.h is required to provide special 256 definitions for this platform. The need for mach/io.h should 257 be avoided when possible. 258 259config NEED_MACH_MEMORY_H 260 bool 261 help 262 Select this when mach/memory.h is required to provide special 263 definitions for this platform. The need for mach/memory.h should 264 be avoided when possible. 265 266config PHYS_OFFSET 267 hex "Physical address of main memory" if MMU 268 depends on !ARM_PATCH_PHYS_VIRT 269 default DRAM_BASE if !MMU 270 default 0x00000000 if ARCH_FOOTBRIDGE 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x20000000 if ARCH_S5PV210 273 default 0xc0000000 if ARCH_SA1100 274 help 275 Please provide the physical address corresponding to the 276 location of main memory in your system. 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config PGTABLE_LEVELS 283 int 284 default 3 if ARM_LPAE 285 default 2 286 287menu "System Type" 288 289config MMU 290 bool "MMU-based Paged Memory Management Support" 291 default y 292 help 293 Select if you want MMU-based virtualised addressing space 294 support by paged memory management. If unsure, say 'Y'. 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 8 298 299config ARCH_MMAP_RND_BITS_MAX 300 default 14 if PAGE_OFFSET=0x40000000 301 default 15 if PAGE_OFFSET=0x80000000 302 default 16 303 304# 305# The "ARM system type" choice list is ordered alphabetically by option 306# text. Please add new entries in the option alphabetic order. 307# 308choice 309 prompt "ARM system type" 310 default ARM_SINGLE_ARMV7M if !MMU 311 default ARCH_MULTIPLATFORM if MMU 312 313config ARCH_MULTIPLATFORM 314 bool "Allow multiple platforms to be selected" 315 depends on MMU 316 select ARCH_FLATMEM_ENABLE 317 select ARCH_SPARSEMEM_ENABLE 318 select ARCH_SELECT_MEMORY_MODEL 319 select ARM_HAS_SG_CHAIN 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select TIMER_OF 323 select COMMON_CLK 324 select GENERIC_IRQ_MULTI_HANDLER 325 select HAVE_PCI 326 select PCI_DOMAINS_GENERIC if PCI 327 select SPARSE_IRQ 328 select USE_OF 329 330config ARM_SINGLE_ARMV7M 331 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 332 depends on !MMU 333 select ARM_NVIC 334 select AUTO_ZRELADDR 335 select TIMER_OF 336 select COMMON_CLK 337 select CPU_V7M 338 select NO_IOPORT_MAP 339 select SPARSE_IRQ 340 select USE_OF 341 342config ARCH_EP93XX 343 bool "EP93xx-based" 344 select ARCH_SPARSEMEM_ENABLE 345 select ARM_AMBA 346 imply ARM_PATCH_PHYS_VIRT 347 select ARM_VIC 348 select AUTO_ZRELADDR 349 select CLKDEV_LOOKUP 350 select CLKSRC_MMIO 351 select CPU_ARM920T 352 select GPIOLIB 353 select HAVE_LEGACY_CLK 354 help 355 This enables support for the Cirrus EP93xx series of CPUs. 356 357config ARCH_FOOTBRIDGE 358 bool "FootBridge" 359 select CPU_SA110 360 select FOOTBRIDGE 361 select HAVE_IDE 362 select NEED_MACH_IO_H if !MMU 363 select NEED_MACH_MEMORY_H 364 help 365 Support for systems based on the DC21285 companion chip 366 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 367 368config ARCH_IOP32X 369 bool "IOP32x-based" 370 depends on MMU 371 select CPU_XSCALE 372 select GPIO_IOP 373 select GPIOLIB 374 select NEED_RET_TO_USER 375 select FORCE_PCI 376 select PLAT_IOP 377 help 378 Support for Intel's 80219 and IOP32X (XScale) family of 379 processors. 380 381config ARCH_IXP4XX 382 bool "IXP4xx-based" 383 depends on MMU 384 select ARCH_HAS_DMA_SET_COHERENT_MASK 385 select ARCH_SUPPORTS_BIG_ENDIAN 386 select CPU_XSCALE 387 select DMABOUNCE if PCI 388 select GENERIC_IRQ_MULTI_HANDLER 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 select NEED_MACH_IO_H 395 select USB_EHCI_BIG_ENDIAN_DESC 396 select USB_EHCI_BIG_ENDIAN_MMIO 397 help 398 Support for Intel's IXP4XX (XScale) family of processors. 399 400config ARCH_DOVE 401 bool "Marvell Dove" 402 select CPU_PJ4 403 select GENERIC_IRQ_MULTI_HANDLER 404 select GPIOLIB 405 select HAVE_PCI 406 select MVEBU_MBUS 407 select PINCTRL 408 select PINCTRL_DOVE 409 select PLAT_ORION_LEGACY 410 select SPARSE_IRQ 411 select PM_GENERIC_DOMAINS if PM 412 help 413 Support for the Marvell Dove SoC 88AP510 414 415config ARCH_PXA 416 bool "PXA2xx/PXA3xx-based" 417 depends on MMU 418 select ARCH_MTD_XIP 419 select ARM_CPU_SUSPEND if PM 420 select AUTO_ZRELADDR 421 select COMMON_CLK 422 select CLKSRC_PXA 423 select CLKSRC_MMIO 424 select TIMER_OF 425 select CPU_XSCALE if !CPU_XSC3 426 select GENERIC_IRQ_MULTI_HANDLER 427 select GPIO_PXA 428 select GPIOLIB 429 select HAVE_IDE 430 select IRQ_DOMAIN 431 select PLAT_PXA 432 select SPARSE_IRQ 433 help 434 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 435 436config ARCH_RPC 437 bool "RiscPC" 438 depends on MMU 439 select ARCH_ACORN 440 select ARCH_MAY_HAVE_PC_FDC 441 select ARCH_SPARSEMEM_ENABLE 442 select ARM_HAS_SG_CHAIN 443 select CPU_SA110 444 select FIQ 445 select HAVE_IDE 446 select HAVE_PATA_PLATFORM 447 select ISA_DMA_API 448 select LEGACY_TIMER_TICK 449 select NEED_MACH_IO_H 450 select NEED_MACH_MEMORY_H 451 select NO_IOPORT_MAP 452 help 453 On the Acorn Risc-PC, Linux can support the internal IDE disk and 454 CD-ROM interface, serial and parallel port, and the floppy drive. 455 456config ARCH_SA1100 457 bool "SA1100-based" 458 select ARCH_MTD_XIP 459 select ARCH_SPARSEMEM_ENABLE 460 select CLKSRC_MMIO 461 select CLKSRC_PXA 462 select TIMER_OF if OF 463 select COMMON_CLK 464 select CPU_FREQ 465 select CPU_SA1100 466 select GENERIC_IRQ_MULTI_HANDLER 467 select GPIOLIB 468 select HAVE_IDE 469 select IRQ_DOMAIN 470 select ISA 471 select NEED_MACH_MEMORY_H 472 select SPARSE_IRQ 473 help 474 Support for StrongARM 11x0 based boards. 475 476config ARCH_S3C24XX 477 bool "Samsung S3C24XX SoCs" 478 select ATAGS 479 select CLKSRC_SAMSUNG_PWM 480 select GPIO_SAMSUNG 481 select GPIOLIB 482 select GENERIC_IRQ_MULTI_HANDLER 483 select HAVE_S3C2410_I2C if I2C 484 select HAVE_S3C_RTC if RTC_CLASS 485 select NEED_MACH_IO_H 486 select S3C2410_WATCHDOG 487 select SAMSUNG_ATAGS 488 select USE_OF 489 select WATCHDOG 490 help 491 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 492 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 493 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 494 Samsung SMDK2410 development board (and derivatives). 495 496config ARCH_OMAP1 497 bool "TI OMAP1" 498 depends on MMU 499 select ARCH_HAS_HOLES_MEMORYMODEL 500 select ARCH_OMAP 501 select CLKDEV_LOOKUP 502 select CLKSRC_MMIO 503 select GENERIC_IRQ_CHIP 504 select GENERIC_IRQ_MULTI_HANDLER 505 select GPIOLIB 506 select HAVE_IDE 507 select HAVE_LEGACY_CLK 508 select IRQ_DOMAIN 509 select NEED_MACH_IO_H if PCCARD 510 select NEED_MACH_MEMORY_H 511 select SPARSE_IRQ 512 help 513 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 514 515endchoice 516 517menu "Multiple platform selection" 518 depends on ARCH_MULTIPLATFORM 519 520comment "CPU Core family selection" 521 522config ARCH_MULTI_V4 523 bool "ARMv4 based platforms (FA526)" 524 depends on !ARCH_MULTI_V6_V7 525 select ARCH_MULTI_V4_V5 526 select CPU_FA526 527 528config ARCH_MULTI_V4T 529 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 530 depends on !ARCH_MULTI_V6_V7 531 select ARCH_MULTI_V4_V5 532 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 533 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 534 CPU_ARM925T || CPU_ARM940T) 535 536config ARCH_MULTI_V5 537 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 538 depends on !ARCH_MULTI_V6_V7 539 select ARCH_MULTI_V4_V5 540 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 541 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 542 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 543 544config ARCH_MULTI_V4_V5 545 bool 546 547config ARCH_MULTI_V6 548 bool "ARMv6 based platforms (ARM11)" 549 select ARCH_MULTI_V6_V7 550 select CPU_V6K 551 552config ARCH_MULTI_V7 553 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 554 default y 555 select ARCH_MULTI_V6_V7 556 select CPU_V7 557 select HAVE_SMP 558 559config ARCH_MULTI_V6_V7 560 bool 561 select MIGHT_HAVE_CACHE_L2X0 562 563config ARCH_MULTI_CPU_AUTO 564 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 565 select ARCH_MULTI_V5 566 567endmenu 568 569config ARCH_VIRT 570 bool "Dummy Virtual Machine" 571 depends on ARCH_MULTI_V7 572 select ARM_AMBA 573 select ARM_GIC 574 select ARM_GIC_V2M if PCI 575 select ARM_GIC_V3 576 select ARM_GIC_V3_ITS if PCI 577 select ARM_PSCI 578 select HAVE_ARM_ARCH_TIMER 579 select ARCH_SUPPORTS_BIG_ENDIAN 580 581# 582# This is sorted alphabetically by mach-* pathname. However, plat-* 583# Kconfigs may be included either alphabetically (according to the 584# plat- suffix) or along side the corresponding mach-* source. 585# 586source "arch/arm/mach-actions/Kconfig" 587 588source "arch/arm/mach-alpine/Kconfig" 589 590source "arch/arm/mach-artpec/Kconfig" 591 592source "arch/arm/mach-asm9260/Kconfig" 593 594source "arch/arm/mach-aspeed/Kconfig" 595 596source "arch/arm/mach-at91/Kconfig" 597 598source "arch/arm/mach-axxia/Kconfig" 599 600source "arch/arm/mach-bcm/Kconfig" 601 602source "arch/arm/mach-berlin/Kconfig" 603 604source "arch/arm/mach-clps711x/Kconfig" 605 606source "arch/arm/mach-cns3xxx/Kconfig" 607 608source "arch/arm/mach-davinci/Kconfig" 609 610source "arch/arm/mach-digicolor/Kconfig" 611 612source "arch/arm/mach-dove/Kconfig" 613 614source "arch/arm/mach-ep93xx/Kconfig" 615 616source "arch/arm/mach-exynos/Kconfig" 617 618source "arch/arm/mach-footbridge/Kconfig" 619 620source "arch/arm/mach-gemini/Kconfig" 621 622source "arch/arm/mach-highbank/Kconfig" 623 624source "arch/arm/mach-hisi/Kconfig" 625 626source "arch/arm/mach-imx/Kconfig" 627 628source "arch/arm/mach-integrator/Kconfig" 629 630source "arch/arm/mach-iop32x/Kconfig" 631 632source "arch/arm/mach-ixp4xx/Kconfig" 633 634source "arch/arm/mach-keystone/Kconfig" 635 636source "arch/arm/mach-lpc32xx/Kconfig" 637 638source "arch/arm/mach-mediatek/Kconfig" 639 640source "arch/arm/mach-meson/Kconfig" 641 642source "arch/arm/mach-milbeaut/Kconfig" 643 644source "arch/arm/mach-mmp/Kconfig" 645 646source "arch/arm/mach-moxart/Kconfig" 647 648source "arch/arm/mach-mstar/Kconfig" 649 650source "arch/arm/mach-mv78xx0/Kconfig" 651 652source "arch/arm/mach-mvebu/Kconfig" 653 654source "arch/arm/mach-mxs/Kconfig" 655 656source "arch/arm/mach-nomadik/Kconfig" 657 658source "arch/arm/mach-npcm/Kconfig" 659 660source "arch/arm/mach-nspire/Kconfig" 661 662source "arch/arm/plat-omap/Kconfig" 663 664source "arch/arm/mach-omap1/Kconfig" 665 666source "arch/arm/mach-omap2/Kconfig" 667 668source "arch/arm/mach-orion5x/Kconfig" 669 670source "arch/arm/mach-oxnas/Kconfig" 671 672source "arch/arm/mach-picoxcell/Kconfig" 673 674source "arch/arm/mach-prima2/Kconfig" 675 676source "arch/arm/mach-pxa/Kconfig" 677source "arch/arm/plat-pxa/Kconfig" 678 679source "arch/arm/mach-qcom/Kconfig" 680 681source "arch/arm/mach-rda/Kconfig" 682 683source "arch/arm/mach-realtek/Kconfig" 684 685source "arch/arm/mach-realview/Kconfig" 686 687source "arch/arm/mach-rockchip/Kconfig" 688 689source "arch/arm/mach-s3c/Kconfig" 690 691source "arch/arm/mach-s5pv210/Kconfig" 692 693source "arch/arm/mach-sa1100/Kconfig" 694 695source "arch/arm/mach-shmobile/Kconfig" 696 697source "arch/arm/mach-socfpga/Kconfig" 698 699source "arch/arm/mach-spear/Kconfig" 700 701source "arch/arm/mach-sti/Kconfig" 702 703source "arch/arm/mach-stm32/Kconfig" 704 705source "arch/arm/mach-sunxi/Kconfig" 706 707source "arch/arm/mach-tango/Kconfig" 708 709source "arch/arm/mach-tegra/Kconfig" 710 711source "arch/arm/mach-u300/Kconfig" 712 713source "arch/arm/mach-uniphier/Kconfig" 714 715source "arch/arm/mach-ux500/Kconfig" 716 717source "arch/arm/mach-versatile/Kconfig" 718 719source "arch/arm/mach-vexpress/Kconfig" 720 721source "arch/arm/mach-vt8500/Kconfig" 722 723source "arch/arm/mach-zx/Kconfig" 724 725source "arch/arm/mach-zynq/Kconfig" 726 727# ARMv7-M architecture 728config ARCH_EFM32 729 bool "Energy Micro efm32" 730 depends on ARM_SINGLE_ARMV7M 731 select GPIOLIB 732 help 733 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 734 processors. 735 736config ARCH_LPC18XX 737 bool "NXP LPC18xx/LPC43xx" 738 depends on ARM_SINGLE_ARMV7M 739 select ARCH_HAS_RESET_CONTROLLER 740 select ARM_AMBA 741 select CLKSRC_LPC32XX 742 select PINCTRL 743 help 744 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 745 high performance microcontrollers. 746 747config ARCH_MPS2 748 bool "ARM MPS2 platform" 749 depends on ARM_SINGLE_ARMV7M 750 select ARM_AMBA 751 select CLKSRC_MPS2 752 help 753 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 754 with a range of available cores like Cortex-M3/M4/M7. 755 756 Please, note that depends which Application Note is used memory map 757 for the platform may vary, so adjustment of RAM base might be needed. 758 759# Definitions to make life easier 760config ARCH_ACORN 761 bool 762 763config PLAT_IOP 764 bool 765 766config PLAT_ORION 767 bool 768 select CLKSRC_MMIO 769 select COMMON_CLK 770 select GENERIC_IRQ_CHIP 771 select IRQ_DOMAIN 772 773config PLAT_ORION_LEGACY 774 bool 775 select PLAT_ORION 776 777config PLAT_PXA 778 bool 779 780config PLAT_VERSATILE 781 bool 782 783source "arch/arm/mm/Kconfig" 784 785config IWMMXT 786 bool "Enable iWMMXt support" 787 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 788 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 789 help 790 Enable support for iWMMXt context switching at run time if 791 running on a CPU that supports it. 792 793if !MMU 794source "arch/arm/Kconfig-nommu" 795endif 796 797config PJ4B_ERRATA_4742 798 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 799 depends on CPU_PJ4B && MACH_ARMADA_370 800 default y 801 help 802 When coming out of either a Wait for Interrupt (WFI) or a Wait for 803 Event (WFE) IDLE states, a specific timing sensitivity exists between 804 the retiring WFI/WFE instructions and the newly issued subsequent 805 instructions. This sensitivity can result in a CPU hang scenario. 806 Workaround: 807 The software must insert either a Data Synchronization Barrier (DSB) 808 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 809 instruction 810 811config ARM_ERRATA_326103 812 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 813 depends on CPU_V6 814 help 815 Executing a SWP instruction to read-only memory does not set bit 11 816 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 817 treat the access as a read, preventing a COW from occurring and 818 causing the faulting task to livelock. 819 820config ARM_ERRATA_411920 821 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 822 depends on CPU_V6 || CPU_V6K 823 help 824 Invalidation of the Instruction Cache operation can 825 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 826 It does not affect the MPCore. This option enables the ARM Ltd. 827 recommended workaround. 828 829config ARM_ERRATA_430973 830 bool "ARM errata: Stale prediction on replaced interworking branch" 831 depends on CPU_V7 832 help 833 This option enables the workaround for the 430973 Cortex-A8 834 r1p* erratum. If a code sequence containing an ARM/Thumb 835 interworking branch is replaced with another code sequence at the 836 same virtual address, whether due to self-modifying code or virtual 837 to physical address re-mapping, Cortex-A8 does not recover from the 838 stale interworking branch prediction. This results in Cortex-A8 839 executing the new code sequence in the incorrect ARM or Thumb state. 840 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 841 and also flushes the branch target cache at every context switch. 842 Note that setting specific bits in the ACTLR register may not be 843 available in non-secure mode. 844 845config ARM_ERRATA_458693 846 bool "ARM errata: Processor deadlock when a false hazard is created" 847 depends on CPU_V7 848 depends on !ARCH_MULTIPLATFORM 849 help 850 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 851 erratum. For very specific sequences of memory operations, it is 852 possible for a hazard condition intended for a cache line to instead 853 be incorrectly associated with a different cache line. This false 854 hazard might then cause a processor deadlock. The workaround enables 855 the L1 caching of the NEON accesses and disables the PLD instruction 856 in the ACTLR register. Note that setting specific bits in the ACTLR 857 register may not be available in non-secure mode. 858 859config ARM_ERRATA_460075 860 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 861 depends on CPU_V7 862 depends on !ARCH_MULTIPLATFORM 863 help 864 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 865 erratum. Any asynchronous access to the L2 cache may encounter a 866 situation in which recent store transactions to the L2 cache are lost 867 and overwritten with stale memory contents from external memory. The 868 workaround disables the write-allocate mode for the L2 cache via the 869 ACTLR register. Note that setting specific bits in the ACTLR register 870 may not be available in non-secure mode. 871 872config ARM_ERRATA_742230 873 bool "ARM errata: DMB operation may be faulty" 874 depends on CPU_V7 && SMP 875 depends on !ARCH_MULTIPLATFORM 876 help 877 This option enables the workaround for the 742230 Cortex-A9 878 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 879 between two write operations may not ensure the correct visibility 880 ordering of the two writes. This workaround sets a specific bit in 881 the diagnostic register of the Cortex-A9 which causes the DMB 882 instruction to behave as a DSB, ensuring the correct behaviour of 883 the two writes. 884 885config ARM_ERRATA_742231 886 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 887 depends on CPU_V7 && SMP 888 depends on !ARCH_MULTIPLATFORM 889 help 890 This option enables the workaround for the 742231 Cortex-A9 891 (r2p0..r2p2) erratum. Under certain conditions, specific to the 892 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 893 accessing some data located in the same cache line, may get corrupted 894 data due to bad handling of the address hazard when the line gets 895 replaced from one of the CPUs at the same time as another CPU is 896 accessing it. This workaround sets specific bits in the diagnostic 897 register of the Cortex-A9 which reduces the linefill issuing 898 capabilities of the processor. 899 900config ARM_ERRATA_643719 901 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 902 depends on CPU_V7 && SMP 903 default y 904 help 905 This option enables the workaround for the 643719 Cortex-A9 (prior to 906 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 907 register returns zero when it should return one. The workaround 908 corrects this value, ensuring cache maintenance operations which use 909 it behave as intended and avoiding data corruption. 910 911config ARM_ERRATA_720789 912 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 913 depends on CPU_V7 914 help 915 This option enables the workaround for the 720789 Cortex-A9 (prior to 916 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 917 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 918 As a consequence of this erratum, some TLB entries which should be 919 invalidated are not, resulting in an incoherency in the system page 920 tables. The workaround changes the TLB flushing routines to invalidate 921 entries regardless of the ASID. 922 923config ARM_ERRATA_743622 924 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 925 depends on CPU_V7 926 depends on !ARCH_MULTIPLATFORM 927 help 928 This option enables the workaround for the 743622 Cortex-A9 929 (r2p*) erratum. Under very rare conditions, a faulty 930 optimisation in the Cortex-A9 Store Buffer may lead to data 931 corruption. This workaround sets a specific bit in the diagnostic 932 register of the Cortex-A9 which disables the Store Buffer 933 optimisation, preventing the defect from occurring. This has no 934 visible impact on the overall performance or power consumption of the 935 processor. 936 937config ARM_ERRATA_751472 938 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 939 depends on CPU_V7 940 depends on !ARCH_MULTIPLATFORM 941 help 942 This option enables the workaround for the 751472 Cortex-A9 (prior 943 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 944 completion of a following broadcasted operation if the second 945 operation is received by a CPU before the ICIALLUIS has completed, 946 potentially leading to corrupted entries in the cache or TLB. 947 948config ARM_ERRATA_754322 949 bool "ARM errata: possible faulty MMU translations following an ASID switch" 950 depends on CPU_V7 951 help 952 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 953 r3p*) erratum. A speculative memory access may cause a page table walk 954 which starts prior to an ASID switch but completes afterwards. This 955 can populate the micro-TLB with a stale entry which may be hit with 956 the new ASID. This workaround places two dsb instructions in the mm 957 switching code so that no page table walks can cross the ASID switch. 958 959config ARM_ERRATA_754327 960 bool "ARM errata: no automatic Store Buffer drain" 961 depends on CPU_V7 && SMP 962 help 963 This option enables the workaround for the 754327 Cortex-A9 (prior to 964 r2p0) erratum. The Store Buffer does not have any automatic draining 965 mechanism and therefore a livelock may occur if an external agent 966 continuously polls a memory location waiting to observe an update. 967 This workaround defines cpu_relax() as smp_mb(), preventing correctly 968 written polling loops from denying visibility of updates to memory. 969 970config ARM_ERRATA_364296 971 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 972 depends on CPU_V6 973 help 974 This options enables the workaround for the 364296 ARM1136 975 r0p2 erratum (possible cache data corruption with 976 hit-under-miss enabled). It sets the undocumented bit 31 in 977 the auxiliary control register and the FI bit in the control 978 register, thus disabling hit-under-miss without putting the 979 processor into full low interrupt latency mode. ARM11MPCore 980 is not affected. 981 982config ARM_ERRATA_764369 983 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 984 depends on CPU_V7 && SMP 985 help 986 This option enables the workaround for erratum 764369 987 affecting Cortex-A9 MPCore with two or more processors (all 988 current revisions). Under certain timing circumstances, a data 989 cache line maintenance operation by MVA targeting an Inner 990 Shareable memory region may fail to proceed up to either the 991 Point of Coherency or to the Point of Unification of the 992 system. This workaround adds a DSB instruction before the 993 relevant cache maintenance functions and sets a specific bit 994 in the diagnostic control register of the SCU. 995 996config ARM_ERRATA_775420 997 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 998 depends on CPU_V7 999 help 1000 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1001 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1002 operation aborts with MMU exception, it might cause the processor 1003 to deadlock. This workaround puts DSB before executing ISB if 1004 an abort may occur on cache maintenance. 1005 1006config ARM_ERRATA_798181 1007 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1008 depends on CPU_V7 && SMP 1009 help 1010 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1011 adequately shooting down all use of the old entries. This 1012 option enables the Linux kernel workaround for this erratum 1013 which sends an IPI to the CPUs that are running the same ASID 1014 as the one being invalidated. 1015 1016config ARM_ERRATA_773022 1017 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1018 depends on CPU_V7 1019 help 1020 This option enables the workaround for the 773022 Cortex-A15 1021 (up to r0p4) erratum. In certain rare sequences of code, the 1022 loop buffer may deliver incorrect instructions. This 1023 workaround disables the loop buffer to avoid the erratum. 1024 1025config ARM_ERRATA_818325_852422 1026 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1027 depends on CPU_V7 1028 help 1029 This option enables the workaround for: 1030 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1031 instruction might deadlock. Fixed in r0p1. 1032 - Cortex-A12 852422: Execution of a sequence of instructions might 1033 lead to either a data corruption or a CPU deadlock. Not fixed in 1034 any Cortex-A12 cores yet. 1035 This workaround for all both errata involves setting bit[12] of the 1036 Feature Register. This bit disables an optimisation applied to a 1037 sequence of 2 instructions that use opposing condition codes. 1038 1039config ARM_ERRATA_821420 1040 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1041 depends on CPU_V7 1042 help 1043 This option enables the workaround for the 821420 Cortex-A12 1044 (all revs) erratum. In very rare timing conditions, a sequence 1045 of VMOV to Core registers instructions, for which the second 1046 one is in the shadow of a branch or abort, can lead to a 1047 deadlock when the VMOV instructions are issued out-of-order. 1048 1049config ARM_ERRATA_825619 1050 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1051 depends on CPU_V7 1052 help 1053 This option enables the workaround for the 825619 Cortex-A12 1054 (all revs) erratum. Within rare timing constraints, executing a 1055 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1056 and Device/Strongly-Ordered loads and stores might cause deadlock 1057 1058config ARM_ERRATA_857271 1059 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1060 depends on CPU_V7 1061 help 1062 This option enables the workaround for the 857271 Cortex-A12 1063 (all revs) erratum. Under very rare timing conditions, the CPU might 1064 hang. The workaround is expected to have a < 1% performance impact. 1065 1066config ARM_ERRATA_852421 1067 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1068 depends on CPU_V7 1069 help 1070 This option enables the workaround for the 852421 Cortex-A17 1071 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1072 execution of a DMB ST instruction might fail to properly order 1073 stores from GroupA and stores from GroupB. 1074 1075config ARM_ERRATA_852423 1076 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for: 1080 - Cortex-A17 852423: Execution of a sequence of instructions might 1081 lead to either a data corruption or a CPU deadlock. Not fixed in 1082 any Cortex-A17 cores yet. 1083 This is identical to Cortex-A12 erratum 852422. It is a separate 1084 config option from the A12 erratum due to the way errata are checked 1085 for and handled. 1086 1087config ARM_ERRATA_857272 1088 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1089 depends on CPU_V7 1090 help 1091 This option enables the workaround for the 857272 Cortex-A17 erratum. 1092 This erratum is not known to be fixed in any A17 revision. 1093 This is identical to Cortex-A12 erratum 857271. It is a separate 1094 config option from the A12 erratum due to the way errata are checked 1095 for and handled. 1096 1097endmenu 1098 1099source "arch/arm/common/Kconfig" 1100 1101menu "Bus support" 1102 1103config ISA 1104 bool 1105 help 1106 Find out whether you have ISA slots on your motherboard. ISA is the 1107 name of a bus system, i.e. the way the CPU talks to the other stuff 1108 inside your box. Other bus systems are PCI, EISA, MicroChannel 1109 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1110 newer boards don't support it. If you have ISA, say Y, otherwise N. 1111 1112# Select ISA DMA controller support 1113config ISA_DMA 1114 bool 1115 select ISA_DMA_API 1116 1117# Select ISA DMA interface 1118config ISA_DMA_API 1119 bool 1120 1121config PCI_NANOENGINE 1122 bool "BSE nanoEngine PCI support" 1123 depends on SA1100_NANOENGINE 1124 help 1125 Enable PCI on the BSE nanoEngine board. 1126 1127config ARM_ERRATA_814220 1128 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1129 depends on CPU_V7 1130 help 1131 The v7 ARM states that all cache and branch predictor maintenance 1132 operations that do not specify an address execute, relative to 1133 each other, in program order. 1134 However, because of this erratum, an L2 set/way cache maintenance 1135 operation can overtake an L1 set/way cache maintenance operation. 1136 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1137 r0p4, r0p5. 1138 1139endmenu 1140 1141menu "Kernel Features" 1142 1143config HAVE_SMP 1144 bool 1145 help 1146 This option should be selected by machines which have an SMP- 1147 capable CPU. 1148 1149 The only effect of this option is to make the SMP-related 1150 options available to the user for configuration. 1151 1152config SMP 1153 bool "Symmetric Multi-Processing" 1154 depends on CPU_V6K || CPU_V7 1155 depends on HAVE_SMP 1156 depends on MMU || ARM_MPU 1157 select IRQ_WORK 1158 help 1159 This enables support for systems with more than one CPU. If you have 1160 a system with only one CPU, say N. If you have a system with more 1161 than one CPU, say Y. 1162 1163 If you say N here, the kernel will run on uni- and multiprocessor 1164 machines, but will use only one CPU of a multiprocessor machine. If 1165 you say Y here, the kernel will run on many, but not all, 1166 uniprocessor machines. On a uniprocessor machine, the kernel 1167 will run faster if you say N here. 1168 1169 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1170 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1171 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1172 1173 If you don't know what to do here, say N. 1174 1175config SMP_ON_UP 1176 bool "Allow booting SMP kernel on uniprocessor systems" 1177 depends on SMP && !XIP_KERNEL && MMU 1178 default y 1179 help 1180 SMP kernels contain instructions which fail on non-SMP processors. 1181 Enabling this option allows the kernel to modify itself to make 1182 these instructions safe. Disabling it allows about 1K of space 1183 savings. 1184 1185 If you don't know what to do here, say Y. 1186 1187config ARM_CPU_TOPOLOGY 1188 bool "Support cpu topology definition" 1189 depends on SMP && CPU_V7 1190 default y 1191 help 1192 Support ARM cpu topology definition. The MPIDR register defines 1193 affinity between processors which is then used to describe the cpu 1194 topology of an ARM System. 1195 1196config SCHED_MC 1197 bool "Multi-core scheduler support" 1198 depends on ARM_CPU_TOPOLOGY 1199 help 1200 Multi-core scheduler support improves the CPU scheduler's decision 1201 making when dealing with multi-core CPU chips at a cost of slightly 1202 increased overhead in some places. If unsure say N here. 1203 1204config SCHED_SMT 1205 bool "SMT scheduler support" 1206 depends on ARM_CPU_TOPOLOGY 1207 help 1208 Improves the CPU scheduler's decision making when dealing with 1209 MultiThreading at a cost of slightly increased overhead in some 1210 places. If unsure say N here. 1211 1212config HAVE_ARM_SCU 1213 bool 1214 help 1215 This option enables support for the ARM snoop control unit 1216 1217config HAVE_ARM_ARCH_TIMER 1218 bool "Architected timer support" 1219 depends on CPU_V7 1220 select ARM_ARCH_TIMER 1221 help 1222 This option enables support for the ARM architected timer 1223 1224config HAVE_ARM_TWD 1225 bool 1226 help 1227 This options enables support for the ARM timer and watchdog unit 1228 1229config MCPM 1230 bool "Multi-Cluster Power Management" 1231 depends on CPU_V7 && SMP 1232 help 1233 This option provides the common power management infrastructure 1234 for (multi-)cluster based systems, such as big.LITTLE based 1235 systems. 1236 1237config MCPM_QUAD_CLUSTER 1238 bool 1239 depends on MCPM 1240 help 1241 To avoid wasting resources unnecessarily, MCPM only supports up 1242 to 2 clusters by default. 1243 Platforms with 3 or 4 clusters that use MCPM must select this 1244 option to allow the additional clusters to be managed. 1245 1246config BIG_LITTLE 1247 bool "big.LITTLE support (Experimental)" 1248 depends on CPU_V7 && SMP 1249 select MCPM 1250 help 1251 This option enables support selections for the big.LITTLE 1252 system architecture. 1253 1254config BL_SWITCHER 1255 bool "big.LITTLE switcher support" 1256 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1257 select CPU_PM 1258 help 1259 The big.LITTLE "switcher" provides the core functionality to 1260 transparently handle transition between a cluster of A15's 1261 and a cluster of A7's in a big.LITTLE system. 1262 1263config BL_SWITCHER_DUMMY_IF 1264 tristate "Simple big.LITTLE switcher user interface" 1265 depends on BL_SWITCHER && DEBUG_KERNEL 1266 help 1267 This is a simple and dummy char dev interface to control 1268 the big.LITTLE switcher core code. It is meant for 1269 debugging purposes only. 1270 1271choice 1272 prompt "Memory split" 1273 depends on MMU 1274 default VMSPLIT_3G 1275 help 1276 Select the desired split between kernel and user memory. 1277 1278 If you are not absolutely sure what you are doing, leave this 1279 option alone! 1280 1281 config VMSPLIT_3G 1282 bool "3G/1G user/kernel split" 1283 config VMSPLIT_3G_OPT 1284 depends on !ARM_LPAE 1285 bool "3G/1G user/kernel split (for full 1G low memory)" 1286 config VMSPLIT_2G 1287 bool "2G/2G user/kernel split" 1288 config VMSPLIT_1G 1289 bool "1G/3G user/kernel split" 1290endchoice 1291 1292config PAGE_OFFSET 1293 hex 1294 default PHYS_OFFSET if !MMU 1295 default 0x40000000 if VMSPLIT_1G 1296 default 0x80000000 if VMSPLIT_2G 1297 default 0xB0000000 if VMSPLIT_3G_OPT 1298 default 0xC0000000 1299 1300config NR_CPUS 1301 int "Maximum number of CPUs (2-32)" 1302 range 2 32 1303 depends on SMP 1304 default "4" 1305 1306config HOTPLUG_CPU 1307 bool "Support for hot-pluggable CPUs" 1308 depends on SMP 1309 select GENERIC_IRQ_MIGRATION 1310 help 1311 Say Y here to experiment with turning CPUs off and on. CPUs 1312 can be controlled through /sys/devices/system/cpu. 1313 1314config ARM_PSCI 1315 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1316 depends on HAVE_ARM_SMCCC 1317 select ARM_PSCI_FW 1318 help 1319 Say Y here if you want Linux to communicate with system firmware 1320 implementing the PSCI specification for CPU-centric power 1321 management operations described in ARM document number ARM DEN 1322 0022A ("Power State Coordination Interface System Software on 1323 ARM processors"). 1324 1325# The GPIO number here must be sorted by descending number. In case of 1326# a multiplatform kernel, we just want the highest value required by the 1327# selected platforms. 1328config ARCH_NR_GPIO 1329 int 1330 default 2048 if ARCH_SOCFPGA 1331 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1332 ARCH_ZYNQ || ARCH_ASPEED 1333 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1334 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1335 default 416 if ARCH_SUNXI 1336 default 392 if ARCH_U8500 1337 default 352 if ARCH_VT8500 1338 default 288 if ARCH_ROCKCHIP 1339 default 264 if MACH_H4700 1340 default 0 1341 help 1342 Maximum number of GPIOs in the system. 1343 1344 If unsure, leave the default value. 1345 1346config HZ_FIXED 1347 int 1348 default 128 if SOC_AT91RM9200 1349 default 0 1350 1351choice 1352 depends on HZ_FIXED = 0 1353 prompt "Timer frequency" 1354 1355config HZ_100 1356 bool "100 Hz" 1357 1358config HZ_200 1359 bool "200 Hz" 1360 1361config HZ_250 1362 bool "250 Hz" 1363 1364config HZ_300 1365 bool "300 Hz" 1366 1367config HZ_500 1368 bool "500 Hz" 1369 1370config HZ_1000 1371 bool "1000 Hz" 1372 1373endchoice 1374 1375config HZ 1376 int 1377 default HZ_FIXED if HZ_FIXED != 0 1378 default 100 if HZ_100 1379 default 200 if HZ_200 1380 default 250 if HZ_250 1381 default 300 if HZ_300 1382 default 500 if HZ_500 1383 default 1000 1384 1385config SCHED_HRTICK 1386 def_bool HIGH_RES_TIMERS 1387 1388config THUMB2_KERNEL 1389 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1390 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1391 default y if CPU_THUMBONLY 1392 select ARM_UNWIND 1393 help 1394 By enabling this option, the kernel will be compiled in 1395 Thumb-2 mode. 1396 1397 If unsure, say N. 1398 1399config ARM_PATCH_IDIV 1400 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1401 depends on CPU_32v7 && !XIP_KERNEL 1402 default y 1403 help 1404 The ARM compiler inserts calls to __aeabi_idiv() and 1405 __aeabi_uidiv() when it needs to perform division on signed 1406 and unsigned integers. Some v7 CPUs have support for the sdiv 1407 and udiv instructions that can be used to implement those 1408 functions. 1409 1410 Enabling this option allows the kernel to modify itself to 1411 replace the first two instructions of these library functions 1412 with the sdiv or udiv plus "bx lr" instructions when the CPU 1413 it is running on supports them. Typically this will be faster 1414 and less power intensive than running the original library 1415 code to do integer division. 1416 1417config AEABI 1418 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1419 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1420 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1421 help 1422 This option allows for the kernel to be compiled using the latest 1423 ARM ABI (aka EABI). This is only useful if you are using a user 1424 space environment that is also compiled with EABI. 1425 1426 Since there are major incompatibilities between the legacy ABI and 1427 EABI, especially with regard to structure member alignment, this 1428 option also changes the kernel syscall calling convention to 1429 disambiguate both ABIs and allow for backward compatibility support 1430 (selected with CONFIG_OABI_COMPAT). 1431 1432 To use this you need GCC version 4.0.0 or later. 1433 1434config OABI_COMPAT 1435 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1436 depends on AEABI && !THUMB2_KERNEL 1437 help 1438 This option preserves the old syscall interface along with the 1439 new (ARM EABI) one. It also provides a compatibility layer to 1440 intercept syscalls that have structure arguments which layout 1441 in memory differs between the legacy ABI and the new ARM EABI 1442 (only for non "thumb" binaries). This option adds a tiny 1443 overhead to all syscalls and produces a slightly larger kernel. 1444 1445 The seccomp filter system will not be available when this is 1446 selected, since there is no way yet to sensibly distinguish 1447 between calling conventions during filtering. 1448 1449 If you know you'll be using only pure EABI user space then you 1450 can say N here. If this option is not selected and you attempt 1451 to execute a legacy ABI binary then the result will be 1452 UNPREDICTABLE (in fact it can be predicted that it won't work 1453 at all). If in doubt say N. 1454 1455config ARCH_HAS_HOLES_MEMORYMODEL 1456 bool 1457 1458config ARCH_SELECT_MEMORY_MODEL 1459 bool 1460 1461config ARCH_FLATMEM_ENABLE 1462 bool 1463 1464config ARCH_SPARSEMEM_ENABLE 1465 bool 1466 select SPARSEMEM_STATIC if SPARSEMEM 1467 1468config HAVE_ARCH_PFN_VALID 1469 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1470 1471config HIGHMEM 1472 bool "High Memory Support" 1473 depends on MMU 1474 help 1475 The address space of ARM processors is only 4 Gigabytes large 1476 and it has to accommodate user address space, kernel address 1477 space as well as some memory mapped IO. That means that, if you 1478 have a large amount of physical memory and/or IO, not all of the 1479 memory can be "permanently mapped" by the kernel. The physical 1480 memory that is not permanently mapped is called "high memory". 1481 1482 Depending on the selected kernel/user memory split, minimum 1483 vmalloc space and actual amount of RAM, you may not need this 1484 option which should result in a slightly faster kernel. 1485 1486 If unsure, say n. 1487 1488config HIGHPTE 1489 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1490 depends on HIGHMEM 1491 default y 1492 help 1493 The VM uses one page of physical memory for each page table. 1494 For systems with a lot of processes, this can use a lot of 1495 precious low memory, eventually leading to low memory being 1496 consumed by page tables. Setting this option will allow 1497 user-space 2nd level page tables to reside in high memory. 1498 1499config CPU_SW_DOMAIN_PAN 1500 bool "Enable use of CPU domains to implement privileged no-access" 1501 depends on MMU && !ARM_LPAE 1502 default y 1503 help 1504 Increase kernel security by ensuring that normal kernel accesses 1505 are unable to access userspace addresses. This can help prevent 1506 use-after-free bugs becoming an exploitable privilege escalation 1507 by ensuring that magic values (such as LIST_POISON) will always 1508 fault when dereferenced. 1509 1510 CPUs with low-vector mappings use a best-efforts implementation. 1511 Their lower 1MB needs to remain accessible for the vectors, but 1512 the remainder of userspace will become appropriately inaccessible. 1513 1514config HW_PERF_EVENTS 1515 def_bool y 1516 depends on ARM_PMU 1517 1518config SYS_SUPPORTS_HUGETLBFS 1519 def_bool y 1520 depends on ARM_LPAE 1521 1522config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1523 def_bool y 1524 depends on ARM_LPAE 1525 1526config ARCH_WANT_GENERAL_HUGETLB 1527 def_bool y 1528 1529config ARM_MODULE_PLTS 1530 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1531 depends on MODULES 1532 default y 1533 help 1534 Allocate PLTs when loading modules so that jumps and calls whose 1535 targets are too far away for their relative offsets to be encoded 1536 in the instructions themselves can be bounced via veneers in the 1537 module's PLT. This allows modules to be allocated in the generic 1538 vmalloc area after the dedicated module memory area has been 1539 exhausted. The modules will use slightly more memory, but after 1540 rounding up to page size, the actual memory footprint is usually 1541 the same. 1542 1543 Disabling this is usually safe for small single-platform 1544 configurations. If unsure, say y. 1545 1546config FORCE_MAX_ZONEORDER 1547 int "Maximum zone order" 1548 default "12" if SOC_AM33XX 1549 default "9" if SA1111 || ARCH_EFM32 1550 default "11" 1551 help 1552 The kernel memory allocator divides physically contiguous memory 1553 blocks into "zones", where each zone is a power of two number of 1554 pages. This option selects the largest power of two that the kernel 1555 keeps in the memory allocator. If you need to allocate very large 1556 blocks of physically contiguous memory, then you may need to 1557 increase this value. 1558 1559 This config option is actually maximum order plus one. For example, 1560 a value of 11 means that the largest free memory block is 2^10 pages. 1561 1562config ALIGNMENT_TRAP 1563 def_bool CPU_CP15_MMU 1564 select HAVE_PROC_CPU if PROC_FS 1565 help 1566 ARM processors cannot fetch/store information which is not 1567 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1568 address divisible by 4. On 32-bit ARM processors, these non-aligned 1569 fetch/store instructions will be emulated in software if you say 1570 here, which has a severe performance impact. This is necessary for 1571 correct operation of some network protocols. With an IP-only 1572 configuration it is safe to say N, otherwise say Y. 1573 1574config UACCESS_WITH_MEMCPY 1575 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1576 depends on MMU 1577 default y if CPU_FEROCEON 1578 help 1579 Implement faster copy_to_user and clear_user methods for CPU 1580 cores where a 8-word STM instruction give significantly higher 1581 memory write throughput than a sequence of individual 32bit stores. 1582 1583 A possible side effect is a slight increase in scheduling latency 1584 between threads sharing the same address space if they invoke 1585 such copy operations with large buffers. 1586 1587 However, if the CPU data cache is using a write-allocate mode, 1588 this option is unlikely to provide any performance gain. 1589 1590config PARAVIRT 1591 bool "Enable paravirtualization code" 1592 help 1593 This changes the kernel so it can modify itself when it is run 1594 under a hypervisor, potentially improving performance significantly 1595 over full virtualization. 1596 1597config PARAVIRT_TIME_ACCOUNTING 1598 bool "Paravirtual steal time accounting" 1599 select PARAVIRT 1600 help 1601 Select this option to enable fine granularity task steal time 1602 accounting. Time spent executing other tasks in parallel with 1603 the current vCPU is discounted from the vCPU power. To account for 1604 that, there can be a small performance impact. 1605 1606 If in doubt, say N here. 1607 1608config XEN_DOM0 1609 def_bool y 1610 depends on XEN 1611 1612config XEN 1613 bool "Xen guest support on ARM" 1614 depends on ARM && AEABI && OF 1615 depends on CPU_V7 && !CPU_V6 1616 depends on !GENERIC_ATOMIC64 1617 depends on MMU 1618 select ARCH_DMA_ADDR_T_64BIT 1619 select ARM_PSCI 1620 select SWIOTLB 1621 select SWIOTLB_XEN 1622 select PARAVIRT 1623 help 1624 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1625 1626config STACKPROTECTOR_PER_TASK 1627 bool "Use a unique stack canary value for each task" 1628 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1629 select GCC_PLUGIN_ARM_SSP_PER_TASK 1630 default y 1631 help 1632 Due to the fact that GCC uses an ordinary symbol reference from 1633 which to load the value of the stack canary, this value can only 1634 change at reboot time on SMP systems, and all tasks running in the 1635 kernel's address space are forced to use the same canary value for 1636 the entire duration that the system is up. 1637 1638 Enable this option to switch to a different method that uses a 1639 different canary value for each task. 1640 1641endmenu 1642 1643menu "Boot options" 1644 1645config USE_OF 1646 bool "Flattened Device Tree support" 1647 select IRQ_DOMAIN 1648 select OF 1649 help 1650 Include support for flattened device tree machine descriptions. 1651 1652config ATAGS 1653 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1654 default y 1655 help 1656 This is the traditional way of passing data to the kernel at boot 1657 time. If you are solely relying on the flattened device tree (or 1658 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1659 to remove ATAGS support from your kernel binary. If unsure, 1660 leave this to y. 1661 1662config DEPRECATED_PARAM_STRUCT 1663 bool "Provide old way to pass kernel parameters" 1664 depends on ATAGS 1665 help 1666 This was deprecated in 2001 and announced to live on for 5 years. 1667 Some old boot loaders still use this way. 1668 1669# Compressed boot loader in ROM. Yes, we really want to ask about 1670# TEXT and BSS so we preserve their values in the config files. 1671config ZBOOT_ROM_TEXT 1672 hex "Compressed ROM boot loader base address" 1673 default 0x0 1674 help 1675 The physical address at which the ROM-able zImage is to be 1676 placed in the target. Platforms which normally make use of 1677 ROM-able zImage formats normally set this to a suitable 1678 value in their defconfig file. 1679 1680 If ZBOOT_ROM is not enabled, this has no effect. 1681 1682config ZBOOT_ROM_BSS 1683 hex "Compressed ROM boot loader BSS address" 1684 default 0x0 1685 help 1686 The base address of an area of read/write memory in the target 1687 for the ROM-able zImage which must be available while the 1688 decompressor is running. It must be large enough to hold the 1689 entire decompressed kernel plus an additional 128 KiB. 1690 Platforms which normally make use of ROM-able zImage formats 1691 normally set this to a suitable value in their defconfig file. 1692 1693 If ZBOOT_ROM is not enabled, this has no effect. 1694 1695config ZBOOT_ROM 1696 bool "Compressed boot loader in ROM/flash" 1697 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1698 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1699 help 1700 Say Y here if you intend to execute your compressed kernel image 1701 (zImage) directly from ROM or flash. If unsure, say N. 1702 1703config ARM_APPENDED_DTB 1704 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1705 depends on OF 1706 help 1707 With this option, the boot code will look for a device tree binary 1708 (DTB) appended to zImage 1709 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1710 1711 This is meant as a backward compatibility convenience for those 1712 systems with a bootloader that can't be upgraded to accommodate 1713 the documented boot protocol using a device tree. 1714 1715 Beware that there is very little in terms of protection against 1716 this option being confused by leftover garbage in memory that might 1717 look like a DTB header after a reboot if no actual DTB is appended 1718 to zImage. Do not leave this option active in a production kernel 1719 if you don't intend to always append a DTB. Proper passing of the 1720 location into r2 of a bootloader provided DTB is always preferable 1721 to this option. 1722 1723config ARM_ATAG_DTB_COMPAT 1724 bool "Supplement the appended DTB with traditional ATAG information" 1725 depends on ARM_APPENDED_DTB 1726 help 1727 Some old bootloaders can't be updated to a DTB capable one, yet 1728 they provide ATAGs with memory configuration, the ramdisk address, 1729 the kernel cmdline string, etc. Such information is dynamically 1730 provided by the bootloader and can't always be stored in a static 1731 DTB. To allow a device tree enabled kernel to be used with such 1732 bootloaders, this option allows zImage to extract the information 1733 from the ATAG list and store it at run time into the appended DTB. 1734 1735choice 1736 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1737 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1738 1739config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1740 bool "Use bootloader kernel arguments if available" 1741 help 1742 Uses the command-line options passed by the boot loader instead of 1743 the device tree bootargs property. If the boot loader doesn't provide 1744 any, the device tree bootargs property will be used. 1745 1746config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1747 bool "Extend with bootloader kernel arguments" 1748 help 1749 The command-line arguments provided by the boot loader will be 1750 appended to the the device tree bootargs property. 1751 1752endchoice 1753 1754config CMDLINE 1755 string "Default kernel command string" 1756 default "" 1757 help 1758 On some architectures (e.g. CATS), there is currently no way 1759 for the boot loader to pass arguments to the kernel. For these 1760 architectures, you should supply some command-line options at build 1761 time by entering them here. As a minimum, you should specify the 1762 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1763 1764choice 1765 prompt "Kernel command line type" if CMDLINE != "" 1766 default CMDLINE_FROM_BOOTLOADER 1767 depends on ATAGS 1768 1769config CMDLINE_FROM_BOOTLOADER 1770 bool "Use bootloader kernel arguments if available" 1771 help 1772 Uses the command-line options passed by the boot loader. If 1773 the boot loader doesn't provide any, the default kernel command 1774 string provided in CMDLINE will be used. 1775 1776config CMDLINE_EXTEND 1777 bool "Extend bootloader kernel arguments" 1778 help 1779 The command-line arguments provided by the boot loader will be 1780 appended to the default kernel command string. 1781 1782config CMDLINE_FORCE 1783 bool "Always use the default kernel command string" 1784 help 1785 Always use the default kernel command string, even if the boot 1786 loader passes other arguments to the kernel. 1787 This is useful if you cannot or don't want to change the 1788 command-line options your boot loader passes to the kernel. 1789endchoice 1790 1791config XIP_KERNEL 1792 bool "Kernel Execute-In-Place from ROM" 1793 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1794 help 1795 Execute-In-Place allows the kernel to run from non-volatile storage 1796 directly addressable by the CPU, such as NOR flash. This saves RAM 1797 space since the text section of the kernel is not loaded from flash 1798 to RAM. Read-write sections, such as the data section and stack, 1799 are still copied to RAM. The XIP kernel is not compressed since 1800 it has to run directly from flash, so it will take more space to 1801 store it. The flash address used to link the kernel object files, 1802 and for storing it, is configuration dependent. Therefore, if you 1803 say Y here, you must know the proper physical address where to 1804 store the kernel image depending on your own flash memory usage. 1805 1806 Also note that the make target becomes "make xipImage" rather than 1807 "make zImage" or "make Image". The final kernel binary to put in 1808 ROM memory will be arch/arm/boot/xipImage. 1809 1810 If unsure, say N. 1811 1812config XIP_PHYS_ADDR 1813 hex "XIP Kernel Physical Location" 1814 depends on XIP_KERNEL 1815 default "0x00080000" 1816 help 1817 This is the physical address in your flash memory the kernel will 1818 be linked for and stored to. This address is dependent on your 1819 own flash usage. 1820 1821config XIP_DEFLATED_DATA 1822 bool "Store kernel .data section compressed in ROM" 1823 depends on XIP_KERNEL 1824 select ZLIB_INFLATE 1825 help 1826 Before the kernel is actually executed, its .data section has to be 1827 copied to RAM from ROM. This option allows for storing that data 1828 in compressed form and decompressed to RAM rather than merely being 1829 copied, saving some precious ROM space. A possible drawback is a 1830 slightly longer boot delay. 1831 1832config KEXEC 1833 bool "Kexec system call (EXPERIMENTAL)" 1834 depends on (!SMP || PM_SLEEP_SMP) 1835 depends on MMU 1836 select KEXEC_CORE 1837 help 1838 kexec is a system call that implements the ability to shutdown your 1839 current kernel, and to start another kernel. It is like a reboot 1840 but it is independent of the system firmware. And like a reboot 1841 you can start any kernel with it, not just Linux. 1842 1843 It is an ongoing process to be certain the hardware in a machine 1844 is properly shutdown, so do not be surprised if this code does not 1845 initially work for you. 1846 1847config ATAGS_PROC 1848 bool "Export atags in procfs" 1849 depends on ATAGS && KEXEC 1850 default y 1851 help 1852 Should the atags used to boot the kernel be exported in an "atags" 1853 file in procfs. Useful with kexec. 1854 1855config CRASH_DUMP 1856 bool "Build kdump crash kernel (EXPERIMENTAL)" 1857 help 1858 Generate crash dump after being started by kexec. This should 1859 be normally only set in special crash dump kernels which are 1860 loaded in the main kernel with kexec-tools into a specially 1861 reserved region and then later executed after a crash by 1862 kdump/kexec. The crash dump kernel must be compiled to a 1863 memory address not used by the main kernel 1864 1865 For more details see Documentation/admin-guide/kdump/kdump.rst 1866 1867config AUTO_ZRELADDR 1868 bool "Auto calculation of the decompressed kernel image address" 1869 help 1870 ZRELADDR is the physical address where the decompressed kernel 1871 image will be placed. If AUTO_ZRELADDR is selected, the address 1872 will be determined at run-time by masking the current IP with 1873 0xf8000000. This assumes the zImage being placed in the first 128MB 1874 from start of memory. 1875 1876config EFI_STUB 1877 bool 1878 1879config EFI 1880 bool "UEFI runtime support" 1881 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1882 select UCS2_STRING 1883 select EFI_PARAMS_FROM_FDT 1884 select EFI_STUB 1885 select EFI_GENERIC_STUB 1886 select EFI_RUNTIME_WRAPPERS 1887 help 1888 This option provides support for runtime services provided 1889 by UEFI firmware (such as non-volatile variables, realtime 1890 clock, and platform reset). A UEFI stub is also provided to 1891 allow the kernel to be booted as an EFI application. This 1892 is only useful for kernels that may run on systems that have 1893 UEFI firmware. 1894 1895config DMI 1896 bool "Enable support for SMBIOS (DMI) tables" 1897 depends on EFI 1898 default y 1899 help 1900 This enables SMBIOS/DMI feature for systems. 1901 1902 This option is only useful on systems that have UEFI firmware. 1903 However, even with this option, the resultant kernel should 1904 continue to boot on existing non-UEFI platforms. 1905 1906 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1907 i.e., the the practice of identifying the platform via DMI to 1908 decide whether certain workarounds for buggy hardware and/or 1909 firmware need to be enabled. This would require the DMI subsystem 1910 to be enabled much earlier than we do on ARM, which is non-trivial. 1911 1912endmenu 1913 1914menu "CPU Power Management" 1915 1916source "drivers/cpufreq/Kconfig" 1917 1918source "drivers/cpuidle/Kconfig" 1919 1920endmenu 1921 1922menu "Floating point emulation" 1923 1924comment "At least one emulation must be selected" 1925 1926config FPE_NWFPE 1927 bool "NWFPE math emulation" 1928 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1929 help 1930 Say Y to include the NWFPE floating point emulator in the kernel. 1931 This is necessary to run most binaries. Linux does not currently 1932 support floating point hardware so you need to say Y here even if 1933 your machine has an FPA or floating point co-processor podule. 1934 1935 You may say N here if you are going to load the Acorn FPEmulator 1936 early in the bootup. 1937 1938config FPE_NWFPE_XP 1939 bool "Support extended precision" 1940 depends on FPE_NWFPE 1941 help 1942 Say Y to include 80-bit support in the kernel floating-point 1943 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1944 Note that gcc does not generate 80-bit operations by default, 1945 so in most cases this option only enlarges the size of the 1946 floating point emulator without any good reason. 1947 1948 You almost surely want to say N here. 1949 1950config FPE_FASTFPE 1951 bool "FastFPE math emulation (EXPERIMENTAL)" 1952 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1953 help 1954 Say Y here to include the FAST floating point emulator in the kernel. 1955 This is an experimental much faster emulator which now also has full 1956 precision for the mantissa. It does not support any exceptions. 1957 It is very simple, and approximately 3-6 times faster than NWFPE. 1958 1959 It should be sufficient for most programs. It may be not suitable 1960 for scientific calculations, but you have to check this for yourself. 1961 If you do not feel you need a faster FP emulation you should better 1962 choose NWFPE. 1963 1964config VFP 1965 bool "VFP-format floating point maths" 1966 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1967 help 1968 Say Y to include VFP support code in the kernel. This is needed 1969 if your hardware includes a VFP unit. 1970 1971 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1972 release notes and additional status information. 1973 1974 Say N if your target does not have VFP hardware. 1975 1976config VFPv3 1977 bool 1978 depends on VFP 1979 default y if CPU_V7 1980 1981config NEON 1982 bool "Advanced SIMD (NEON) Extension support" 1983 depends on VFPv3 && CPU_V7 1984 help 1985 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1986 Extension. 1987 1988config KERNEL_MODE_NEON 1989 bool "Support for NEON in kernel mode" 1990 depends on NEON && AEABI 1991 help 1992 Say Y to include support for NEON in kernel mode. 1993 1994endmenu 1995 1996menu "Power management options" 1997 1998source "kernel/power/Kconfig" 1999 2000config ARCH_SUSPEND_POSSIBLE 2001 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2002 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2003 def_bool y 2004 2005config ARM_CPU_SUSPEND 2006 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2007 depends on ARCH_SUSPEND_POSSIBLE 2008 2009config ARCH_HIBERNATION_POSSIBLE 2010 bool 2011 depends on MMU 2012 default y if ARCH_SUSPEND_POSSIBLE 2013 2014endmenu 2015 2016source "drivers/firmware/Kconfig" 2017 2018if CRYPTO 2019source "arch/arm/crypto/Kconfig" 2020endif 2021 2022source "arch/arm/Kconfig.assembler" 2023