1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_CACHE_ALIASING 9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 10 select ARCH_HAS_CURRENT_STACK_POINTER 11 select ARCH_HAS_DEBUG_VIRTUAL if MMU 12 select ARCH_HAS_DMA_ALLOC if MMU 13 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 14 select ARCH_HAS_ELF_RANDOMIZE 15 select ARCH_HAS_FORTIFY_SOURCE 16 select ARCH_HAS_KEEPINITRD 17 select ARCH_HAS_KCOV 18 select ARCH_HAS_MEMBARRIER_SYNC_CORE 19 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 20 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 21 select ARCH_HAS_SETUP_DMA_OPS 22 select ARCH_HAS_SET_MEMORY 23 select ARCH_STACKWALK 24 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 25 select ARCH_HAS_STRICT_MODULE_RWX if MMU 26 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 27 select ARCH_HAS_SYNC_DMA_FOR_CPU 28 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 29 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 30 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 31 select ARCH_HAS_GCOV_PROFILE_ALL 32 select ARCH_KEEP_MEMBLOCK 33 select ARCH_HAS_UBSAN 34 select ARCH_MIGHT_HAVE_PC_PARPORT 35 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 36 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 37 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 38 select ARCH_SUPPORTS_ATOMIC_RMW 39 select ARCH_SUPPORTS_CFI_CLANG 40 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 41 select ARCH_SUPPORTS_PER_VMA_LOCK 42 select ARCH_USE_BUILTIN_BSWAP 43 select ARCH_USE_CMPXCHG_LOCKREF 44 select ARCH_USE_MEMTEST 45 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 46 select ARCH_WANT_GENERAL_HUGETLB 47 select ARCH_WANT_IPC_PARSE_VERSION 48 select ARCH_WANT_LD_ORPHAN_WARN 49 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 50 select BUILDTIME_TABLE_SORT if MMU 51 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 52 select CLONE_BACKWARDS 53 select CPU_PM if SUSPEND || CPU_IDLE 54 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 55 select DMA_DECLARE_COHERENT 56 select DMA_GLOBAL_POOL if !MMU 57 select DMA_OPS 58 select DMA_NONCOHERENT_MMAP if MMU 59 select EDAC_SUPPORT 60 select EDAC_ATOMIC_SCRUB 61 select GENERIC_ALLOCATOR 62 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 63 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 64 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 65 select GENERIC_IRQ_IPI if SMP 66 select GENERIC_CPU_AUTOPROBE 67 select GENERIC_EARLY_IOREMAP 68 select GENERIC_IDLE_POLL_SETUP 69 select GENERIC_IRQ_MULTI_HANDLER 70 select GENERIC_IRQ_PROBE 71 select GENERIC_IRQ_SHOW 72 select GENERIC_IRQ_SHOW_LEVEL 73 select GENERIC_LIB_DEVMEM_IS_ALLOWED 74 select GENERIC_PCI_IOMAP 75 select GENERIC_SCHED_CLOCK 76 select GENERIC_SMP_IDLE_THREAD 77 select HARDIRQS_SW_RESEND 78 select HAS_IOPORT 79 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 80 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 81 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 83 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 84 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 85 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 86 select HAVE_ARCH_MMAP_RND_BITS if MMU 87 select HAVE_ARCH_PFN_VALID 88 select HAVE_ARCH_SECCOMP 89 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 90 select HAVE_ARCH_STACKLEAK 91 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 92 select HAVE_ARCH_TRACEHOOK 93 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 94 select HAVE_ARM_SMCCC if CPU_V7 95 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 96 select HAVE_CONTEXT_TRACKING_USER 97 select HAVE_C_RECORDMCOUNT 98 select HAVE_BUILDTIME_MCOUNT_SORT 99 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 100 select HAVE_DMA_CONTIGUOUS if MMU 101 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 102 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 103 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 104 select HAVE_EXIT_THREAD 105 select HAVE_GUP_FAST if ARM_LPAE 106 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 107 select HAVE_FUNCTION_ERROR_INJECTION 108 select HAVE_FUNCTION_GRAPH_TRACER 109 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 110 select HAVE_GCC_PLUGINS 111 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 112 select HAVE_IRQ_TIME_ACCOUNTING 113 select HAVE_KERNEL_GZIP 114 select HAVE_KERNEL_LZ4 115 select HAVE_KERNEL_LZMA 116 select HAVE_KERNEL_LZO 117 select HAVE_KERNEL_XZ 118 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 119 select HAVE_KRETPROBES if HAVE_KPROBES 120 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) 121 select HAVE_MOD_ARCH_SPECIFIC 122 select HAVE_NMI 123 select HAVE_OPTPROBES if !THUMB2_KERNEL 124 select HAVE_PAGE_SIZE_4KB 125 select HAVE_PCI if MMU 126 select HAVE_PERF_EVENTS 127 select HAVE_PERF_REGS 128 select HAVE_PERF_USER_STACK_DUMP 129 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 130 select HAVE_REGS_AND_STACK_ACCESS_API 131 select HAVE_RSEQ 132 select HAVE_STACKPROTECTOR 133 select HAVE_SYSCALL_TRACEPOINTS 134 select HAVE_UID16 135 select HAVE_VIRT_CPU_ACCOUNTING_GEN 136 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 137 select IRQ_FORCED_THREADING 138 select LOCK_MM_AND_FIND_VMA 139 select MODULES_USE_ELF_REL 140 select NEED_DMA_MAP_STATE 141 select OF_EARLY_FLATTREE if OF 142 select OLD_SIGACTION 143 select OLD_SIGSUSPEND3 144 select PCI_DOMAINS_GENERIC if PCI 145 select PCI_SYSCALL if PCI 146 select PERF_USE_VMALLOC 147 select RTC_LIB 148 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 149 select SYS_SUPPORTS_APM_EMULATION 150 select THREAD_INFO_IN_TASK 151 select TIMER_OF if OF 152 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 153 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 154 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 155 # Above selects are sorted alphabetically; please add new ones 156 # according to that. Thanks. 157 help 158 The ARM series is a line of low-power-consumption RISC chip designs 159 licensed by ARM Ltd and targeted at embedded applications and 160 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 161 manufactured, but legacy ARM-based PC hardware remains popular in 162 Europe. There is an ARM Linux project with a web page at 163 <http://www.arm.linux.org.uk/>. 164 165config ARM_HAS_GROUP_RELOCS 166 def_bool y 167 depends on !LD_IS_LLD || LLD_VERSION >= 140000 168 depends on !COMPILE_TEST 169 help 170 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 171 relocations, which have been around for a long time, but were not 172 supported in LLD until version 14. The combined range is -/+ 256 MiB, 173 which is usually sufficient, but not for allyesconfig, so we disable 174 this feature when doing compile testing. 175 176config ARM_DMA_USE_IOMMU 177 bool 178 select NEED_SG_DMA_LENGTH 179 180if ARM_DMA_USE_IOMMU 181 182config ARM_DMA_IOMMU_ALIGNMENT 183 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 184 range 4 9 185 default 8 186 help 187 DMA mapping framework by default aligns all buffers to the smallest 188 PAGE_SIZE order which is greater than or equal to the requested buffer 189 size. This works well for buffers up to a few hundreds kilobytes, but 190 for larger buffers it just a waste of address space. Drivers which has 191 relatively small addressing window (like 64Mib) might run out of 192 virtual space with just a few allocations. 193 194 With this parameter you can specify the maximum PAGE_SIZE order for 195 DMA IOMMU buffers. Larger buffers will be aligned only to this 196 specified order. The order is expressed as a power of two multiplied 197 by the PAGE_SIZE. 198 199endif 200 201config SYS_SUPPORTS_APM_EMULATION 202 bool 203 204config HAVE_TCM 205 bool 206 select GENERIC_ALLOCATOR 207 208config HAVE_PROC_CPU 209 bool 210 211config NO_IOPORT_MAP 212 bool 213 214config SBUS 215 bool 216 217config STACKTRACE_SUPPORT 218 bool 219 default y 220 221config LOCKDEP_SUPPORT 222 bool 223 default y 224 225config ARCH_HAS_ILOG2_U32 226 bool 227 228config ARCH_HAS_ILOG2_U64 229 bool 230 231config ARCH_HAS_BANDGAP 232 bool 233 234config FIX_EARLYCON_MEM 235 def_bool y if MMU 236 237config GENERIC_HWEIGHT 238 bool 239 default y 240 241config GENERIC_CALIBRATE_DELAY 242 bool 243 default y 244 245config ARCH_MAY_HAVE_PC_FDC 246 bool 247 248config ARCH_SUPPORTS_UPROBES 249 def_bool y 250 251config GENERIC_ISA_DMA 252 bool 253 254config FIQ 255 bool 256 257config ARCH_MTD_XIP 258 bool 259 260config ARM_PATCH_PHYS_VIRT 261 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 262 default y 263 depends on MMU 264 help 265 Patch phys-to-virt and virt-to-phys translation functions at 266 boot and module load time according to the position of the 267 kernel in system memory. 268 269 This can only be used with non-XIP MMU kernels where the base 270 of physical memory is at a 2 MiB boundary. 271 272 Only disable this option if you know that you do not require 273 this feature (eg, building a kernel for a single machine) and 274 you need to shrink the kernel to the minimal size. 275 276config NEED_MACH_IO_H 277 bool 278 help 279 Select this when mach/io.h is required to provide special 280 definitions for this platform. The need for mach/io.h should 281 be avoided when possible. 282 283config NEED_MACH_MEMORY_H 284 bool 285 help 286 Select this when mach/memory.h is required to provide special 287 definitions for this platform. The need for mach/memory.h should 288 be avoided when possible. 289 290config PHYS_OFFSET 291 hex "Physical address of main memory" if MMU 292 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 293 default DRAM_BASE if !MMU 294 default 0x00000000 if ARCH_FOOTBRIDGE 295 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 296 default 0xa0000000 if ARCH_PXA 297 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 298 default 0 299 help 300 Please provide the physical address corresponding to the 301 location of main memory in your system. 302 303config GENERIC_BUG 304 def_bool y 305 depends on BUG 306 307config PGTABLE_LEVELS 308 int 309 default 3 if ARM_LPAE 310 default 2 311 312menu "System Type" 313 314config MMU 315 bool "MMU-based Paged Memory Management Support" 316 default y 317 help 318 Select if you want MMU-based virtualised addressing space 319 support by paged memory management. If unsure, say 'Y'. 320 321config ARM_SINGLE_ARMV7M 322 def_bool !MMU 323 select ARM_NVIC 324 select CPU_V7M 325 select NO_IOPORT_MAP 326 327config ARCH_MMAP_RND_BITS_MIN 328 default 8 329 330config ARCH_MMAP_RND_BITS_MAX 331 default 14 if PAGE_OFFSET=0x40000000 332 default 15 if PAGE_OFFSET=0x80000000 333 default 16 334 335config ARCH_MULTIPLATFORM 336 bool "Require kernel to be portable to multiple machines" if EXPERT 337 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 338 default y 339 help 340 In general, all Arm machines can be supported in a single 341 kernel image, covering either Armv4/v5 or Armv6/v7. 342 343 However, some configuration options require hardcoding machine 344 specific physical addresses or enable errata workarounds that may 345 break other machines. 346 347 Selecting N here allows using those options, including 348 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 349 350source "arch/arm/Kconfig.platforms" 351 352# 353# This is sorted alphabetically by mach-* pathname. However, plat-* 354# Kconfigs may be included either alphabetically (according to the 355# plat- suffix) or along side the corresponding mach-* source. 356# 357source "arch/arm/mach-actions/Kconfig" 358 359source "arch/arm/mach-alpine/Kconfig" 360 361source "arch/arm/mach-artpec/Kconfig" 362 363source "arch/arm/mach-aspeed/Kconfig" 364 365source "arch/arm/mach-at91/Kconfig" 366 367source "arch/arm/mach-axxia/Kconfig" 368 369source "arch/arm/mach-bcm/Kconfig" 370 371source "arch/arm/mach-berlin/Kconfig" 372 373source "arch/arm/mach-clps711x/Kconfig" 374 375source "arch/arm/mach-davinci/Kconfig" 376 377source "arch/arm/mach-digicolor/Kconfig" 378 379source "arch/arm/mach-dove/Kconfig" 380 381source "arch/arm/mach-ep93xx/Kconfig" 382 383source "arch/arm/mach-exynos/Kconfig" 384 385source "arch/arm/mach-footbridge/Kconfig" 386 387source "arch/arm/mach-gemini/Kconfig" 388 389source "arch/arm/mach-highbank/Kconfig" 390 391source "arch/arm/mach-hisi/Kconfig" 392 393source "arch/arm/mach-hpe/Kconfig" 394 395source "arch/arm/mach-imx/Kconfig" 396 397source "arch/arm/mach-ixp4xx/Kconfig" 398 399source "arch/arm/mach-keystone/Kconfig" 400 401source "arch/arm/mach-lpc32xx/Kconfig" 402 403source "arch/arm/mach-mediatek/Kconfig" 404 405source "arch/arm/mach-meson/Kconfig" 406 407source "arch/arm/mach-milbeaut/Kconfig" 408 409source "arch/arm/mach-mmp/Kconfig" 410 411source "arch/arm/mach-mstar/Kconfig" 412 413source "arch/arm/mach-mv78xx0/Kconfig" 414 415source "arch/arm/mach-mvebu/Kconfig" 416 417source "arch/arm/mach-mxs/Kconfig" 418 419source "arch/arm/mach-nomadik/Kconfig" 420 421source "arch/arm/mach-npcm/Kconfig" 422 423source "arch/arm/mach-omap1/Kconfig" 424 425source "arch/arm/mach-omap2/Kconfig" 426 427source "arch/arm/mach-orion5x/Kconfig" 428 429source "arch/arm/mach-pxa/Kconfig" 430 431source "arch/arm/mach-qcom/Kconfig" 432 433source "arch/arm/mach-realtek/Kconfig" 434 435source "arch/arm/mach-rpc/Kconfig" 436 437source "arch/arm/mach-rockchip/Kconfig" 438 439source "arch/arm/mach-s3c/Kconfig" 440 441source "arch/arm/mach-s5pv210/Kconfig" 442 443source "arch/arm/mach-sa1100/Kconfig" 444 445source "arch/arm/mach-shmobile/Kconfig" 446 447source "arch/arm/mach-socfpga/Kconfig" 448 449source "arch/arm/mach-spear/Kconfig" 450 451source "arch/arm/mach-sti/Kconfig" 452 453source "arch/arm/mach-stm32/Kconfig" 454 455source "arch/arm/mach-sunxi/Kconfig" 456 457source "arch/arm/mach-tegra/Kconfig" 458 459source "arch/arm/mach-ux500/Kconfig" 460 461source "arch/arm/mach-versatile/Kconfig" 462 463source "arch/arm/mach-vt8500/Kconfig" 464 465source "arch/arm/mach-zynq/Kconfig" 466 467# ARMv7-M architecture 468config ARCH_LPC18XX 469 bool "NXP LPC18xx/LPC43xx" 470 depends on ARM_SINGLE_ARMV7M 471 select ARCH_HAS_RESET_CONTROLLER 472 select ARM_AMBA 473 select CLKSRC_LPC32XX 474 select PINCTRL 475 help 476 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 477 high performance microcontrollers. 478 479config ARCH_MPS2 480 bool "ARM MPS2 platform" 481 depends on ARM_SINGLE_ARMV7M 482 select ARM_AMBA 483 select CLKSRC_MPS2 484 help 485 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 486 with a range of available cores like Cortex-M3/M4/M7. 487 488 Please, note that depends which Application Note is used memory map 489 for the platform may vary, so adjustment of RAM base might be needed. 490 491# Definitions to make life easier 492config ARCH_ACORN 493 bool 494 495config PLAT_ORION 496 bool 497 select CLKSRC_MMIO 498 select GENERIC_IRQ_CHIP 499 select IRQ_DOMAIN 500 501config PLAT_ORION_LEGACY 502 bool 503 select PLAT_ORION 504 505config PLAT_VERSATILE 506 bool 507 508source "arch/arm/mm/Kconfig" 509 510config IWMMXT 511 bool "Enable iWMMXt support" 512 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 513 default y if PXA27x || PXA3xx || ARCH_MMP 514 help 515 Enable support for iWMMXt context switching at run time if 516 running on a CPU that supports it. 517 518if !MMU 519source "arch/arm/Kconfig-nommu" 520endif 521 522config PJ4B_ERRATA_4742 523 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 524 depends on CPU_PJ4B && MACH_ARMADA_370 525 default y 526 help 527 When coming out of either a Wait for Interrupt (WFI) or a Wait for 528 Event (WFE) IDLE states, a specific timing sensitivity exists between 529 the retiring WFI/WFE instructions and the newly issued subsequent 530 instructions. This sensitivity can result in a CPU hang scenario. 531 Workaround: 532 The software must insert either a Data Synchronization Barrier (DSB) 533 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 534 instruction 535 536config ARM_ERRATA_326103 537 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 538 depends on CPU_V6 539 help 540 Executing a SWP instruction to read-only memory does not set bit 11 541 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 542 treat the access as a read, preventing a COW from occurring and 543 causing the faulting task to livelock. 544 545config ARM_ERRATA_411920 546 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 547 depends on CPU_V6 || CPU_V6K 548 help 549 Invalidation of the Instruction Cache operation can 550 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 551 It does not affect the MPCore. This option enables the ARM Ltd. 552 recommended workaround. 553 554config ARM_ERRATA_430973 555 bool "ARM errata: Stale prediction on replaced interworking branch" 556 depends on CPU_V7 557 help 558 This option enables the workaround for the 430973 Cortex-A8 559 r1p* erratum. If a code sequence containing an ARM/Thumb 560 interworking branch is replaced with another code sequence at the 561 same virtual address, whether due to self-modifying code or virtual 562 to physical address re-mapping, Cortex-A8 does not recover from the 563 stale interworking branch prediction. This results in Cortex-A8 564 executing the new code sequence in the incorrect ARM or Thumb state. 565 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 566 and also flushes the branch target cache at every context switch. 567 Note that setting specific bits in the ACTLR register may not be 568 available in non-secure mode. 569 570config ARM_ERRATA_458693 571 bool "ARM errata: Processor deadlock when a false hazard is created" 572 depends on CPU_V7 573 depends on !ARCH_MULTIPLATFORM 574 help 575 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 576 erratum. For very specific sequences of memory operations, it is 577 possible for a hazard condition intended for a cache line to instead 578 be incorrectly associated with a different cache line. This false 579 hazard might then cause a processor deadlock. The workaround enables 580 the L1 caching of the NEON accesses and disables the PLD instruction 581 in the ACTLR register. Note that setting specific bits in the ACTLR 582 register may not be available in non-secure mode and thus is not 583 available on a multiplatform kernel. This should be applied by the 584 bootloader instead. 585 586config ARM_ERRATA_460075 587 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 588 depends on CPU_V7 589 depends on !ARCH_MULTIPLATFORM 590 help 591 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 592 erratum. Any asynchronous access to the L2 cache may encounter a 593 situation in which recent store transactions to the L2 cache are lost 594 and overwritten with stale memory contents from external memory. The 595 workaround disables the write-allocate mode for the L2 cache via the 596 ACTLR register. Note that setting specific bits in the ACTLR register 597 may not be available in non-secure mode and thus is not available on 598 a multiplatform kernel. This should be applied by the bootloader 599 instead. 600 601config ARM_ERRATA_742230 602 bool "ARM errata: DMB operation may be faulty" 603 depends on CPU_V7 && SMP 604 depends on !ARCH_MULTIPLATFORM 605 help 606 This option enables the workaround for the 742230 Cortex-A9 607 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 608 between two write operations may not ensure the correct visibility 609 ordering of the two writes. This workaround sets a specific bit in 610 the diagnostic register of the Cortex-A9 which causes the DMB 611 instruction to behave as a DSB, ensuring the correct behaviour of 612 the two writes. Note that setting specific bits in the diagnostics 613 register may not be available in non-secure mode and thus is not 614 available on a multiplatform kernel. This should be applied by the 615 bootloader instead. 616 617config ARM_ERRATA_742231 618 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 619 depends on CPU_V7 && SMP 620 depends on !ARCH_MULTIPLATFORM 621 help 622 This option enables the workaround for the 742231 Cortex-A9 623 (r2p0..r2p2) erratum. Under certain conditions, specific to the 624 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 625 accessing some data located in the same cache line, may get corrupted 626 data due to bad handling of the address hazard when the line gets 627 replaced from one of the CPUs at the same time as another CPU is 628 accessing it. This workaround sets specific bits in the diagnostic 629 register of the Cortex-A9 which reduces the linefill issuing 630 capabilities of the processor. Note that setting specific bits in the 631 diagnostics register may not be available in non-secure mode and thus 632 is not available on a multiplatform kernel. This should be applied by 633 the bootloader instead. 634 635config ARM_ERRATA_643719 636 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 637 depends on CPU_V7 && SMP 638 default y 639 help 640 This option enables the workaround for the 643719 Cortex-A9 (prior to 641 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 642 register returns zero when it should return one. The workaround 643 corrects this value, ensuring cache maintenance operations which use 644 it behave as intended and avoiding data corruption. 645 646config ARM_ERRATA_720789 647 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 648 depends on CPU_V7 649 help 650 This option enables the workaround for the 720789 Cortex-A9 (prior to 651 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 652 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 653 As a consequence of this erratum, some TLB entries which should be 654 invalidated are not, resulting in an incoherency in the system page 655 tables. The workaround changes the TLB flushing routines to invalidate 656 entries regardless of the ASID. 657 658config ARM_ERRATA_743622 659 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 660 depends on CPU_V7 661 depends on !ARCH_MULTIPLATFORM 662 help 663 This option enables the workaround for the 743622 Cortex-A9 664 (r2p*) erratum. Under very rare conditions, a faulty 665 optimisation in the Cortex-A9 Store Buffer may lead to data 666 corruption. This workaround sets a specific bit in the diagnostic 667 register of the Cortex-A9 which disables the Store Buffer 668 optimisation, preventing the defect from occurring. This has no 669 visible impact on the overall performance or power consumption of the 670 processor. Note that setting specific bits in the diagnostics register 671 may not be available in non-secure mode and thus is not available on a 672 multiplatform kernel. This should be applied by the bootloader instead. 673 674config ARM_ERRATA_751472 675 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 676 depends on CPU_V7 677 depends on !ARCH_MULTIPLATFORM 678 help 679 This option enables the workaround for the 751472 Cortex-A9 (prior 680 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 681 completion of a following broadcasted operation if the second 682 operation is received by a CPU before the ICIALLUIS has completed, 683 potentially leading to corrupted entries in the cache or TLB. 684 Note that setting specific bits in the diagnostics register may 685 not be available in non-secure mode and thus is not available on 686 a multiplatform kernel. This should be applied by the bootloader 687 instead. 688 689config ARM_ERRATA_754322 690 bool "ARM errata: possible faulty MMU translations following an ASID switch" 691 depends on CPU_V7 692 help 693 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 694 r3p*) erratum. A speculative memory access may cause a page table walk 695 which starts prior to an ASID switch but completes afterwards. This 696 can populate the micro-TLB with a stale entry which may be hit with 697 the new ASID. This workaround places two dsb instructions in the mm 698 switching code so that no page table walks can cross the ASID switch. 699 700config ARM_ERRATA_754327 701 bool "ARM errata: no automatic Store Buffer drain" 702 depends on CPU_V7 && SMP 703 help 704 This option enables the workaround for the 754327 Cortex-A9 (prior to 705 r2p0) erratum. The Store Buffer does not have any automatic draining 706 mechanism and therefore a livelock may occur if an external agent 707 continuously polls a memory location waiting to observe an update. 708 This workaround defines cpu_relax() as smp_mb(), preventing correctly 709 written polling loops from denying visibility of updates to memory. 710 711config ARM_ERRATA_364296 712 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 713 depends on CPU_V6 714 help 715 This options enables the workaround for the 364296 ARM1136 716 r0p2 erratum (possible cache data corruption with 717 hit-under-miss enabled). It sets the undocumented bit 31 in 718 the auxiliary control register and the FI bit in the control 719 register, thus disabling hit-under-miss without putting the 720 processor into full low interrupt latency mode. ARM11MPCore 721 is not affected. 722 723config ARM_ERRATA_764369 724 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 725 depends on CPU_V7 && SMP 726 help 727 This option enables the workaround for erratum 764369 728 affecting Cortex-A9 MPCore with two or more processors (all 729 current revisions). Under certain timing circumstances, a data 730 cache line maintenance operation by MVA targeting an Inner 731 Shareable memory region may fail to proceed up to either the 732 Point of Coherency or to the Point of Unification of the 733 system. This workaround adds a DSB instruction before the 734 relevant cache maintenance functions and sets a specific bit 735 in the diagnostic control register of the SCU. 736 737config ARM_ERRATA_764319 738 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 739 depends on CPU_V7 740 help 741 This option enables the workaround for the 764319 Cortex-A9 erratum. 742 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 743 unexpected Undefined Instruction exception when the DBGSWENABLE 744 external pin is set to 0, even when the CP14 accesses are performed 745 from a privileged mode. This work around catches the exception in a 746 way the kernel does not stop execution. 747 748config ARM_ERRATA_775420 749 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 750 depends on CPU_V7 751 help 752 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 753 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 754 operation aborts with MMU exception, it might cause the processor 755 to deadlock. This workaround puts DSB before executing ISB if 756 an abort may occur on cache maintenance. 757 758config ARM_ERRATA_798181 759 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 760 depends on CPU_V7 && SMP 761 help 762 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 763 adequately shooting down all use of the old entries. This 764 option enables the Linux kernel workaround for this erratum 765 which sends an IPI to the CPUs that are running the same ASID 766 as the one being invalidated. 767 768config ARM_ERRATA_773022 769 bool "ARM errata: incorrect instructions may be executed from loop buffer" 770 depends on CPU_V7 771 help 772 This option enables the workaround for the 773022 Cortex-A15 773 (up to r0p4) erratum. In certain rare sequences of code, the 774 loop buffer may deliver incorrect instructions. This 775 workaround disables the loop buffer to avoid the erratum. 776 777config ARM_ERRATA_818325_852422 778 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 779 depends on CPU_V7 780 help 781 This option enables the workaround for: 782 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 783 instruction might deadlock. Fixed in r0p1. 784 - Cortex-A12 852422: Execution of a sequence of instructions might 785 lead to either a data corruption or a CPU deadlock. Not fixed in 786 any Cortex-A12 cores yet. 787 This workaround for all both errata involves setting bit[12] of the 788 Feature Register. This bit disables an optimisation applied to a 789 sequence of 2 instructions that use opposing condition codes. 790 791config ARM_ERRATA_821420 792 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 793 depends on CPU_V7 794 help 795 This option enables the workaround for the 821420 Cortex-A12 796 (all revs) erratum. In very rare timing conditions, a sequence 797 of VMOV to Core registers instructions, for which the second 798 one is in the shadow of a branch or abort, can lead to a 799 deadlock when the VMOV instructions are issued out-of-order. 800 801config ARM_ERRATA_825619 802 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 803 depends on CPU_V7 804 help 805 This option enables the workaround for the 825619 Cortex-A12 806 (all revs) erratum. Within rare timing constraints, executing a 807 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 808 and Device/Strongly-Ordered loads and stores might cause deadlock 809 810config ARM_ERRATA_857271 811 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 812 depends on CPU_V7 813 help 814 This option enables the workaround for the 857271 Cortex-A12 815 (all revs) erratum. Under very rare timing conditions, the CPU might 816 hang. The workaround is expected to have a < 1% performance impact. 817 818config ARM_ERRATA_852421 819 bool "ARM errata: A17: DMB ST might fail to create order between stores" 820 depends on CPU_V7 821 help 822 This option enables the workaround for the 852421 Cortex-A17 823 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 824 execution of a DMB ST instruction might fail to properly order 825 stores from GroupA and stores from GroupB. 826 827config ARM_ERRATA_852423 828 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 829 depends on CPU_V7 830 help 831 This option enables the workaround for: 832 - Cortex-A17 852423: Execution of a sequence of instructions might 833 lead to either a data corruption or a CPU deadlock. Not fixed in 834 any Cortex-A17 cores yet. 835 This is identical to Cortex-A12 erratum 852422. It is a separate 836 config option from the A12 erratum due to the way errata are checked 837 for and handled. 838 839config ARM_ERRATA_857272 840 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 841 depends on CPU_V7 842 help 843 This option enables the workaround for the 857272 Cortex-A17 erratum. 844 This erratum is not known to be fixed in any A17 revision. 845 This is identical to Cortex-A12 erratum 857271. It is a separate 846 config option from the A12 erratum due to the way errata are checked 847 for and handled. 848 849endmenu 850 851source "arch/arm/common/Kconfig" 852 853menu "Bus support" 854 855config ISA 856 bool 857 help 858 Find out whether you have ISA slots on your motherboard. ISA is the 859 name of a bus system, i.e. the way the CPU talks to the other stuff 860 inside your box. Other bus systems are PCI, EISA, MicroChannel 861 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 862 newer boards don't support it. If you have ISA, say Y, otherwise N. 863 864# Select ISA DMA interface 865config ISA_DMA_API 866 bool 867 868config ARM_ERRATA_814220 869 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 870 depends on CPU_V7 871 help 872 The v7 ARM states that all cache and branch predictor maintenance 873 operations that do not specify an address execute, relative to 874 each other, in program order. 875 However, because of this erratum, an L2 set/way cache maintenance 876 operation can overtake an L1 set/way cache maintenance operation. 877 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 878 r0p4, r0p5. 879 880endmenu 881 882menu "Kernel Features" 883 884config HAVE_SMP 885 bool 886 help 887 This option should be selected by machines which have an SMP- 888 capable CPU. 889 890 The only effect of this option is to make the SMP-related 891 options available to the user for configuration. 892 893config SMP 894 bool "Symmetric Multi-Processing" 895 depends on CPU_V6K || CPU_V7 896 depends on HAVE_SMP 897 depends on MMU || ARM_MPU 898 select IRQ_WORK 899 help 900 This enables support for systems with more than one CPU. If you have 901 a system with only one CPU, say N. If you have a system with more 902 than one CPU, say Y. 903 904 If you say N here, the kernel will run on uni- and multiprocessor 905 machines, but will use only one CPU of a multiprocessor machine. If 906 you say Y here, the kernel will run on many, but not all, 907 uniprocessor machines. On a uniprocessor machine, the kernel 908 will run faster if you say N here. 909 910 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 911 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 912 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 913 914 If you don't know what to do here, say N. 915 916config SMP_ON_UP 917 bool "Allow booting SMP kernel on uniprocessor systems" 918 depends on SMP && MMU 919 default y 920 help 921 SMP kernels contain instructions which fail on non-SMP processors. 922 Enabling this option allows the kernel to modify itself to make 923 these instructions safe. Disabling it allows about 1K of space 924 savings. 925 926 If you don't know what to do here, say Y. 927 928 929config CURRENT_POINTER_IN_TPIDRURO 930 def_bool y 931 depends on CPU_32v6K && !CPU_V6 932 933config IRQSTACKS 934 def_bool y 935 select HAVE_IRQ_EXIT_ON_IRQ_STACK 936 select HAVE_SOFTIRQ_ON_OWN_STACK 937 938config ARM_CPU_TOPOLOGY 939 bool "Support cpu topology definition" 940 depends on SMP && CPU_V7 941 default y 942 help 943 Support ARM cpu topology definition. The MPIDR register defines 944 affinity between processors which is then used to describe the cpu 945 topology of an ARM System. 946 947config SCHED_MC 948 bool "Multi-core scheduler support" 949 depends on ARM_CPU_TOPOLOGY 950 help 951 Multi-core scheduler support improves the CPU scheduler's decision 952 making when dealing with multi-core CPU chips at a cost of slightly 953 increased overhead in some places. If unsure say N here. 954 955config SCHED_SMT 956 bool "SMT scheduler support" 957 depends on ARM_CPU_TOPOLOGY 958 help 959 Improves the CPU scheduler's decision making when dealing with 960 MultiThreading at a cost of slightly increased overhead in some 961 places. If unsure say N here. 962 963config HAVE_ARM_SCU 964 bool 965 help 966 This option enables support for the ARM snoop control unit 967 968config HAVE_ARM_ARCH_TIMER 969 bool "Architected timer support" 970 depends on CPU_V7 971 select ARM_ARCH_TIMER 972 help 973 This option enables support for the ARM architected timer 974 975config HAVE_ARM_TWD 976 bool 977 help 978 This options enables support for the ARM timer and watchdog unit 979 980config MCPM 981 bool "Multi-Cluster Power Management" 982 depends on CPU_V7 && SMP 983 help 984 This option provides the common power management infrastructure 985 for (multi-)cluster based systems, such as big.LITTLE based 986 systems. 987 988config MCPM_QUAD_CLUSTER 989 bool 990 depends on MCPM 991 help 992 To avoid wasting resources unnecessarily, MCPM only supports up 993 to 2 clusters by default. 994 Platforms with 3 or 4 clusters that use MCPM must select this 995 option to allow the additional clusters to be managed. 996 997config BIG_LITTLE 998 bool "big.LITTLE support (Experimental)" 999 depends on CPU_V7 && SMP 1000 select MCPM 1001 help 1002 This option enables support selections for the big.LITTLE 1003 system architecture. 1004 1005config BL_SWITCHER 1006 bool "big.LITTLE switcher support" 1007 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1008 select CPU_PM 1009 help 1010 The big.LITTLE "switcher" provides the core functionality to 1011 transparently handle transition between a cluster of A15's 1012 and a cluster of A7's in a big.LITTLE system. 1013 1014config BL_SWITCHER_DUMMY_IF 1015 tristate "Simple big.LITTLE switcher user interface" 1016 depends on BL_SWITCHER && DEBUG_KERNEL 1017 help 1018 This is a simple and dummy char dev interface to control 1019 the big.LITTLE switcher core code. It is meant for 1020 debugging purposes only. 1021 1022choice 1023 prompt "Memory split" 1024 depends on MMU 1025 default VMSPLIT_3G 1026 help 1027 Select the desired split between kernel and user memory. 1028 1029 If you are not absolutely sure what you are doing, leave this 1030 option alone! 1031 1032 config VMSPLIT_3G 1033 bool "3G/1G user/kernel split" 1034 config VMSPLIT_3G_OPT 1035 depends on !ARM_LPAE 1036 bool "3G/1G user/kernel split (for full 1G low memory)" 1037 config VMSPLIT_2G 1038 bool "2G/2G user/kernel split" 1039 config VMSPLIT_1G 1040 bool "1G/3G user/kernel split" 1041endchoice 1042 1043config PAGE_OFFSET 1044 hex 1045 default PHYS_OFFSET if !MMU 1046 default 0x40000000 if VMSPLIT_1G 1047 default 0x80000000 if VMSPLIT_2G 1048 default 0xB0000000 if VMSPLIT_3G_OPT 1049 default 0xC0000000 1050 1051config KASAN_SHADOW_OFFSET 1052 hex 1053 depends on KASAN 1054 default 0x1f000000 if PAGE_OFFSET=0x40000000 1055 default 0x5f000000 if PAGE_OFFSET=0x80000000 1056 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1057 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1058 default 0xffffffff 1059 1060config NR_CPUS 1061 int "Maximum number of CPUs (2-32)" 1062 range 2 16 if DEBUG_KMAP_LOCAL 1063 range 2 32 if !DEBUG_KMAP_LOCAL 1064 depends on SMP 1065 default "4" 1066 help 1067 The maximum number of CPUs that the kernel can support. 1068 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1069 debugging is enabled, which uses half of the per-CPU fixmap 1070 slots as guard regions. 1071 1072config HOTPLUG_CPU 1073 bool "Support for hot-pluggable CPUs" 1074 depends on SMP 1075 select GENERIC_IRQ_MIGRATION 1076 help 1077 Say Y here to experiment with turning CPUs off and on. CPUs 1078 can be controlled through /sys/devices/system/cpu. 1079 1080config ARM_PSCI 1081 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1082 depends on HAVE_ARM_SMCCC 1083 select ARM_PSCI_FW 1084 help 1085 Say Y here if you want Linux to communicate with system firmware 1086 implementing the PSCI specification for CPU-centric power 1087 management operations described in ARM document number ARM DEN 1088 0022A ("Power State Coordination Interface System Software on 1089 ARM processors"). 1090 1091config HZ_FIXED 1092 int 1093 default 128 if SOC_AT91RM9200 1094 default 0 1095 1096choice 1097 depends on HZ_FIXED = 0 1098 prompt "Timer frequency" 1099 1100config HZ_100 1101 bool "100 Hz" 1102 1103config HZ_200 1104 bool "200 Hz" 1105 1106config HZ_250 1107 bool "250 Hz" 1108 1109config HZ_300 1110 bool "300 Hz" 1111 1112config HZ_500 1113 bool "500 Hz" 1114 1115config HZ_1000 1116 bool "1000 Hz" 1117 1118endchoice 1119 1120config HZ 1121 int 1122 default HZ_FIXED if HZ_FIXED != 0 1123 default 100 if HZ_100 1124 default 200 if HZ_200 1125 default 250 if HZ_250 1126 default 300 if HZ_300 1127 default 500 if HZ_500 1128 default 1000 1129 1130config SCHED_HRTICK 1131 def_bool HIGH_RES_TIMERS 1132 1133config THUMB2_KERNEL 1134 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1135 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1136 default y if CPU_THUMBONLY 1137 select ARM_UNWIND 1138 help 1139 By enabling this option, the kernel will be compiled in 1140 Thumb-2 mode. 1141 1142 If unsure, say N. 1143 1144config ARM_PATCH_IDIV 1145 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1146 depends on CPU_32v7 1147 default y 1148 help 1149 The ARM compiler inserts calls to __aeabi_idiv() and 1150 __aeabi_uidiv() when it needs to perform division on signed 1151 and unsigned integers. Some v7 CPUs have support for the sdiv 1152 and udiv instructions that can be used to implement those 1153 functions. 1154 1155 Enabling this option allows the kernel to modify itself to 1156 replace the first two instructions of these library functions 1157 with the sdiv or udiv plus "bx lr" instructions when the CPU 1158 it is running on supports them. Typically this will be faster 1159 and less power intensive than running the original library 1160 code to do integer division. 1161 1162config AEABI 1163 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1164 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1165 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1166 help 1167 This option allows for the kernel to be compiled using the latest 1168 ARM ABI (aka EABI). This is only useful if you are using a user 1169 space environment that is also compiled with EABI. 1170 1171 Since there are major incompatibilities between the legacy ABI and 1172 EABI, especially with regard to structure member alignment, this 1173 option also changes the kernel syscall calling convention to 1174 disambiguate both ABIs and allow for backward compatibility support 1175 (selected with CONFIG_OABI_COMPAT). 1176 1177 To use this you need GCC version 4.0.0 or later. 1178 1179config OABI_COMPAT 1180 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1181 depends on AEABI && !THUMB2_KERNEL 1182 help 1183 This option preserves the old syscall interface along with the 1184 new (ARM EABI) one. It also provides a compatibility layer to 1185 intercept syscalls that have structure arguments which layout 1186 in memory differs between the legacy ABI and the new ARM EABI 1187 (only for non "thumb" binaries). This option adds a tiny 1188 overhead to all syscalls and produces a slightly larger kernel. 1189 1190 The seccomp filter system will not be available when this is 1191 selected, since there is no way yet to sensibly distinguish 1192 between calling conventions during filtering. 1193 1194 If you know you'll be using only pure EABI user space then you 1195 can say N here. If this option is not selected and you attempt 1196 to execute a legacy ABI binary then the result will be 1197 UNPREDICTABLE (in fact it can be predicted that it won't work 1198 at all). If in doubt say N. 1199 1200config ARCH_SELECT_MEMORY_MODEL 1201 def_bool y 1202 1203config ARCH_FLATMEM_ENABLE 1204 def_bool !(ARCH_RPC || ARCH_SA1100) 1205 1206config ARCH_SPARSEMEM_ENABLE 1207 def_bool !ARCH_FOOTBRIDGE 1208 select SPARSEMEM_STATIC if SPARSEMEM 1209 1210config HIGHMEM 1211 bool "High Memory Support" 1212 depends on MMU 1213 select KMAP_LOCAL 1214 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1215 help 1216 The address space of ARM processors is only 4 Gigabytes large 1217 and it has to accommodate user address space, kernel address 1218 space as well as some memory mapped IO. That means that, if you 1219 have a large amount of physical memory and/or IO, not all of the 1220 memory can be "permanently mapped" by the kernel. The physical 1221 memory that is not permanently mapped is called "high memory". 1222 1223 Depending on the selected kernel/user memory split, minimum 1224 vmalloc space and actual amount of RAM, you may not need this 1225 option which should result in a slightly faster kernel. 1226 1227 If unsure, say n. 1228 1229config HIGHPTE 1230 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1231 depends on HIGHMEM 1232 default y 1233 help 1234 The VM uses one page of physical memory for each page table. 1235 For systems with a lot of processes, this can use a lot of 1236 precious low memory, eventually leading to low memory being 1237 consumed by page tables. Setting this option will allow 1238 user-space 2nd level page tables to reside in high memory. 1239 1240config ARM_PAN 1241 bool "Enable privileged no-access" 1242 depends on MMU 1243 default y 1244 help 1245 Increase kernel security by ensuring that normal kernel accesses 1246 are unable to access userspace addresses. This can help prevent 1247 use-after-free bugs becoming an exploitable privilege escalation 1248 by ensuring that magic values (such as LIST_POISON) will always 1249 fault when dereferenced. 1250 1251 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1252 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1253 1254config CPU_SW_DOMAIN_PAN 1255 def_bool y 1256 depends on ARM_PAN && !ARM_LPAE 1257 help 1258 Enable use of CPU domains to implement privileged no-access. 1259 1260 CPUs with low-vector mappings use a best-efforts implementation. 1261 Their lower 1MB needs to remain accessible for the vectors, but 1262 the remainder of userspace will become appropriately inaccessible. 1263 1264config CPU_TTBR0_PAN 1265 def_bool y 1266 depends on ARM_PAN && ARM_LPAE 1267 help 1268 Enable privileged no-access by disabling TTBR0 page table walks when 1269 running in kernel mode. 1270 1271config HW_PERF_EVENTS 1272 def_bool y 1273 depends on ARM_PMU 1274 1275config ARM_MODULE_PLTS 1276 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1277 depends on MODULES 1278 select KASAN_VMALLOC if KASAN 1279 default y 1280 help 1281 Allocate PLTs when loading modules so that jumps and calls whose 1282 targets are too far away for their relative offsets to be encoded 1283 in the instructions themselves can be bounced via veneers in the 1284 module's PLT. This allows modules to be allocated in the generic 1285 vmalloc area after the dedicated module memory area has been 1286 exhausted. The modules will use slightly more memory, but after 1287 rounding up to page size, the actual memory footprint is usually 1288 the same. 1289 1290 Disabling this is usually safe for small single-platform 1291 configurations. If unsure, say y. 1292 1293config ARCH_FORCE_MAX_ORDER 1294 int "Order of maximal physically contiguous allocations" 1295 default "11" if SOC_AM33XX 1296 default "8" if SA1111 1297 default "10" 1298 help 1299 The kernel page allocator limits the size of maximal physically 1300 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1301 defines the maximal power of two of number of pages that can be 1302 allocated as a single contiguous block. This option allows 1303 overriding the default setting when ability to allocate very 1304 large blocks of physically contiguous memory is required. 1305 1306 Don't change if unsure. 1307 1308config ALIGNMENT_TRAP 1309 def_bool CPU_CP15_MMU 1310 select HAVE_PROC_CPU if PROC_FS 1311 help 1312 ARM processors cannot fetch/store information which is not 1313 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1314 address divisible by 4. On 32-bit ARM processors, these non-aligned 1315 fetch/store instructions will be emulated in software if you say 1316 here, which has a severe performance impact. This is necessary for 1317 correct operation of some network protocols. With an IP-only 1318 configuration it is safe to say N, otherwise say Y. 1319 1320config UACCESS_WITH_MEMCPY 1321 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1322 depends on MMU 1323 default y if CPU_FEROCEON 1324 help 1325 Implement faster copy_to_user and clear_user methods for CPU 1326 cores where a 8-word STM instruction give significantly higher 1327 memory write throughput than a sequence of individual 32bit stores. 1328 1329 A possible side effect is a slight increase in scheduling latency 1330 between threads sharing the same address space if they invoke 1331 such copy operations with large buffers. 1332 1333 However, if the CPU data cache is using a write-allocate mode, 1334 this option is unlikely to provide any performance gain. 1335 1336config PARAVIRT 1337 bool "Enable paravirtualization code" 1338 help 1339 This changes the kernel so it can modify itself when it is run 1340 under a hypervisor, potentially improving performance significantly 1341 over full virtualization. 1342 1343config PARAVIRT_TIME_ACCOUNTING 1344 bool "Paravirtual steal time accounting" 1345 select PARAVIRT 1346 help 1347 Select this option to enable fine granularity task steal time 1348 accounting. Time spent executing other tasks in parallel with 1349 the current vCPU is discounted from the vCPU power. To account for 1350 that, there can be a small performance impact. 1351 1352 If in doubt, say N here. 1353 1354config XEN_DOM0 1355 def_bool y 1356 depends on XEN 1357 1358config XEN 1359 bool "Xen guest support on ARM" 1360 depends on ARM && AEABI && OF 1361 depends on CPU_V7 && !CPU_V6 1362 depends on !GENERIC_ATOMIC64 1363 depends on MMU 1364 select ARCH_DMA_ADDR_T_64BIT 1365 select ARM_PSCI 1366 select SWIOTLB 1367 select SWIOTLB_XEN 1368 select PARAVIRT 1369 help 1370 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1371 1372config CC_HAVE_STACKPROTECTOR_TLS 1373 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1374 1375config STACKPROTECTOR_PER_TASK 1376 bool "Use a unique stack canary value for each task" 1377 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1378 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1379 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1380 default y 1381 help 1382 Due to the fact that GCC uses an ordinary symbol reference from 1383 which to load the value of the stack canary, this value can only 1384 change at reboot time on SMP systems, and all tasks running in the 1385 kernel's address space are forced to use the same canary value for 1386 the entire duration that the system is up. 1387 1388 Enable this option to switch to a different method that uses a 1389 different canary value for each task. 1390 1391endmenu 1392 1393menu "Boot options" 1394 1395config USE_OF 1396 bool "Flattened Device Tree support" 1397 select IRQ_DOMAIN 1398 select OF 1399 help 1400 Include support for flattened device tree machine descriptions. 1401 1402config ARCH_WANT_FLAT_DTB_INSTALL 1403 def_bool y 1404 1405config ATAGS 1406 bool "Support for the traditional ATAGS boot data passing" 1407 default y 1408 help 1409 This is the traditional way of passing data to the kernel at boot 1410 time. If you are solely relying on the flattened device tree (or 1411 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1412 to remove ATAGS support from your kernel binary. 1413 1414config DEPRECATED_PARAM_STRUCT 1415 bool "Provide old way to pass kernel parameters" 1416 depends on ATAGS 1417 help 1418 This was deprecated in 2001 and announced to live on for 5 years. 1419 Some old boot loaders still use this way. 1420 1421# Compressed boot loader in ROM. Yes, we really want to ask about 1422# TEXT and BSS so we preserve their values in the config files. 1423config ZBOOT_ROM_TEXT 1424 hex "Compressed ROM boot loader base address" 1425 default 0x0 1426 help 1427 The physical address at which the ROM-able zImage is to be 1428 placed in the target. Platforms which normally make use of 1429 ROM-able zImage formats normally set this to a suitable 1430 value in their defconfig file. 1431 1432 If ZBOOT_ROM is not enabled, this has no effect. 1433 1434config ZBOOT_ROM_BSS 1435 hex "Compressed ROM boot loader BSS address" 1436 default 0x0 1437 help 1438 The base address of an area of read/write memory in the target 1439 for the ROM-able zImage which must be available while the 1440 decompressor is running. It must be large enough to hold the 1441 entire decompressed kernel plus an additional 128 KiB. 1442 Platforms which normally make use of ROM-able zImage formats 1443 normally set this to a suitable value in their defconfig file. 1444 1445 If ZBOOT_ROM is not enabled, this has no effect. 1446 1447config ZBOOT_ROM 1448 bool "Compressed boot loader in ROM/flash" 1449 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1450 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1451 help 1452 Say Y here if you intend to execute your compressed kernel image 1453 (zImage) directly from ROM or flash. If unsure, say N. 1454 1455config ARM_APPENDED_DTB 1456 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1457 depends on OF 1458 help 1459 With this option, the boot code will look for a device tree binary 1460 (DTB) appended to zImage 1461 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1462 1463 This is meant as a backward compatibility convenience for those 1464 systems with a bootloader that can't be upgraded to accommodate 1465 the documented boot protocol using a device tree. 1466 1467 Beware that there is very little in terms of protection against 1468 this option being confused by leftover garbage in memory that might 1469 look like a DTB header after a reboot if no actual DTB is appended 1470 to zImage. Do not leave this option active in a production kernel 1471 if you don't intend to always append a DTB. Proper passing of the 1472 location into r2 of a bootloader provided DTB is always preferable 1473 to this option. 1474 1475config ARM_ATAG_DTB_COMPAT 1476 bool "Supplement the appended DTB with traditional ATAG information" 1477 depends on ARM_APPENDED_DTB 1478 help 1479 Some old bootloaders can't be updated to a DTB capable one, yet 1480 they provide ATAGs with memory configuration, the ramdisk address, 1481 the kernel cmdline string, etc. Such information is dynamically 1482 provided by the bootloader and can't always be stored in a static 1483 DTB. To allow a device tree enabled kernel to be used with such 1484 bootloaders, this option allows zImage to extract the information 1485 from the ATAG list and store it at run time into the appended DTB. 1486 1487choice 1488 prompt "Kernel command line type" 1489 depends on ARM_ATAG_DTB_COMPAT 1490 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1491 1492config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1493 bool "Use bootloader kernel arguments if available" 1494 help 1495 Uses the command-line options passed by the boot loader instead of 1496 the device tree bootargs property. If the boot loader doesn't provide 1497 any, the device tree bootargs property will be used. 1498 1499config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1500 bool "Extend with bootloader kernel arguments" 1501 help 1502 The command-line arguments provided by the boot loader will be 1503 appended to the the device tree bootargs property. 1504 1505endchoice 1506 1507config CMDLINE 1508 string "Default kernel command string" 1509 default "" 1510 help 1511 On some architectures (e.g. CATS), there is currently no way 1512 for the boot loader to pass arguments to the kernel. For these 1513 architectures, you should supply some command-line options at build 1514 time by entering them here. As a minimum, you should specify the 1515 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1516 1517choice 1518 prompt "Kernel command line type" 1519 depends on CMDLINE != "" 1520 default CMDLINE_FROM_BOOTLOADER 1521 1522config CMDLINE_FROM_BOOTLOADER 1523 bool "Use bootloader kernel arguments if available" 1524 help 1525 Uses the command-line options passed by the boot loader. If 1526 the boot loader doesn't provide any, the default kernel command 1527 string provided in CMDLINE will be used. 1528 1529config CMDLINE_EXTEND 1530 bool "Extend bootloader kernel arguments" 1531 help 1532 The command-line arguments provided by the boot loader will be 1533 appended to the default kernel command string. 1534 1535config CMDLINE_FORCE 1536 bool "Always use the default kernel command string" 1537 help 1538 Always use the default kernel command string, even if the boot 1539 loader passes other arguments to the kernel. 1540 This is useful if you cannot or don't want to change the 1541 command-line options your boot loader passes to the kernel. 1542endchoice 1543 1544config XIP_KERNEL 1545 bool "Kernel Execute-In-Place from ROM" 1546 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1547 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1548 help 1549 Execute-In-Place allows the kernel to run from non-volatile storage 1550 directly addressable by the CPU, such as NOR flash. This saves RAM 1551 space since the text section of the kernel is not loaded from flash 1552 to RAM. Read-write sections, such as the data section and stack, 1553 are still copied to RAM. The XIP kernel is not compressed since 1554 it has to run directly from flash, so it will take more space to 1555 store it. The flash address used to link the kernel object files, 1556 and for storing it, is configuration dependent. Therefore, if you 1557 say Y here, you must know the proper physical address where to 1558 store the kernel image depending on your own flash memory usage. 1559 1560 Also note that the make target becomes "make xipImage" rather than 1561 "make zImage" or "make Image". The final kernel binary to put in 1562 ROM memory will be arch/arm/boot/xipImage. 1563 1564 If unsure, say N. 1565 1566config XIP_PHYS_ADDR 1567 hex "XIP Kernel Physical Location" 1568 depends on XIP_KERNEL 1569 default "0x00080000" 1570 help 1571 This is the physical address in your flash memory the kernel will 1572 be linked for and stored to. This address is dependent on your 1573 own flash usage. 1574 1575config XIP_DEFLATED_DATA 1576 bool "Store kernel .data section compressed in ROM" 1577 depends on XIP_KERNEL 1578 select ZLIB_INFLATE 1579 help 1580 Before the kernel is actually executed, its .data section has to be 1581 copied to RAM from ROM. This option allows for storing that data 1582 in compressed form and decompressed to RAM rather than merely being 1583 copied, saving some precious ROM space. A possible drawback is a 1584 slightly longer boot delay. 1585 1586config ARCH_SUPPORTS_KEXEC 1587 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1588 1589config ATAGS_PROC 1590 bool "Export atags in procfs" 1591 depends on ATAGS && KEXEC 1592 default y 1593 help 1594 Should the atags used to boot the kernel be exported in an "atags" 1595 file in procfs. Useful with kexec. 1596 1597config ARCH_SUPPORTS_CRASH_DUMP 1598 def_bool y 1599 1600config AUTO_ZRELADDR 1601 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1602 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1603 help 1604 ZRELADDR is the physical address where the decompressed kernel 1605 image will be placed. If AUTO_ZRELADDR is selected, the address 1606 will be determined at run-time, either by masking the current IP 1607 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1608 This assumes the zImage being placed in the first 128MB from 1609 start of memory. 1610 1611config EFI_STUB 1612 bool 1613 1614config EFI 1615 bool "UEFI runtime support" 1616 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1617 select UCS2_STRING 1618 select EFI_PARAMS_FROM_FDT 1619 select EFI_STUB 1620 select EFI_GENERIC_STUB 1621 select EFI_RUNTIME_WRAPPERS 1622 help 1623 This option provides support for runtime services provided 1624 by UEFI firmware (such as non-volatile variables, realtime 1625 clock, and platform reset). A UEFI stub is also provided to 1626 allow the kernel to be booted as an EFI application. This 1627 is only useful for kernels that may run on systems that have 1628 UEFI firmware. 1629 1630config DMI 1631 bool "Enable support for SMBIOS (DMI) tables" 1632 depends on EFI 1633 default y 1634 help 1635 This enables SMBIOS/DMI feature for systems. 1636 1637 This option is only useful on systems that have UEFI firmware. 1638 However, even with this option, the resultant kernel should 1639 continue to boot on existing non-UEFI platforms. 1640 1641 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1642 i.e., the the practice of identifying the platform via DMI to 1643 decide whether certain workarounds for buggy hardware and/or 1644 firmware need to be enabled. This would require the DMI subsystem 1645 to be enabled much earlier than we do on ARM, which is non-trivial. 1646 1647endmenu 1648 1649menu "CPU Power Management" 1650 1651source "drivers/cpufreq/Kconfig" 1652 1653source "drivers/cpuidle/Kconfig" 1654 1655endmenu 1656 1657menu "Floating point emulation" 1658 1659comment "At least one emulation must be selected" 1660 1661config FPE_NWFPE 1662 bool "NWFPE math emulation" 1663 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1664 help 1665 Say Y to include the NWFPE floating point emulator in the kernel. 1666 This is necessary to run most binaries. Linux does not currently 1667 support floating point hardware so you need to say Y here even if 1668 your machine has an FPA or floating point co-processor podule. 1669 1670 You may say N here if you are going to load the Acorn FPEmulator 1671 early in the bootup. 1672 1673config FPE_NWFPE_XP 1674 bool "Support extended precision" 1675 depends on FPE_NWFPE 1676 help 1677 Say Y to include 80-bit support in the kernel floating-point 1678 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1679 Note that gcc does not generate 80-bit operations by default, 1680 so in most cases this option only enlarges the size of the 1681 floating point emulator without any good reason. 1682 1683 You almost surely want to say N here. 1684 1685config FPE_FASTFPE 1686 bool "FastFPE math emulation (EXPERIMENTAL)" 1687 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1688 help 1689 Say Y here to include the FAST floating point emulator in the kernel. 1690 This is an experimental much faster emulator which now also has full 1691 precision for the mantissa. It does not support any exceptions. 1692 It is very simple, and approximately 3-6 times faster than NWFPE. 1693 1694 It should be sufficient for most programs. It may be not suitable 1695 for scientific calculations, but you have to check this for yourself. 1696 If you do not feel you need a faster FP emulation you should better 1697 choose NWFPE. 1698 1699config VFP 1700 bool "VFP-format floating point maths" 1701 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1702 help 1703 Say Y to include VFP support code in the kernel. This is needed 1704 if your hardware includes a VFP unit. 1705 1706 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1707 release notes and additional status information. 1708 1709 Say N if your target does not have VFP hardware. 1710 1711config VFPv3 1712 bool 1713 depends on VFP 1714 default y if CPU_V7 1715 1716config NEON 1717 bool "Advanced SIMD (NEON) Extension support" 1718 depends on VFPv3 && CPU_V7 1719 help 1720 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1721 Extension. 1722 1723config KERNEL_MODE_NEON 1724 bool "Support for NEON in kernel mode" 1725 depends on NEON && AEABI 1726 help 1727 Say Y to include support for NEON in kernel mode. 1728 1729endmenu 1730 1731menu "Power management options" 1732 1733source "kernel/power/Kconfig" 1734 1735config ARCH_SUSPEND_POSSIBLE 1736 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1737 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1738 def_bool y 1739 1740config ARM_CPU_SUSPEND 1741 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1742 depends on ARCH_SUSPEND_POSSIBLE 1743 1744config ARCH_HIBERNATION_POSSIBLE 1745 bool 1746 depends on MMU 1747 default y if ARCH_SUSPEND_POSSIBLE 1748 1749endmenu 1750 1751source "arch/arm/Kconfig.assembler" 1752