1/* 2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 12#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 13#include <asm/errno.h> 14#include <asm/arcregs.h> 15#include <asm/irqflags.h> 16 17 .cpu HS 18 19#define VECTOR .word 20 21;############################ Vector Table ################################# 22 23 .section .vector,"a",@progbits 24 .align 4 25 26# Initial 16 slots are Exception Vectors 27VECTOR res_service ; Reset Vector 28VECTOR mem_service ; Mem exception 29VECTOR instr_service ; Instrn Error 30VECTOR EV_MachineCheck ; Fatal Machine check 31VECTOR EV_TLBMissI ; Intruction TLB miss 32VECTOR EV_TLBMissD ; Data TLB miss 33VECTOR EV_TLBProtV ; Protection Violation 34VECTOR EV_PrivilegeV ; Privilege Violation 35VECTOR EV_SWI ; Software Breakpoint 36VECTOR EV_Trap ; Trap exception 37VECTOR EV_Extension ; Extn Instruction Exception 38VECTOR EV_DivZero ; Divide by Zero 39VECTOR EV_DCError ; Data Cache Error 40VECTOR EV_Misaligned ; Misaligned Data Access 41VECTOR reserved ; Reserved slots 42VECTOR reserved ; Reserved slots 43 44# Begin Interrupt Vectors 45VECTOR handle_interrupt ; (16) Timer0 46VECTOR handle_interrupt ; unused (Timer1) 47VECTOR handle_interrupt ; unused (WDT) 48VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI) 49VECTOR handle_interrupt ; (20) perf Interrupt 50VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI) 51VECTOR handle_interrupt ; unused 52VECTOR handle_interrupt ; (23) unused 53# End of fixed IRQs 54 55.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8 56 VECTOR handle_interrupt 57.endr 58 59 .section .text, "ax",@progbits 60 61reserved: 62 flag 1 ; Unexpected event, halt 63 64;##################### Interrupt Handling ############################## 65 66ENTRY(handle_interrupt) 67 68 INTERRUPT_PROLOGUE irq 69 70 clri ; To make status32.IE agree with CPU internal state 71 72#ifdef CONFIG_TRACE_IRQFLAGS 73 TRACE_ASM_IRQ_DISABLE 74#endif 75 76 lr r0, [ICAUSE] 77 mov blink, ret_from_exception 78 79 b.d arch_do_IRQ 80 mov r1, sp 81 82END(handle_interrupt) 83 84;################### Non TLB Exception Handling ############################# 85 86ENTRY(EV_SWI) 87 flag 1 88END(EV_SWI) 89 90ENTRY(EV_DivZero) 91 flag 1 92END(EV_DivZero) 93 94ENTRY(EV_DCError) 95 flag 1 96END(EV_DCError) 97 98; --------------------------------------------- 99; Memory Error Exception Handler 100; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 101; Instruction fetch or Data access, under a single Exception Vector 102; --------------------------------------------- 103 104ENTRY(mem_service) 105 106 EXCEPTION_PROLOGUE 107 108 lr r0, [efa] 109 mov r1, sp 110 111 FAKE_RET_FROM_EXCPN 112 113 bl do_memory_error 114 b ret_from_exception 115END(mem_service) 116 117ENTRY(EV_Misaligned) 118 119 EXCEPTION_PROLOGUE 120 121 lr r0, [efa] ; Faulting Data address 122 mov r1, sp 123 124 FAKE_RET_FROM_EXCPN 125 126 SAVE_CALLEE_SAVED_USER 127 mov r2, sp ; callee_regs 128 129 bl do_misaligned_access 130 131 ; TBD: optimize - do this only if a callee reg was involved 132 ; either a dst of emulated LD/ST or src with address-writeback 133 RESTORE_CALLEE_SAVED_USER 134 135 b ret_from_exception 136END(EV_Misaligned) 137 138; --------------------------------------------- 139; Protection Violation Exception Handler 140; --------------------------------------------- 141 142ENTRY(EV_TLBProtV) 143 144 EXCEPTION_PROLOGUE 145 146 lr r0, [efa] ; Faulting Data address 147 mov r1, sp ; pt_regs 148 149 FAKE_RET_FROM_EXCPN 150 151 mov blink, ret_from_exception 152 b do_page_fault 153 154END(EV_TLBProtV) 155 156; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 157; need to call do_page_fault(). 158; ECR in pt_regs provides whether access was R/W/X 159 160.global call_do_page_fault 161.set call_do_page_fault, EV_TLBProtV 162 163;############# Common Handlers for ARCompact and ARCv2 ############## 164 165#include "entry.S" 166 167;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 168; 169; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 170; IRQ shd definitely not happen between now and rtie 171; All 2 entry points to here already disable interrupts 172 173.Lrestore_regs: 174 175 # Interrpts are actually disabled from this point on, but will get 176 # reenabled after we return from interrupt/exception. 177 # But irq tracer needs to be told now... 178 TRACE_ASM_IRQ_ENABLE 179 180 ld r0, [sp, PT_status32] ; U/K mode at time of entry 181 lr r10, [AUX_IRQ_ACT] 182 183 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 184 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 185 186;####### Return from Intr ####### 187 188debug_marker_l1: 189 bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 190 191.Lisr_ret_fast_path: 192 ; Handle special case #1: (Entry via Exception, Return via IRQ) 193 ; 194 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 195 ; task now returning to U mode (riding the Intr) 196 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 197 ; won't be switched to correct U mode value (from AUX_SP) 198 ; So force AUX_IRQ_ACT.U for such a case 199 200 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 201 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 202 sr r11, [AUX_IRQ_ACT] 203 204 INTERRUPT_EPILOGUE irq 205 rtie 206 207;####### Return from Exception / pure kernel mode ####### 208 209.Lexcept_ret: ; Expects r0 has PT_status32 210 211debug_marker_syscall: 212 EXCEPTION_EPILOGUE 213 rtie 214 215;####### Return from Intr to insn in delay slot ####### 216 217; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 218; 219; Intr returning to a Delay Slot (DS) insn 220; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 221; entry was via Exception in DS which got preempted in kernel). 222; 223; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround 224; 225; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline 226; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly 227 228.Lintr_ret_to_delay_slot: 229debug_marker_ds: 230 231 ld r2, [@intr_to_DE_cnt] 232 add r2, r2, 1 233 st r2, [@intr_to_DE_cnt] 234 235 ld r2, [sp, PT_ret] 236 ld r3, [sp, PT_status32] 237 238 ; STAT32 for Int return created from scratch 239 ; (No delay dlot, disable Further intr in trampoline) 240 241 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 242 st r0, [sp, PT_status32] 243 244 mov r1, .Lintr_ret_to_delay_slot_2 245 st r1, [sp, PT_ret] 246 247 ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots 248 st r2, [sp, 0] 249 st r3, [sp, 4] 250 251 b .Lisr_ret_fast_path 252 253.Lintr_ret_to_delay_slot_2: 254 ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP 255 sub sp, sp, SZ_PT_REGS 256 st r9, [sp, -4] 257 258 ld r9, [sp, 0] 259 sr r9, [eret] 260 261 ld r9, [sp, 4] 262 sr r9, [erstatus] 263 264 ; restore AUX_USER_SP if returning to U mode 265 bbit0 r9, STATUS_U_BIT, 1f 266 ld r9, [sp, PT_sp] 267 sr r9, [AUX_USER_SP] 268 2691: 270 ld r9, [sp, 8] 271 sr r9, [erbta] 272 273 ld r9, [sp, -4] 274 add sp, sp, SZ_PT_REGS 275 276 ; return from pure kernel mode to delay slot 277 rtie 278 279END(ret_from_exception) 280