xref: /linux/Documentation/sound/codecs/tas675x.rst (revision 26b8eb8a98c18b2ee4ea76d99fa2b2a5ccbc1b6c) 
1.. SPDX-License-Identifier: GPL-2.0
2
3======================================
4TAS675x Codec Mixer Controls
5======================================
6
7This document describes the ALSA mixer controls for the TAS675x
84-channel amplifier driver.
9
10For device tree bindings, see:
11Documentation/devicetree/bindings/sound/ti,tas67524.yaml
12
13DSP Signal Path Mode
14====================
15
16DSP Signal Path Mode
17--------------------
18
19:Description: Signal processing mode selection.
20:Type:        Enumerated
21:Default:     Normal
22:Options:     Normal, LLP, FFLP
23:Register:    0x32 bits [1:0]
24
25Normal
26  Full DSP with all features available.
27
28LLP (Low Latency Path)
29  Bypasses DSP processing. DSP protection features (Thermal Foldback,
30  PVDD Foldback, Clip Detect) and Real-Time Load Diagnostics unavailable.
31
32FFLP (Full Feature Low Latency Path)
33  Reduced latency. Real-Time Load Diagnostics unavailable.
34
35The following controls are unavailable in LLP mode:
36``Thermal Foldback Switch``, ``PVDD Foldback Switch``,
37``DC Blocker Bypass Switch``, ``Clip Detect Switch``, ``Audio SDOUT Switch``.
38
39The following controls require Normal mode (unavailable in FFLP and LLP):
40``CHx RTLDG Switch``, ``RTLDG Clip Mask Switch``, ``ISENSE Calibration Switch``,
41``RTLDG Open Load Threshold``, ``RTLDG Short Load Threshold``,
42``CHx RTLDG Impedance``.
43
44Volume Controls
45===============
46
47Analog Playback Volume
48----------------------
49
50:Description: Analog output gain for all channels (CH1/CH2 and CH3/CH4 pairs).
51:Type:        Volume (TLV)
52:Default:     0 dB
53:Range:       -15.5 dB to 0 dB (0.5 dB steps)
54:Register:    0x4A (CH1/CH2), 0x4B (CH3/CH4)
55
56Analog Gain Ramp Step
57---------------------
58
59:Description: Anti-pop ramp step duration for analog gain transitions.
60:Type:        Enumerated
61:Default:     15us
62:Options:     15us, 60us, 200us, 400us
63:Register:    0x4E bits [3:2]
64
65CHx Digital Playback Volume
66---------------------------
67
68:Description: Per-channel digital volume control (x = 1, 2, 3, 4).
69:Type:        Volume (TLV)
70:Default:     0 dB
71:Range:       -103 dB to 0 dB (0.5 dB steps)
72:Bounds:      0x30 (min/mute) to 0xFF (max)
73:Register:    0x40 (CH1), 0x41 (CH2), 0x42 (CH3), 0x43 (CH4)
74
75Volume Ramp Down Rate
76---------------------
77
78:Description: Update frequency during mute transition.
79:Type:        Enumerated
80:Default:     16 FS
81:Options:     4 FS, 16 FS, 32 FS, Instant
82:Register:    0x44 bits [7:6]
83
84Volume Ramp Down Step
85---------------------
86
87:Description: dB change per update during mute.
88:Type:        Enumerated
89:Default:     0.5dB
90:Options:     4dB, 2dB, 1dB, 0.5dB
91:Register:    0x44 bits [5:4]
92
93Volume Ramp Up Rate
94-------------------
95
96:Description: Update frequency during unmute transition.
97:Type:        Enumerated
98:Default:     16 FS
99:Options:     4 FS, 16 FS, 32 FS, Instant
100:Register:    0x44 bits [3:2]
101
102Volume Ramp Up Step
103-------------------
104
105:Description: dB change per update during unmute.
106:Type:        Enumerated
107:Default:     0.5dB
108:Options:     4dB, 2dB, 1dB, 0.5dB
109:Register:    0x44 bits [1:0]
110
111CH1/2 Volume Combine
112--------------------
113
114:Description: Links digital volume controls for CH1 and CH2.
115:Type:        Enumerated
116:Default:     Independent
117:Options:     Independent, CH2 follows CH1, CH1 follows CH2
118:Register:    0x46 bits [1:0]
119
120CH3/4 Volume Combine
121--------------------
122
123:Description: Links digital volume controls for CH3 and CH4.
124:Type:        Enumerated
125:Default:     Independent
126:Options:     Independent, CH4 follows CH3, CH3 follows CH4
127:Register:    0x46 bits [3:2]
128
129Auto Mute & Silence Detection
130==============================
131
132CHx Auto Mute Switch
133--------------------
134
135:Description: Enables automatic muting on zero-signal detection (x = 1, 2, 3, 4).
136:Type:        Boolean Switch
137:Default:     Disabled (0)
138:Register:    0x47 bit [0] (CH1), bit [1] (CH2), bit [2] (CH3), bit [3] (CH4)
139
140Auto Mute Combine Switch
141------------------------
142
143:Description: Coordinated muting behaviour across all channels.
144:Type:        Boolean Switch
145:Default:     Disabled (0)
146:Behavior:    Disabled: channels mute independently when their signal is zero.
147              Enabled: all channels mute together only when all detect zero
148              signal; unmute when any channel has non-zero signal.
149:Register:    0x47 bit [4]
150
151CHx Auto Mute Time
152------------------
153
154:Description: Duration of zero signal before muting triggers (x = 1, 2, 3, 4).
155:Type:        Enumerated
156:Default:     11.5ms
157:Options:     11.5ms, 53ms, 106.5ms, 266.5ms, 535ms, 1065ms, 2665ms, 5330ms
158:Register:    0x48 bits [7:4] (CH1), bits [3:0] (CH2),
159              0x49 bits [7:4] (CH3), bits [3:0] (CH4)
160:Note:        Values are at 96 kHz. At 48 kHz, times are doubled.
161
162Clock & EMI Management
163======================
164
165Spread Spectrum Mode
166--------------------
167
168:Description: Frequency dithering mode to reduce peak EMI.
169:Type:        Enumerated
170:Default:     Disabled
171:Options:     Disabled, Triangle, Random, Triangle and Random
172:Register:    0x61 bits [1:0]
173
174SS Triangle Range
175-----------------
176
177:Description: Frequency deviation range for Triangle spread spectrum.
178:Type:        Enumerated
179:Default:     6.5%
180:Options:     6.5%, 13.5%, 5%, 10%
181:Register:    0x62 bits [1:0]
182:Note:        Applies only when Spread Spectrum Mode includes Triangle.
183
184SS Random Range
185---------------
186
187:Description: Frequency deviation range for Random spread spectrum.
188:Type:        Enumerated
189:Default:     0.83%
190:Options:     0.83%, 2.50%, 5.83%, 12.50%, 25.83%
191:Register:    0x62 bits [6:4]
192:Note:        Applies only when Spread Spectrum Mode includes Random.
193
194SS Random Dwell Range
195---------------------
196
197:Description: Dwell time range for Random spread spectrum (FSS = spread
198              spectrum modulation frequency).
199:Type:        Enumerated
200:Default:     1/FSS to 2/FSS
201:Options:     1/FSS to 2/FSS, 1/FSS to 4/FSS, 1/FSS to 8/FSS, 1/FSS to 15/FSS
202:Register:    0x62 bits [3:2]
203:Note:        Applies only when Spread Spectrum Mode includes Random.
204
205SS Triangle Dwell Min
206---------------------
207
208:Description: Minimum dwell time at Triangle spread spectrum frequency extremes.
209:Type:        Integer
210:Default:     0
211:Range:       0 to 15 (0 = feature disabled)
212:Register:    0x66 bits [7:4]
213:Note:        Counts in FSS clock cycles. The modulator holds the extreme
214              frequency for at least this many FSS cycles before reversing.
215              When Dwell Min equals Dwell Max, the dwell feature is inactive.
216              For FSS values at each PWM frequency refer to the "Spread
217              Spectrum" section of the TRM.
218
219SS Triangle Dwell Max
220---------------------
221
222:Description: Maximum dwell time at Triangle spread spectrum frequency extremes.
223:Type:        Integer
224:Default:     0
225:Range:       0 to 15 (0 = feature disabled)
226:Register:    0x66 bits [3:0]
227:Note:        Counts in FSS clock cycles. Must be >= Dwell Min. When Dwell Max
228              equals Dwell Min, the dwell feature is inactive.
229
230Hardware Protection
231===================
232
233OTSD Auto Recovery Switch
234--------------------------
235
236:Description: Enables automatic recovery from over-temperature shutdown.
237:Type:        Boolean Switch
238:Default:     Disabled (0)
239:Register:    0x8F bit [1]
240:Note:        When disabled, manual fault clearing is required after OTSD events.
241
242Overcurrent Limit Level
243-----------------------
244
245:Description: Current-limit trip point sensitivity.
246:Type:        Enumerated
247:Default:     Level 4
248:Options:     Level 4, Level 3, Level 2, Level 1
249:Register:    0x55 bits [1:0]
250:Note:        Level 4 is the least sensitive (highest trip current); Level 1 is
251              the most sensitive. The exact ILIM values depend on operating
252              conditions (PVDD voltage, switching frequency, and temperature).
253              Refer to the Electrical Characteristics table and the
254              "Overcurrent Limit (Cycle-By-Cycle)" section of the TRM.
255
256CHx OTW Threshold
257-----------------
258
259:Description: Over-temperature warning threshold per channel (x = 1, 2, 3, 4).
260:Type:        Enumerated
261:Default:     >95C
262:Options:     Disabled, >95C, >110C, >125C, >135C, >145C, >155C, >165C
263:Register:    0xE2 bits [6:4] (CH1), bits [2:0] (CH2),
264              0xE3 bits [6:4] (CH3), bits [2:0] (CH4)
265
266Temperature and Voltage Monitoring
267===================================
268
269PVDD Sense
270----------
271
272:Description: Supply voltage sense register.
273:Type:        Integer (read-only)
274:Range:       0 to 255
275:Conversion:  value × 0.19 V
276:Register:    0x74
277
278Global Temperature
279------------------
280
281:Description: Global die temperature sense register.
282:Type:        Integer (read-only)
283:Range:       0 to 255
284:Conversion:  (value × 0.5 °C) − 50 °C
285:Register:    0x75
286
287CHx Temperature Range
288---------------------
289
290:Description: Per-channel coarse temperature range indicator (x = 1, 2, 3, 4).
291:Type:        Integer (read-only)
292:Range:       0 to 3
293:Mapping:     0 = <80 °C, 1 = 80–100 °C, 2 = 100–120 °C, 3 = >120 °C
294:Register:    0xBB bits [7:6] (CH1), bits [5:4] (CH2),
295              0xBC bits [3:2] (CH3), bits [1:0] (CH4)
296
297Load Diagnostics
298================
299
300The TAS675x provides three load diagnostic modes:
301
302DC Load Diagnostics (DC LDG)
303  Measures DC resistance to detect S2G (short-to-ground), S2P
304  (short-to-power), OL (open load), and SL (shorted load) faults.
305
306AC Load Diagnostics (AC LDG)
307  Measures complex AC impedance at a configurable frequency. Detects
308  capacitive loads and tweeter configurations.
309
310Real-Time Load Diagnostics (RTLDG)
311  Monitors impedance continuously during playback using a pilot tone.
312  Normal DSP mode only, at 48 kHz or 96 kHz.
313
314Fast Boot Mode
315--------------
316
317By default the device runs DC load diagnostics at initialization before
318accepting audio. Setting ``ti,fast-boot`` in the device tree bypasses this
319initial diagnostic run for faster startup. Automatic diagnostics after
320fault recovery remain enabled.
321
322DC Load Diagnostics
323-------------------
324
325The ``CHx DC LDG Report`` 4-bit fault field uses the following encoding:
326
327  ======  ===========  ===================================================
328  Bit     Fault        Description
329  ======  ===========  ===================================================
330  [3]     S2G          Short-to-Ground
331  [2]     S2P          Short-to-Power
332  [1]     OL           Open Load
333  [0]     SL           Shorted Load
334  ======  ===========  ===================================================
335
336DC LDG Trigger
337~~~~~~~~~~~~~~
338
339:Description: Triggers manual DC load diagnostics on all channels.
340:Type:        Boolean (write-only)
341:Note:        Returns -EBUSY if any DAI stream (playback or capture) is active.
342              The driver manages all channel state transitions. Blocks until
343              diagnostics complete or time out (300 ms).
344
345DC LDG Auto Diagnostics Switch
346~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
347
348:Description: Enables automatic DC diagnostics after fault recovery.
349:Type:        Boolean Switch
350:Default:     Enabled (1)
351:Register:    0xB0 bit [0]
352:Note:        Active-low, when enabled, affected channels re-run diagnostics after
353              fault recovery and retry approximately every 750 ms until resolved.
354
355CHx LO LDG Switch
356~~~~~~~~~~~~~~~~~
357
358:Description: Enables line output load detection per channel (x = 1, 2, 3, 4).
359:Type:        Boolean Switch
360:Default:     Disabled (0)
361:Register:    0xB1 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
362:Note:        When enabled and DC diagnostics report OL, the device tests for
363              a high-impedance line output load.
364
365DC LDG SLOL Ramp Time
366~~~~~~~~~~~~~~~~~~~~~
367
368:Description: Voltage ramp time for shorted-load and open-load detection.
369:Type:        Enumerated
370:Default:     15 ms
371:Options:     15 ms, 30 ms, 10 ms, 20 ms
372:Register:    0xB2 bits [7:6]
373
374DC LDG SLOL Settling Time
375~~~~~~~~~~~~~~~~~~~~~~~~~~
376
377:Description: Settling time for shorted-load and open-load detection.
378:Type:        Enumerated
379:Default:     10 ms
380:Options:     10 ms, 5 ms, 20 ms, 15 ms
381:Register:    0xB2 bits [5:4]
382
383DC LDG S2PG Ramp Time
384~~~~~~~~~~~~~~~~~~~~~
385
386:Description: Voltage ramp time for short-to-power and short-to-ground detection.
387:Type:        Enumerated
388:Default:     5 ms
389:Options:     5 ms, 2.5 ms, 10 ms, 15 ms
390:Register:    0xB2 bits [3:2]
391
392DC LDG S2PG Settling Time
393~~~~~~~~~~~~~~~~~~~~~~~~~~
394
395:Description: Settling time for short-to-power and short-to-ground detection.
396:Type:        Enumerated
397:Default:     10 ms
398:Options:     10 ms, 5 ms, 20 ms, 30 ms
399:Register:    0xB2 bits [1:0]
400
401CHx DC LDG SL Threshold
402~~~~~~~~~~~~~~~~~~~~~~~~
403
404:Description: Shorted-load detection threshold per channel (x = 1, 2, 3, 4).
405:Type:        Enumerated
406:Default:     1 Ohm
407:Options:     0.5 Ohm, 1 Ohm, 1.5 Ohm, 2 Ohm, 2.5 Ohm,
408              3 Ohm, 3.5 Ohm, 4 Ohm, 4.5 Ohm, 5 Ohm
409:Register:    0xB3 bits [7:4] (CH1), bits [3:0] (CH2),
410              0xB4 bits [7:4] (CH3), bits [3:0] (CH4)
411
412DC LDG Result
413~~~~~~~~~~~~~
414
415:Description: Overall DC diagnostic result register.
416:Type:        Integer (read-only)
417:Range:       0x00 to 0xFF
418:Register:    0xC2
419:Bit Encoding:
420
421  ========  =====================================================
422  Bits      Description
423  ========  =====================================================
424  [7:4]     Line output detection result, one bit per channel
425  [3:0]     DC diagnostic pass/fail per channel (1=pass, 0=fail)
426  ========  =====================================================
427
428CHx DC LDG Report
429~~~~~~~~~~~~~~~~~
430
431:Description: DC diagnostic fault status per channel (x = 1, 2, 3, 4).
432:Type:        Integer (read-only)
433:Range:       0x0 to 0xF
434:Register:    0xC0 bits [7:4] (CH1), bits [3:0] (CH2),
435              0xC1 bits [7:4] (CH3), bits [3:0] (CH4)
436:Note:        See fault bit encoding table at the start of this section.
437
438CHx LO LDG Report
439~~~~~~~~~~~~~~~~~
440
441:Description: Line output load detection result per channel (x = 1, 2, 3, 4).
442:Type:        Boolean (read-only)
443:Values:      0 = not detected, 1 = line output load detected
444:Register:    0xC2 bit [7] (CH1), bit [6] (CH2), bit [5] (CH3), bit [4] (CH4)
445
446CHx DC Resistance
447~~~~~~~~~~~~~~~~~
448
449:Description: Measured DC load resistance per channel (x = 1, 2, 3, 4).
450:Type:        Float (read-only, displayed in ohms)
451:Resolution:  0.1 ohm per code (10-bit value)
452:Range:       0.0 to 102.3 ohms
453:Register:    0xD9 bits [7:6]/[5:4]/[3:2]/[1:0] (MSB for CH1–CH4),
454              0xDA (CH1 LSB), 0xDB (CH2 LSB), 0xDC (CH3 LSB), 0xDD (CH4 LSB)
455
456AC Load Diagnostics
457-------------------
458
459AC LDG Trigger
460~~~~~~~~~~~~~~
461
462:Description: Triggers AC impedance measurement on all channels.
463:Type:        Boolean (write-only)
464:Note:        Returns -EBUSY if any DAI stream (playback or capture) is active.
465              The driver transitions all channels to SLEEP state before starting
466              the measurement. Blocks until diagnostics complete or time out.
467
468AC LDG Gain
469~~~~~~~~~~~
470
471:Description: Measurement resolution for AC diagnostics.
472:Type:        Boolean Switch
473:Default:     1 (Gain 8)
474:Values:      0 = 0.8 ohm/code (Gain 1), 1 = 0.1 ohm/code (Gain 8)
475:Register:    0xB5 bit [4]
476:Note:        Gain 8 recommended for load impedances below 8 ohms.
477
478AC LDG Test Frequency
479~~~~~~~~~~~~~~~~~~~~~
480
481:Description: Test signal frequency for AC impedance measurement.
482:Type:        Integer
483:Default:     200 (0xC8 = 18.75 kHz)
484:Range:       0x01 to 0xFF (0x00 reserved)
485:Formula:     Frequency = 93.75 Hz × register value
486:Register:    0xB8
487
488CHx AC LDG Real / CHx AC LDG Imag
489~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
490
491:Description: Real and imaginary AC impedance components per channel
492              (x = 1, 2, 3, 4).
493:Type:        Integer (read-only)
494:Range:       0x00 to 0xFF (8-bit signed)
495:Register:    0xC3 (CH1 Real), 0xC4 (CH1 Imag), 0xC5 (CH2 Real), 0xC6 (CH2 Imag),
496              0xC7 (CH3 Real), 0xC8 (CH3 Imag), 0xC9 (CH4 Real), 0xCA (CH4 Imag)
497:Note:        Scale set by AC LDG Gain.
498
499Speaker Protection & Detection
500-------------------------------
501
502Tweeter Detection Switch
503~~~~~~~~~~~~~~~~~~~~~~~~
504
505:Description: Enables tweeter detection using the AC impedance magnitude comparator.
506:Type:        Boolean Switch
507:Default:     Enabled (1)
508:Register:    0xB6 bit [0]
509:Note:        The underlying register bit is TWEETER DETECT DISABLE (active-low).
510              Control value 1 = detection enabled (register bit 0), 0 = disabled
511              (register bit 1).
512
513Tweeter Detect Threshold
514~~~~~~~~~~~~~~~~~~~~~~~~~
515
516:Description: Magnitude threshold for tweeter detection.
517:Type:        Integer
518:Default:     0
519:Range:       0x00 to 0xFF
520:Resolution:  0.8 ohm/code (AC LDG Gain=0) or 0.1 ohm/code (AC LDG Gain=1)
521:Register:    0xB7
522
523CHx Tweeter Detect Report
524~~~~~~~~~~~~~~~~~~~~~~~~~~
525
526:Description: Tweeter detection result per channel (x = 1, 2, 3, 4).
527:Type:        Boolean (read-only)
528:Values:      0 = no tweeter detected, 1 = tweeter detected
529:Register:    0xCB bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
530
531DSP Protection Features
532=======================
533
534These controls are unavailable in LLP mode.
535
536Thermal Foldback Switch
537-----------------------
538
539:Description: Enables dynamic gain reduction based on die temperature.
540:Type:        Boolean Switch
541:Default:     Disabled (0)
542:Register:    0x3A bit [0]
543
544PVDD Foldback Switch
545--------------------
546
547:Description: Enables automatic gain limiting when supply voltage drops
548              (Automatic Gain Limiter).
549:Type:        Boolean Switch
550:Default:     Disabled (0)
551:Register:    0x3A bit [4]
552
553DC Blocker Bypass Switch
554------------------------
555
556:Description: Bypasses the DC-blocking high-pass filter.
557:Type:        Boolean Switch
558:Default:     Not bypassed (0)
559:Register:    0x39 bit [0]
560
561Clip Detect Switch
562------------------
563
564:Description: Enables DSP-based clip detection (Pseudo-Analog Clip Detect).
565:Type:        Boolean Switch
566:Default:     Disabled (0)
567:Register:    0x93 bit [6]
568
569Audio SDOUT Switch
570------------------
571
572:Description: Routes post-processed audio to the SDOUT pin instead of
573              Vpredict data.
574:Type:        Boolean Switch
575:Default:     Disabled (0)
576:Register:    0x3A bit [5]
577:Note:        When enabled, replaces Vpredict data on SDOUT with post-processed
578              SDIN. All SDOUT configurations that apply to Vpredict also apply
579              to SDIN-to-SDOUT transmission.
580
581Real-Time Load Diagnostics
582===========================
583
584These controls require Normal DSP mode at 48 kHz or 96 kHz. They are
585unavailable at 192 kHz and in FFLP and LLP modes.
586
587
588CHx RTLDG Switch
589----------------
590
591:Description: Enables real-time impedance monitoring during playback
592              (x = 1, 2, 3, 4).
593:Type:        Boolean Switch
594:Default:     Disabled (0)
595:Register:    0x37 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
596
597RTLDG Clip Mask Switch
598----------------------
599
600:Description: Suppresses impedance updates during clipping events.
601:Type:        Boolean Switch
602:Default:     Enabled (1)
603:Register:    0x37 bit [4]
604
605ISENSE Calibration Switch
606--------------------------
607
608:Description: Enables current sense calibration for accurate impedance
609              measurements.
610:Type:        Boolean Switch
611:Default:     Disabled (0)
612:Register:    0x5B bit [3]
613
614RTLDG Open Load Threshold
615--------------------------
616
617:Description: DSP coefficient for open load fault detection threshold.
618:Type:        DSP coefficient (extended control)
619:Register:    DSP Book 0x8C, page 0x22, 0x98
620
621RTLDG Short Load Threshold
622---------------------------
623
624:Description: DSP coefficient for shorted load fault detection threshold.
625:Type:        DSP coefficient (extended control)
626:Register:    DSP Book 0x8C, page 0x22, 0x9C
627
628CHx RTLDG Impedance
629-------------------
630
631:Description: Real-time load impedance per channel (x = 1, 2, 3, 4).
632:Type:        Float (read-only, displayed in ohms)
633:Register:    0xD1–0xD2 (CH1), 0xD3–0xD4 (CH2), 0xD5–0xD6 (CH3), 0xD7–0xD8 (CH4)
634:Note:        Valid only during PLAY state with RTLDG enabled at 48 or
635              96 kHz. Holds stale data in SLEEP, MUTE, or Hi-Z states.
636
637Fault Monitoring
638================
639
640The driver monitors faults via IRQ or periodic polling (fallback when
641no ``interrupts`` DT property is present). Detected faults are logged
642and cleared so affected channels can recover.
643
644Kernel log messages use the format::
645
646  tas675x <addr>: <Name> Latched: 0x<value>
647
648Critical faults are logged at ``CRIT`` level; warnings at ``WARN``.
649
650The following fault registers are monitored:
651
652Critical Faults
653---------------
654
655These faults place affected channels into the FAULT state. The driver
656issues fault clear (register 0x01 bit 3) to allow recovery.
657
658Overtemperature Shutdown (0x87)
659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
660
661  ========  ==========================================
662  Bits      Description
663  ========  ==========================================
664  [4]       Global OTSD
665  [3:0]     CH1-CH4 OTSD respectively
666  ========  ==========================================
667
668Fires when die temperature exceeds the OTSD threshold. If auto-recovery
669is enabled (``OTSD Auto Recovery Switch``), channels return to their
670previous state after cooling. Otherwise fault clear is required.
671
672Overcurrent / DC Fault (0x8E)
673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
674
675  ========  ==========================================
676  Bits      Description
677  ========  ==========================================
678  [7:4]     Overcurrent Shutdown, CH1-CH4 respectively
679  [3:0]     DC Fault, CH1-CH4 respectively
680  ========  ==========================================
681
682Overcurrent shutdown occurs when output current reaches the shutdown
683threshold (e.g. output short to GND). DC fault fires when DC offset
684exceeds the DCFAULT threshold.
685
686Real-Time Load Diagnostic Fault (0x8B)
687~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
688
689  ========  ==========================================
690  Bits      Description
691  ========  ==========================================
692  [7:4]     Shorted Load faults, CH1-CH4 respectively
693  [3:0]     Open Load faults, CH1-CH4 respectively
694  ========  ==========================================
695
696Reported during playback when RTLDG detects impedance outside the
697configured open/short thresholds. Requires RTLDG and current sense to
698be enabled, and a sampling rate of 48 kHz or 96 kHz.
699
700CBC Fault/Warning (0x8D)
701~~~~~~~~~~~~~~~~~~~~~~~~
702
703  ========  ==========================================
704  Bits      Description
705  ========  ==========================================
706  [7:4]     Load current warning, CH1-CH4 respectively
707  [3:0]     Load current fault, CH1-CH4 respectively
708  ========  ==========================================
709
710Cycle-by-cycle current limiting events. A warning fires when the
711current limit is active for at least 25% of a 21.3 ms window. A fault
712fires if the warning persists for 170.4 ms continuously.
713
714Warnings
715--------
716
717These conditions are logged but do not place channels into FAULT state.
718Corresponding register bits are cleared when read. Nonetheless, the driver
719still clears all events as warnings also latch the (mapped) FAULT pin.
720
721Power Fault (0x86)
722~~~~~~~~~~~~~~~~~~
723
724  ========  ==========================================
725  Bits      Description
726  ========  ==========================================
727  [7]       DVDD Power-On-Reset
728  [4]       DVDD Undervoltage
729  [3]       PVDD Overvoltage
730  [2]       VBAT Overvoltage
731  [1]       PVDD Undervoltage
732  [0]       VBAT Undervoltage
733  ========  ==========================================
734
735Supply-related events. DVDD POR at bit 7 is expected after every
736power-up and can be ignored.
737
738CP / OUTM Soft Short Fault (0x7D)
739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
740
741  ========  ==========================================
742  Bits      Description
743  ========  ==========================================
744  [5:2]     OUTM soft short, CH4-CH1 respectively
745  [1]       Charge Pump UVLO (latched)
746  [0]       Charge Pump UVLO (unlatched/live status)
747  ========  ==========================================
748
749Per-channel out_minus soft short faults and charge pump undervoltage lockout.
750
751Clock Fault (0x8A)
752~~~~~~~~~~~~~~~~~~
753
754  ========  ==========================================
755  Bits      Description
756  ========  ==========================================
757  [0]       Clock error
758  ========  ==========================================
759
760Fires on clock halt or unsupported SCLK/FSYNC ratio. Only logged when
761a stream is active (suppressed during idle to avoid noise from normal
762stream stop/start transitions). See `Clock Fault Behaviour`_ below.
763
764Overtemperature Warning (0x88)
765~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
766
767  ========  ==========================================
768  Bits      Description
769  ========  ==========================================
770  [4]       Global OTW
771  [3:0]     CH1-CH4 OTW respectively
772  ========  ==========================================
773
774Fires when temperature crosses the OTW threshold. The device continues
775to operate. Only logged on change to avoid log spam.
776
777Clip Warning (0x89)
778~~~~~~~~~~~~~~~~~~~
779
780  ========  ==========================================
781  Bits      Description
782  ========  ==========================================
783  [3:0]     CH1-CH4 clip detected respectively
784  ========  ==========================================
785
786Fires when the audio signal magnitude exceeds the clip detection
787threshold. Requires Clip Detect to be enabled. Only logged when a
788stream is active.
789
790Driver Known Limitations
791========================
792
793Clock Fault Behaviour
794---------------------
795
796On Stream Stop
797~~~~~~~~~~~~~~
798
799Every time a playback stream stops the FAULT pin briefly asserts. The
800ASoC PCM trigger stop sequence calls DAIs in reverse order, so the CPU
801DAI stops SCLK before the codec can transition to sleep. The device
802detects the clock halt and latches ``CLK_FAULT_LATCHED``, which asserts
803the FAULT pin. The driver clears the latch in the ``mute_stream``
804callback that follows, so the FAULT pin flicker lasts only a few
805milliseconds. Audio output is not affected and no kernel log message
806is produced.
807
808On Rapid Rate Switching
809~~~~~~~~~~~~~~~~~~~~~~~
810
811When streams are started in rapid succession, an intermittent
812``Clock Fault Latched: 0x01`` message may appear in the kernel log.
813A (conservative) ~0.5 second gap between sessions eliminates this.
814
815References
816==========
817
818- TAS675x Technical Reference Manual: SLOU589A
819- Device Tree Bindings: Documentation/devicetree/bindings/sound/ti,tas67524.yaml
820- ALSA Control Name Conventions: Documentation/sound/designs/control-names.rst
821