xref: /linux/Documentation/sound/codecs/tas675x.rst (revision fab183d632628381b466a41479489541ac0e29a0) 
1.. SPDX-License-Identifier: GPL-2.0
2
3======================================
4TAS675x Codec Mixer Controls
5======================================
6
7This document describes the ALSA mixer controls for the TAS675x
84-channel amplifier driver.
9
10For device tree bindings, see:
11Documentation/devicetree/bindings/sound/ti,tas67524.yaml
12
13DSP Signal Path Mode
14====================
15
16DSP Signal Path Mode
17--------------------
18
19:Description: Signal processing mode selection.
20:Type:        Enumerated
21:Default:     Normal
22:Options:     Normal, LLP, FFLP
23:Register:    0x32 bits [1:0]
24
25Normal
26  Full DSP with all features available.
27
28LLP (Low Latency Path)
29  Bypasses DSP processing. DSP protection features (Thermal Foldback,
30  PVDD Foldback, Clip Detect) and Real-Time Load Diagnostics unavailable.
31
32FFLP (Full Feature Low Latency Path)
33  Reduced latency. Real-Time Load Diagnostics unavailable.
34
35The following controls are unavailable in LLP mode:
36``Thermal Foldback Switch``, ``PVDD Foldback Switch``,
37``DC Blocker Bypass Switch``, ``Clip Detect Switch``, ``Audio SDOUT Switch``.
38
39The following controls require Normal mode (unavailable in FFLP and LLP):
40``CHx RTLDG Switch``, ``RTLDG Clip Mask Switch``, ``ISENSE Calibration Switch``,
41``RTLDG Open Load Threshold``, ``RTLDG Short Load Threshold``,
42``CHx RTLDG Impedance``.
43
44Volume Controls
45===============
46
47Analog Playback Volume
48----------------------
49
50:Description: Analog output gain for all channels (CH1/CH2 and CH3/CH4 pairs).
51:Type:        Volume (TLV)
52:Default:     0 dB
53:Range:       -15.5 dB to 0 dB (0.5 dB steps)
54:Register:    0x4A (CH1/CH2), 0x4B (CH3/CH4)
55
56Analog Gain Ramp Step
57---------------------
58
59:Description: Anti-pop ramp step duration for analog gain transitions.
60:Type:        Enumerated
61:Default:     15us
62:Options:     15us, 60us, 200us, 400us
63:Register:    0x4E bits [3:2]
64
65CHx Digital Playback Volume
66---------------------------
67
68:Description: Per-channel digital volume control (x = 1, 2, 3, 4).
69:Type:        Volume (TLV)
70:Default:     0 dB
71:Range:       -103 dB to 0 dB (0.5 dB steps)
72:Bounds:      0x30 (min/mute) to 0xFF (max)
73:Register:    0x40 (CH1), 0x41 (CH2), 0x42 (CH3), 0x43 (CH4)
74
75Volume Ramp Down Rate
76---------------------
77
78:Description: Update frequency during mute transition.
79:Type:        Enumerated
80:Default:     16 FS
81:Options:     4 FS, 16 FS, 32 FS, Instant
82:Register:    0x44 bits [7:6]
83
84Volume Ramp Down Step
85---------------------
86
87:Description: dB change per update during mute.
88:Type:        Enumerated
89:Default:     0.5dB
90:Options:     4dB, 2dB, 1dB, 0.5dB
91:Register:    0x44 bits [5:4]
92
93Volume Ramp Up Rate
94-------------------
95
96:Description: Update frequency during unmute transition.
97:Type:        Enumerated
98:Default:     16 FS
99:Options:     4 FS, 16 FS, 32 FS, Instant
100:Register:    0x44 bits [3:2]
101
102Volume Ramp Up Step
103-------------------
104
105:Description: dB change per update during unmute.
106:Type:        Enumerated
107:Default:     0.5dB
108:Options:     4dB, 2dB, 1dB, 0.5dB
109:Register:    0x44 bits [1:0]
110
111CH1/2 Volume Combine
112--------------------
113
114:Description: Links digital volume controls for CH1 and CH2.
115:Type:        Enumerated
116:Default:     Independent
117:Options:     Independent, CH2 follows CH1, CH1 follows CH2
118:Register:    0x46 bits [1:0]
119
120CH3/4 Volume Combine
121--------------------
122
123:Description: Links digital volume controls for CH3 and CH4.
124:Type:        Enumerated
125:Default:     Independent
126:Options:     Independent, CH4 follows CH3, CH3 follows CH4
127:Register:    0x46 bits [3:2]
128
129Auto Mute & Silence Detection
130==============================
131
132CHx Auto Mute Switch
133--------------------
134
135:Description: Enables automatic muting on zero-signal detection (x = 1, 2, 3, 4).
136:Type:        Boolean Switch
137:Default:     Disabled (0)
138:Register:    0x47 bit [0] (CH1), bit [1] (CH2), bit [2] (CH3), bit [3] (CH4)
139
140Auto Mute Combine Switch
141------------------------
142
143:Description: Coordinated muting behaviour across all channels.
144:Type:        Boolean Switch
145:Default:     Disabled (0)
146:Behavior:    Disabled: channels mute independently when their signal is zero.
147              Enabled: all channels mute together only when all detect zero
148              signal; unmute when any channel has non-zero signal.
149:Register:    0x47 bit [4]
150
151CHx Auto Mute Time
152------------------
153
154:Description: Duration of zero signal before muting triggers (x = 1, 2, 3, 4).
155:Type:        Enumerated
156:Default:     11.5ms
157:Options:     11.5ms, 53ms, 106.5ms, 266.5ms, 535ms, 1065ms, 2665ms, 5330ms
158:Register:    0x48 bits [7:4] (CH1), bits [3:0] (CH2),
159              0x49 bits [7:4] (CH3), bits [3:0] (CH4)
160:Note:        Values are at 96 kHz. At 48 kHz, times are doubled.
161
162Clock & EMI Management
163======================
164
165Spread Spectrum Mode
166--------------------
167
168:Description: Frequency dithering mode to reduce peak EMI.
169:Type:        Enumerated
170:Default:     Disabled
171:Options:     Disabled, Triangle, Random, Triangle and Random
172:Register:    0x61 bits [1:0]
173
174SS Triangle Range
175-----------------
176
177:Description: Frequency deviation range for Triangle spread spectrum.
178:Type:        Enumerated
179:Default:     6.5%
180:Options:     6.5%, 13.5%, 5%, 10%
181:Register:    0x62 bits [1:0]
182:Note:        Applies only when Spread Spectrum Mode includes Triangle.
183
184SS Random Range
185---------------
186
187:Description: Frequency deviation range for Random spread spectrum.
188:Type:        Enumerated
189:Default:     0.83%
190:Options:     0.83%, 2.50%, 5.83%, 12.50%, 25.83%
191:Register:    0x62 bits [6:4]
192:Note:        Applies only when Spread Spectrum Mode includes Random.
193
194SS Random Dwell Range
195---------------------
196
197:Description: Dwell time range for Random spread spectrum (FSS = spread
198              spectrum modulation frequency).
199:Type:        Enumerated
200:Default:     1/FSS to 2/FSS
201:Options:     1/FSS to 2/FSS, 1/FSS to 4/FSS, 1/FSS to 8/FSS, 1/FSS to 15/FSS
202:Register:    0x62 bits [3:2]
203:Note:        Applies only when Spread Spectrum Mode includes Random.
204
205SS Triangle Dwell Min
206---------------------
207
208:Description: Minimum dwell time at Triangle spread spectrum frequency extremes.
209:Type:        Integer
210:Default:     0
211:Range:       0 to 15 (0 = feature disabled)
212:Register:    0x66 bits [7:4]
213:Note:        Counts in FSS clock cycles. The modulator holds the extreme
214              frequency for at least this many FSS cycles before reversing.
215              When Dwell Min equals Dwell Max, the dwell feature is inactive.
216              For FSS values at each PWM frequency refer to the "Spread
217              Spectrum" section of the TRM.
218
219SS Triangle Dwell Max
220---------------------
221
222:Description: Maximum dwell time at Triangle spread spectrum frequency extremes.
223:Type:        Integer
224:Default:     0
225:Range:       0 to 15 (0 = feature disabled)
226:Register:    0x66 bits [3:0]
227:Note:        Counts in FSS clock cycles. Must be >= Dwell Min. When Dwell Max
228              equals Dwell Min, the dwell feature is inactive.
229
230Hardware Protection
231===================
232
233OTSD Auto Recovery Switch
234--------------------------
235
236:Description: Enables automatic recovery from over-temperature shutdown.
237:Type:        Boolean Switch
238:Default:     Disabled (0)
239:Register:    0x8F bit [1]
240:Note:        When disabled, manual fault clearing is required after OTSD events.
241
242Overcurrent Limit Level
243-----------------------
244
245:Description: Current-limit trip point sensitivity.
246:Type:        Enumerated
247:Default:     Level 4
248:Options:     Level 4, Level 3, Level 2, Level 1
249:Register:    0x55 bits [1:0]
250:Note:        Level 4 is the least sensitive (highest trip current); Level 1 is
251              the most sensitive. The exact ILIM values depend on operating
252              conditions (PVDD voltage, switching frequency, and temperature).
253              Refer to the Electrical Characteristics table and the
254              "Overcurrent Limit (Cycle-By-Cycle)" section of the TRM.
255
256CHx OTW Threshold
257-----------------
258
259:Description: Over-temperature warning threshold per channel (x = 1, 2, 3, 4).
260:Type:        Enumerated
261:Default:     >95C
262:Options:     Disabled, >95C, >110C, >125C, >135C, >145C, >155C, >165C
263:Register:    0xE2 bits [6:4] (CH1), bits [2:0] (CH2),
264              0xE3 bits [6:4] (CH3), bits [2:0] (CH4)
265
266Temperature and Voltage Monitoring
267===================================
268
269PVDD Sense
270----------
271
272:Description: Supply voltage sense register.
273:Type:        Integer (read-only)
274:Range:       0 to 255
275:Conversion:  value × 0.19 V
276:Register:    0x74
277
278Global Temperature
279------------------
280
281:Description: Global die temperature sense register.
282:Type:        Integer (read-only)
283:Range:       0 to 255
284:Conversion:  value × 2.19 K; subtract 273.15 for °C
285:Register:    0x75
286
287CHx Temperature Range
288---------------------
289
290:Description: Per-channel coarse temperature range indicator (x = 1, 2, 3, 4).
291:Type:        Integer (read-only)
292:Range:       0 to 7
293:Mapping:     0 = <95 °C, 1 = 95–110 °C, 2 = 110–125 °C, 3 = 125–135 °C,
294              4 = 135–145 °C, 5 = 145–155 °C, 6 = 155–165 °C, 7 = >165 °C
295:Register:    0xBB bits [2:0] (CH1), bits [5:3] (CH2),
296              0xBC bits [2:0] (CH3), bits [5:3] (CH4)
297
298Load Diagnostics
299================
300
301The TAS675x provides three load diagnostic modes:
302
303DC Load Diagnostics (DC LDG)
304  Measures DC resistance to detect S2G (short-to-ground), S2P
305  (short-to-power), OL (open load), and SL (shorted load) faults.
306
307AC Load Diagnostics (AC LDG)
308  Measures complex AC impedance at a configurable frequency. Detects
309  capacitive loads and tweeter configurations.
310
311Real-Time Load Diagnostics (RTLDG)
312  Monitors impedance continuously during playback using a pilot tone.
313  Normal DSP mode only, at 48 kHz or 96 kHz.
314
315Fast Boot Mode
316--------------
317
318By default the device runs DC load diagnostics at initialization before
319accepting audio. Setting ``ti,fast-boot`` in the device tree bypasses this
320initial diagnostic run for faster startup. Automatic diagnostics after
321fault recovery remain enabled.
322
323DC Load Diagnostics
324-------------------
325
326The ``CHx DC LDG Report`` 4-bit fault field uses the following encoding:
327
328  ======  ===========  ===================================================
329  Bit     Fault        Description
330  ======  ===========  ===================================================
331  [3]     S2G          Short-to-Ground
332  [2]     S2P          Short-to-Power
333  [1]     OL           Open Load
334  [0]     SL           Shorted Load
335  ======  ===========  ===================================================
336
337DC LDG Trigger
338~~~~~~~~~~~~~~
339
340:Description: Triggers manual DC load diagnostics on all channels.
341:Type:        Boolean (write-only)
342:Note:        Returns -EBUSY if any DAI stream (playback or capture) is active.
343              The driver manages all channel state transitions. Blocks until
344              diagnostics complete or time out (300 ms).
345
346DC LDG Auto Diagnostics Switch
347~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
348
349:Description: Enables automatic DC diagnostics after fault recovery.
350:Type:        Boolean Switch
351:Default:     Enabled (1)
352:Register:    0xB0 bit [0]
353:Note:        Active-low, when enabled, affected channels re-run diagnostics after
354              fault recovery and retry approximately every 750 ms until resolved.
355
356CHx LO LDG Switch
357~~~~~~~~~~~~~~~~~
358
359:Description: Enables line output load detection per channel (x = 1, 2, 3, 4).
360:Type:        Boolean Switch
361:Default:     Disabled (0)
362:Register:    0xB1 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
363:Note:        When enabled and DC diagnostics report OL, the device tests for
364              a high-impedance line output load.
365
366DC LDG SLOL Ramp Time
367~~~~~~~~~~~~~~~~~~~~~
368
369:Description: Voltage ramp time for shorted-load and open-load detection.
370:Type:        Enumerated
371:Default:     15 ms
372:Options:     15 ms, 30 ms, 10 ms, 20 ms
373:Register:    0xB2 bits [7:6]
374
375DC LDG SLOL Settling Time
376~~~~~~~~~~~~~~~~~~~~~~~~~~
377
378:Description: Settling time for shorted-load and open-load detection.
379:Type:        Enumerated
380:Default:     10 ms
381:Options:     10 ms, 5 ms, 20 ms, 15 ms
382:Register:    0xB2 bits [5:4]
383
384DC LDG S2PG Ramp Time
385~~~~~~~~~~~~~~~~~~~~~
386
387:Description: Voltage ramp time for short-to-power and short-to-ground detection.
388:Type:        Enumerated
389:Default:     5 ms
390:Options:     5 ms, 2.5 ms, 10 ms, 15 ms
391:Register:    0xB2 bits [3:2]
392
393DC LDG S2PG Settling Time
394~~~~~~~~~~~~~~~~~~~~~~~~~~
395
396:Description: Settling time for short-to-power and short-to-ground detection.
397:Type:        Enumerated
398:Default:     10 ms
399:Options:     10 ms, 5 ms, 20 ms, 30 ms
400:Register:    0xB2 bits [1:0]
401
402CHx DC LDG SL Threshold
403~~~~~~~~~~~~~~~~~~~~~~~~
404
405:Description: Shorted-load detection threshold per channel (x = 1, 2, 3, 4).
406:Type:        Enumerated
407:Default:     1 Ohm
408:Options:     0.5 Ohm, 1 Ohm, 1.5 Ohm, 2 Ohm, 2.5 Ohm,
409              3 Ohm, 3.5 Ohm, 4 Ohm, 4.5 Ohm, 5 Ohm
410:Register:    0xB3 bits [7:4] (CH1), bits [3:0] (CH2),
411              0xB4 bits [7:4] (CH3), bits [3:0] (CH4)
412
413DC LDG Result
414~~~~~~~~~~~~~
415
416:Description: Overall DC diagnostic result register.
417:Type:        Integer (read-only)
418:Range:       0x00 to 0xFF
419:Register:    0xC2
420:Bit Encoding:
421
422  ========  =====================================================
423  Bits      Description
424  ========  =====================================================
425  [7:4]     Line output detection result, one bit per channel
426  [3:0]     DC diagnostic pass/fail per channel (1=pass, 0=fail)
427  ========  =====================================================
428
429CHx DC LDG Report
430~~~~~~~~~~~~~~~~~
431
432:Description: DC diagnostic fault status per channel (x = 1, 2, 3, 4).
433:Type:        Integer (read-only)
434:Range:       0x0 to 0xF
435:Register:    0xC0 bits [7:4] (CH1), bits [3:0] (CH2),
436              0xC1 bits [7:4] (CH3), bits [3:0] (CH4)
437:Note:        See fault bit encoding table at the start of this section.
438
439CHx LO LDG Report
440~~~~~~~~~~~~~~~~~
441
442:Description: Line output load detection result per channel (x = 1, 2, 3, 4).
443:Type:        Boolean (read-only)
444:Values:      0 = not detected, 1 = line output load detected
445:Register:    0xC2 bit [7] (CH1), bit [6] (CH2), bit [5] (CH3), bit [4] (CH4)
446
447CHx DC Resistance
448~~~~~~~~~~~~~~~~~
449
450:Description: Measured DC load resistance per channel (x = 1, 2, 3, 4).
451:Type:        Float (read-only, displayed in ohms)
452:Resolution:  0.1 ohm per code (10-bit value)
453:Range:       0.0 to 102.3 ohms
454:Register:    0xD9 bits [7:6]/[5:4]/[3:2]/[1:0] (MSB for CH1–CH4),
455              0xDA (CH1 LSB), 0xDB (CH2 LSB), 0xDC (CH3 LSB), 0xDD (CH4 LSB)
456
457AC Load Diagnostics
458-------------------
459
460AC LDG Trigger
461~~~~~~~~~~~~~~
462
463:Description: Triggers AC impedance measurement on all channels.
464:Type:        Boolean (write-only)
465:Note:        Returns -EBUSY if any DAI stream (playback or capture) is active.
466              The driver transitions all channels to SLEEP state before starting
467              the measurement. Blocks until diagnostics complete or time out.
468
469AC LDG Gain
470~~~~~~~~~~~
471
472:Description: Measurement resolution for AC diagnostics.
473:Type:        Boolean Switch
474:Default:     1 (Gain 8)
475:Values:      0 = 0.8 ohm/code (Gain 1), 1 = 0.1 ohm/code (Gain 8)
476:Register:    0xB5 bit [4]
477:Note:        Gain 8 recommended for load impedances below 8 ohms.
478
479AC LDG Test Frequency
480~~~~~~~~~~~~~~~~~~~~~
481
482:Description: Test signal frequency for AC impedance measurement.
483:Type:        Integer
484:Default:     200 (0xC8 = 18.75 kHz)
485:Range:       0x01 to 0xFF (0x00 reserved)
486:Formula:     Frequency = 93.75 Hz × register value
487:Register:    0xB8
488
489CHx AC LDG Real / CHx AC LDG Imag
490~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
491
492:Description: Real and imaginary AC impedance components per channel
493              (x = 1, 2, 3, 4).
494:Type:        Integer (read-only)
495:Range:       0x00 to 0xFF (8-bit signed)
496:Register:    0xC3 (CH1 Real), 0xC4 (CH1 Imag), 0xC5 (CH2 Real), 0xC6 (CH2 Imag),
497              0xC7 (CH3 Real), 0xC8 (CH3 Imag), 0xC9 (CH4 Real), 0xCA (CH4 Imag)
498:Note:        Scale set by AC LDG Gain.
499
500Speaker Protection & Detection
501-------------------------------
502
503Tweeter Detection Switch
504~~~~~~~~~~~~~~~~~~~~~~~~
505
506:Description: Enables tweeter detection using the AC impedance magnitude comparator.
507:Type:        Boolean Switch
508:Default:     Enabled (1)
509:Register:    0xB6 bit [0]
510:Note:        The underlying register bit is TWEETER DETECT DISABLE (active-low).
511              Control value 1 = detection enabled (register bit 0), 0 = disabled
512              (register bit 1).
513
514Tweeter Detect Threshold
515~~~~~~~~~~~~~~~~~~~~~~~~~
516
517:Description: Magnitude threshold for tweeter detection.
518:Type:        Integer
519:Default:     0
520:Range:       0x00 to 0xFF
521:Resolution:  0.8 ohm/code (AC LDG Gain=0) or 0.1 ohm/code (AC LDG Gain=1)
522:Register:    0xB7
523
524CHx Tweeter Detect Report
525~~~~~~~~~~~~~~~~~~~~~~~~~~
526
527:Description: Tweeter detection result per channel (x = 1, 2, 3, 4).
528:Type:        Boolean (read-only)
529:Values:      0 = no tweeter detected, 1 = tweeter detected
530:Register:    0xCB bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
531
532DSP Protection Features
533=======================
534
535These controls are unavailable in LLP mode.
536
537Thermal Foldback Switch
538-----------------------
539
540:Description: Enables dynamic gain reduction based on die temperature.
541:Type:        Boolean Switch
542:Default:     Disabled (0)
543:Register:    0x3A bit [0]
544
545PVDD Foldback Switch
546--------------------
547
548:Description: Enables automatic gain limiting when supply voltage drops
549              (Automatic Gain Limiter).
550:Type:        Boolean Switch
551:Default:     Disabled (0)
552:Register:    0x3A bit [4]
553
554DC Blocker Bypass Switch
555------------------------
556
557:Description: Bypasses the DC-blocking high-pass filter.
558:Type:        Boolean Switch
559:Default:     Not bypassed (0)
560:Register:    0x39 bit [0]
561
562Clip Detect Switch
563------------------
564
565:Description: Enables DSP-based clip detection (Pseudo-Analog Clip Detect).
566:Type:        Boolean Switch
567:Default:     Disabled (0)
568:Register:    0x93 bit [6]
569
570Audio SDOUT Switch
571------------------
572
573:Description: Routes post-processed audio to the SDOUT pin instead of
574              Vpredict data.
575:Type:        Boolean Switch
576:Default:     Disabled (0)
577:Register:    0x3A bit [5]
578:Note:        When enabled, replaces Vpredict data on SDOUT with post-processed
579              SDIN. All SDOUT configurations that apply to Vpredict also apply
580              to SDIN-to-SDOUT transmission.
581
582Real-Time Load Diagnostics
583===========================
584
585These controls require Normal DSP mode at 48 kHz or 96 kHz. They are
586unavailable at 192 kHz and in FFLP and LLP modes.
587
588
589CHx RTLDG Switch
590----------------
591
592:Description: Enables real-time impedance monitoring during playback
593              (x = 1, 2, 3, 4).
594:Type:        Boolean Switch
595:Default:     Disabled (0)
596:Register:    0x37 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
597
598RTLDG Clip Mask Switch
599----------------------
600
601:Description: Suppresses impedance updates during clipping events.
602:Type:        Boolean Switch
603:Default:     Enabled (1)
604:Register:    0x37 bit [4]
605
606ISENSE Calibration Switch
607--------------------------
608
609:Description: Enables current sense calibration for accurate impedance
610              measurements.
611:Type:        Boolean Switch
612:Default:     Disabled (0)
613:Register:    0x5B bit [3]
614
615RTLDG Open Load Threshold
616--------------------------
617
618:Description: DSP coefficient for open load fault detection threshold.
619:Type:        DSP coefficient (extended control)
620:Register:    DSP Book 0x8C, page 0x22, 0x98
621
622RTLDG Short Load Threshold
623---------------------------
624
625:Description: DSP coefficient for shorted load fault detection threshold.
626:Type:        DSP coefficient (extended control)
627:Register:    DSP Book 0x8C, page 0x22, 0x9C
628
629CHx RTLDG Impedance
630-------------------
631
632:Description: Real-time load impedance per channel (x = 1, 2, 3, 4).
633:Type:        Float (read-only, displayed in ohms)
634:Register:    0xD1–0xD2 (CH1), 0xD3–0xD4 (CH2), 0xD5–0xD6 (CH3), 0xD7–0xD8 (CH4)
635:Note:        Valid only during PLAY state with RTLDG enabled at 48 or
636              96 kHz. Holds stale data in SLEEP, MUTE, or Hi-Z states.
637
638Fault Monitoring
639================
640
641The driver monitors faults via IRQ or periodic polling (fallback when
642no ``interrupts`` DT property is present). Detected faults are logged
643and cleared so affected channels can recover.
644
645Kernel log messages use the format::
646
647  tas675x <addr>: <Name> Latched: 0x<value>
648
649Critical faults are logged at ``CRIT`` level; warnings at ``WARN``.
650
651The following fault registers are monitored:
652
653Critical Faults
654---------------
655
656These faults place affected channels into the FAULT state. The driver
657issues fault clear (register 0x01 bit 3) to allow recovery.
658
659Overtemperature Shutdown (0x87)
660~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
661
662  ========  ==========================================
663  Bits      Description
664  ========  ==========================================
665  [4]       Global OTSD
666  [3:0]     CH1-CH4 OTSD respectively
667  ========  ==========================================
668
669Fires when die temperature exceeds the OTSD threshold. If auto-recovery
670is enabled (``OTSD Auto Recovery Switch``), channels return to their
671previous state after cooling. Otherwise fault clear is required.
672
673Overcurrent / DC Fault (0x8E)
674~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
675
676  ========  ==========================================
677  Bits      Description
678  ========  ==========================================
679  [7:4]     Overcurrent Shutdown, CH1-CH4 respectively
680  [3:0]     DC Fault, CH1-CH4 respectively
681  ========  ==========================================
682
683Overcurrent shutdown occurs when output current reaches the shutdown
684threshold (e.g. output short to GND). DC fault fires when DC offset
685exceeds the DCFAULT threshold.
686
687Real-Time Load Diagnostic Fault (0x8B)
688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
689
690  ========  ==========================================
691  Bits      Description
692  ========  ==========================================
693  [7:4]     Shorted Load faults, CH1-CH4 respectively
694  [3:0]     Open Load faults, CH1-CH4 respectively
695  ========  ==========================================
696
697Reported during playback when RTLDG detects impedance outside the
698configured open/short thresholds. Requires RTLDG and current sense to
699be enabled, and a sampling rate of 48 kHz or 96 kHz.
700
701CBC Fault/Warning (0x8D)
702~~~~~~~~~~~~~~~~~~~~~~~~
703
704  ========  ==========================================
705  Bits      Description
706  ========  ==========================================
707  [7:4]     Load current warning, CH1-CH4 respectively
708  [3:0]     Load current fault, CH1-CH4 respectively
709  ========  ==========================================
710
711Cycle-by-cycle current limiting events. A warning fires when the
712current limit is active for at least 25% of a 21.3 ms window. A fault
713fires if the warning persists for 170.4 ms continuously.
714
715Warnings
716--------
717
718These conditions are logged but do not place channels into FAULT state.
719Corresponding register bits are cleared when read. Nonetheless, the driver
720still clears all events as warnings also latch the (mapped) FAULT pin.
721
722Power Fault (0x86)
723~~~~~~~~~~~~~~~~~~
724
725  ========  ==========================================
726  Bits      Description
727  ========  ==========================================
728  [7]       DVDD Power-On-Reset
729  [4]       DVDD Undervoltage
730  [3]       PVDD Overvoltage
731  [2]       VBAT Overvoltage
732  [1]       PVDD Undervoltage
733  [0]       VBAT Undervoltage
734  ========  ==========================================
735
736Supply-related events. DVDD POR at bit 7 is expected after every
737power-up and can be ignored.
738
739CP / OUTM Soft Short Fault (0x7D)
740~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
741
742  ========  ==========================================
743  Bits      Description
744  ========  ==========================================
745  [5:2]     OUTM soft short, CH4-CH1 respectively
746  [1]       Charge Pump UVLO (latched)
747  [0]       Charge Pump UVLO (unlatched/live status)
748  ========  ==========================================
749
750Per-channel out_minus soft short faults and charge pump undervoltage lockout.
751
752Clock Fault (0x8A)
753~~~~~~~~~~~~~~~~~~
754
755  ========  ==========================================
756  Bits      Description
757  ========  ==========================================
758  [0]       Clock error
759  ========  ==========================================
760
761Fires on clock halt or unsupported SCLK/FSYNC ratio. Only logged when
762a stream is active (suppressed during idle to avoid noise from normal
763stream stop/start transitions). See `Clock Fault Behaviour`_ below.
764
765Overtemperature Warning (0x88)
766~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
767
768  ========  ==========================================
769  Bits      Description
770  ========  ==========================================
771  [4]       Global OTW
772  [3:0]     CH1-CH4 OTW respectively
773  ========  ==========================================
774
775Fires when temperature crosses the OTW threshold. The device continues
776to operate. Only logged on change to avoid log spam.
777
778Clip Warning (0x89)
779~~~~~~~~~~~~~~~~~~~
780
781  ========  ==========================================
782  Bits      Description
783  ========  ==========================================
784  [3:0]     CH1-CH4 clip detected respectively
785  ========  ==========================================
786
787Fires when the audio signal magnitude exceeds the clip detection
788threshold. Requires Clip Detect to be enabled. Only logged when a
789stream is active.
790
791Driver Known Limitations
792========================
793
794Clock Fault Behaviour
795---------------------
796
797On Stream Stop
798~~~~~~~~~~~~~~
799
800Every time a playback stream stops the FAULT pin briefly asserts. The
801ASoC PCM trigger stop sequence calls DAIs in reverse order, so the CPU
802DAI stops SCLK before the codec can transition to sleep. The device
803detects the clock halt and latches ``CLK_FAULT_LATCHED``, which asserts
804the FAULT pin. The driver clears the latch in the ``mute_stream``
805callback that follows, so the FAULT pin flicker lasts only a few
806milliseconds. Audio output is not affected and no kernel log message
807is produced.
808
809On Rapid Rate Switching
810~~~~~~~~~~~~~~~~~~~~~~~
811
812When streams are started in rapid succession, an intermittent
813``Clock Fault Latched: 0x01`` message may appear in the kernel log.
814A (conservative) ~0.5 second gap between sessions eliminates this.
815
816References
817==========
818
819- TAS675x Technical Reference Manual: SLOU589A
820- Device Tree Bindings: Documentation/devicetree/bindings/sound/ti,tas67524.yaml
821- ALSA Control Name Conventions: Documentation/sound/designs/control-names.rst
822