1================== 2 User Mode Queues 3================== 4 5Introduction 6============ 7 8Similar to the KFD, GPU engine queues move into userspace. The idea is to let 9user processes manage their submissions to the GPU engines directly, bypassing 10IOCTL calls to the driver to submit work. This reduces overhead and also allows 11the GPU to submit work to itself. Applications can set up work graphs of jobs 12across multiple GPU engines without needing trips through the CPU. 13 14UMDs directly interface with firmware via per application shared memory areas. 15The main vehicle for this is queue. A queue is a ring buffer with a read 16pointer (rptr) and a write pointer (wptr). The UMD writes IP specific packets 17into the queue and the firmware processes those packets, kicking off work on the 18GPU engines. The CPU in the application (or another queue or device) updates 19the wptr to tell the firmware how far into the ring buffer to process packets 20and the rtpr provides feedback to the UMD on how far the firmware has progressed 21in executing those packets. When the wptr and the rptr are equal, the queue is 22idle. 23 24Theory of Operation 25=================== 26 27The various engines on modern AMD GPUs support multiple queues per engine with a 28scheduling firmware which handles dynamically scheduling user queues on the 29available hardware queue slots. When the number of user queues outnumbers the 30available hardware queue slots, the scheduling firmware dynamically maps and 31unmaps queues based on priority and time quanta. The state of each user queue 32is managed in the kernel driver in an MQD (Memory Queue Descriptor). This is a 33buffer in GPU accessible memory that stores the state of a user queue. The 34scheduling firmware uses the MQD to load the queue state into an HQD (Hardware 35Queue Descriptor) when a user queue is mapped. Each user queue requires a 36number of additional buffers which represent the ring buffer and any metadata 37needed by the engine for runtime operation. On most engines this consists of 38the ring buffer itself, a rptr buffer (where the firmware will shadow the rptr 39to userspace), a wptr buffer (where the application will write the wptr for the 40firmware to fetch it), and a doorbell. A doorbell is a piece of one of the 41device's MMIO BARs which can be mapped to specific user queues. When the 42application writes to the doorbell, it will signal the firmware to take some 43action. Writing to the doorbell wakes the firmware and causes it to fetch the 44wptr and start processing the packets in the queue. Each 4K page of the doorbell 45BAR supports specific offset ranges for specific engines. The doorbell of a 46queue must be mapped into the aperture aligned to the IP used by the queue 47(e.g., GFX, VCN, SDMA, etc.). These doorbell apertures are set up via NBIO 48registers. Doorbells are 32 bit or 64 bit (depending on the engine) chunks of 49the doorbell BAR. A 4K doorbell page provides 512 64-bit doorbells for up to 50512 user queues. A subset of each page is reserved for each IP type supported 51on the device. The user can query the doorbell ranges for each IP via the INFO 52IOCTL. See the IOCTL Interfaces section for more information. 53 54When an application wants to create a user queue, it allocates the necessary 55buffers for the queue (ring buffer, wptr and rptr, context save areas, etc.). 56These can be separate buffers or all part of one larger buffer. The application 57would map the buffer(s) into its GPUVM and use the GPU virtual addresses of for 58the areas of memory they want to use for the user queue. They would also 59allocate a doorbell page for the doorbells used by the user queues. The 60application would then populate the MQD in the USERQ IOCTL structure with the 61GPU virtual addresses and doorbell index they want to use. The user can also 62specify the attributes for the user queue (priority, whether the queue is secure 63for protected content, etc.). The application would then call the USERQ 64CREATE IOCTL to create the queue using the specified MQD details in the IOCTL. 65The kernel driver then validates the MQD provided by the application and 66translates the MQD into the engine specific MQD format for the IP. The IP 67specific MQD would be allocated and the queue would be added to the run list 68maintained by the scheduling firmware. Once the queue has been created, the 69application can write packets directly into the queue, update the wptr, and 70write to the doorbell offset to kick off work in the user queue. 71 72When the application is done with the user queue, it would call the USERQ 73FREE IOCTL to destroy it. The kernel driver would preempt the queue and 74remove it from the scheduling firmware's run list. Then the IP specific MQD 75would be freed and the user queue state would be cleaned up. 76 77Some engines may require the aggregated doorbell too if the engine does not 78support doorbells from unmapped queues. The aggregated doorbell is a special 79page of doorbell space which wakes the scheduler. In cases where the engine may 80be oversubscribed, some queues may not be mapped. If the doorbell is rung when 81the queue is not mapped, the engine firmware may miss the request. Some 82scheduling firmware may work around this by polling wptr shadows when the 83hardware is oversubscribed, other engines may support doorbell updates from 84unmapped queues. In the event that one of these options is not available, the 85kernel driver will map a page of aggregated doorbell space into each GPUVM 86space. The UMD will then update the doorbell and wptr as normal and then write 87to the aggregated doorbell as well. 88 89Special Packets 90--------------- 91 92In order to support legacy implicit synchronization, as well as mixed user and 93kernel queues, we need a synchronization mechanism that is secure. Because 94kernel queues or memory management tasks depend on kernel fences, we need a way 95for user queues to update memory that the kernel can use for a fence, that can't 96be messed with by a bad actor. To support this, we've added a protected fence 97packet. This packet works by writing a monotonically increasing value to 98a memory location that only privileged clients have write access to. User 99queues only have read access. When this packet is executed, the memory location 100is updated and other queues (kernel or user) can see the results. The 101user application would submit this packet in their command stream. The actual 102packet format varies from IP to IP (GFX/Compute, SDMA, VCN, etc.), but the 103behavior is the same. The packet submission is handled in userspace. The 104kernel driver sets up the privileged memory used for each user queue when it 105sets the queues up when the application creates them. 106 107 108Memory Management 109================= 110 111It is assumed that all buffers mapped into the GPUVM space for the process are 112valid when engines on the GPU are running. The kernel driver will only allow 113user queues to run when all buffers are mapped. If there is a memory event that 114requires buffer migration, the kernel driver will preempt the user queues, 115migrate buffers to where they need to be, update the GPUVM page tables and 116invaldidate the TLB, and then resume the user queues. 117 118Interaction with Kernel Queues 119============================== 120 121Depending on the IP and the scheduling firmware, you can enable kernel queues 122and user queues at the same time, however, you are limited by the HQD slots. 123Kernel queues are always mapped so any work that goes into kernel queues will 124take priority. This limits the available HQD slots for user queues. 125 126Not all IPs will support user queues on all GPUs. As such, UMDs will need to 127support both user queues and kernel queues depending on the IP. For example, a 128GPU may support user queues for GFX, compute, and SDMA, but not for VCN, JPEG, 129and VPE. UMDs need to support both. The kernel driver provides a way to 130determine if user queues and kernel queues are supported on a per IP basis. 131UMDs can query this information via the INFO IOCTL and determine whether to use 132kernel queues or user queues for each IP. 133 134Queue Resets 135============ 136 137For most engines, queues can be reset individually. GFX, compute, and SDMA 138queues can be reset individually. When a hung queue is detected, it can be 139reset either via the scheduling firmware or MMIO. Since there are no kernel 140fences for most user queues, they will usually only be detected when some other 141event happens; e.g., a memory event which requires migration of buffers. When 142the queues are preempted, if the queue is hung, the preemption will fail. 143Driver will then look up the queues that failed to preempt and reset them and 144record which queues are hung. 145 146On the UMD side, we will add a USERQ QUERY_STATUS IOCTL to query the queue 147status. UMD will provide the queue id in the IOCTL and the kernel driver 148will check if it has already recorded the queue as hung (e.g., due to failed 149peemption) and report back the status. 150 151IOCTL Interfaces 152================ 153 154GPU virtual addresses used for queues and related data (rptrs, wptrs, context 155save areas, etc.) should be validated by the kernel mode driver to prevent the 156user from specifying invalid GPU virtual addresses. If the user provides 157invalid GPU virtual addresses or doorbell indicies, the IOCTL should return an 158error message. These buffers should also be tracked in the kernel driver so 159that if the user attempts to unmap the buffer(s) from the GPUVM, the umap call 160would return an error. 161 162INFO 163---- 164There are several new INFO queries related to user queues in order to query the 165size of user queue meta data needed for a user queue (e.g., context save areas 166or shadow buffers), whether kernel or user queues or both are supported 167for each IP type, and the offsets for each IP type in each doorbell page. 168 169USERQ 170----- 171The USERQ IOCTL is used for creating, freeing, and querying the status of user 172queues. It supports 3 opcodes: 173 1741. CREATE - Create a user queue. The application provides an MQD-like structure 175 that defines the type of queue and associated metadata and flags for that 176 queue type. Returns the queue id. 1772. FREE - Free a user queue. 1783. QUERY_STATUS - Query that status of a queue. Used to check if the queue is 179 healthy or not. E.g., if the queue has been reset. (WIP) 180 181USERQ_SIGNAL 182------------ 183The USERQ_SIGNAL IOCTL is used to provide a list of sync objects to be signaled. 184 185USERQ_WAIT 186---------- 187The USERQ_WAIT IOCTL is used to provide a list of sync object to be waited on. 188 189Kernel and User Queues 190====================== 191 192In order to properly validate and test performance, we have a driver option to 193select what type of queues are enabled (kernel queues, user queues or both). 194The user_queue driver parameter allows you to enable kernel queues only (0), 195user queues and kernel queues (1), and user queues only (2). Enabling user 196queues only will free up static queue assignments that would otherwise be used 197by kernel queues for use by the scheduling firmware. Some kernel queues are 198required for kernel driver operation and they will always be created. When the 199kernel queues are not enabled, they are not registered with the drm scheduler 200and the CS IOCTL will reject any incoming command submissions which target those 201queue types. Kernel queues only mirrors the behavior on all existing GPUs. 202Enabling both queues allows for backwards compatibility with old userspace while 203still supporting user queues. 204