1.. SPDX-License-Identifier: GPL-2.0 2 3====================================== 4Motorcomm yt8xxx PHY properties (_DSD) 5====================================== 6 7This document describes ACPI _DSD device properties for Motorcomm yt8xxx 8Ethernet PHYs supported by the in-kernel driver in 9``drivers/net/phy/motorcomm.c``. 10 11The properties are exposed on the PHY device object under the MDIO bus ACPI 12device (the same objects that are registered via 13``fwnode_mdiobus_register_phy()``). MAC-side connection properties such as 14``phy-handle`` and ``phy-mode`` are documented in [acpi-mdio-phy]_. 15 16Property names and semantics are intentionally aligned with the Devicetree 17binding [motorcomm-yt8xxx]_ so that the same driver code path 18(``device_property_*`` on ``&phydev->mdio.dev``) can consume firmware 19described either as Devicetree or ACPI _DSD. 20 21UUID and placement 22================== 23 24Per [acpi-dsd-properties-rules]_ and [acpi-mdio-phy]_, properties must be 25placed in an _DSD package using the standard Device Properties UUID:: 26 27 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") 28 29Properties 30========== 31 32Unless noted otherwise, integer properties use the same allowed values and 33defaults as [motorcomm-yt8xxx]_. 34 35``rx-internal-delay-ps`` (u32, optional) 36 RGMII RX internal delay in picoseconds. Only meaningful when the link is 37 using RGMII modes with RX internal delay; see [motorcomm-yt8xxx]_. 38 39``tx-internal-delay-ps`` (u32, optional) 40 RGMII TX internal delay in picoseconds. Only meaningful when the link is 41 using RGMII modes with TX internal delay; see [motorcomm-yt8xxx]_. 42 43``motorcomm,clk-out-frequency-hz`` (u32, optional) 44 Clock output frequency on the PHY clock output pin. Allowed values and 45 default are defined in [motorcomm-yt8xxx]_. 46 47``motorcomm,keep-pll-enabled`` (boolean, optional) 48 If true, keep the PLL enabled even when there is no link (useful for using 49 the clock output without an Ethernet link). See [motorcomm-yt8xxx]_. 50 51``motorcomm,auto-sleep-disabled`` (boolean, optional) 52 If true, disable the PHY auto-sleep behavior described in 53 [motorcomm-yt8xxx]_. 54 55``motorcomm,rx-clk-drv-microamp`` (u32, optional) 56 Drive strength for the ``rx_clk`` RGMII pad in microamps. Allowed values 57 depend on the configured RGMII LDO voltage; see [motorcomm-yt8xxx]_. 58 59``motorcomm,rx-data-drv-microamp`` (u32, optional) 60 Drive strength for the ``rx_data`` and ``rx_ctl`` RGMII pads in microamps. 61 See [motorcomm-yt8xxx]_. 62 63``motorcomm,tx-clk-adj-enabled`` (boolean, optional) 64 Enables adjustments related to ``motorcomm,tx-clk-*-inverted`` usage; see 65 [motorcomm-yt8xxx]_. 66 67``motorcomm,tx-clk-10-inverted`` (boolean, optional) 68``motorcomm,tx-clk-100-inverted`` (boolean, optional) 69``motorcomm,tx-clk-1000-inverted`` (boolean, optional) 70 Per-speed TX clock inversion options; see [motorcomm-yt8xxx]_. 71 72ASL example (illustrative) 73========================== 74 75The example below only shows PHY-local _DSD properties. A real platform 76still needs a MAC ``phy-handle`` and ``phy-mode`` package as in 77[acpi-mdio-phy]_. 78 79.. code-block:: none 80 81 Scope (\_SB.MDI0) 82 { 83 Device (PHY4) 84 { 85 Name (_ADR, 0x4) 86 87 Name (_DSD, Package () { 88 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 89 Package () { 90 Package (2) { "rx-internal-delay-ps", 2100 }, 91 Package (2) { "tx-internal-delay-ps", 150 }, 92 Package (2) { "motorcomm,clk-out-frequency-hz", 0 }, 93 Package (2) { "motorcomm,keep-pll-enabled", 1 }, 94 Package (2) { "motorcomm,auto-sleep-disabled", 1 }, 95 } 96 }) 97 } 98 } 99 100References 101========== 102 103.. [acpi-mdio-phy] Documentation/firmware-guide/acpi/dsd/phy.rst 104.. [acpi-dsd-properties-rules] 105 Documentation/firmware-guide/acpi/DSD-properties-rules.rst 106.. [motorcomm-yt8xxx] 107 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml 108