1============================================ 2PCA953x I²C GPIO expander compatibility list 3============================================ 4 5:Author: Levente Révész <levente.revesz@eilabs.com> 6 7I went through all the datasheets and created this note listing 8chip functions and register layouts. 9 10Overview of chips 11================= 12 13Chips with the basic 4 registers 14-------------------------------- 15 16These chips have 4 register banks: input, output, invert and direction. 17Each of these banks contains (lines/8) registers, one for each GPIO port. 18 19Banks offset is always a power of 2: 20 21- 4 lines -> bank offset is 1 22- 8 lines -> bank offset is 1 23- 16 lines -> bank offset is 2 24- 24 lines -> bank offset is 4 25- 32 lines -> bank offset is 4 26- 40 lines -> bank offset is 8 27 28For example, register layout of GPIO expander with 24 lines: 29 30+------+-----------------+--------+ 31| addr | function | bank | 32+======+=================+========+ 33| 00 | input port0 | | 34+------+-----------------+ | 35| 01 | input port1 | bank 0 | 36+------+-----------------+ | 37| 02 | input port2 | | 38+------+-----------------+--------+ 39| 03 | n/a | | 40+------+-----------------+--------+ 41| 04 | output port0 | | 42+------+-----------------+ | 43| 05 | output port1 | bank 1 | 44+------+-----------------+ | 45| 06 | output port2 | | 46+------+-----------------+--------+ 47| 07 | n/a | | 48+------+-----------------+--------+ 49| 08 | invert port0 | | 50+------+-----------------+ | 51| 09 | invert port1 | bank 2 | 52+------+-----------------+ | 53| 0A | invert port2 | | 54+------+-----------------+--------+ 55| 0B | n/a | | 56+------+-----------------+--------+ 57| 0C | direction port0 | | 58+------+-----------------+ | 59| 0D | direction port1 | bank 3 | 60+------+-----------------+ | 61| 0E | direction port2 | | 62+------+-----------------+--------+ 63| 0F | n/a | | 64+------+-----------------+--------+ 65 66.. note:: 67 This is followed by all supported chips, except by pcal6534. 68 69The table below shows the offsets for each of the compatible chips: 70 71========== ===== ========= ===== ====== ====== ========= 72compatible lines interrupt input output invert direction 73========== ===== ========= ===== ====== ====== ========= 74pca9536 4 no 00 01 02 03 75pca9537 4 yes 00 01 02 03 76pca6408 8 yes 00 01 02 03 77tca6408 8 yes 00 01 02 03 78pca9534 8 yes 00 01 02 03 79pca9538 8 yes 00 01 02 03 80pca9554 8 yes 00 01 02 03 81tca9554 8 yes 00 01 02 03 82pca9556 8 no 00 01 02 03 83pca9557 8 no 00 01 02 03 84pca6107 8 yes 00 01 02 03 85pca6416 16 yes 00 02 04 06 86tca6416 16 yes 00 02 04 06 87pca9535 16 yes 00 02 04 06 88pca9539 16 yes 00 02 04 06 89tca9539 16 yes 00 02 04 06 90pca9555 16 yes 00 02 04 06 91max7318 16 yes 00 02 04 06 92tca6424 24 yes 00 04 08 0C 93========== ===== ========= ===== ====== ====== ========= 94 95Chips with additional timeout_en register 96----------------------------------------- 97 98These Maxim chips have a bus timeout function which can be enabled in 99the timeout_en register. This is present in only two chips. Defaults to 100timeout disabled. 101 102========== ===== ========= ===== ====== ====== ========= ========== 103compatible lines interrupt input output invert direction timeout_en 104========== ===== ========= ===== ====== ====== ========= ========== 105max7310 8 no 00 01 02 03 04 106max7312 16 yes 00 02 04 06 08 107========== ===== ========= ===== ====== ====== ========= ========== 108 109Chips with additional int_mask register 110--------------------------------------- 111 112These chips have an interrupt mask register in addition to the 4 basic 113registers. The interrupt masks default to all interrupts disabled. To 114use interrupts with these chips, the driver has to set the int_mask 115register. 116 117========== ===== ========= ===== ====== ====== ========= ======== 118compatible lines interrupt input output invert direction int_mask 119========== ===== ========= ===== ====== ====== ========= ======== 120pca9505 40 yes 00 08 10 18 20 121pca9506 40 yes 00 08 10 18 20 122========== ===== ========= ===== ====== ====== ========= ======== 123 124Chips with additional int_mask and out_conf registers 125----------------------------------------------------- 126 127This chip has an interrupt mask register, and an output port 128configuration register, which can select between push-pull and 129open-drain modes. Each bit controls two lines. Both of these registers 130are present in PCAL chips as well, albeit the out_conf works 131differently. 132 133========== ===== ========= ===== ====== ====== ========= ======== ======== 134compatible lines interrupt input output invert direction int_mask out_conf 135========== ===== ========= ===== ====== ====== ========= ======== ======== 136pca9698 40 yes 00 08 10 18 20 28 137========== ===== ========= ===== ====== ====== ========= ======== ======== 138 139pca9698 also has a "master output" register for setting all outputs per 140port to the same value simultaneously, and a chip specific mode register 141for various additional chip settings. 142 143========== ============= ==== 144compatible master_output mode 145========== ============= ==== 146pca9698 29 2A 147========== ============= ==== 148 149Chips with LED blink and intensity control 150------------------------------------------ 151 152These Maxim chips have no invert register. 153 154They have two sets of output registers (output0 and output1). An internal 155timer alternates the effective output between the values set in these 156registers, if blink mode is enabled in the blink register. The 157master_intensity register and the intensity registers together define 158the PWM intensity value for each pair of outputs. 159 160These chips can be used as simple GPIO expanders if the driver handles the 161input, output0 and direction registers. 162 163========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 164compatible lines interrupt input output0 direction output1 master_intensity blink intensity 165========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 166max7315 8 yes 00 01 03 09 0E 0F 10 167max7313 16 yes 00 02 06 0A 0E 0F 10 168========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 169 170Basic PCAL chips 171---------------- 172 173========== ===== ========= ===== ====== ====== ========= 174compatible lines interrupt input output invert direction 175========== ===== ========= ===== ====== ====== ========= 176pcal6408 8 yes 00 01 02 03 177pcal9554b 8 yes 00 01 02 03 178pcal6416 16 yes 00 02 04 06 179pcal9535 16 yes 00 02 04 06 180pcal9555a 16 yes 00 02 04 06 181tcal6408 8 yes 00 01 02 03 182tcal6416 16 yes 00 02 04 06 183========== ===== ========= ===== ====== ====== ========= 184 185These chips have several additional features: 186 187 1. output drive strength setting (out_strength) 188 2. input latch (in_latch) 189 3. pull-up/pull-down (pull_in, pull_sel) 190 4. push-pull/open-drain outputs (out_conf) 191 5. interrupt mask and interrupt status (int_mask, int_status) 192 193========== ============ ======== ======= ======== ======== ========== ======== 194compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf 195========== ============ ======== ======= ======== ======== ========== ======== 196pcal6408 40 42 43 44 45 46 4F 197pcal9554b 40 42 43 44 45 46 4F 198pcal6416 40 44 46 48 4A 4C 4F 199pcal9535 40 44 46 48 4A 4C 4F 200pcal9555a 40 44 46 48 4A 4C 4F 201tcal6408 40 42 43 44 45 46 4F 202tcal6416 40 44 46 48 4A 4C 4F 203========== ============ ======== ======= ======== ======== ========== ======== 204 205Currently the driver has support for the input latch, pull-up/pull-down 206and uses int_mask and int_status for interrupts. 207 208PCAL chips with extended interrupt and output configuration functions 209--------------------------------------------------------------------- 210 211========== ===== ========= ===== ====== ====== ========= 212compatible lines interrupt input output invert direction 213========== ===== ========= ===== ====== ====== ========= 214pcal6524 24 yes 00 04 08 0C 215pcal6534 34 yes 00 05 0A 0F 216========== ===== ========= ===== ====== ====== ========= 217 218These chips have the full PCAL register set, plus the following functions: 219 220 1. interrupt event selection: level, rising, falling, any edge 221 2. clear interrupt status per line 222 3. read input without clearing interrupt status 223 4. individual output config (push-pull/open-drain) per output line 224 5. debounce inputs 225 226========== ============ ======== ======= ======== ======== ========== ======== 227compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf 228========== ============ ======== ======= ======== ======== ========== ======== 229pcal6524 40 48 4C 50 54 58 5C 230pcal6534 30 3A 3F 44 49 4E 53 231========== ============ ======== ======= ======== ======== ========== ======== 232 233========== ======== ========= ============ ============== ======== ============== 234compatible int_edge int_clear input_status indiv_out_conf debounce debounce_count 235========== ======== ========= ============ ============== ======== ============== 236pcal6524 60 68 6C 70 74 76 237pcal6534 54 5E 63 68 6D 6F 238========== ======== ========= ============ ============== ======== ============== 239 240As can be seen in the table above, pcal6534 does not follow the usual 241bank spacing rule. Its banks are closely packed instead. 242 243PCA957X chips with a completely different register layout 244--------------------------------------------------------- 245 246These chips have the basic 4 registers, but at unusual addresses. 247 248Additionally, they have: 249 250 1. pull-up/pull-down (pull_sel) 251 2. a global pull enable, defaults to disabled (config) 252 3. interrupt mask, interrupt status (int_mask, int_status) 253 254========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 255compatible lines interrupt input invert config pull_sel direction output int_mask int_status 256========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 257pca9574 8 yes 00 01 02 03 04 05 06 07 258pca9575 16 yes 00 02 04 06 08 0A 0C 0E 259========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 260 261Currently the driver supports none of the advanced features. 262 263XRA1202 264------- 265 266Basic 4 registers, plus advanced features: 267 268 1. interrupt mask, defaults to interrupts disabled 269 2. interrupt status 270 3. interrupt event selection, level, rising, falling, any edge 271 (int_mask, rising_mask, falling_mask) 272 4. pull-up (no pull-down) 273 5. tri-state 274 6. debounce 275 276========== ===== ========= ===== ====== ====== ========= ========= 277compatible lines interrupt input output invert direction pullup_en 278========== ===== ========= ===== ====== ====== ========= ========= 279xra1202 8 yes 00 01 02 03 04 280========== ===== ========= ===== ====== ====== ========= ========= 281 282========== ======== ======== ========== =========== ============ ======== 283compatible int_mask tristate int_status rising_mask falling_mask debounce 284========== ======== ======== ========== =========== ============ ======== 285xra1202 05 06 07 08 09 0A 286========== ======== ======== ========== =========== ============ ======== 287 288Overview of functions 289===================== 290 291This section lists chip functions that are supported by the driver 292already, or are at least common in multiple chips. 293 294Input, Output, Invert, Direction 295-------------------------------- 296 297The basic 4 GPIO functions are present in all but one chip category, i.e. 298`Chips with LED blink and intensity control`_ are missing the invert 299register. 300 3013 different layouts are used for these registers: 302 303 1. banks 0, 1, 2, 3 with bank offsets of 2^n 304 - all other chips 305 306 2. banks 0, 1, 2, 3 with closely packed banks 307 - pcal6534 308 309 3. banks 0, 5, 1, 4 with bank offsets of 2^n 310 - pca9574 311 - pca9575 312 313Interrupts 314---------- 315 316Only an interrupt mask register 317~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 318The same layout is used for all of these: 319 320 1. bank 5 with bank offsets of 2^n 321 - pca9505 322 - pca9506 323 - pca9698 324 325Interrupt mask and interrupt status registers 326~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 327These work the same way in all of the chips: mask and status have 328one bit per line, 1 in the mask means interrupt enabled. 329 330Layouts: 331 332 1. base offset 0x40, bank 5 and bank 6, bank offsets of 2^n 333 - pcal6408 334 - pcal6416 335 - pcal9535 336 - pcal9554b 337 - pcal9555a 338 - pcal6524 339 - tcal6408 340 - tcal6416 341 342 2. base offset 0x30, bank 5 and 6, closely packed banks 343 - pcal6534 344 345 3. bank 6 and 7, bank offsets of 2^n 346 - pca9574 347 - pca9575 348 349 4. bank 5 and 7, bank offsets of 2^n 350 - xra1202 351 352Interrupt on specific edges 353~~~~~~~~~~~~~~~~~~~~~~~~~~~ 354`PCAL chips with extended interrupt and output configuration functions`_ 355have an int_edge register. This contains 2 bits per line, one of 4 events 356can be selected for each line: 357 358 0: level, 1: rising edge, 2: falling edge, 3: any edge 359 360Layouts: 361 362 1. base offset 0x40, bank 7, bank offsets of 2^n 363 364 - pcal6524 365 366 2. base offset 0x30, bank 7 + offset 0x01, closely packed banks 367 (out_conf is 1 byte, not (lines/8) bytes, hence the 0x01 offset) 368 369 - pcal6534 370 371`XRA1202`_ chips have a different mechanism for the same thing: they have 372a rising mask and a falling mask, with one bit per line. 373 374Layout: 375 376 1. bank 5, bank offsets of 2^n 377 378Input latch 379----------- 380 381Only `Basic PCAL chips`_ and 382`PCAL chips with extended interrupt and output configuration functions`_ 383have this function. When the latch is enabled, the interrupt is not cleared 384until the input port is read. When the latch is disabled, the interrupt 385is cleared even if the input register is not read, if the input pin returns 386to the logic value it had before generating the interrupt. Defaults to latch 387disabled. 388 389Currently the driver enables the latch for each line with interrupt 390enabled. 391 392An interrupt status register records which pins triggered an interrupt. 393However, the status register and the input port register must be read 394separately; there is no atomic mechanism to read both simultaneously, so races 395are possible. Refer to the chapter `Interrupt source detection`_ to understand 396the implications of this and how the driver still makes use of the latching 397feature. 398 399 1. base offset 0x40, bank 2, bank offsets of 2^n 400 - pcal6408 401 - pcal6416 402 - pcal9535 403 - pcal9554b 404 - pcal9555a 405 - pcal6524 406 - tcal6408 407 - tcal6416 408 409 2. base offset 0x30, bank 2, closely packed banks 410 - pcal6534 411 412Pull-up and pull-down 413--------------------- 414 415`Basic PCAL chips`_ and 416`PCAL chips with extended interrupt and output configuration functions`_ 417use the same mechanism: their pull_en register enables the pull-up or pull-down 418function, and their pull_sel register chooses the direction. They all use one 419bit per line. 420 421 0: pull-down, 1: pull-up 422 423Layouts: 424 425 1. base offset 0x40, bank 3 (en) and 4 (sel), bank offsets of 2^n 426 - pcal6408 427 - pcal6416 428 - pcal9535 429 - pcal9554b 430 - pcal9555a 431 - pcal6524 432 433 2. base offset 0x30, bank 3 (en) and 4 (sel), closely packed banks 434 - pcal6534 435 436`PCA957X chips with a completely different register layout`_ have a pull_sel 437register with one bit per line, and a global pull_en bit in their config 438register. 439 440Layout: 441 442 1. bank 2 (config), bank 3 (sel), bank offsets of 2^n 443 - pca9574 444 - pca9575 445 446`XRA1202`_ chips can only pull-up. They have a pullup_en register. 447 448Layout: 449 450 1. bank 4, bank offsets of 2^n 451 - xra1202 452 453Push-pull and open-drain 454------------------------ 455 456`Chips with additional int_mask and out_conf registers`_ have this function, 457but only for select IO ports. Register has 1 bit per 2 lines. In pca9698, 458only port0 and port1 have this function. 459 460 0: open-drain, 1: push-pull 461 462Layout: 463 464 1. base offset 5*bankoffset 465 - pca9698 466 467`Basic PCAL chips`_ have 1 bit per port in one single out_conf register. 468Only whole ports can be configured. 469 470 0: push-pull, 1: open-drain 471 472Layout: 473 474 1. base offset 0x4F 475 - pcal6408 476 - pcal6416 477 - pcal9535 478 - pcal9554b 479 - pcal9555a 480 - tcal6408 481 - tcal6416 482 483`PCAL chips with extended interrupt and output configuration functions`_ 484can set this for each line individually. They have the same per-port out_conf 485register as `Basic PCAL chips`_, but they also have an indiv_out_conf register 486with one bit per line, which inverts the effect of the port-wise setting. 487 488 0: push-pull, 1: open-drain 489 490Layouts: 491 492 1. base offset 0x40 + 7*bankoffset (out_conf), 493 base offset 0x60, bank 4 (indiv_out_conf) with bank offset of 2^n 494 495 - pcal6524 496 497 2. base offset 0x30 + 7*banksize (out_conf), 498 base offset 0x54, bank 4 (indiv_out_conf), closely packed banks 499 500 - pcal6534 501 502This function is currently not supported by the driver. 503 504Output drive strength 505--------------------- 506 507Only PCAL chips have this function. 2 bits per line. 508 509==== ============== 510bits drive strength 511==== ============== 512 00 0.25x 513 01 0.50x 514 10 0.75x 515 11 1.00x 516==== ============== 517 518 1. base offset 0x40, bank 0 and 1, bank offsets of 2^n 519 - pcal6408 520 - pcal6416 521 - pcal9535 522 - pcal9554b 523 - pcal9555a 524 - pcal6524 525 - tcal6408 526 - tcal6416 527 528 2. base offset 0x30, bank 0 and 1, closely packed banks 529 - pcal6534 530 531Currently not supported by the driver. 532 533Interrupt source detection 534========================== 535 536When triggered by the GPIO expander's interrupt, the driver determines which 537IRQs are pending by reading the input port register. 538 539To be able to filter on specific interrupt events for all compatible devices, 540the driver keeps track of the previous input state of the lines, and emits an 541IRQ only for the correct edge or level. This system works irrespective of the 542number of enabled interrupts. Events will not be missed even if they occur 543between the GPIO expander's interrupt and the actual I2C read. Edges could of 544course be missed if the related signal level changes back to the value 545previously saved by the driver before the I2C read. PCAL variants offer input 546latching for that reason. 547 548PCAL input latching 549------------------- 550 551The PCAL variants have an input latch and the driver enables this for all 552interrupt-enabled lines. The interrupt is then only cleared when the input port 553is read out. These variants provide an interrupt status register that records 554which pins triggered an interrupt, but the status and input registers cannot be 555read atomically. If another interrupt occurs on a different line after the 556status register has been read but before the input port register is sampled, 557that event will not be reflected in the earlier status snapshot, so relying 558solely on the interrupt status register is insufficient. 559 560Thus, the PCAL variants also have to use the existing level-change logic. 561 562For short pulses, the first edge is captured when the input register is read, 563but if the signal returns to its previous level before this read, the second 564edge is not observed. As a result, successive pulses can produce identical 565input values at read time and no level change is detected, causing interrupts 566to be missed. Below timing diagram shows this situation where the top signal is 567the input pin level and the bottom signal indicates the latched value:: 568 569 ─────┐ ┌──*───────────────┐ ┌──*─────────────────┐ ┌──*─── 570 │ │ . │ │ . │ │ . 571 │ │ │ │ │ │ │ │ │ 572 └──*──┘ │ └──*──┘ │ └──*──┘ │ 573 Input │ │ │ │ │ │ 574 ▼ │ ▼ │ ▼ │ 575 IRQ │ IRQ │ IRQ │ 576 . . . 577 ─────┐ .┌──────────────┐ .┌────────────────┐ .┌── 578 │ │ │ │ │ │ 579 │ │ │ │ │ │ 580 └────────*┘ └────────*┘ └────────*┘ 581 Latched │ │ │ 582 ▼ ▼ ▼ 583 READ 0 READ 0 READ 0 584 NO CHANGE NO CHANGE 585 586To deal with this, events indicated by the interrupt status register are merged 587with events detected through the existing level-change logic. As a result: 588 589- short pulses, whose second edges are invisible, are detected via the 590 interrupt status register, and 591- interrupts that occur between the status and input reads are still 592 caught by the generic level-change logic. 593 594Note that this is still best-effort: the status and input registers are read 595separately, and short pulses on other lines may occur in between those reads. 596Such pulses can still be latched as an interrupt without leaving an observable 597level change at read time, and may not be attributable to a specific edge. This 598does not reduce detection compared to the generic path, but reflects inherent 599atomicity limitations. 600 601Datasheets 602========== 603 604- MAX7310: https://datasheets.maximintegrated.com/en/ds/MAX7310.pdf 605- MAX7312: https://datasheets.maximintegrated.com/en/ds/MAX7312.pdf 606- MAX7313: https://datasheets.maximintegrated.com/en/ds/MAX7313.pdf 607- MAX7315: https://datasheets.maximintegrated.com/en/ds/MAX7315.pdf 608- MAX7318: https://datasheets.maximintegrated.com/en/ds/MAX7318.pdf 609- PCA6107: https://pdf1.alldatasheet.com/datasheet-pdf/view/161780/TI/PCA6107.html 610- PCA6408A: https://www.nxp.com/docs/en/data-sheet/PCA6408A.pdf 611- PCA6416A: https://www.nxp.com/docs/en/data-sheet/PCA6416A.pdf 612- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf 613- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf 614- PCA9534: https://www.nxp.com/docs/en/data-sheet/PCA9534.pdf 615- PCA9535: https://www.nxp.com/docs/en/data-sheet/PCA9535_PCA9535C.pdf 616- PCA9536: https://www.nxp.com/docs/en/data-sheet/PCA9536.pdf 617- PCA9537: https://www.nxp.com/docs/en/data-sheet/PCA9537.pdf 618- PCA9538: https://www.nxp.com/docs/en/data-sheet/PCA9538.pdf 619- PCA9539: https://www.nxp.com/docs/en/data-sheet/PCA9539_PCA9539R.pdf 620- PCA9554: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf 621- PCA9555: https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf 622- PCA9556: https://www.nxp.com/docs/en/data-sheet/PCA9556.pdf 623- PCA9557: https://www.nxp.com/docs/en/data-sheet/PCA9557.pdf 624- PCA9574: https://www.nxp.com/docs/en/data-sheet/PCA9574.pdf 625- PCA9575: https://www.nxp.com/docs/en/data-sheet/PCA9575.pdf 626- PCA9698: https://www.nxp.com/docs/en/data-sheet/PCA9698.pdf 627- PCAL6408A: https://www.nxp.com/docs/en/data-sheet/PCAL6408A.pdf 628- PCAL6416A: https://www.nxp.com/docs/en/data-sheet/PCAL6416A.pdf 629- PCAL6524: https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf 630- PCAL6534: https://www.nxp.com/docs/en/data-sheet/PCAL6534.pdf 631- PCAL9535A: https://www.nxp.com/docs/en/data-sheet/PCAL9535A.pdf 632- PCAL9554B: https://www.nxp.com/docs/en/data-sheet/PCAL9554B_PCAL9554C.pdf 633- PCAL9555A: https://www.nxp.com/docs/en/data-sheet/PCAL9555A.pdf 634- TCA6408A: https://www.ti.com/lit/gpn/tca6408a 635- TCA6416: https://www.ti.com/lit/gpn/tca6416 636- TCA6424: https://www.ti.com/lit/gpn/tca6424 637- TCA9539: https://www.ti.com/lit/gpn/tca9539 638- TCA9554: https://www.ti.com/lit/gpn/tca9554 639- XRA1202: https://assets.maxlinear.com/web/documents/xra1202_1202p_101_042213.pdf 640