1============================================ 2PCA953x I²C GPIO expander compatibility list 3============================================ 4 5:Author: Levente Révész <levente.revesz@eilabs.com> 6 7I went through all the datasheets and created this note listing 8chip functions and register layouts. 9 10Overview of chips 11================= 12 13Chips with the basic 4 registers 14-------------------------------- 15 16These chips have 4 register banks: input, output, invert and direction. 17Each of these banks contains (lines/8) registers, one for each GPIO port. 18 19Banks offset is always a power of 2: 20 21- 4 lines -> bank offset is 1 22- 8 lines -> bank offset is 1 23- 16 lines -> bank offset is 2 24- 24 lines -> bank offset is 4 25- 32 lines -> bank offset is 4 26- 40 lines -> bank offset is 8 27 28For example, register layout of GPIO expander with 24 lines: 29 30+------+-----------------+--------+ 31| addr | function | bank | 32+======+=================+========+ 33| 00 | input port0 | | 34+------+-----------------+ | 35| 01 | input port1 | bank 0 | 36+------+-----------------+ | 37| 02 | input port2 | | 38+------+-----------------+--------+ 39| 03 | n/a | | 40+------+-----------------+--------+ 41| 04 | output port0 | | 42+------+-----------------+ | 43| 05 | output port1 | bank 1 | 44+------+-----------------+ | 45| 06 | output port2 | | 46+------+-----------------+--------+ 47| 07 | n/a | | 48+------+-----------------+--------+ 49| 08 | invert port0 | | 50+------+-----------------+ | 51| 09 | invert port1 | bank 2 | 52+------+-----------------+ | 53| 0A | invert port2 | | 54+------+-----------------+--------+ 55| 0B | n/a | | 56+------+-----------------+--------+ 57| 0C | direction port0 | | 58+------+-----------------+ | 59| 0D | direction port1 | bank 3 | 60+------+-----------------+ | 61| 0E | direction port2 | | 62+------+-----------------+--------+ 63| 0F | n/a | | 64+------+-----------------+--------+ 65 66.. note:: 67 This is followed by all supported chips, except by pcal6534. 68 69The table below shows the offsets for each of the compatible chips: 70 71========== ===== ========= ===== ====== ====== ========= 72compatible lines interrupt input output invert direction 73========== ===== ========= ===== ====== ====== ========= 74pca9536 4 no 00 01 02 03 75pca9537 4 yes 00 01 02 03 76pca6408 8 yes 00 01 02 03 77tca6408 8 yes 00 01 02 03 78pca9534 8 yes 00 01 02 03 79pca9538 8 yes 00 01 02 03 80pca9554 8 yes 00 01 02 03 81tca9554 8 yes 00 01 02 03 82pca9556 8 no 00 01 02 03 83pca9557 8 no 00 01 02 03 84pca6107 8 yes 00 01 02 03 85pca6416 16 yes 00 02 04 06 86tca6416 16 yes 00 02 04 06 87pca9535 16 yes 00 02 04 06 88pca9539 16 yes 00 02 04 06 89tca9539 16 yes 00 02 04 06 90pca9555 16 yes 00 02 04 06 91max7318 16 yes 00 02 04 06 92tca6424 24 yes 00 04 08 0C 93========== ===== ========= ===== ====== ====== ========= 94 95Chips with additional timeout_en register 96----------------------------------------- 97 98These Maxim chips have a bus timeout function which can be enabled in 99the timeout_en register. This is present in only two chips. Defaults to 100timeout disabled. 101 102========== ===== ========= ===== ====== ====== ========= ========== 103compatible lines interrupt input output invert direction timeout_en 104========== ===== ========= ===== ====== ====== ========= ========== 105max7310 8 no 00 01 02 03 04 106max7312 16 yes 00 02 04 06 08 107========== ===== ========= ===== ====== ====== ========= ========== 108 109Chips with additional int_mask register 110--------------------------------------- 111 112These chips have an interrupt mask register in addition to the 4 basic 113registers. The interrupt masks default to all interrupts disabled. To 114use interrupts with these chips, the driver has to set the int_mask 115register. 116 117========== ===== ========= ===== ====== ====== ========= ======== 118compatible lines interrupt input output invert direction int_mask 119========== ===== ========= ===== ====== ====== ========= ======== 120pca9505 40 yes 00 08 10 18 20 121pca9506 40 yes 00 08 10 18 20 122========== ===== ========= ===== ====== ====== ========= ======== 123 124Chips with additional int_mask and out_conf registers 125----------------------------------------------------- 126 127This chip has an interrupt mask register, and an output port 128configuration register, which can select between push-pull and 129open-drain modes. Each bit controls two lines. Both of these registers 130are present in PCAL chips as well, albeit the out_conf works 131differently. 132 133========== ===== ========= ===== ====== ====== ========= ======== ======== 134compatible lines interrupt input output invert direction int_mask out_conf 135========== ===== ========= ===== ====== ====== ========= ======== ======== 136pca9698 40 yes 00 08 10 18 20 28 137========== ===== ========= ===== ====== ====== ========= ======== ======== 138 139pca9698 also has a "master output" register for setting all outputs per 140port to the same value simultaneously, and a chip specific mode register 141for various additional chip settings. 142 143========== ============= ==== 144compatible master_output mode 145========== ============= ==== 146pca9698 29 2A 147========== ============= ==== 148 149Chips with LED blink and intensity control 150------------------------------------------ 151 152These Maxim chips have no invert register. 153 154They have two sets of output registers (output0 and output1). An internal 155timer alternates the effective output between the values set in these 156registers, if blink mode is enabled in the blink register. The 157master_intensity register and the intensity registers together define 158the PWM intensity value for each pair of outputs. 159 160These chips can be used as simple GPIO expanders if the driver handles the 161input, output0 and direction registers. 162 163========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 164compatible lines interrupt input output0 direction output1 master_intensity blink intensity 165========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 166max7315 8 yes 00 01 03 09 0E 0F 10 167max7313 16 yes 00 02 06 0A 0E 0F 10 168========== ===== ========= ===== ======= ========= ======= ================ ===== ========= 169 170Basic PCAL chips 171---------------- 172 173========== ===== ========= ===== ====== ====== ========= 174compatible lines interrupt input output invert direction 175========== ===== ========= ===== ====== ====== ========= 176pcal6408 8 yes 00 01 02 03 177pcal9554b 8 yes 00 01 02 03 178pcal6416 16 yes 00 02 04 06 179pcal9535 16 yes 00 02 04 06 180pcal9555a 16 yes 00 02 04 06 181========== ===== ========= ===== ====== ====== ========= 182 183These chips have several additional features: 184 185 1. output drive strength setting (out_strength) 186 2. input latch (in_latch) 187 3. pull-up/pull-down (pull_in, pull_sel) 188 4. push-pull/open-drain outputs (out_conf) 189 5. interrupt mask and interrupt status (int_mask, int_status) 190 191========== ============ ======== ======= ======== ======== ========== ======== 192compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf 193========== ============ ======== ======= ======== ======== ========== ======== 194pcal6408 40 42 43 44 45 46 4F 195pcal9554b 40 42 43 44 45 46 4F 196pcal6416 40 44 46 48 4A 4C 4F 197pcal9535 40 44 46 48 4A 4C 4F 198pcal9555a 40 44 46 48 4A 4C 4F 199========== ============ ======== ======= ======== ======== ========== ======== 200 201Currently the driver has support for the input latch, pull-up/pull-down 202and uses int_mask and int_status for interrupts. 203 204PCAL chips with extended interrupt and output configuration functions 205--------------------------------------------------------------------- 206 207========== ===== ========= ===== ====== ====== ========= 208compatible lines interrupt input output invert direction 209========== ===== ========= ===== ====== ====== ========= 210pcal6524 24 yes 00 04 08 0C 211pcal6534 34 yes 00 05 0A 0F 212========== ===== ========= ===== ====== ====== ========= 213 214These chips have the full PCAL register set, plus the following functions: 215 216 1. interrupt event selection: level, rising, falling, any edge 217 2. clear interrupt status per line 218 3. read input without clearing interrupt status 219 4. individual output config (push-pull/open-drain) per output line 220 5. debounce inputs 221 222========== ============ ======== ======= ======== ======== ========== ======== 223compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf 224========== ============ ======== ======= ======== ======== ========== ======== 225pcal6524 40 48 4C 50 54 58 5C 226pcal6534 30 3A 3F 44 49 4E 53 227========== ============ ======== ======= ======== ======== ========== ======== 228 229========== ======== ========= ============ ============== ======== ============== 230compatible int_edge int_clear input_status indiv_out_conf debounce debounce_count 231========== ======== ========= ============ ============== ======== ============== 232pcal6524 60 68 6C 70 74 76 233pcal6534 54 5E 63 68 6D 6F 234========== ======== ========= ============ ============== ======== ============== 235 236As can be seen in the table above, pcal6534 does not follow the usual 237bank spacing rule. Its banks are closely packed instead. 238 239PCA957X chips with a completely different register layout 240--------------------------------------------------------- 241 242These chips have the basic 4 registers, but at unusual addresses. 243 244Additionally, they have: 245 246 1. pull-up/pull-down (pull_sel) 247 2. a global pull enable, defaults to disabled (config) 248 3. interrupt mask, interrupt status (int_mask, int_status) 249 250========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 251compatible lines interrupt input invert config pull_sel direction output int_mask int_status 252========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 253pca9574 8 yes 00 01 02 03 04 05 06 07 254pca9575 16 yes 00 02 04 06 08 0A 0C 0E 255========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ========== 256 257Currently the driver supports none of the advanced features. 258 259XRA1202 260------- 261 262Basic 4 registers, plus advanced features: 263 264 1. interrupt mask, defaults to interrupts disabled 265 2. interrupt status 266 3. interrupt event selection, level, rising, falling, any edge 267 (int_mask, rising_mask, falling_mask) 268 4. pull-up (no pull-down) 269 5. tri-state 270 6. debounce 271 272========== ===== ========= ===== ====== ====== ========= ========= 273compatible lines interrupt input output invert direction pullup_en 274========== ===== ========= ===== ====== ====== ========= ========= 275xra1202 8 yes 00 01 02 03 04 276========== ===== ========= ===== ====== ====== ========= ========= 277 278========== ======== ======== ========== =========== ============ ======== 279compatible int_mask tristate int_status rising_mask falling_mask debounce 280========== ======== ======== ========== =========== ============ ======== 281xra1202 05 06 07 08 09 0A 282========== ======== ======== ========== =========== ============ ======== 283 284Overview of functions 285===================== 286 287This section lists chip functions that are supported by the driver 288already, or are at least common in multiple chips. 289 290Input, Output, Invert, Direction 291-------------------------------- 292 293The basic 4 GPIO functions are present in all but one chip category, i.e. 294`Chips with LED blink and intensity control`_ are missing the invert 295register. 296 2973 different layouts are used for these registers: 298 299 1. banks 0, 1, 2, 3 with bank offsets of 2^n 300 - all other chips 301 302 2. banks 0, 1, 2, 3 with closely packed banks 303 - pcal6534 304 305 3. banks 0, 5, 1, 4 with bank offsets of 2^n 306 - pca9574 307 - pca9575 308 309Interrupts 310---------- 311 312Only an interrupt mask register 313~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 314The same layout is used for all of these: 315 316 1. bank 5 with bank offsets of 2^n 317 - pca9505 318 - pca9506 319 - pca9698 320 321Interrupt mask and interrupt status registers 322~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 323These work the same way in all of the chips: mask and status have 324one bit per line, 1 in the mask means interrupt enabled. 325 326Layouts: 327 328 1. base offset 0x40, bank 5 and bank 6, bank offsets of 2^n 329 - pcal6408 330 - pcal6416 331 - pcal9535 332 - pcal9554b 333 - pcal9555a 334 - pcal6524 335 336 2. base offset 0x30, bank 5 and 6, closely packed banks 337 - pcal6534 338 339 3. bank 6 and 7, bank offsets of 2^n 340 - pca9574 341 - pca9575 342 343 4. bank 5 and 7, bank offsets of 2^n 344 - xra1202 345 346Interrupt on specific edges 347~~~~~~~~~~~~~~~~~~~~~~~~~~~ 348`PCAL chips with extended interrupt and output configuration functions`_ 349have an int_edge register. This contains 2 bits per line, one of 4 events 350can be selected for each line: 351 352 0: level, 1: rising edge, 2: falling edge, 3: any edge 353 354Layouts: 355 356 1. base offset 0x40, bank 7, bank offsets of 2^n 357 358 - pcal6524 359 360 2. base offset 0x30, bank 7 + offset 0x01, closely packed banks 361 (out_conf is 1 byte, not (lines/8) bytes, hence the 0x01 offset) 362 363 - pcal6534 364 365`XRA1202`_ chips have a different mechanism for the same thing: they have 366a rising mask and a falling mask, with one bit per line. 367 368Layout: 369 370 1. bank 5, bank offsets of 2^n 371 372Input latch 373----------- 374 375Only `Basic PCAL chips`_ and 376`PCAL chips with extended interrupt and output configuration functions`_ 377have this function. When the latch is enabled, the interrupt is not cleared 378until the input port is read. When the latch is disabled, the interrupt 379is cleared even if the input register is not read, if the input pin returns 380to the logic value it had before generating the interrupt. Defaults to latch 381disabled. 382 383Currently the driver enables the latch for each line with interrupt 384enabled. 385 386 1. base offset 0x40, bank 2, bank offsets of 2^n 387 - pcal6408 388 - pcal6416 389 - pcal9535 390 - pcal9554b 391 - pcal9555a 392 - pcal6524 393 394 2. base offset 0x30, bank 2, closely packed banks 395 - pcal6534 396 397Pull-up and pull-down 398--------------------- 399 400`Basic PCAL chips`_ and 401`PCAL chips with extended interrupt and output configuration functions`_ 402use the same mechanism: their pull_en register enables the pull-up or pull-down 403function, and their pull_sel register chooses the direction. They all use one 404bit per line. 405 406 0: pull-down, 1: pull-up 407 408Layouts: 409 410 1. base offset 0x40, bank 3 (en) and 4 (sel), bank offsets of 2^n 411 - pcal6408 412 - pcal6416 413 - pcal9535 414 - pcal9554b 415 - pcal9555a 416 - pcal6524 417 418 2. base offset 0x30, bank 3 (en) and 4 (sel), closely packed banks 419 - pcal6534 420 421`PCA957X chips with a completely different register layout`_ have a pull_sel 422register with one bit per line, and a global pull_en bit in their config 423register. 424 425Layout: 426 427 1. bank 2 (config), bank 3 (sel), bank offsets of 2^n 428 - pca9574 429 - pca9575 430 431`XRA1202`_ chips can only pull-up. They have a pullup_en register. 432 433Layout: 434 435 1. bank 4, bank offsets of 2^n 436 - xra1202 437 438Push-pull and open-drain 439------------------------ 440 441`Chips with additional int_mask and out_conf registers`_ have this function, 442but only for select IO ports. Register has 1 bit per 2 lines. In pca9698, 443only port0 and port1 have this function. 444 445 0: open-drain, 1: push-pull 446 447Layout: 448 449 1. base offset 5*bankoffset 450 - pca9698 451 452`Basic PCAL chips`_ have 1 bit per port in one single out_conf register. 453Only whole ports can be configured. 454 455 0: push-pull, 1: open-drain 456 457Layout: 458 459 1. base offset 0x4F 460 - pcal6408 461 - pcal6416 462 - pcal9535 463 - pcal9554b 464 - pcal9555a 465 466`PCAL chips with extended interrupt and output configuration functions`_ 467can set this for each line individually. They have the same per-port out_conf 468register as `Basic PCAL chips`_, but they also have an indiv_out_conf register 469with one bit per line, which inverts the effect of the port-wise setting. 470 471 0: push-pull, 1: open-drain 472 473Layouts: 474 475 1. base offset 0x40 + 7*bankoffset (out_conf), 476 base offset 0x60, bank 4 (indiv_out_conf) with bank offset of 2^n 477 478 - pcal6524 479 480 2. base offset 0x30 + 7*banksize (out_conf), 481 base offset 0x54, bank 4 (indiv_out_conf), closely packed banks 482 483 - pcal6534 484 485This function is currently not supported by the driver. 486 487Output drive strength 488--------------------- 489 490Only PCAL chips have this function. 2 bits per line. 491 492==== ============== 493bits drive strength 494==== ============== 495 00 0.25x 496 01 0.50x 497 10 0.75x 498 11 1.00x 499==== ============== 500 501 1. base offset 0x40, bank 0 and 1, bank offsets of 2^n 502 - pcal6408 503 - pcal6416 504 - pcal9535 505 - pcal9554b 506 - pcal9555a 507 - pcal6524 508 509 2. base offset 0x30, bank 0 and 1, closely packed banks 510 - pcal6534 511 512Currently not supported by the driver. 513 514Datasheets 515========== 516 517- MAX7310: https://datasheets.maximintegrated.com/en/ds/MAX7310.pdf 518- MAX7312: https://datasheets.maximintegrated.com/en/ds/MAX7312.pdf 519- MAX7313: https://datasheets.maximintegrated.com/en/ds/MAX7313.pdf 520- MAX7315: https://datasheets.maximintegrated.com/en/ds/MAX7315.pdf 521- MAX7318: https://datasheets.maximintegrated.com/en/ds/MAX7318.pdf 522- PCA6107: https://pdf1.alldatasheet.com/datasheet-pdf/view/161780/TI/PCA6107.html 523- PCA6408A: https://www.nxp.com/docs/en/data-sheet/PCA6408A.pdf 524- PCA6416A: https://www.nxp.com/docs/en/data-sheet/PCA6416A.pdf 525- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf 526- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf 527- PCA9534: https://www.nxp.com/docs/en/data-sheet/PCA9534.pdf 528- PCA9535: https://www.nxp.com/docs/en/data-sheet/PCA9535_PCA9535C.pdf 529- PCA9536: https://www.nxp.com/docs/en/data-sheet/PCA9536.pdf 530- PCA9537: https://www.nxp.com/docs/en/data-sheet/PCA9537.pdf 531- PCA9538: https://www.nxp.com/docs/en/data-sheet/PCA9538.pdf 532- PCA9539: https://www.nxp.com/docs/en/data-sheet/PCA9539_PCA9539R.pdf 533- PCA9554: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf 534- PCA9555: https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf 535- PCA9556: https://www.nxp.com/docs/en/data-sheet/PCA9556.pdf 536- PCA9557: https://www.nxp.com/docs/en/data-sheet/PCA9557.pdf 537- PCA9574: https://www.nxp.com/docs/en/data-sheet/PCA9574.pdf 538- PCA9575: https://www.nxp.com/docs/en/data-sheet/PCA9575.pdf 539- PCA9698: https://www.nxp.com/docs/en/data-sheet/PCA9698.pdf 540- PCAL6408A: https://www.nxp.com/docs/en/data-sheet/PCAL6408A.pdf 541- PCAL6416A: https://www.nxp.com/docs/en/data-sheet/PCAL6416A.pdf 542- PCAL6524: https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf 543- PCAL6534: https://www.nxp.com/docs/en/data-sheet/PCAL6534.pdf 544- PCAL9535A: https://www.nxp.com/docs/en/data-sheet/PCAL9535A.pdf 545- PCAL9554B: https://www.nxp.com/docs/en/data-sheet/PCAL9554B_PCAL9554C.pdf 546- PCAL9555A: https://www.nxp.com/docs/en/data-sheet/PCAL9555A.pdf 547- TCA6408A: https://www.ti.com/lit/gpn/tca6408a 548- TCA6416: https://www.ti.com/lit/gpn/tca6416 549- TCA6424: https://www.ti.com/lit/gpn/tca6424 550- TCA9539: https://www.ti.com/lit/gpn/tca9539 551- TCA9554: https://www.ti.com/lit/gpn/tca9554 552- XRA1202: https://assets.maxlinear.com/web/documents/xra1202_1202p_101_042213.pdf 553