1.. SPDX-License-Identifier: GPL-2.0 2 3============= 4Single Device 5============= 6This cxl-cli configuration dump shows the following host configuration: 7 8* A single socket system with one CXL root 9* CXL Root has Four (4) CXL Host Bridges 10* One CXL Host Bridges has a single CXL Memory Expander Attached 11* No interleave is present. 12 13This output is generated by :code:`cxl list -v` and describes the relationships 14between objects exposed in :code:`/sys/bus/cxl/devices/`. 15 16:: 17 18 [ 19 { 20 "bus":"root0", 21 "provider":"ACPI.CXL", 22 "nr_dports":4, 23 "dports":[ 24 { 25 "dport":"pci0000:00", 26 "alias":"ACPI0016:01", 27 "id":0 28 }, 29 { 30 "dport":"pci0000:a8", 31 "alias":"ACPI0016:02", 32 "id":4 33 }, 34 { 35 "dport":"pci0000:2a", 36 "alias":"ACPI0016:03", 37 "id":1 38 }, 39 { 40 "dport":"pci0000:d2", 41 "alias":"ACPI0016:00", 42 "id":5 43 } 44 ], 45 46This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL 47Host Bridges. The `Root` can be considered the singular upstream port attached 48to the platform's memory controller - which routes memory requests to it. 49 50The `ports:root0` section lays out how each of these downstream ports are 51configured. If a port is not configured (id's 0, 1, and 4), they are omitted. 52 53:: 54 55 "ports:root0":[ 56 { 57 "port":"port1", 58 "host":"pci0000:d2", 59 "depth":1, 60 "nr_dports":3, 61 "dports":[ 62 { 63 "dport":"0000:d2:01.1", 64 "alias":"device:02", 65 "id":0 66 }, 67 { 68 "dport":"0000:d2:01.3", 69 "alias":"device:05", 70 "id":2 71 }, 72 { 73 "dport":"0000:d2:07.1", 74 "alias":"device:0d", 75 "id":113 76 } 77 ], 78 79This chunk shows the available downstream ports associated with the CXL Host 80Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream 81ports: :code:`dport1`, :code:`dport2`, and :code:`dport113`.. 82 83:: 84 85 "endpoints:port1":[ 86 { 87 "endpoint":"endpoint5", 88 "host":"mem0", 89 "parent_dport":"0000:d2:01.1", 90 "depth":2, 91 "memdev":{ 92 "memdev":"mem0", 93 "ram_size":137438953472, 94 "serial":0, 95 "numa_node":0, 96 "host":"0000:d3:00.0" 97 }, 98 "decoders:endpoint5":[ 99 { 100 "decoder":"decoder5.0", 101 "resource":825975898112, 102 "size":137438953472, 103 "interleave_ways":1, 104 "region":"region0", 105 "dpa_resource":0, 106 "dpa_size":137438953472, 107 "mode":"ram" 108 } 109 ] 110 } 111 ], 112 113This chunk shows the endpoints attached to the host bridge :code:`port1`. 114 115:code:`endpoint5` contains a single configured decoder :code:`decoder5.0` 116which has the same interleave configuration as :code:`region0` (shown later). 117 118Next we have the decoders belonging to the host bridge: 119 120:: 121 122 "decoders:port1":[ 123 { 124 "decoder":"decoder1.0", 125 "resource":825975898112, 126 "size":137438953472, 127 "interleave_ways":1, 128 "region":"region0", 129 "nr_targets":1, 130 "targets":[ 131 { 132 "target":"0000:d2:01.1", 133 "alias":"device:02", 134 "position":0, 135 "id":0 136 } 137 ] 138 } 139 ] 140 }, 141 142Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose only 143target is :code:`dport1` - which is attached to :code:`endpoint5`. 144 145The next chunk shows the three CXL host bridges without attached endpoints. 146 147:: 148 149 { 150 "port":"port2", 151 "host":"pci0000:00", 152 "depth":1, 153 "nr_dports":2, 154 "dports":[ 155 { 156 "dport":"0000:00:01.3", 157 "alias":"device:55", 158 "id":2 159 }, 160 { 161 "dport":"0000:00:07.1", 162 "alias":"device:5d", 163 "id":113 164 } 165 ] 166 }, 167 { 168 "port":"port3", 169 "host":"pci0000:a8", 170 "depth":1, 171 "nr_dports":1, 172 "dports":[ 173 { 174 "dport":"0000:a8:01.1", 175 "alias":"device:c3", 176 "id":0 177 } 178 ] 179 }, 180 { 181 "port":"port4", 182 "host":"pci0000:2a", 183 "depth":1, 184 "nr_dports":1, 185 "dports":[ 186 { 187 "dport":"0000:2a:01.1", 188 "alias":"device:d0", 189 "id":0 190 } 191 ] 192 } 193 ], 194 195Next we have the `Root Decoders` belonging to :code:`root0`. This root decoder 196is a pass-through decoder because :code:`interleave_ways` is set to :code:`1`. 197 198This information is generated by the CXL driver reading the ACPI CEDT CMFWS. 199 200:: 201 202 "decoders:root0":[ 203 { 204 "decoder":"decoder0.0", 205 "resource":825975898112, 206 "size":137438953472, 207 "interleave_ways":1, 208 "max_available_extent":0, 209 "volatile_capable":true, 210 "nr_targets":1, 211 "targets":[ 212 { 213 "target":"pci0000:d2", 214 "alias":"ACPI0016:00", 215 "position":0, 216 "id":5 217 } 218 ], 219 220Finally we have the `Memory Region` associated with the `Root Decoder` 221:code:`decoder0.0`. This region describes the discrete region associated 222with the lone device. 223 224:: 225 226 "regions:decoder0.0":[ 227 { 228 "region":"region0", 229 "resource":825975898112, 230 "size":137438953472, 231 "type":"ram", 232 "interleave_ways":1, 233 "decode_state":"commit", 234 "mappings":[ 235 { 236 "position":0, 237 "memdev":"mem0", 238 "decoder":"decoder5.0" 239 } 240 ] 241 } 242 ] 243 } 244 ] 245 } 246 ] 247