xref: /linux/Documentation/devicetree/bindings/usb/ti,dwc3.yaml (revision 99ef60d119f3b2621067dd5fc1ea4a37360709e4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/ti,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments OMAP DWC3 USB Glue Layer
8
9maintainers:
10  - Felipe Balbi <balbi@ti.com>
11
12description:
13  Texas Instruments glue layer for Synopsys DesignWare USB3 (DWC3)
14  controller on OMAP and AM43xx SoCs. Manages SoC-specific integration
15  including register mapping, interrupt routing, UTMI/PIPE interface mode
16  selection (HW/SW), and child DWC3 core instantiation via address space
17  translation. Supports both legacy single-instance and multi-instance
18  (numbered) configurations.
19
20properties:
21  compatible:
22    enum:
23      - ti,dwc3
24      - ti,am437x-dwc3
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  utmi-mode:
33    $ref: /schemas/types.yaml#/definitions/uint32
34    description:
35      Controls the source of UTMI/PIPE status for VBUS and OTG ID.
36      1 for HW mode, 2 for SW mode.
37    enum: [1, 2]
38
39  "#address-cells":
40    const: 1
41
42  "#size-cells":
43    const: 1
44
45  ranges: true
46
47  extcon:
48    $ref: /schemas/types.yaml#/definitions/phandle
49    description:
50      Phandle for the extcon device used to detect connect/
51      disconnect events.
52
53  vbus-supply:
54    description: Phandle to the regulator device tree node if needed.
55
56patternProperties:
57  "^usb@[0-9a-f]+$":
58    type: object
59    $ref: snps,dwc3.yaml#
60    unevaluatedProperties: false
61
62required:
63  - reg
64  - compatible
65  - interrupts
66  - "#address-cells"
67  - "#size-cells"
68  - utmi-mode
69  - ranges
70
71unevaluatedProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76    omap_dwc3_1@0 {
77        compatible = "ti,dwc3";
78        reg = <0x0 0x10000>;
79        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
80        #address-cells = <1>;
81        #size-cells = <1>;
82        utmi-mode = <2>;
83        ranges = <0 0 0x20000>;
84
85        usb@10000 {
86            compatible = "snps,dwc3";
87            reg = <0x10000 0x17000>;
88            interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
89                         <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
90                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
91            interrupt-names = "peripheral", "host", "otg";
92            phys = <&usb2_phy1>, <&usb3_phy1>;
93            phy-names = "usb2-phy", "usb3-phy";
94            maximum-speed = "super-speed";
95            dr_mode = "otg";
96            snps,dis_u3_susphy_quirk;
97            snps,dis_u2_susphy_quirk;
98        };
99    };
100...
101