1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12description: 13 Describes the Qualcomm USB block, based on Synopsys DWC3. 14 15select: 16 properties: 17 compatible: 18 contains: 19 const: qcom,snps-dwc3 20 required: 21 - compatible 22 23properties: 24 compatible: 25 items: 26 - enum: 27 - qcom,glymur-dwc3 28 - qcom,glymur-dwc3-mp 29 - qcom,ipq4019-dwc3 30 - qcom,ipq5018-dwc3 31 - qcom,ipq5332-dwc3 32 - qcom,ipq5424-dwc3 33 - qcom,ipq6018-dwc3 34 - qcom,ipq8064-dwc3 35 - qcom,ipq8074-dwc3 36 - qcom,ipq9574-dwc3 37 - qcom,kaanapali-dwc3 38 - qcom,milos-dwc3 39 - qcom,msm8953-dwc3 40 - qcom,msm8994-dwc3 41 - qcom,msm8996-dwc3 42 - qcom,msm8998-dwc3 43 - qcom,qcm2290-dwc3 44 - qcom,qcs404-dwc3 45 - qcom,qcs615-dwc3 46 - qcom,qcs8300-dwc3 47 - qcom,qdu1000-dwc3 48 - qcom,sa8775p-dwc3 49 - qcom,sar2130p-dwc3 50 - qcom,sc7180-dwc3 51 - qcom,sc7280-dwc3 52 - qcom,sc8180x-dwc3 53 - qcom,sc8180x-dwc3-mp 54 - qcom,sc8280xp-dwc3 55 - qcom,sc8280xp-dwc3-mp 56 - qcom,sdm660-dwc3 57 - qcom,sdm670-dwc3 58 - qcom,sdm845-dwc3 59 - qcom,sdx55-dwc3 60 - qcom,sdx65-dwc3 61 - qcom,sdx75-dwc3 62 - qcom,sm4250-dwc3 63 - qcom,sm6115-dwc3 64 - qcom,sm6125-dwc3 65 - qcom,sm6350-dwc3 66 - qcom,sm6375-dwc3 67 - qcom,sm8150-dwc3 68 - qcom,sm8250-dwc3 69 - qcom,sm8350-dwc3 70 - qcom,sm8450-dwc3 71 - qcom,sm8550-dwc3 72 - qcom,sm8650-dwc3 73 - qcom,sm8750-dwc3 74 - qcom,x1e80100-dwc3 75 - qcom,x1e80100-dwc3-mp 76 - const: qcom,snps-dwc3 77 78 reg: 79 maxItems: 1 80 81 power-domains: 82 maxItems: 1 83 84 required-opps: 85 maxItems: 1 86 87 clocks: 88 description: | 89 Several clocks are used, depending on the variant. Typical ones are:: 90 - cfg_noc:: System Config NOC clock. 91 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 92 60MHz for HS operation. 93 - iface:: System bus AXI clock. 94 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 95 power mode (U3). 96 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 97 mode. Its frequency should be 19.2MHz. 98 minItems: 1 99 maxItems: 9 100 101 clock-names: 102 minItems: 1 103 maxItems: 9 104 105 dma-coherent: true 106 107 iommus: 108 maxItems: 1 109 110 resets: 111 maxItems: 1 112 113 interconnects: 114 maxItems: 2 115 116 interconnect-names: 117 items: 118 - const: usb-ddr 119 - const: apps-usb 120 121 interrupts: 122 description: | 123 Different types of interrupts are used based on HS PHY used on target: 124 - dwc_usb3: Core DWC3 interrupt 125 - pwr_event: Used for wakeup based on other power events. 126 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 127 hs_phy_irq which is not triggered by default and its 128 functionality is mutually exclusive to that of 129 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 130 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 131 expose only a single IRQ whose behavior can be modified 132 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 133 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 134 of PHY address space. 135 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 136 DM pads of the SoC. These are used for wakeup 137 only on SoCs with non-QUSB2 targets with 138 exception of SDM670/SDM845/SM6350. 139 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 140 minItems: 3 141 maxItems: 19 142 143 interrupt-names: 144 minItems: 3 145 maxItems: 19 146 147 qcom,select-utmi-as-pipe-clk: 148 description: 149 If present, disable USB3 pipe_clk requirement. 150 Used when dwc3 operates without SSPHY and only 151 HS/FS/LS modes are supported. 152 type: boolean 153 154 wakeup-source: true 155 156# Required child node: 157 158required: 159 - compatible 160 - reg 161 - clocks 162 - clock-names 163 - interrupts 164 - interrupt-names 165 166allOf: 167 - $ref: snps,dwc3-common.yaml# 168 - if: 169 properties: 170 compatible: 171 contains: 172 enum: 173 - qcom,ipq4019-dwc3 174 - qcom,ipq5332-dwc3 175 then: 176 properties: 177 clocks: 178 maxItems: 3 179 clock-names: 180 items: 181 - const: core 182 - const: sleep 183 - const: mock_utmi 184 185 - if: 186 properties: 187 compatible: 188 contains: 189 enum: 190 - qcom,ipq8064-dwc3 191 then: 192 properties: 193 clocks: 194 items: 195 - description: Master/Core clock, has to be >= 125 MHz 196 for SS operation and >= 60MHz for HS operation. 197 clock-names: 198 items: 199 - const: core 200 201 - if: 202 properties: 203 compatible: 204 contains: 205 enum: 206 - qcom,ipq9574-dwc3 207 - qcom,kaanapali-dwc3 208 - qcom,msm8953-dwc3 209 - qcom,msm8996-dwc3 210 - qcom,msm8998-dwc3 211 - qcom,qcs8300-dwc3 212 - qcom,sa8775p-dwc3 213 - qcom,sc7180-dwc3 214 - qcom,sc7280-dwc3 215 - qcom,sdm670-dwc3 216 - qcom,sdm845-dwc3 217 - qcom,sdx55-dwc3 218 - qcom,sdx65-dwc3 219 - qcom,sdx75-dwc3 220 - qcom,sm6350-dwc3 221 - qcom,sm8750-dwc3 222 then: 223 properties: 224 clocks: 225 maxItems: 5 226 clock-names: 227 items: 228 - const: cfg_noc 229 - const: core 230 - const: iface 231 - const: sleep 232 - const: mock_utmi 233 234 - if: 235 properties: 236 compatible: 237 contains: 238 enum: 239 - qcom,ipq6018-dwc3 240 then: 241 properties: 242 clocks: 243 minItems: 3 244 maxItems: 4 245 clock-names: 246 oneOf: 247 - items: 248 - const: core 249 - const: sleep 250 - const: mock_utmi 251 - items: 252 - const: cfg_noc 253 - const: core 254 - const: sleep 255 - const: mock_utmi 256 257 - if: 258 properties: 259 compatible: 260 contains: 261 enum: 262 - qcom,ipq8074-dwc3 263 - qcom,qdu1000-dwc3 264 then: 265 properties: 266 clocks: 267 maxItems: 4 268 clock-names: 269 items: 270 - const: cfg_noc 271 - const: core 272 - const: sleep 273 - const: mock_utmi 274 275 - if: 276 properties: 277 compatible: 278 contains: 279 enum: 280 - qcom,ipq5018-dwc3 281 - qcom,msm8994-dwc3 282 - qcom,qcs404-dwc3 283 then: 284 properties: 285 clocks: 286 maxItems: 4 287 clock-names: 288 items: 289 - const: core 290 - const: iface 291 - const: sleep 292 - const: mock_utmi 293 294 - if: 295 properties: 296 compatible: 297 contains: 298 enum: 299 - qcom,sc8280xp-dwc3 300 - qcom,sc8280xp-dwc3-mp 301 - qcom,x1e80100-dwc3 302 - qcom,x1e80100-dwc3-mp 303 then: 304 properties: 305 clocks: 306 maxItems: 9 307 clock-names: 308 items: 309 - const: cfg_noc 310 - const: core 311 - const: iface 312 - const: sleep 313 - const: mock_utmi 314 - const: noc_aggr 315 - const: noc_aggr_north 316 - const: noc_aggr_south 317 - const: noc_sys 318 319 - if: 320 properties: 321 compatible: 322 contains: 323 enum: 324 - qcom,sdm660-dwc3 325 then: 326 properties: 327 clocks: 328 minItems: 4 329 maxItems: 5 330 clock-names: 331 oneOf: 332 - items: 333 - const: cfg_noc 334 - const: core 335 - const: iface 336 - const: sleep 337 - const: mock_utmi 338 - items: 339 - const: cfg_noc 340 - const: core 341 - const: sleep 342 - const: mock_utmi 343 344 - if: 345 properties: 346 compatible: 347 contains: 348 enum: 349 - qcom,milos-dwc3 350 - qcom,qcm2290-dwc3 351 - qcom,qcs615-dwc3 352 - qcom,sar2130p-dwc3 353 - qcom,sc8180x-dwc3 354 - qcom,sc8180x-dwc3-mp 355 - qcom,sm6115-dwc3 356 - qcom,sm6125-dwc3 357 - qcom,sm8150-dwc3 358 - qcom,sm8250-dwc3 359 - qcom,sm8450-dwc3 360 - qcom,sm8550-dwc3 361 - qcom,sm8650-dwc3 362 then: 363 properties: 364 clocks: 365 minItems: 6 366 clock-names: 367 items: 368 - const: cfg_noc 369 - const: core 370 - const: iface 371 - const: sleep 372 - const: mock_utmi 373 - const: xo 374 375 - if: 376 properties: 377 compatible: 378 contains: 379 enum: 380 - qcom,sm8350-dwc3 381 then: 382 properties: 383 clocks: 384 minItems: 5 385 maxItems: 6 386 clock-names: 387 minItems: 5 388 items: 389 - const: cfg_noc 390 - const: core 391 - const: iface 392 - const: sleep 393 - const: mock_utmi 394 - const: xo 395 396 - if: 397 properties: 398 compatible: 399 contains: 400 enum: 401 - qcom,glymur-dwc3 402 - qcom,glymur-dwc3-mp 403 404 then: 405 properties: 406 clocks: 407 maxItems: 7 408 clock-names: 409 items: 410 - const: cfg_noc 411 - const: core 412 - const: iface 413 - const: sleep 414 - const: mock_utmi 415 - const: noc_aggr_north 416 - const: noc_aggr_south 417 418 - if: 419 properties: 420 compatible: 421 contains: 422 enum: 423 - qcom,ipq6018-dwc3 424 - qcom,ipq8074-dwc3 425 - qcom,msm8953-dwc3 426 - qcom,msm8998-dwc3 427 then: 428 properties: 429 interrupts: 430 minItems: 3 431 maxItems: 4 432 interrupt-names: 433 minItems: 3 434 items: 435 - const: dwc_usb3 436 - const: pwr_event 437 - const: qusb2_phy 438 - const: ss_phy_irq 439 440 - if: 441 properties: 442 compatible: 443 contains: 444 enum: 445 - qcom,msm8994-dwc3 446 - qcom,msm8996-dwc3 447 - qcom,qcs404-dwc3 448 - qcom,sdm660-dwc3 449 - qcom,sm6115-dwc3 450 - qcom,sm6125-dwc3 451 then: 452 properties: 453 interrupts: 454 minItems: 4 455 maxItems: 5 456 interrupt-names: 457 minItems: 4 458 items: 459 - const: dwc_usb3 460 - const: pwr_event 461 - const: qusb2_phy 462 - const: hs_phy_irq 463 - const: ss_phy_irq 464 465 - if: 466 properties: 467 compatible: 468 contains: 469 enum: 470 - qcom,ipq5018-dwc3 471 - qcom,ipq5332-dwc3 472 then: 473 properties: 474 interrupts: 475 maxItems: 4 476 interrupt-names: 477 items: 478 - const: dwc_usb3 479 - const: pwr_event 480 - const: dp_hs_phy_irq 481 - const: dm_hs_phy_irq 482 483 - if: 484 properties: 485 compatible: 486 contains: 487 enum: 488 - qcom,glymur-dwc3 489 - qcom,milos-dwc3 490 - qcom,x1e80100-dwc3 491 then: 492 properties: 493 interrupts: 494 minItems: 4 495 maxItems: 5 496 interrupt-names: 497 minItems: 4 498 items: 499 - const: dwc_usb3 500 - const: pwr_event 501 - const: dp_hs_phy_irq 502 - const: dm_hs_phy_irq 503 - const: ss_phy_irq 504 505 - if: 506 properties: 507 compatible: 508 contains: 509 enum: 510 - qcom,ipq4019-dwc3 511 - qcom,ipq8064-dwc3 512 - qcom,kaanapali-dwc3 513 - qcom,qcs615-dwc3 514 - qcom,qcs8300-dwc3 515 - qcom,qdu1000-dwc3 516 - qcom,sa8775p-dwc3 517 - qcom,sc7180-dwc3 518 - qcom,sc7280-dwc3 519 - qcom,sc8180x-dwc3 520 - qcom,sc8280xp-dwc3 521 - qcom,sdm670-dwc3 522 - qcom,sdm845-dwc3 523 - qcom,sdx55-dwc3 524 - qcom,sdx65-dwc3 525 - qcom,sdx75-dwc3 526 - qcom,sm4250-dwc3 527 - qcom,sm6350-dwc3 528 - qcom,sm8150-dwc3 529 - qcom,sm8250-dwc3 530 - qcom,sm8350-dwc3 531 - qcom,sm8450-dwc3 532 - qcom,sm8550-dwc3 533 - qcom,sm8650-dwc3 534 - qcom,sm8750-dwc3 535 then: 536 properties: 537 interrupts: 538 minItems: 5 539 maxItems: 6 540 interrupt-names: 541 minItems: 5 542 items: 543 - const: dwc_usb3 544 - const: pwr_event 545 - const: hs_phy_irq 546 - const: dp_hs_phy_irq 547 - const: dm_hs_phy_irq 548 - const: ss_phy_irq 549 550 - if: 551 properties: 552 compatible: 553 contains: 554 enum: 555 - qcom,glymur-dwc3-mp 556 - qcom,sc8180x-dwc3-mp 557 - qcom,x1e80100-dwc3-mp 558 then: 559 properties: 560 interrupts: 561 minItems: 11 562 maxItems: 11 563 interrupt-names: 564 items: 565 - const: dwc_usb3 566 - const: pwr_event_1 567 - const: pwr_event_2 568 - const: hs_phy_1 569 - const: hs_phy_2 570 - const: dp_hs_phy_1 571 - const: dm_hs_phy_1 572 - const: dp_hs_phy_2 573 - const: dm_hs_phy_2 574 - const: ss_phy_1 575 - const: ss_phy_2 576 577 - if: 578 properties: 579 compatible: 580 contains: 581 enum: 582 - qcom,sc8280xp-dwc3-mp 583 then: 584 properties: 585 interrupts: 586 minItems: 19 587 maxItems: 19 588 interrupt-names: 589 items: 590 - const: dwc_usb3 591 - const: pwr_event_1 592 - const: pwr_event_2 593 - const: pwr_event_3 594 - const: pwr_event_4 595 - const: hs_phy_1 596 - const: hs_phy_2 597 - const: hs_phy_3 598 - const: hs_phy_4 599 - const: dp_hs_phy_1 600 - const: dm_hs_phy_1 601 - const: dp_hs_phy_2 602 - const: dm_hs_phy_2 603 - const: dp_hs_phy_3 604 - const: dm_hs_phy_3 605 - const: dp_hs_phy_4 606 - const: dm_hs_phy_4 607 - const: ss_phy_1 608 - const: ss_phy_2 609 610unevaluatedProperties: false 611 612examples: 613 - | 614 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 615 #include <dt-bindings/interrupt-controller/arm-gic.h> 616 #include <dt-bindings/interrupt-controller/irq.h> 617 soc { 618 #address-cells = <2>; 619 #size-cells = <2>; 620 621 usb@a600000 { 622 compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3"; 623 reg = <0 0x0a600000 0 0x100000>; 624 625 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 626 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 627 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 628 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 629 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 630 clock-names = "cfg_noc", 631 "core", 632 "iface", 633 "sleep", 634 "mock_utmi"; 635 636 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 637 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 638 assigned-clock-rates = <19200000>, <150000000>; 639 640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 644 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 645 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", 647 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 648 649 power-domains = <&gcc USB30_PRIM_GDSC>; 650 651 resets = <&gcc GCC_USB30_PRIM_BCR>; 652 653 iommus = <&apps_smmu 0x740 0>; 654 snps,dis_u2_susphy_quirk; 655 snps,dis_enblslpm_quirk; 656 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 657 phy-names = "usb2-phy", "usb3-phy"; 658 }; 659 }; 660... 661