1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12description: 13 Describes the Qualcomm USB block, based on Synopsys DWC3. 14 15select: 16 properties: 17 compatible: 18 contains: 19 const: qcom,snps-dwc3 20 required: 21 - compatible 22 23properties: 24 compatible: 25 items: 26 - enum: 27 - qcom,ipq4019-dwc3 28 - qcom,ipq5018-dwc3 29 - qcom,ipq5332-dwc3 30 - qcom,ipq5424-dwc3 31 - qcom,ipq6018-dwc3 32 - qcom,ipq8064-dwc3 33 - qcom,ipq8074-dwc3 34 - qcom,ipq9574-dwc3 35 - qcom,milos-dwc3 36 - qcom,msm8953-dwc3 37 - qcom,msm8994-dwc3 38 - qcom,msm8996-dwc3 39 - qcom,msm8998-dwc3 40 - qcom,qcm2290-dwc3 41 - qcom,qcs404-dwc3 42 - qcom,qcs615-dwc3 43 - qcom,qcs8300-dwc3 44 - qcom,qdu1000-dwc3 45 - qcom,sa8775p-dwc3 46 - qcom,sar2130p-dwc3 47 - qcom,sc7180-dwc3 48 - qcom,sc7280-dwc3 49 - qcom,sc8180x-dwc3 50 - qcom,sc8180x-dwc3-mp 51 - qcom,sc8280xp-dwc3 52 - qcom,sc8280xp-dwc3-mp 53 - qcom,sdm660-dwc3 54 - qcom,sdm670-dwc3 55 - qcom,sdm845-dwc3 56 - qcom,sdx55-dwc3 57 - qcom,sdx65-dwc3 58 - qcom,sdx75-dwc3 59 - qcom,sm4250-dwc3 60 - qcom,sm6115-dwc3 61 - qcom,sm6125-dwc3 62 - qcom,sm6350-dwc3 63 - qcom,sm6375-dwc3 64 - qcom,sm8150-dwc3 65 - qcom,sm8250-dwc3 66 - qcom,sm8350-dwc3 67 - qcom,sm8450-dwc3 68 - qcom,sm8550-dwc3 69 - qcom,sm8650-dwc3 70 - qcom,x1e80100-dwc3 71 - qcom,x1e80100-dwc3-mp 72 - const: qcom,snps-dwc3 73 74 reg: 75 maxItems: 1 76 77 power-domains: 78 maxItems: 1 79 80 required-opps: 81 maxItems: 1 82 83 clocks: 84 description: | 85 Several clocks are used, depending on the variant. Typical ones are:: 86 - cfg_noc:: System Config NOC clock. 87 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 88 60MHz for HS operation. 89 - iface:: System bus AXI clock. 90 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 91 power mode (U3). 92 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 93 mode. Its frequency should be 19.2MHz. 94 minItems: 1 95 maxItems: 9 96 97 clock-names: 98 minItems: 1 99 maxItems: 9 100 101 dma-coherent: true 102 103 iommus: 104 maxItems: 1 105 106 resets: 107 maxItems: 1 108 109 interconnects: 110 maxItems: 2 111 112 interconnect-names: 113 items: 114 - const: usb-ddr 115 - const: apps-usb 116 117 interrupts: 118 description: | 119 Different types of interrupts are used based on HS PHY used on target: 120 - dwc_usb3: Core DWC3 interrupt 121 - pwr_event: Used for wakeup based on other power events. 122 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 123 hs_phy_irq which is not triggered by default and its 124 functionality is mutually exclusive to that of 125 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 126 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 127 expose only a single IRQ whose behavior can be modified 128 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 129 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 130 of PHY address space. 131 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 132 DM pads of the SoC. These are used for wakeup 133 only on SoCs with non-QUSB2 targets with 134 exception of SDM670/SDM845/SM6350. 135 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 136 minItems: 3 137 maxItems: 19 138 139 interrupt-names: 140 minItems: 3 141 maxItems: 19 142 143 qcom,select-utmi-as-pipe-clk: 144 description: 145 If present, disable USB3 pipe_clk requirement. 146 Used when dwc3 operates without SSPHY and only 147 HS/FS/LS modes are supported. 148 type: boolean 149 150 wakeup-source: true 151 152# Required child node: 153 154required: 155 - compatible 156 - reg 157 - clocks 158 - clock-names 159 - interrupts 160 - interrupt-names 161 162allOf: 163 - $ref: snps,dwc3-common.yaml# 164 - if: 165 properties: 166 compatible: 167 contains: 168 enum: 169 - qcom,ipq4019-dwc3 170 - qcom,ipq5332-dwc3 171 then: 172 properties: 173 clocks: 174 maxItems: 3 175 clock-names: 176 items: 177 - const: core 178 - const: sleep 179 - const: mock_utmi 180 181 - if: 182 properties: 183 compatible: 184 contains: 185 enum: 186 - qcom,ipq8064-dwc3 187 then: 188 properties: 189 clocks: 190 items: 191 - description: Master/Core clock, has to be >= 125 MHz 192 for SS operation and >= 60MHz for HS operation. 193 clock-names: 194 items: 195 - const: core 196 197 - if: 198 properties: 199 compatible: 200 contains: 201 enum: 202 - qcom,ipq9574-dwc3 203 - qcom,msm8953-dwc3 204 - qcom,msm8996-dwc3 205 - qcom,msm8998-dwc3 206 - qcom,qcs8300-dwc3 207 - qcom,sa8775p-dwc3 208 - qcom,sc7180-dwc3 209 - qcom,sc7280-dwc3 210 - qcom,sdm670-dwc3 211 - qcom,sdm845-dwc3 212 - qcom,sdx55-dwc3 213 - qcom,sdx65-dwc3 214 - qcom,sdx75-dwc3 215 - qcom,sm6350-dwc3 216 then: 217 properties: 218 clocks: 219 maxItems: 5 220 clock-names: 221 items: 222 - const: cfg_noc 223 - const: core 224 - const: iface 225 - const: sleep 226 - const: mock_utmi 227 228 - if: 229 properties: 230 compatible: 231 contains: 232 enum: 233 - qcom,ipq6018-dwc3 234 then: 235 properties: 236 clocks: 237 minItems: 3 238 maxItems: 4 239 clock-names: 240 oneOf: 241 - items: 242 - const: core 243 - const: sleep 244 - const: mock_utmi 245 - items: 246 - const: cfg_noc 247 - const: core 248 - const: sleep 249 - const: mock_utmi 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 enum: 256 - qcom,ipq8074-dwc3 257 - qcom,qdu1000-dwc3 258 then: 259 properties: 260 clocks: 261 maxItems: 4 262 clock-names: 263 items: 264 - const: cfg_noc 265 - const: core 266 - const: sleep 267 - const: mock_utmi 268 269 - if: 270 properties: 271 compatible: 272 contains: 273 enum: 274 - qcom,ipq5018-dwc3 275 - qcom,msm8994-dwc3 276 - qcom,qcs404-dwc3 277 then: 278 properties: 279 clocks: 280 maxItems: 4 281 clock-names: 282 items: 283 - const: core 284 - const: iface 285 - const: sleep 286 - const: mock_utmi 287 288 - if: 289 properties: 290 compatible: 291 contains: 292 enum: 293 - qcom,sc8280xp-dwc3 294 - qcom,sc8280xp-dwc3-mp 295 - qcom,x1e80100-dwc3 296 - qcom,x1e80100-dwc3-mp 297 then: 298 properties: 299 clocks: 300 maxItems: 9 301 clock-names: 302 items: 303 - const: cfg_noc 304 - const: core 305 - const: iface 306 - const: sleep 307 - const: mock_utmi 308 - const: noc_aggr 309 - const: noc_aggr_north 310 - const: noc_aggr_south 311 - const: noc_sys 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,sdm660-dwc3 319 then: 320 properties: 321 clocks: 322 minItems: 4 323 maxItems: 5 324 clock-names: 325 oneOf: 326 - items: 327 - const: cfg_noc 328 - const: core 329 - const: iface 330 - const: sleep 331 - const: mock_utmi 332 - items: 333 - const: cfg_noc 334 - const: core 335 - const: sleep 336 - const: mock_utmi 337 338 - if: 339 properties: 340 compatible: 341 contains: 342 enum: 343 - qcom,milos-dwc3 344 - qcom,qcm2290-dwc3 345 - qcom,qcs615-dwc3 346 - qcom,sar2130p-dwc3 347 - qcom,sc8180x-dwc3 348 - qcom,sc8180x-dwc3-mp 349 - qcom,sm6115-dwc3 350 - qcom,sm6125-dwc3 351 - qcom,sm8150-dwc3 352 - qcom,sm8250-dwc3 353 - qcom,sm8450-dwc3 354 - qcom,sm8550-dwc3 355 - qcom,sm8650-dwc3 356 then: 357 properties: 358 clocks: 359 minItems: 6 360 clock-names: 361 items: 362 - const: cfg_noc 363 - const: core 364 - const: iface 365 - const: sleep 366 - const: mock_utmi 367 - const: xo 368 369 - if: 370 properties: 371 compatible: 372 contains: 373 enum: 374 - qcom,sm8350-dwc3 375 then: 376 properties: 377 clocks: 378 minItems: 5 379 maxItems: 6 380 clock-names: 381 minItems: 5 382 items: 383 - const: cfg_noc 384 - const: core 385 - const: iface 386 - const: sleep 387 - const: mock_utmi 388 - const: xo 389 390 - if: 391 properties: 392 compatible: 393 contains: 394 enum: 395 - qcom,ipq5018-dwc3 396 - qcom,ipq6018-dwc3 397 - qcom,ipq8074-dwc3 398 - qcom,msm8953-dwc3 399 - qcom,msm8998-dwc3 400 then: 401 properties: 402 interrupts: 403 minItems: 3 404 maxItems: 4 405 interrupt-names: 406 minItems: 3 407 items: 408 - const: dwc_usb3 409 - const: pwr_event 410 - const: qusb2_phy 411 - const: ss_phy_irq 412 413 - if: 414 properties: 415 compatible: 416 contains: 417 enum: 418 - qcom,msm8996-dwc3 419 - qcom,qcs404-dwc3 420 - qcom,sdm660-dwc3 421 - qcom,sm6115-dwc3 422 - qcom,sm6125-dwc3 423 then: 424 properties: 425 interrupts: 426 minItems: 4 427 maxItems: 5 428 interrupt-names: 429 minItems: 4 430 items: 431 - const: dwc_usb3 432 - const: pwr_event 433 - const: qusb2_phy 434 - const: hs_phy_irq 435 - const: ss_phy_irq 436 437 - if: 438 properties: 439 compatible: 440 contains: 441 enum: 442 - qcom,ipq5332-dwc3 443 then: 444 properties: 445 interrupts: 446 maxItems: 4 447 interrupt-names: 448 items: 449 - const: dwc_usb3 450 - const: pwr_event 451 - const: dp_hs_phy_irq 452 - const: dm_hs_phy_irq 453 454 - if: 455 properties: 456 compatible: 457 contains: 458 enum: 459 - qcom,milos-dwc3 460 - qcom,x1e80100-dwc3 461 then: 462 properties: 463 interrupts: 464 minItems: 4 465 maxItems: 5 466 interrupt-names: 467 minItems: 4 468 items: 469 - const: dwc_usb3 470 - const: pwr_event 471 - const: dp_hs_phy_irq 472 - const: dm_hs_phy_irq 473 - const: ss_phy_irq 474 475 - if: 476 properties: 477 compatible: 478 contains: 479 enum: 480 - qcom,ipq4019-dwc3 481 - qcom,ipq8064-dwc3 482 - qcom,msm8994-dwc3 483 - qcom,qcs615-dwc3 484 - qcom,qcs8300-dwc3 485 - qcom,qdu1000-dwc3 486 - qcom,sa8775p-dwc3 487 - qcom,sc7180-dwc3 488 - qcom,sc7280-dwc3 489 - qcom,sc8180x-dwc3 490 - qcom,sc8280xp-dwc3 491 - qcom,sdm670-dwc3 492 - qcom,sdm845-dwc3 493 - qcom,sdx55-dwc3 494 - qcom,sdx65-dwc3 495 - qcom,sdx75-dwc3 496 - qcom,sm4250-dwc3 497 - qcom,sm6350-dwc3 498 - qcom,sm8150-dwc3 499 - qcom,sm8250-dwc3 500 - qcom,sm8350-dwc3 501 - qcom,sm8450-dwc3 502 - qcom,sm8550-dwc3 503 - qcom,sm8650-dwc3 504 then: 505 properties: 506 interrupts: 507 minItems: 5 508 maxItems: 6 509 interrupt-names: 510 minItems: 5 511 items: 512 - const: dwc_usb3 513 - const: pwr_event 514 - const: hs_phy_irq 515 - const: dp_hs_phy_irq 516 - const: dm_hs_phy_irq 517 - const: ss_phy_irq 518 519 - if: 520 properties: 521 compatible: 522 contains: 523 enum: 524 - qcom,sc8180x-dwc3-mp 525 - qcom,x1e80100-dwc3-mp 526 then: 527 properties: 528 interrupts: 529 minItems: 11 530 maxItems: 11 531 interrupt-names: 532 items: 533 - const: dwc_usb3 534 - const: pwr_event_1 535 - const: pwr_event_2 536 - const: hs_phy_1 537 - const: hs_phy_2 538 - const: dp_hs_phy_1 539 - const: dm_hs_phy_1 540 - const: dp_hs_phy_2 541 - const: dm_hs_phy_2 542 - const: ss_phy_1 543 - const: ss_phy_2 544 545 - if: 546 properties: 547 compatible: 548 contains: 549 enum: 550 - qcom,sc8280xp-dwc3-mp 551 then: 552 properties: 553 interrupts: 554 minItems: 19 555 maxItems: 19 556 interrupt-names: 557 items: 558 - const: dwc_usb3 559 - const: pwr_event_1 560 - const: pwr_event_2 561 - const: pwr_event_3 562 - const: pwr_event_4 563 - const: hs_phy_1 564 - const: hs_phy_2 565 - const: hs_phy_3 566 - const: hs_phy_4 567 - const: dp_hs_phy_1 568 - const: dm_hs_phy_1 569 - const: dp_hs_phy_2 570 - const: dm_hs_phy_2 571 - const: dp_hs_phy_3 572 - const: dm_hs_phy_3 573 - const: dp_hs_phy_4 574 - const: dm_hs_phy_4 575 - const: ss_phy_1 576 - const: ss_phy_2 577 578unevaluatedProperties: false 579 580examples: 581 - | 582 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 583 #include <dt-bindings/interrupt-controller/arm-gic.h> 584 #include <dt-bindings/interrupt-controller/irq.h> 585 soc { 586 #address-cells = <2>; 587 #size-cells = <2>; 588 589 usb@a600000 { 590 compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3"; 591 reg = <0 0x0a600000 0 0x100000>; 592 593 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 594 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 595 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 596 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 597 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 598 clock-names = "cfg_noc", 599 "core", 600 "iface", 601 "sleep", 602 "mock_utmi"; 603 604 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 605 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 606 assigned-clock-rates = <19200000>, <150000000>; 607 608 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 612 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 613 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 614 interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", 615 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 616 617 power-domains = <&gcc USB30_PRIM_GDSC>; 618 619 resets = <&gcc GCC_USB30_PRIM_BCR>; 620 621 iommus = <&apps_smmu 0x740 0>; 622 snps,dis_u2_susphy_quirk; 623 snps,dis_enblslpm_quirk; 624 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 625 phy-names = "usb2-phy", "usb3-phy"; 626 }; 627 }; 628... 629